2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/endian.h>
37 #include <sys/ctype.h>
40 #include <sys/taskqueue.h>
42 #include <machine/bus.h>
44 #include <dev/ata/ata-all.h>
45 #include <dev/ata/ata-pci.h>
49 static int ata_generic_status(device_t dev);
50 static int ata_wait(struct ata_channel *ch, struct ata_device *, u_int8_t);
51 static void ata_pio_read(struct ata_request *, int);
52 static void ata_pio_write(struct ata_request *, int);
53 static void ata_tf_read(struct ata_request *);
54 static void ata_tf_write(struct ata_request *);
57 * low level ATA functions
60 ata_generic_hw(device_t dev)
62 struct ata_channel *ch = device_get_softc(dev);
64 ch->hw.begin_transaction = ata_begin_transaction;
65 ch->hw.end_transaction = ata_end_transaction;
66 ch->hw.status = ata_generic_status;
67 ch->hw.softreset = NULL;
68 ch->hw.command = ata_generic_command;
69 ch->hw.tf_read = ata_tf_read;
70 ch->hw.tf_write = ata_tf_write;
71 ch->hw.pm_read = NULL;
72 ch->hw.pm_write = NULL;
75 /* must be called with ATA channel locked and state_mtx held */
77 ata_begin_transaction(struct ata_request *request)
79 struct ata_channel *ch = device_get_softc(request->parent);
80 struct ata_device *atadev = device_get_softc(request->dev);
83 ATA_DEBUG_RQ(request, "begin transaction");
85 /* disable ATAPI DMA writes if HW doesn't support it */
86 if ((ch->flags & ATA_ATAPI_DMA_RO) &&
87 ((request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)) ==
88 (ATA_R_ATAPI | ATA_R_DMA | ATA_R_WRITE)))
89 request->flags &= ~ATA_R_DMA;
91 /* check for 48 bit access and convert if needed */
92 ata_modify_if_48bit(request);
94 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA)) {
96 /* ATA PIO data transfer and control commands */
99 /* record command direction here as our request might be gone later */
100 int write = (request->flags & ATA_R_WRITE);
103 if (ch->hw.command(request)) {
104 device_printf(request->dev, "error issuing %s command\n",
105 ata_cmd2str(request));
106 request->result = EIO;
110 /* device reset doesn't interrupt */
111 if (request->u.ata.command == ATA_DEVICE_RESET) {
113 int timeout = 1000000;
116 request->status = ATA_IDX_INB(ch, ATA_STATUS);
117 } while (request->status & ATA_S_BUSY && timeout--);
118 if (request->status & ATA_S_ERROR)
119 request->error = ATA_IDX_INB(ch, ATA_ERROR);
123 /* if write command output the data */
125 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) {
126 device_printf(request->dev,
127 "timeout waiting for write DRQ\n");
128 request->result = EIO;
131 ata_pio_write(request, request->transfersize);
136 /* ATA DMA data transfer commands */
138 /* check sanity, setup SG list and DMA engine */
139 if ((error = ch->dma.load(request, NULL, &dummy))) {
140 device_printf(request->dev, "setting up DMA failed\n");
141 request->result = error;
146 if (ch->hw.command(request)) {
147 device_printf(request->dev, "error issuing %s command\n",
148 ata_cmd2str(request));
149 request->result = EIO;
153 /* start DMA engine */
154 if (ch->dma.start && ch->dma.start(request)) {
155 device_printf(request->dev, "error starting DMA\n");
156 request->result = EIO;
161 /* ATAPI PIO commands */
163 /* is this just a POLL DSC command ? */
164 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
165 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit));
167 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
168 request->result = EBUSY;
172 /* start ATAPI operation */
173 if (ch->hw.command(request)) {
174 device_printf(request->dev, "error issuing ATA PACKET command\n");
175 request->result = EIO;
180 /* ATAPI DMA commands */
181 case ATA_R_ATAPI|ATA_R_DMA:
182 /* is this just a POLL DSC command ? */
183 if (request->u.atapi.ccb[0] == ATAPI_POLL_DSC) {
184 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit));
186 if (!(ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_DSC))
187 request->result = EBUSY;
191 /* check sanity, setup SG list and DMA engine */
192 if ((error = ch->dma.load(request, NULL, &dummy))) {
193 device_printf(request->dev, "setting up DMA failed\n");
194 request->result = error;
198 /* start ATAPI operation */
199 if (ch->hw.command(request)) {
200 device_printf(request->dev, "error issuing ATA PACKET command\n");
201 request->result = EIO;
205 /* start DMA engine */
206 if (ch->dma.start && ch->dma.start(request)) {
207 request->result = EIO;
213 printf("ata_begin_transaction OOPS!!!\n");
216 ch->dma.unload(request);
217 return ATA_OP_FINISHED;
220 callout_reset(&request->callout, request->timeout * hz,
221 (timeout_t*)ata_timeout, request);
222 return ATA_OP_CONTINUES;
225 /* must be called with ATA channel locked and state_mtx held */
227 ata_end_transaction(struct ata_request *request)
229 struct ata_channel *ch = device_get_softc(request->parent);
230 struct ata_device *atadev = device_get_softc(request->dev);
233 ATA_DEBUG_RQ(request, "end transaction");
235 /* clear interrupt and get status */
236 request->status = ATA_IDX_INB(ch, ATA_STATUS);
238 switch (request->flags & (ATA_R_ATAPI | ATA_R_DMA | ATA_R_CONTROL)) {
240 /* ATA PIO data transfer and control commands */
243 /* on timeouts we have no data or anything so just return */
244 if (request->flags & ATA_R_TIMEOUT)
247 /* on control commands read back registers to the request struct */
248 if (request->flags & ATA_R_CONTROL) {
249 ch->hw.tf_read(request);
252 /* if we got an error we are done with the HW */
253 if (request->status & ATA_S_ERROR) {
254 request->error = ATA_IDX_INB(ch, ATA_ERROR);
258 /* are we moving data ? */
259 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
261 /* if read data get it */
262 if (request->flags & ATA_R_READ) {
263 int flags = ATA_S_DRQ;
265 if (request->u.ata.command != ATA_ATAPI_IDENTIFY)
266 flags |= ATA_S_READY;
267 if (ata_wait(ch, atadev, flags) < 0) {
268 device_printf(request->dev,
269 "timeout waiting for read DRQ\n");
270 request->result = EIO;
273 ata_pio_read(request, request->transfersize);
276 /* update how far we've gotten */
277 request->donecount += request->transfersize;
279 /* do we need a scoop more ? */
280 if (request->bytecount > request->donecount) {
282 /* set this transfer size according to HW capabilities */
283 request->transfersize =
284 min((request->bytecount - request->donecount),
285 request->transfersize);
287 /* if data write command, output the data */
288 if (request->flags & ATA_R_WRITE) {
290 /* if we get an error here we are done with the HW */
291 if (ata_wait(ch, atadev, (ATA_S_READY | ATA_S_DRQ)) < 0) {
292 device_printf(request->dev,
293 "timeout waiting for write DRQ\n");
294 request->status = ATA_IDX_INB(ch, ATA_STATUS);
298 /* output data and return waiting for new interrupt */
299 ata_pio_write(request, request->transfersize);
303 /* if data read command, return & wait for interrupt */
304 if (request->flags & ATA_R_READ)
311 /* ATA DMA data transfer commands */
314 /* stop DMA engine and get status */
316 request->dma->status = ch->dma.stop(request);
318 /* did we get error or data */
319 if (request->status & ATA_S_ERROR)
320 request->error = ATA_IDX_INB(ch, ATA_ERROR);
321 else if (request->dma->status & ATA_BMSTAT_ERROR)
322 request->status |= ATA_S_ERROR;
323 else if (!(request->flags & ATA_R_TIMEOUT))
324 request->donecount = request->bytecount;
326 /* release SG list etc */
327 ch->dma.unload(request);
332 /* ATAPI PIO commands */
334 length = ATA_IDX_INB(ch, ATA_CYL_LSB)|(ATA_IDX_INB(ch, ATA_CYL_MSB)<<8);
336 /* on timeouts we have no data or anything so just return */
337 if (request->flags & ATA_R_TIMEOUT)
340 switch ((ATA_IDX_INB(ch, ATA_IREASON) & (ATA_I_CMD | ATA_I_IN)) |
341 (request->status & ATA_S_DRQ)) {
344 /* this seems to be needed for some (slow) devices */
347 if (!(request->status & ATA_S_DRQ)) {
348 device_printf(request->dev, "command interrupt without DRQ\n");
349 request->status = ATA_S_ERROR;
352 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
353 (atadev->param.config &
354 ATA_PROTO_MASK)== ATA_PROTO_ATAPI_12 ? 6 : 8);
355 /* return wait for interrupt */
359 if (request->flags & ATA_R_READ) {
360 request->status = ATA_S_ERROR;
361 device_printf(request->dev,
362 "%s trying to write on read buffer\n",
363 ata_cmd2str(request));
367 ata_pio_write(request, length);
368 request->donecount += length;
370 /* set next transfer size according to HW capabilities */
371 request->transfersize = min((request->bytecount-request->donecount),
372 request->transfersize);
373 /* return wait for interrupt */
377 if (request->flags & ATA_R_WRITE) {
378 request->status = ATA_S_ERROR;
379 device_printf(request->dev,
380 "%s trying to read on write buffer\n",
381 ata_cmd2str(request));
384 ata_pio_read(request, length);
385 request->donecount += length;
387 /* set next transfer size according to HW capabilities */
388 request->transfersize = min((request->bytecount-request->donecount),
389 request->transfersize);
390 /* return wait for interrupt */
393 case ATAPI_P_DONEDRQ:
394 device_printf(request->dev,
395 "WARNING - %s DONEDRQ non conformant device\n",
396 ata_cmd2str(request));
397 if (request->flags & ATA_R_READ) {
398 ata_pio_read(request, length);
399 request->donecount += length;
401 else if (request->flags & ATA_R_WRITE) {
402 ata_pio_write(request, length);
403 request->donecount += length;
406 request->status = ATA_S_ERROR;
411 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
412 request->error = ATA_IDX_INB(ch, ATA_ERROR);
416 device_printf(request->dev, "unknown transfer phase\n");
417 request->status = ATA_S_ERROR;
423 /* ATAPI DMA commands */
424 case ATA_R_ATAPI|ATA_R_DMA:
426 /* stop DMA engine and get status */
428 request->dma->status = ch->dma.stop(request);
430 /* did we get error or data */
431 if (request->status & (ATA_S_ERROR | ATA_S_DWF))
432 request->error = ATA_IDX_INB(ch, ATA_ERROR);
433 else if (request->dma->status & ATA_BMSTAT_ERROR)
434 request->status |= ATA_S_ERROR;
435 else if (!(request->flags & ATA_R_TIMEOUT))
436 request->donecount = request->bytecount;
438 /* release SG list etc */
439 ch->dma.unload(request);
445 printf("ata_end_transaction OOPS!!\n");
448 callout_stop(&request->callout);
449 return ATA_OP_FINISHED;
452 return ATA_OP_CONTINUES;
455 /* must be called with ATA channel locked and state_mtx held */
457 ata_generic_reset(device_t dev)
459 struct ata_channel *ch = device_get_softc(dev);
461 u_int8_t ostat0 = 0, stat0 = 0, ostat1 = 0, stat1 = 0;
462 u_int8_t err = 0, lsb = 0, msb = 0;
463 int mask = 0, timeout;
465 /* do we have any signs of ATA/ATAPI HW being present ? */
466 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER));
468 ostat0 = ATA_IDX_INB(ch, ATA_STATUS);
469 if ((ostat0 & 0xf8) != 0xf8 && ostat0 != 0xa5) {
474 /* in some setups we dont want to test for a slave */
475 if (!(ch->flags & ATA_NO_SLAVE)) {
476 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_SLAVE));
478 ostat1 = ATA_IDX_INB(ch, ATA_STATUS);
479 if ((ostat1 & 0xf8) != 0xf8 && ostat1 != 0xa5) {
486 device_printf(dev, "reset tp1 mask=%02x ostat0=%02x ostat1=%02x\n",
487 mask, ostat0, ostat1);
489 /* if nothing showed up there is no need to get any further */
490 /* XXX SOS is that too strong?, we just might loose devices here */
495 /* reset (both) devices on this channel */
496 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(ATA_MASTER));
498 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS | ATA_A_RESET);
500 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_IDS);
502 ATA_IDX_INB(ch, ATA_ERROR);
504 /* wait for BUSY to go inactive */
505 for (timeout = 0; timeout < 310; timeout++) {
506 if ((mask & 0x01) && (stat0 & ATA_S_BUSY)) {
507 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_MASTER));
509 err = ATA_IDX_INB(ch, ATA_ERROR);
510 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
511 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
512 stat0 = ATA_IDX_INB(ch, ATA_STATUS);
515 "stat0=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
516 stat0, err, lsb, msb);
517 if (stat0 == err && lsb == err && msb == err &&
518 timeout > (stat0 & ATA_S_BUSY ? 100 : 10))
520 if (!(stat0 & ATA_S_BUSY)) {
521 if ((err & 0x7f) == ATA_E_ILI) {
522 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
523 ch->devices |= ATA_ATAPI_MASTER;
525 else if (stat0 & ATA_S_READY) {
526 ch->devices |= ATA_ATA_MASTER;
529 else if ((stat0 & 0x0f) && err == lsb && err == msb) {
535 if ((mask & 0x02) && (stat1 & ATA_S_BUSY) &&
536 !((mask & 0x01) && (stat0 & ATA_S_BUSY))) {
537 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(ATA_SLAVE));
539 err = ATA_IDX_INB(ch, ATA_ERROR);
540 lsb = ATA_IDX_INB(ch, ATA_CYL_LSB);
541 msb = ATA_IDX_INB(ch, ATA_CYL_MSB);
542 stat1 = ATA_IDX_INB(ch, ATA_STATUS);
545 "stat1=0x%02x err=0x%02x lsb=0x%02x msb=0x%02x\n",
546 stat1, err, lsb, msb);
547 if (stat1 == err && lsb == err && msb == err &&
548 timeout > (stat1 & ATA_S_BUSY ? 100 : 10))
550 if (!(stat1 & ATA_S_BUSY)) {
551 if ((err & 0x7f) == ATA_E_ILI) {
552 if (lsb == ATAPI_MAGIC_LSB && msb == ATAPI_MAGIC_MSB) {
553 ch->devices |= ATA_ATAPI_SLAVE;
555 else if (stat1 & ATA_S_READY) {
556 ch->devices |= ATA_ATA_SLAVE;
559 else if ((stat1 & 0x0f) && err == lsb && err == msb) {
565 if (mask == 0x00) /* nothing to wait for */
567 if (mask == 0x01) /* wait for master only */
568 if (!(stat0 & ATA_S_BUSY) || (stat0 == 0xff && timeout > 10))
570 if (mask == 0x02) /* wait for slave only */
571 if (!(stat1 & ATA_S_BUSY) || (stat1 == 0xff && timeout > 10))
573 if (mask == 0x03) { /* wait for both master & slave */
574 if (!(stat0 & ATA_S_BUSY) && !(stat1 & ATA_S_BUSY))
576 if ((stat0 == 0xff) && (timeout > 20))
578 if ((stat1 == 0xff) && (timeout > 20))
585 device_printf(dev, "reset tp2 stat0=%02x stat1=%02x devices=0x%x\n",
586 stat0, stat1, ch->devices);
589 /* must be called with ATA channel locked and state_mtx held */
591 ata_generic_status(device_t dev)
593 struct ata_channel *ch = device_get_softc(dev);
595 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY) {
597 if (ATA_IDX_INB(ch, ATA_ALTSTAT) & ATA_S_BUSY)
604 ata_wait(struct ata_channel *ch, struct ata_device *atadev, u_int8_t mask)
611 /* wait at max 1 second for device to get !BUSY */
612 while (timeout < 1000000) {
613 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
615 /* if drive fails status, reselect the drive and try again */
616 if (status == 0xff) {
617 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit));
624 if (!(status & ATA_S_BUSY))
627 if (timeout > 1000) {
636 if (timeout >= 1000000)
639 return (status & ATA_S_ERROR);
643 /* wait 50 msec for bits wanted */
646 status = ATA_IDX_INB(ch, ATA_ALTSTAT);
647 if ((status & mask) == mask)
648 return (status & ATA_S_ERROR);
655 ata_generic_command(struct ata_request *request)
657 struct ata_channel *ch = device_get_softc(request->parent);
658 struct ata_device *atadev = device_get_softc(request->dev);
661 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA | ATA_DEV(atadev->unit));
663 /* ready to issue command ? */
664 if (ata_wait(ch, atadev, 0) < 0) {
665 device_printf(request->dev, "timeout waiting to issue command\n");
669 /* enable interrupt */
670 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
672 if (request->flags & ATA_R_ATAPI) {
675 /* issue packet command to controller */
676 if (request->flags & ATA_R_DMA) {
677 ATA_IDX_OUTB(ch, ATA_FEATURE, ATA_F_DMA);
678 ATA_IDX_OUTB(ch, ATA_CYL_LSB, 0);
679 ATA_IDX_OUTB(ch, ATA_CYL_MSB, 0);
682 ATA_IDX_OUTB(ch, ATA_FEATURE, 0);
683 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->transfersize);
684 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->transfersize >> 8);
686 ATA_IDX_OUTB(ch, ATA_COMMAND, ATA_PACKET_CMD);
688 /* command interrupt device ? just return and wait for interrupt */
689 if ((atadev->param.config & ATA_DRQ_MASK) == ATA_DRQ_INTR)
692 /* wait for ready to write ATAPI command block */
694 int reason = ATA_IDX_INB(ch, ATA_IREASON);
695 int status = ATA_IDX_INB(ch, ATA_STATUS);
697 if (((reason & (ATA_I_CMD | ATA_I_IN)) |
698 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
703 device_printf(request->dev, "timeout waiting for ATAPI ready\n");
704 request->result = EIO;
708 /* this seems to be needed for some (slow) devices */
711 /* output command block */
712 ATA_IDX_OUTSW_STRM(ch, ATA_DATA, (int16_t *)request->u.atapi.ccb,
713 (atadev->param.config & ATA_PROTO_MASK) ==
714 ATA_PROTO_ATAPI_12 ? 6 : 8);
717 ch->hw.tf_write(request);
719 /* issue command to controller */
720 ATA_IDX_OUTB(ch, ATA_COMMAND, request->u.ata.command);
726 ata_tf_read(struct ata_request *request)
728 struct ata_channel *ch = device_get_softc(request->parent);
729 struct ata_device *atadev = device_get_softc(request->dev);
731 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
732 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT | ATA_A_HOB);
733 request->u.ata.count = (ATA_IDX_INB(ch, ATA_COUNT) << 8);
735 ((u_int64_t)(ATA_IDX_INB(ch, ATA_SECTOR)) << 24) |
736 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_LSB)) << 32) |
737 ((u_int64_t)(ATA_IDX_INB(ch, ATA_CYL_MSB)) << 40);
739 ATA_IDX_OUTB(ch, ATA_CONTROL, ATA_A_4BIT);
740 request->u.ata.count |= ATA_IDX_INB(ch, ATA_COUNT);
741 request->u.ata.lba |=
742 (ATA_IDX_INB(ch, ATA_SECTOR) |
743 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
744 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16));
747 request->u.ata.count = ATA_IDX_INB(ch, ATA_COUNT);
748 request->u.ata.lba = ATA_IDX_INB(ch, ATA_SECTOR) |
749 (ATA_IDX_INB(ch, ATA_CYL_LSB) << 8) |
750 (ATA_IDX_INB(ch, ATA_CYL_MSB) << 16) |
751 ((ATA_IDX_INB(ch, ATA_DRIVE) & 0xf) << 24);
756 ata_tf_write(struct ata_request *request)
758 struct ata_channel *ch = device_get_softc(request->parent);
759 struct ata_device *atadev = device_get_softc(request->dev);
761 if (atadev->flags & ATA_D_48BIT_ACTIVE) {
762 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature >> 8);
763 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
764 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count >> 8);
765 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
766 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba >> 24);
767 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
768 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 32);
769 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
770 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 40);
771 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
772 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(atadev->unit));
775 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
776 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
777 if (atadev->flags & ATA_D_USE_CHS) {
780 if (atadev->param.atavalid & ATA_FLAG_54_58) {
781 heads = atadev->param.current_heads;
782 sectors = atadev->param.current_sectors;
785 heads = atadev->param.heads;
786 sectors = atadev->param.sectors;
789 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
790 ATA_IDX_OUTB(ch, ATA_CYL_LSB,
791 (request->u.ata.lba / (sectors * heads)));
792 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
793 (request->u.ata.lba / (sectors * heads)) >> 8);
794 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(atadev->unit) |
795 (((request->u.ata.lba% (sectors * heads)) /
799 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
800 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
801 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
802 ATA_IDX_OUTB(ch, ATA_DRIVE,
803 ATA_D_IBM | ATA_D_LBA | ATA_DEV(atadev->unit) |
804 ((request->u.ata.lba >> 24) & 0x0f));
810 ata_pio_read(struct ata_request *request, int length)
812 struct ata_channel *ch = device_get_softc(request->parent);
813 int size = min(request->transfersize, length);
816 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
817 ATA_IDX_INSW_STRM(ch, ATA_DATA,
818 (void*)((uintptr_t)request->data+request->donecount),
819 size / sizeof(int16_t));
821 ATA_IDX_INSL_STRM(ch, ATA_DATA,
822 (void*)((uintptr_t)request->data+request->donecount),
823 size / sizeof(int32_t));
825 if (request->transfersize < length) {
826 device_printf(request->dev, "WARNING - %s read data overrun %d>%d\n",
827 ata_cmd2str(request), length, request->transfersize);
828 for (resid = request->transfersize; resid < length;
829 resid += sizeof(int16_t))
830 ATA_IDX_INW(ch, ATA_DATA);
835 ata_pio_write(struct ata_request *request, int length)
837 struct ata_channel *ch = device_get_softc(request->parent);
838 int size = min(request->transfersize, length);
841 if (ch->flags & ATA_USE_16BIT || (size % sizeof(int32_t)))
842 ATA_IDX_OUTSW_STRM(ch, ATA_DATA,
843 (void*)((uintptr_t)request->data+request->donecount),
844 size / sizeof(int16_t));
846 ATA_IDX_OUTSL_STRM(ch, ATA_DATA,
847 (void*)((uintptr_t)request->data+request->donecount),
848 size / sizeof(int32_t));
850 if (request->transfersize < length) {
851 device_printf(request->dev, "WARNING - %s write data underrun %d>%d\n",
852 ata_cmd2str(request), length, request->transfersize);
853 for (resid = request->transfersize; resid < length;
854 resid += sizeof(int16_t))
855 ATA_IDX_OUTW(ch, ATA_DATA, 0);