2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/module.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
38 #include <sys/endian.h>
39 #include <sys/malloc.h>
41 #include <sys/mutex.h>
43 #include <sys/taskqueue.h>
45 #include <machine/stdarg.h>
46 #include <machine/resource.h>
47 #include <machine/bus.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/ata/ata-all.h>
52 #include <dev/ata/ata-pci.h>
55 /* local prototypes */
56 static int ata_ali_chipinit(device_t dev);
57 static int ata_ali_chipdeinit(device_t dev);
58 static int ata_ali_ch_attach(device_t dev);
59 static int ata_ali_sata_ch_attach(device_t dev);
60 static void ata_ali_reset(device_t dev);
61 static int ata_ali_setmode(device_t dev, int target, int mode);
68 struct ali_sata_resources {
69 struct resource *bars[4];
73 * Acer Labs Inc (ALI) chipset support functions
76 ata_ali_probe(device_t dev)
78 struct ata_pci_controller *ctlr = device_get_softc(dev);
79 static const struct ata_chip_id ids[] =
80 {{ ATA_ALI_5289, 0x00, 2, ALI_SATA, ATA_SA150, "M5289" },
81 { ATA_ALI_5288, 0x00, 4, ALI_SATA, ATA_SA300, "M5288" },
82 { ATA_ALI_5287, 0x00, 4, ALI_SATA, ATA_SA150, "M5287" },
83 { ATA_ALI_5281, 0x00, 2, ALI_SATA, ATA_SA150, "M5281" },
84 { ATA_ALI_5228, 0xc5, 0, ALI_NEW, ATA_UDMA6, "M5228" },
85 { ATA_ALI_5229, 0xc5, 0, ALI_NEW, ATA_UDMA6, "M5229" },
86 { ATA_ALI_5229, 0xc4, 0, ALI_NEW, ATA_UDMA5, "M5229" },
87 { ATA_ALI_5229, 0xc2, 0, ALI_NEW, ATA_UDMA4, "M5229" },
88 { ATA_ALI_5229, 0x20, 0, ALI_OLD, ATA_UDMA2, "M5229" },
89 { ATA_ALI_5229, 0x00, 0, ALI_OLD, ATA_WDMA2, "M5229" },
92 if (pci_get_vendor(dev) != ATA_ACER_LABS_ID)
95 if (!(ctlr->chip = ata_match_chip(dev, ids)))
99 ctlr->chipinit = ata_ali_chipinit;
100 ctlr->chipdeinit = ata_ali_chipdeinit;
101 return (BUS_PROBE_LOW_PRIORITY);
105 ata_ali_chipinit(device_t dev)
107 struct ata_pci_controller *ctlr = device_get_softc(dev);
108 struct ali_sata_resources *res;
111 if (ata_setup_interrupt(dev, ata_generic_intr))
114 switch (ctlr->chip->cfg2) {
116 ctlr->channels = ctlr->chip->cfg1;
117 ctlr->ch_attach = ata_ali_sata_ch_attach;
118 ctlr->ch_detach = ata_pci_ch_detach;
119 ctlr->setmode = ata_sata_setmode;
120 ctlr->getrev = ata_sata_getrev;
122 /* Allocate resources for later use by channel attach routines. */
123 res = malloc(sizeof(struct ali_sata_resources), M_ATAPCI, M_WAITOK);
124 for (i = 0; i < 4; i++) {
126 res->bars[i] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
128 if (res->bars[i] == NULL) {
129 device_printf(dev, "Failed to allocate BAR %d\n", i);
130 for (i--; i >=0; i--)
131 bus_release_resource(dev, SYS_RES_IOPORT,
132 PCIR_BAR(i), res->bars[i]);
137 ctlr->chipset_data = res;
141 /* use device interrupt as byte count end */
142 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
144 /* enable cable detection and UDMA support on revisions < 0xc7 */
145 if (ctlr->chip->chiprev < 0xc7)
146 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) |
149 /* enable ATAPI UDMA mode (even if we are going to do PIO) */
150 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) |
151 (ctlr->chip->chiprev >= 0xc7 ? 0x03 : 0x01), 1);
153 /* only chips with revision > 0xc4 can do 48bit DMA */
154 if (ctlr->chip->chiprev <= 0xc4)
156 "using PIO transfers above 137GB as workaround for "
157 "48bit DMA access bug, expect reduced performance\n");
158 ctlr->ch_attach = ata_ali_ch_attach;
159 ctlr->ch_detach = ata_pci_ch_detach;
160 ctlr->reset = ata_ali_reset;
161 ctlr->setmode = ata_ali_setmode;
165 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
166 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
167 ctlr->setmode = ata_ali_setmode;
174 ata_ali_chipdeinit(device_t dev)
176 struct ata_pci_controller *ctlr = device_get_softc(dev);
177 struct ali_sata_resources *res;
180 if (ctlr->chip->cfg2 == ALI_SATA) {
181 res = ctlr->chipset_data;
182 for (i = 0; i < 4; i++) {
183 if (res->bars[i] != NULL) {
184 bus_release_resource(dev, SYS_RES_IOPORT,
185 PCIR_BAR(i), res->bars[i]);
189 ctlr->chipset_data = NULL;
195 ata_ali_ch_attach(device_t dev)
197 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
198 struct ata_channel *ch = device_get_softc(dev);
200 /* setup the usual register normal pci style */
201 if (ata_pci_ch_attach(dev))
204 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7)
205 ch->flags |= ATA_CHECKS_CABLE;
206 /* older chips can't do 48bit DMA transfers */
207 if (ctlr->chip->chiprev <= 0xc4) {
208 ch->flags |= ATA_NO_48BIT_DMA;
209 if (ch->dma.max_iosize > 256 * 512)
210 ch->dma.max_iosize = 256 * 512;
212 if (ctlr->chip->cfg2 & ALI_NEW)
213 ch->flags |= ATA_NO_ATAPI_DMA;
219 ata_ali_sata_ch_attach(device_t dev)
221 device_t parent = device_get_parent(dev);
222 struct ata_pci_controller *ctlr = device_get_softc(parent);
223 struct ata_channel *ch = device_get_softc(dev);
224 struct ali_sata_resources *res;
225 struct resource *io = NULL, *ctlio = NULL;
226 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
229 res = ctlr->chipset_data;
232 ctlio = res->bars[3];
235 ctlio = res->bars[1];
237 ata_pci_dmainit(dev);
238 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
239 ch->r_io[i].res = io;
240 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
242 ch->r_io[ATA_CONTROL].res = ctlio;
243 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
244 ch->r_io[ATA_IDX_ADDR].res = io;
245 ata_default_registers(dev);
247 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
248 ch->r_io[i].res = ctlr->r_res1;
249 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
252 ch->flags |= ATA_NO_SLAVE;
253 ch->flags |= ATA_SATA;
255 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
261 ata_ali_reset(device_t dev)
263 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
264 struct ata_channel *ch = device_get_softc(dev);
268 ata_generic_reset(dev);
271 * workaround for datacorruption bug found on at least SUN Blade-100
272 * find the ISA function on the southbridge and disable then enable
273 * the ATA channel tristate buffer
275 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
276 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
277 for (i = 0; i < nchildren; i++) {
278 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
279 pci_write_config(children[i], 0x58,
280 pci_read_config(children[i], 0x58, 1) &
281 ~(0x04 << ch->unit), 1);
282 pci_write_config(children[i], 0x58,
283 pci_read_config(children[i], 0x58, 1) |
284 (0x04 << ch->unit), 1);
288 free(children, M_TEMP);
294 ata_ali_setmode(device_t dev, int target, int mode)
296 device_t parent = device_get_parent(dev);
297 struct ata_pci_controller *ctlr = device_get_softc(parent);
298 struct ata_channel *ch = device_get_softc(dev);
299 int devno = (ch->unit << 1) + target;
301 static const uint32_t piotimings[] =
302 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
303 0x00310001, 0x006d0003, 0x00330001, 0x00310001 };
304 static const uint8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f,
308 mode = min(mode, ctlr->chip->max_dma);
310 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) {
311 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
312 pci_read_config(parent, 0x4a, 1) & (1 << ch->unit)) {
313 ata_print_cable(dev, "controller");
317 if (ctlr->chip->cfg2 & ALI_OLD) {
318 /* doesn't support ATAPI DMA on write */
319 ch->flags |= ATA_ATAPI_DMA_RO;
320 if (ch->devices & ATA_ATAPI_MASTER &&
321 ch->devices & ATA_ATAPI_SLAVE) {
322 /* doesn't support ATAPI DMA on two ATAPI devices */
323 device_printf(dev, "two atapi devices on this channel,"
325 mode = min(mode, ATA_PIO_MAX);
329 word54 = pci_read_config(parent, 0x54, 4);
330 if (mode >= ATA_UDMA0) {
331 word54 &= ~(0x000f000f << (devno << 2));
332 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
336 word54 &= ~(0x0008000f << (devno << 2));
339 pci_write_config(parent, 0x54, word54, 4);
340 /* Set PIO/WDMA mode */
341 pci_write_config(parent, 0x58 + (ch->unit << 2),
342 piotimings[ata_mode2idx(piomode)], 4);
346 ATA_DECLARE_DRIVER(ata_ali);