2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/ata/ata-all.h>
51 #include <dev/ata/ata-pci.h>
54 /* local prototypes */
55 static int ata_ahci_ctlr_reset(device_t dev);
56 static int ata_ahci_suspend(device_t dev);
57 static int ata_ahci_status(device_t dev);
58 static int ata_ahci_begin_transaction(struct ata_request *request);
59 static int ata_ahci_end_transaction(struct ata_request *request);
60 static int ata_ahci_pm_read(device_t dev, int port, int reg, u_int32_t *result);
61 static int ata_ahci_pm_write(device_t dev, int port, int reg, u_int32_t result);
62 static u_int32_t ata_ahci_softreset(device_t dev, int port);
63 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
64 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *equest);
67 * AHCI v1.x compliant SATA chipset support functions
70 ata_ahci_probe(device_t dev)
72 struct ata_pci_controller *ctlr = device_get_softc(dev);
75 /* is this a possible AHCI candidate ? */
76 if (pci_get_subclass(dev) != PCIS_STORAGE_SATA)
79 /* is this PCI device flagged as an AHCI compliant chip ? */
80 if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0)
84 sprintf(buffer, "%s (ID=%08x) AHCI controller",
85 ata_pcivendor2str(dev), pci_get_devid(dev));
87 sprintf(buffer, "%s AHCI controller", ata_pcivendor2str(dev));
88 device_set_desc_copy(dev, buffer);
89 ctlr->chipinit = ata_ahci_chipinit;
94 ata_ahci_chipinit(device_t dev)
96 struct ata_pci_controller *ctlr = device_get_softc(dev);
99 /* if we have a memory BAR(5) we are likely on an AHCI part */
100 ctlr->r_type2 = SYS_RES_MEMORY;
101 ctlr->r_rid2 = PCIR_BAR(5);
102 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
103 &ctlr->r_rid2, RF_ACTIVE)))
106 /* setup interrupt delivery if not done allready by a vendor driver */
108 if (ata_setup_interrupt(dev, ata_generic_intr))
112 device_printf(dev, "AHCI called from vendor specific driver\n");
114 /* reset controller */
115 ata_ahci_ctlr_reset(dev);
117 /* get the number of HW channels */
119 MAX(flsl(ATA_INL(ctlr->r_res2, ATA_AHCI_PI)),
120 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1);
122 ctlr->reset = ata_ahci_reset;
123 ctlr->dmainit = ata_ahci_dmainit;
124 ctlr->allocate = ata_ahci_allocate;
125 ctlr->setmode = ata_sata_setmode;
126 ctlr->suspend = ata_ahci_suspend;
127 ctlr->resume = ata_ahci_ctlr_reset;
129 /* enable PCI interrupt */
130 pci_write_config(dev, PCIR_COMMAND,
131 pci_read_config(dev, PCIR_COMMAND, 2) & ~0x0400, 2);
133 /* announce we support the HW */
134 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
136 "AHCI Version %x%x.%x%x controller with %d ports PM %s\n",
137 (version >> 24) & 0xff, (version >> 16) & 0xff,
138 (version >> 8) & 0xff, version & 0xff,
139 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_NPMASK) + 1,
140 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_SPM) ?
141 "supported" : "not supported");
146 ata_ahci_ctlr_reset(device_t dev)
148 struct ata_pci_controller *ctlr = device_get_softc(dev);
150 /* enable AHCI mode */
151 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
153 /* reset AHCI controller */
154 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR);
156 if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
157 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
158 device_printf(dev, "AHCI controller reset failure\n");
162 /* reenable AHCI mode */
163 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
165 /* clear interrupts */
166 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
168 /* enable AHCI interrupts */
169 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
170 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
176 ata_ahci_suspend(device_t dev)
178 struct ata_pci_controller *ctlr = device_get_softc(dev);
180 /* disable interupts so the state change(s) doesn't trigger */
181 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
182 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & (~ATA_AHCI_GHC_IE));
188 ata_ahci_allocate(device_t dev)
190 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
191 struct ata_channel *ch = device_get_softc(dev);
192 int offset = ch->unit << 7;
194 /* set the SATA resources */
195 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
196 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
197 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
198 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
199 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
200 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
201 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
202 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
204 ch->hw.status = ata_ahci_status;
205 ch->hw.begin_transaction = ata_ahci_begin_transaction;
206 ch->hw.end_transaction = ata_ahci_end_transaction;
207 ch->hw.command = NULL; /* not used here */
208 ch->hw.softreset = ata_ahci_softreset;
209 ch->hw.pm_read = ata_ahci_pm_read;
210 ch->hw.pm_write = ata_ahci_pm_write;
216 ata_ahci_status(device_t dev)
218 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
219 struct ata_channel *ch = device_get_softc(dev);
220 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
221 int offset = ch->unit << 7;
223 #define ATA_AHCI_STATBITS \
224 (ATA_AHCI_P_IX_IF|ATA_AHCI_P_IX_HBD|ATA_AHCI_P_IX_HBF|ATA_AHCI_P_IX_TFE)
226 if (action & (1 << ch->unit)) {
227 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
228 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
230 /* clear interrupt(s) */
231 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
232 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, action & (1 << ch->unit));
234 /* do we have any PHY events ? */
235 if (istatus & (ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC))
236 ata_sata_phy_check_events(dev);
238 /* do we have a potentially hanging engine to take care of? */
239 /* XXX SOS what todo on NCQ */
240 if ((istatus & ATA_AHCI_STATBITS) && (cstatus & 1)) {
242 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
245 /* kill off all activity on this channel */
246 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
247 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
249 /* XXX SOS this is not entirely wrong */
252 if (timeout++ > 1000) {
253 device_printf(dev, "stopping AHCI engine failed\n");
256 } while (ATA_INL(ctlr->r_res2,
257 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
259 /* start operations on this channel */
260 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
261 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
266 /* XXX SOS what todo on NCQ */
267 return (!(cstatus & 1));
272 /* must be called with ATA channel locked and state_mtx held */
274 ata_ahci_begin_transaction(struct ata_request *request)
276 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
277 struct ata_channel *ch = device_get_softc(request->parent);
278 struct ata_device *atadev = device_get_softc(request->dev);
279 struct ata_ahci_cmd_tab *ctp;
280 struct ata_ahci_cmd_list *clp;
281 int offset = ch->unit << 7;
282 int port = atadev->unit & 0x0f;
286 /* get a piece of the workspace for this request */
287 ctp = (struct ata_ahci_cmd_tab *)
288 (ch->dma.work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE*request->tag));
290 /* setup the FIS for this request */
291 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
292 device_printf(request->dev, "setting up SATA FIS failed\n");
293 request->result = EIO;
294 return ATA_OP_FINISHED;
297 /* if request moves data setup and load SG list */
298 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
299 if (ch->dma.load(request, ctp->prd_tab, &entries)) {
300 device_printf(request->dev, "setting up DMA failed\n");
301 request->result = EIO;
302 return ATA_OP_FINISHED;
306 /* setup the command list entry */
307 clp = (struct ata_ahci_cmd_list *)
308 (ch->dma.work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE*request->tag));
310 clp->prd_length = entries;
311 clp->cmd_flags = (request->flags & ATA_R_WRITE ? ATA_AHCI_CMD_WRITE : 0) |
312 (request->flags & ATA_R_ATAPI ?
313 (ATA_AHCI_CMD_ATAPI | ATA_AHCI_CMD_PREFETCH) : 0) |
314 (fis_size / sizeof(u_int32_t)) |
317 clp->cmd_table_phys = htole64(ch->dma.work_bus + ATA_AHCI_CT_OFFSET +
318 (ATA_AHCI_CT_SIZE * request->tag));
320 /* clear eventual ACTIVE bit */
321 ATA_IDX_OUTL(ch, ATA_SACTIVE,
322 ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << request->tag));
324 /* set command type bit */
325 if (request->flags & ATA_R_ATAPI)
326 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
327 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
328 ATA_AHCI_P_CMD_ATAPI);
330 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
331 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
332 ~ATA_AHCI_P_CMD_ATAPI);
334 /* set PM port to address */
335 //ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBS + offset, (port << 8) | 0x00000001);
337 /* issue command to controller */
338 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << request->tag));
340 if (!(request->flags & ATA_R_ATAPI)) {
341 /* device reset doesn't interrupt */
342 if (request->u.ata.command == ATA_DEVICE_RESET) {
344 int timeout = 1000000;
348 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
349 } while ((tf_data & ATA_S_BUSY) && timeout--);
351 device_printf(ch->dev, "device_reset timeout=%dus\n",
352 (1000000-timeout)*10);
353 request->status = tf_data;
354 if (request->status & ATA_S_ERROR)
355 request->error = tf_data >> 8;
356 return ATA_OP_FINISHED;
360 /* start the timeout */
361 callout_reset(&request->callout, request->timeout * hz,
362 (timeout_t*)ata_timeout, request);
363 return ATA_OP_CONTINUES;
366 /* must be called with ATA channel locked and state_mtx held */
368 ata_ahci_end_transaction(struct ata_request *request)
370 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
371 struct ata_channel *ch = device_get_softc(request->parent);
372 struct ata_ahci_cmd_list *clp;
374 int offset = ch->unit << 7;
376 /* kill the timeout */
377 callout_stop(&request->callout);
380 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
381 request->status = tf_data;
383 /* if error status get details */
384 if (request->status & ATA_S_ERROR)
385 request->error = tf_data >> 8;
387 /* on control commands read back registers to the request struct */
388 if (request->flags & ATA_R_CONTROL) {
389 struct ata_device *atadev = device_get_softc(request->dev);
390 u_int8_t *fis = ch->dma.work + ATA_AHCI_FB_OFFSET + 0x40;
392 request->u.ata.count = fis[12] | ((u_int16_t)fis[13] << 8);
393 request->u.ata.lba = fis[4] | ((u_int64_t)fis[5] << 8) |
394 ((u_int64_t)fis[6] << 16);
395 if (atadev->flags & ATA_D_48BIT_ACTIVE)
396 request->u.ata.lba |= ((u_int64_t)fis[8] << 24) |
397 ((u_int64_t)fis[9] << 32) |
398 ((u_int64_t)fis[10] << 40);
400 request->u.ata.lba |= ((u_int64_t)(fis[7] & 0x0f) << 24);
403 /* record how much data we actually moved */
404 clp = (struct ata_ahci_cmd_list *)
405 (ch->dma.work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE*request->tag));
406 request->donecount = clp->bytecount;
408 /* release SG list etc */
409 ch->dma.unload(request);
411 return ATA_OP_FINISHED;
415 ata_ahci_issue_cmd(device_t dev, u_int16_t flags, int timeout)
417 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
418 struct ata_channel *ch = device_get_softc(dev);
419 struct ata_ahci_cmd_list *clp =
420 (struct ata_ahci_cmd_list *)(ch->dma.work + ATA_AHCI_CL_OFFSET);
421 struct ata_ahci_cmd_tab *ctp =
422 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
423 u_int32_t status = 0;
424 int offset = ch->unit << 7;
425 int port = (ctp->cfis[1] & 0x0f);
429 clp->cmd_flags = (20 / sizeof(u_int32_t)) | flags | (port << 12);
431 clp->cmd_table_phys = htole64(ch->dma.work_bus + ATA_AHCI_CT_OFFSET);
434 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBS + offset, (port << 8) | 0x00000001);
436 /* issue command to controller */
437 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, 1);
439 /* poll for command finished */
440 for (count = 0; count < timeout; count++) {
442 if (!((status = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset)) & 1))
446 /* clear interrupts */
447 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
448 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
451 device_printf(dev, "ahci_issue_cmd time=%dms cnt=%dms status=%08x\n",
452 timeout, count, status);
453 if (timeout && (count >= timeout))
460 ata_ahci_pm_read(device_t dev, int port, int reg, u_int32_t *result)
462 struct ata_channel *ch = device_get_softc(dev);
463 struct ata_ahci_cmd_tab *ctp =
464 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
465 u_int8_t *fis = ch->dma.work + ATA_AHCI_FB_OFFSET + 0x40;
467 bzero(ctp->cfis, 64);
468 ctp->cfis[0] = 0x27; /* host to device */
469 ctp->cfis[1] = 0x8f; /* command FIS to PM port */
470 ctp->cfis[2] = ATA_READ_PM;
472 ctp->cfis[7] = port | ATA_D_LBA;
473 ctp->cfis[15] = ATA_A_4BIT;
475 if (ata_ahci_issue_cmd(dev, 0, 10)) {
476 device_printf(dev, "error reading PM port\n");
480 *result = fis[12] | (fis[4] << 8) | (fis[5] << 16) | (fis[6] << 24);
485 ata_ahci_pm_write(device_t dev, int port, int reg, u_int32_t value)
487 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
488 struct ata_channel *ch = device_get_softc(dev);
489 struct ata_ahci_cmd_tab *ctp =
490 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
491 int offset = ch->unit << 7;
493 bzero(ctp->cfis, 64);
494 ctp->cfis[0] = 0x27; /* host to device */
495 ctp->cfis[1] = 0x8f; /* command FIS to PM port */
496 ctp->cfis[2] = ATA_WRITE_PM;
498 ctp->cfis[7] = port | ATA_D_LBA;
499 ctp->cfis[12] = value & 0xff;
500 ctp->cfis[4] = (value >> 8) & 0xff;;
501 ctp->cfis[5] = (value >> 16) & 0xff;;
502 ctp->cfis[6] = (value >> 24) & 0xff;;
503 ctp->cfis[15] = ATA_A_4BIT;
505 if (ata_ahci_issue_cmd(dev, 0, 100)) {
506 device_printf(dev, "error writing PM port\n");
510 return (ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset) >> 8) & 0xff;
514 ata_ahci_restart(device_t dev)
516 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
517 struct ata_channel *ch = device_get_softc(dev);
519 int offset = ch->unit << 7;
522 /* kill off all activity on this channel */
523 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
524 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
525 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
527 /* XXX SOS this is not entirely wrong */
531 if (timeout++ > 1000) {
532 device_printf(dev, "stopping AHCI engine failed\n");
536 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
538 /* issue Command List Override if supported */
539 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_CLO) {
540 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
541 cmd |= ATA_AHCI_P_CMD_CLO;
542 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
546 if (timeout++ > 1000) {
547 device_printf(dev, "executing CLO failed\n");
551 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
554 /* clear SATA error register */
555 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
557 /* clear any interrupts pending on this channel */
558 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
559 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
561 /* start operations on this channel */
562 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
563 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
564 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST) |
565 (ch->devices & ATA_PORTMULTIPLIER ? ATA_AHCI_P_CMD_PMA : 0));
569 ata_ahci_softreset(device_t dev, int port)
571 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
572 struct ata_channel *ch = device_get_softc(dev);
573 int offset = ch->unit << 7;
576 struct ata_ahci_cmd_tab *ctp =
577 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
579 /* kick controller into sane state if needed */
580 ata_ahci_restart(dev);
582 /* pull reset active */
583 bzero(ctp->cfis, 64);
585 ctp->cfis[1] = port & 0x0f;
586 //ctp->cfis[7] = ATA_D_LBA | ATA_D_IBM;
587 ctp->cfis[15] = (ATA_A_4BIT | ATA_A_RESET);
589 if (ata_ahci_issue_cmd(dev, ATA_AHCI_CMD_RESET | ATA_AHCI_CMD_CLR_BUSY,100))
590 device_printf(dev, "setting SRST failed ??\n");
595 /* pull reset inactive -> device softreset */
596 bzero(ctp->cfis, 64);
598 ctp->cfis[1] = port & 0x0f;
599 //ctp->cfis[7] = ATA_D_LBA | ATA_D_IBM;
600 ctp->cfis[15] = ATA_A_4BIT;
601 if (ata_ahci_issue_cmd(dev, 0, 0))
609 if (timeout++ > 1000) {
610 device_printf(dev, "still BUSY after softreset\n");
613 } while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset) & ATA_S_BUSY);
615 device_printf(dev, "BUSY wait time=%dms\n", timeout);
617 return ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
621 ata_ahci_reset(device_t dev)
623 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
624 struct ata_channel *ch = device_get_softc(dev);
626 u_int32_t cmd, signature;
627 int offset = ch->unit << 7;
629 if (!(ATA_INL(ctlr->r_res2, ATA_AHCI_PI) & (1 << ch->unit))) {
630 device_printf(dev, "port not implemented\n");
634 /* setup work areas */
635 work = ch->dma.work_bus + ATA_AHCI_CL_OFFSET;
636 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
637 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
639 work = ch->dma.work_bus + ATA_AHCI_FB_OFFSET;
640 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
641 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
643 /* enable wanted port interrupts */
644 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
645 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
646 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
647 ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC | ATA_AHCI_P_IX_DP |
648 ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB | ATA_AHCI_P_IX_DS |
649 ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
651 /* activate the channel and power/spin up device */
652 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
653 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD));
655 ata_ahci_restart(dev);
657 /* enable FIS based switching */
658 //ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBS + offset, 0x00000003);
660 if (!ata_sata_phy_reset(dev)) {
662 device_printf(dev, "phy reset found no device\n");
665 /* kill off all activity on this channel */
666 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
667 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
668 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
672 /* only probe for PortMultiplier if HW has support */
673 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_SPM)
674 signature = ata_ahci_softreset(dev, ATA_PM);
676 signature = ata_ahci_softreset(dev, 0);
679 device_printf(dev, "SIGNATURE: %08x\n", signature);
683 ch->devices = ATA_ATA_MASTER;
686 ch->devices = ATA_PORTMULTIPLIER;
687 ata_pm_identify(dev);
690 ch->devices = ATA_ATAPI_MASTER;
692 default: /* SOS XXX */
694 device_printf(dev, "No signature, asuming disk device\n");
695 ch->devices = ATA_ATA_MASTER;
698 device_printf(dev, "ahci_reset devices=%08x\n", ch->devices);
702 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
704 struct ata_dmasetprd_args *args = xsc;
705 struct ata_ahci_dma_prd *prd = args->dmatab;
708 if (!(args->error = error)) {
709 for (i = 0; i < nsegs; i++) {
710 prd[i].dba = htole64(segs[i].ds_addr);
711 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
715 KASSERT(nsegs <= ATA_AHCI_DMA_ENTRIES, ("too many DMA segment entries\n"));
720 ata_ahci_dmainit(device_t dev)
722 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
723 struct ata_channel *ch = device_get_softc(dev);
726 /* note start and stop are not used here */
727 ch->dma.setprd = ata_ahci_dmasetprd;
728 ch->dma.max_iosize = 8192 * DEV_BSIZE;
729 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
730 ch->dma.max_address = BUS_SPACE_MAXADDR;
734 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
736 bzero(ctp->cfis, 64);
737 if (request->flags & ATA_R_ATAPI) {
738 bzero(ctp->acmd, 32);
739 bcopy(request->u.atapi.ccb, ctp->acmd, 16);
741 return ata_request2fis_h2d(request, &ctp->cfis[0]);
744 ATA_DECLARE_DRIVER(ata_ahci);