2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/module.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
38 #include <sys/endian.h>
39 #include <sys/malloc.h>
41 #include <sys/mutex.h>
43 #include <sys/taskqueue.h>
45 #include <machine/stdarg.h>
46 #include <machine/resource.h>
47 #include <machine/bus.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/ata/ata-all.h>
52 #include <dev/ata/ata-pci.h>
55 /* local prototypes */
56 static int ata_highpoint_chipinit(device_t dev);
57 static int ata_highpoint_ch_attach(device_t dev);
58 static int ata_highpoint_setmode(device_t dev, int target, int mode);
59 static int ata_highpoint_check_80pin(device_t dev, int mode);
70 * HighPoint chipset support functions
73 ata_highpoint_probe(device_t dev)
75 struct ata_pci_controller *ctlr = device_get_softc(dev);
76 const struct ata_chip_id *idx;
77 static const struct ata_chip_id ids[] =
78 {{ ATA_HPT374, 0x07, HPT_374, 0, ATA_UDMA6, "HPT374" },
79 { ATA_HPT372, 0x02, HPT_372, 0, ATA_UDMA6, "HPT372N" },
80 { ATA_HPT372, 0x01, HPT_372, 0, ATA_UDMA6, "HPT372" },
81 { ATA_HPT371, 0x01, HPT_372, 0, ATA_UDMA6, "HPT371" },
82 { ATA_HPT366, 0x05, HPT_372, 0, ATA_UDMA6, "HPT372" },
83 { ATA_HPT366, 0x03, HPT_370, 0, ATA_UDMA5, "HPT370" },
84 { ATA_HPT366, 0x02, HPT_366, 0, ATA_UDMA4, "HPT368" },
85 { ATA_HPT366, 0x00, HPT_366, HPT_OLD, ATA_UDMA4, "HPT366" },
86 { ATA_HPT302, 0x01, HPT_372, 0, ATA_UDMA6, "HPT302" },
90 if (pci_get_vendor(dev) != ATA_HIGHPOINT_ID)
93 if (!(idx = ata_match_chip(dev, ids)))
96 strcpy(buffer, "HighPoint ");
97 strcat(buffer, idx->text);
98 if (idx->cfg1 == HPT_374) {
99 if (pci_get_function(dev) == 0)
100 strcat(buffer, " (channel 0+1)");
101 if (pci_get_function(dev) == 1)
102 strcat(buffer, " (channel 2+3)");
104 sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
105 device_set_desc_copy(dev, buffer);
107 ctlr->chipinit = ata_highpoint_chipinit;
108 return (BUS_PROBE_LOW_PRIORITY);
112 ata_highpoint_chipinit(device_t dev)
114 struct ata_pci_controller *ctlr = device_get_softc(dev);
116 if (ata_setup_interrupt(dev, ata_generic_intr))
119 if (ctlr->chip->cfg2 == HPT_OLD) {
120 /* disable interrupt prediction */
121 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
124 /* disable interrupt prediction */
125 pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
126 pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
128 /* enable interrupts */
129 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
132 if (ctlr->chip->cfg1 < HPT_372)
133 pci_write_config(dev, 0x5b, 0x22, 1);
135 pci_write_config(dev, 0x5b,
136 (pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
138 ctlr->ch_attach = ata_highpoint_ch_attach;
139 ctlr->ch_detach = ata_pci_ch_detach;
140 ctlr->setmode = ata_highpoint_setmode;
145 ata_highpoint_ch_attach(device_t dev)
147 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
148 struct ata_channel *ch = device_get_softc(dev);
150 /* setup the usual register normal pci style */
151 if (ata_pci_ch_attach(dev))
153 ch->flags |= ATA_ALWAYS_DMASTAT;
154 ch->flags |= ATA_CHECKS_CABLE;
155 if (ctlr->chip->cfg1 == HPT_366)
156 ch->flags |= ATA_NO_ATAPI_DMA;
161 ata_highpoint_setmode(device_t dev, int target, int mode)
163 device_t parent = device_get_parent(dev);
164 struct ata_pci_controller *ctlr = device_get_softc(parent);
165 struct ata_channel *ch = device_get_softc(dev);
166 int devno = (ch->unit << 1) + target;
167 static const uint32_t timings33[][4] = {
168 /* HPT366 HPT370 HPT372 HPT374 mode */
169 { 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
170 { 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
171 { 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
172 { 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
173 { 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
174 { 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
175 { 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
176 { 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
177 { 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
178 { 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
179 { 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
180 { 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
181 { 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
182 { 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
183 { 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
186 mode = min(mode, ctlr->chip->max_dma);
187 mode = ata_highpoint_check_80pin(dev, mode);
189 * most if not all HPT chips cant really handle that the device is
190 * running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
191 * a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
193 mode = min(mode, ATA_UDMA5);
194 pci_write_config(parent, 0x40 + (devno << 2),
195 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
200 ata_highpoint_check_80pin(device_t dev, int mode)
202 device_t parent = device_get_parent(dev);
203 struct ata_pci_controller *ctlr = device_get_softc(parent);
204 struct ata_channel *ch = device_get_softc(dev);
205 u_int8_t reg, val, res;
207 if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(parent) == 1) {
208 reg = ch->unit ? 0x57 : 0x53;
209 val = pci_read_config(parent, reg, 1);
210 pci_write_config(parent, reg, val | 0x80, 1);
214 val = pci_read_config(parent, reg, 1);
215 pci_write_config(parent, reg, val & 0xfe, 1);
217 res = pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
218 pci_write_config(parent, reg, val, 1);
220 if (ata_dma_check_80pin && mode > ATA_UDMA2 && res) {
221 ata_print_cable(dev, "controller");
227 ATA_DECLARE_DRIVER(ata_highpoint);