2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/module.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
38 #include <sys/endian.h>
39 #include <sys/malloc.h>
41 #include <sys/mutex.h>
43 #include <sys/taskqueue.h>
45 #include <machine/stdarg.h>
46 #include <machine/resource.h>
47 #include <machine/bus.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/ata/ata-all.h>
52 #include <dev/ata/ata-pci.h>
55 /* local prototypes */
56 static int ata_ite_chipinit(device_t dev);
57 static int ata_ite_ch_attach(device_t dev);
58 static int ata_ite_821x_setmode(device_t dev, int target, int mode);
59 static int ata_ite_8213_setmode(device_t dev, int target, int mode);
62 * Integrated Technology Express Inc. (ITE) chipset support functions
65 ata_ite_probe(device_t dev)
67 struct ata_pci_controller *ctlr = device_get_softc(dev);
68 static const struct ata_chip_id ids[] =
69 {{ ATA_IT8213F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8213F" },
70 { ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
71 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
74 if (pci_get_vendor(dev) != ATA_ITE_ID)
77 if (!(ctlr->chip = ata_match_chip(dev, ids)))
81 ctlr->chipinit = ata_ite_chipinit;
82 return (BUS_PROBE_LOW_PRIORITY);
86 ata_ite_chipinit(device_t dev)
88 struct ata_pci_controller *ctlr = device_get_softc(dev);
90 if (ata_setup_interrupt(dev, ata_generic_intr))
93 if (ctlr->chip->chipid == ATA_IT8213F) {
94 /* the ITE 8213F only has one channel */
97 ctlr->setmode = ata_ite_8213_setmode;
100 /* set PCI mode and 66Mhz reference clock */
101 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
103 /* set default active & recover timings */
104 pci_write_config(dev, 0x54, 0x31, 1);
105 pci_write_config(dev, 0x56, 0x31, 1);
107 ctlr->setmode = ata_ite_821x_setmode;
108 /* No timing restrictions initially. */
109 ctlr->chipset_data = NULL;
111 ctlr->ch_attach = ata_ite_ch_attach;
116 ata_ite_ch_attach(device_t dev)
118 struct ata_channel *ch = device_get_softc(dev);
121 error = ata_pci_ch_attach(dev);
122 ch->flags |= ATA_CHECKS_CABLE;
123 ch->flags |= ATA_NO_ATAPI_DMA;
128 ata_ite_821x_setmode(device_t dev, int target, int mode)
130 device_t parent = device_get_parent(dev);
131 struct ata_pci_controller *ctlr = device_get_softc(parent);
132 struct ata_channel *ch = device_get_softc(dev);
133 int devno = (ch->unit << 1) + target;
135 uint8_t *timings = (uint8_t*)(&ctlr->chipset_data);
136 static const uint8_t udmatiming[] =
137 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
138 static const uint8_t chtiming[] =
139 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
141 mode = min(mode, ctlr->chip->max_dma);
142 /* check the CBLID bits for 80 conductor cable detection */
143 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
144 (pci_read_config(parent, 0x40, 2) &
145 (ch->unit ? (1<<3) : (1<<2)))) {
146 ata_print_cable(dev, "controller");
149 if (mode >= ATA_UDMA0) {
150 /* enable UDMA mode */
151 pci_write_config(parent, 0x50,
152 pci_read_config(parent, 0x50, 1) &
153 ~(1 << (devno + 3)), 1);
154 /* set UDMA timing */
155 pci_write_config(parent,
156 0x56 + (ch->unit << 2) + target,
157 udmatiming[mode & ATA_MODE_MASK], 1);
160 /* disable UDMA mode */
161 pci_write_config(parent, 0x50,
162 pci_read_config(parent, 0x50, 1) |
163 (1 << (devno + 3)), 1);
166 timings[devno] = chtiming[ata_mode2idx(piomode)];
167 /* set active and recover timing (shared between master & slave) */
168 pci_write_config(parent, 0x54 + (ch->unit << 2),
169 max(timings[ch->unit << 1], timings[(ch->unit << 1) + 1]), 1);
174 ata_ite_8213_setmode(device_t dev, int target, int mode)
176 device_t parent = device_get_parent(dev);
177 struct ata_pci_controller *ctlr = device_get_softc(parent);
179 u_int16_t reg40 = pci_read_config(parent, 0x40, 2);
180 u_int8_t reg44 = pci_read_config(parent, 0x44, 1);
181 u_int8_t reg48 = pci_read_config(parent, 0x48, 1);
182 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2);
183 u_int16_t reg54 = pci_read_config(parent, 0x54, 2);
184 u_int16_t mask40 = 0, new40 = 0;
185 u_int8_t mask44 = 0, new44 = 0;
186 static const uint8_t timings[] =
187 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 };
188 static const uint8_t utimings[] =
189 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 };
191 mode = min(mode, ctlr->chip->max_dma);
193 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
194 !(reg54 & (0x10 << target))) {
195 ata_print_cable(dev, "controller");
198 /* Enable/disable UDMA and set timings. */
199 if (mode >= ATA_UDMA0) {
200 pci_write_config(parent, 0x48, reg48 | (0x0001 << target), 2);
201 pci_write_config(parent, 0x4a,
202 (reg4a & ~(0x3 << (target << 2))) |
203 (utimings[mode & ATA_MODE_MASK] << (target<<2)), 2);
206 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << target), 2);
207 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (target << 2))),2);
210 /* Set UDMA reference clock (33/66/133MHz). */
211 reg54 &= ~(0x1001 << target);
212 if (mode >= ATA_UDMA5)
213 reg54 |= (0x1000 << target);
214 else if (mode >= ATA_UDMA3)
215 reg54 |= (0x1 << target);
216 pci_write_config(parent, 0x54, reg54, 2);
217 /* Allow PIO/WDMA timing controls. */
220 /* Set PIO/WDMA timings. */
222 reg40 |= (ata_atapi(dev, target) ? 0x04 : 0x00);
224 new40 = timings[ata_mode2idx(piomode)] << 8;
227 reg40 |= (ata_atapi(dev, target) ? 0x40 : 0x00);
229 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) |
230 (timings[ata_mode2idx(piomode)] & 0x03);
232 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4);
233 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1);
237 ATA_DECLARE_DRIVER(ata_ite);