2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/module.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
38 #include <sys/endian.h>
39 #include <sys/malloc.h>
41 #include <sys/mutex.h>
43 #include <sys/taskqueue.h>
45 #include <machine/stdarg.h>
46 #include <machine/resource.h>
47 #include <machine/bus.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/ata/ata-all.h>
52 #include <dev/ata/ata-pci.h>
55 /* local prototypes */
56 static int ata_cmd_ch_attach(device_t dev);
57 static int ata_cmd_status(device_t dev);
58 static int ata_cmd_setmode(device_t dev, int target, int mode);
59 static int ata_sii_ch_attach(device_t dev);
60 static int ata_sii_ch_detach(device_t dev);
61 static int ata_sii_status(device_t dev);
62 static void ata_sii_reset(device_t dev);
63 static int ata_sii_setmode(device_t dev, int target, int mode);
68 #define SII_SETCLK 0x02
73 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
76 ata_sii_probe(device_t dev)
78 struct ata_pci_controller *ctlr = device_get_softc(dev);
79 static const struct ata_chip_id ids[] =
80 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" },
81 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" },
82 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
83 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
84 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" },
85 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
86 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
87 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" },
88 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" },
89 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" },
90 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" },
91 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" },
94 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID)
97 if (!(ctlr->chip = ata_match_chip(dev, ids)))
101 ctlr->chipinit = ata_sii_chipinit;
102 return (BUS_PROBE_LOW_PRIORITY);
106 ata_sii_chipinit(device_t dev)
108 struct ata_pci_controller *ctlr = device_get_softc(dev);
110 if (ata_setup_interrupt(dev, ata_generic_intr))
113 switch (ctlr->chip->cfg1) {
115 ctlr->r_type2 = SYS_RES_MEMORY;
116 ctlr->r_rid2 = PCIR_BAR(5);
117 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
118 &ctlr->r_rid2, RF_ACTIVE))){
119 if (ctlr->chip->chipid != ATA_SII0680 ||
120 (pci_read_config(dev, 0x8a, 1) & 1))
124 if (ctlr->chip->cfg2 & SII_SETCLK) {
125 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
126 pci_write_config(dev, 0x8a,
127 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
128 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
129 device_printf(dev, "%s could not set ATA133 clock\n",
133 /* if we have 4 channels enable the second set */
134 if (ctlr->chip->cfg2 & SII_4CH) {
135 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
139 /* dont block interrupts from any channel */
140 pci_write_config(dev, 0x48,
141 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
143 /* enable PCI interrupt as BIOS might not */
144 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
147 ctlr->ch_attach = ata_sii_ch_attach;
148 ctlr->ch_detach = ata_sii_ch_detach;
151 if (ctlr->chip->max_dma >= ATA_SA150) {
152 ctlr->reset = ata_sii_reset;
153 ctlr->setmode = ata_sata_setmode;
154 ctlr->getrev = ata_sata_getrev;
157 ctlr->setmode = ata_sii_setmode;
161 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
162 device_printf(dev, "HW has secondary channel disabled\n");
166 /* enable interrupt as BIOS might not */
167 pci_write_config(dev, 0x71, 0x01, 1);
169 ctlr->ch_attach = ata_cmd_ch_attach;
170 ctlr->ch_detach = ata_pci_ch_detach;
171 ctlr->setmode = ata_cmd_setmode;
178 ata_cmd_ch_attach(device_t dev)
180 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
181 struct ata_channel *ch = device_get_softc(dev);
183 /* setup the usual register normal pci style */
184 if (ata_pci_ch_attach(dev))
187 if (ctlr->chip->cfg2 & SII_INTR)
188 ch->hw.status = ata_cmd_status;
190 ch->flags |= ATA_NO_ATAPI_DMA;
196 ata_cmd_status(device_t dev)
198 struct ata_channel *ch = device_get_softc(dev);
201 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) &
202 (ch->unit ? 0x08 : 0x04))) {
203 pci_write_config(device_get_parent(dev), 0x71,
204 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
205 return ata_pci_status(dev);
211 ata_cmd_setmode(device_t dev, int target, int mode)
213 device_t parent = device_get_parent(dev);
214 struct ata_pci_controller *ctlr = device_get_softc(parent);
215 struct ata_channel *ch = device_get_softc(dev);
216 int devno = (ch->unit << 1) + target;
217 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
218 int ureg = ch->unit ? 0x7b : 0x73;
220 static const uint8_t piotimings[] =
221 { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f };
222 static const uint8_t udmatimings[][2] =
223 { { 0x31, 0xc2 }, { 0x21, 0x82 }, { 0x11, 0x42 },
224 { 0x25, 0x8a }, { 0x15, 0x4a }, { 0x05, 0x0a } };
226 mode = min(mode, ctlr->chip->max_dma);
227 if (mode >= ATA_UDMA0) {
228 u_int8_t umode = pci_read_config(parent, ureg, 1);
230 umode &= ~(target == 0 ? 0x35 : 0xca);
231 umode |= udmatimings[mode & ATA_MODE_MASK][target];
232 pci_write_config(parent, ureg, umode, 1);
235 pci_write_config(parent, ureg,
236 pci_read_config(parent, ureg, 1) &
237 ~(target == 0 ? 0x35 : 0xca), 1);
240 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1);
245 ata_sii_ch_attach(device_t dev)
247 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
248 struct ata_channel *ch = device_get_softc(dev);
249 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
252 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
253 ch->r_io[i].res = ctlr->r_res2;
254 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
256 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
257 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
258 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
259 ata_default_registers(dev);
261 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
262 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
263 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
264 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
265 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
266 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
268 if (ctlr->chip->max_dma >= ATA_SA150) {
269 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
270 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
271 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
272 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
273 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
274 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
275 ch->flags |= ATA_NO_SLAVE;
276 ch->flags |= ATA_SATA;
277 ch->flags |= ATA_KNOWN_PRESENCE;
279 /* enable PHY state change interrupt */
280 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
283 if (ctlr->chip->cfg2 & SII_BUG) {
284 /* work around errata in early chips */
285 ch->dma.boundary = 8192;
286 ch->dma.segsize = 15 * DEV_BSIZE;
290 ch->hw.status = ata_sii_status;
291 if (ctlr->chip->cfg2 & SII_SETCLK)
292 ch->flags |= ATA_CHECKS_CABLE;
294 ata_pci_dmainit(dev);
300 ata_sii_ch_detach(device_t dev)
303 ata_pci_dmafini(dev);
308 ata_sii_status(device_t dev)
310 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
311 struct ata_channel *ch = device_get_softc(dev);
312 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
313 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
315 /* do we have any PHY events ? */
316 if (ctlr->chip->max_dma >= ATA_SA150 &&
317 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
318 ata_sata_phy_check_events(dev, -1);
320 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
321 return ata_pci_status(dev);
327 ata_sii_reset(device_t dev)
329 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
330 struct ata_channel *ch = device_get_softc(dev);
331 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8);
334 /* Apply R_ERR on DMA activate FIS errata workaround. */
335 val = ATA_INL(ctlr->r_res2, 0x14c + offset);
336 if ((val & 0x3) == 0x1)
337 ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3);
339 if (ata_sata_phy_reset(dev, -1, 1))
340 ata_generic_reset(dev);
346 ata_sii_setmode(device_t dev, int target, int mode)
348 device_t parent = device_get_parent(dev);
349 struct ata_pci_controller *ctlr = device_get_softc(parent);
350 struct ata_channel *ch = device_get_softc(dev);
351 int rego = (ch->unit << 4) + (target << 1);
352 int mreg = ch->unit ? 0x84 : 0x80;
353 int mask = 0x03 << (target << 2);
354 int mval = pci_read_config(parent, mreg, 1) & ~mask;
356 u_int8_t preg = 0xa4 + rego;
357 u_int8_t dreg = 0xa8 + rego;
358 u_int8_t ureg = 0xac + rego;
359 static const uint16_t piotimings[] =
360 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
361 static const uint16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
362 static const uint8_t udmatimings[] =
363 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
365 mode = min(mode, ctlr->chip->max_dma);
367 if (ctlr->chip->cfg2 & SII_SETCLK) {
368 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
369 (pci_read_config(parent, 0x79, 1) &
370 (ch->unit ? 0x02 : 0x01))) {
371 ata_print_cable(dev, "controller");
375 if (mode >= ATA_UDMA0) {
376 pci_write_config(parent, mreg,
377 mval | (0x03 << (target << 2)), 1);
378 pci_write_config(parent, ureg,
379 (pci_read_config(parent, ureg, 1) & ~0x3f) |
380 udmatimings[mode & ATA_MODE_MASK], 1);
382 } else if (mode >= ATA_WDMA0) {
383 pci_write_config(parent, mreg,
384 mval | (0x02 << (target << 2)), 1);
385 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
386 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
387 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
389 pci_write_config(parent, mreg,
390 mval | (0x01 << (target << 2)), 1);
393 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2);
397 ATA_DECLARE_DRIVER(ata_sii);