2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification, immediately at the beginning of the file.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/module.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
38 #include <sys/endian.h>
39 #include <sys/malloc.h>
41 #include <sys/mutex.h>
43 #include <sys/taskqueue.h>
45 #include <machine/stdarg.h>
46 #include <machine/resource.h>
47 #include <machine/bus.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <dev/ata/ata-all.h>
52 #include <dev/ata/ata-pci.h>
55 /* local prototypes */
56 static int ata_via_chipinit(device_t dev);
57 static int ata_via_ch_attach(device_t dev);
58 static int ata_via_ch_detach(device_t dev);
59 static void ata_via_reset(device_t dev);
60 static int ata_via_status(device_t dev);
61 static int ata_via_old_setmode(device_t dev, int target, int mode);
62 static void ata_via_southbridge_fixup(device_t dev);
63 static int ata_via_new_setmode(device_t dev, int target, int mode);
64 static int ata_via_sata_ch_attach(device_t dev);
65 static int ata_via_sata_getrev(device_t dev, int target);
66 static int ata_via_sata_setmode(device_t dev, int target, int mode);
67 static void ata_via_sata_reset(device_t dev);
68 static int ata_via_sata_scr_read(device_t dev, int port, int reg,
70 static int ata_via_sata_scr_write(device_t dev, int port, int reg,
72 static int ata_via_sata_status(device_t dev);
86 * VIA Technologies Inc. chipset support functions
89 ata_via_probe(device_t dev)
91 struct ata_pci_controller *ctlr = device_get_softc(dev);
92 static const struct ata_chip_id ids[] =
93 {{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
94 { ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
95 { ATA_VIA82C596, 0x12, VIA66, VIACLK, ATA_UDMA4, "82C596B" },
96 { ATA_VIA82C596, 0x00, VIA33, 0x00, ATA_UDMA2, "82C596" },
97 { ATA_VIA82C686, 0x40, VIA100, VIABUG, ATA_UDMA5, "82C686B"},
98 { ATA_VIA82C686, 0x10, VIA66, VIACLK, ATA_UDMA4, "82C686A" },
99 { ATA_VIA82C686, 0x00, VIA33, 0x00, ATA_UDMA2, "82C686" },
100 { ATA_VIA8231, 0x00, VIA100, VIABUG, ATA_UDMA5, "8231" },
101 { ATA_VIA8233, 0x00, VIA100, 0x00, ATA_UDMA5, "8233" },
102 { ATA_VIA8233C, 0x00, VIA100, 0x00, ATA_UDMA5, "8233C" },
103 { ATA_VIA8233A, 0x00, VIA133, 0x00, ATA_UDMA6, "8233A" },
104 { ATA_VIA8235, 0x00, VIA133, 0x00, ATA_UDMA6, "8235" },
105 { ATA_VIA8237, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
106 { ATA_VIA8237A, 0x00, VIA133, 0x00, ATA_UDMA6, "8237A" },
107 { ATA_VIA8237S, 0x00, VIA133, 0x00, ATA_UDMA6, "8237S" },
108 { ATA_VIA8237_5372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
109 { ATA_VIA8237_7372, 0x00, VIA133, 0x00, ATA_UDMA6, "8237" },
110 { ATA_VIA8251, 0x00, VIA133, 0x00, ATA_UDMA6, "8251" },
111 { ATA_VIACX700, 0x00, VIA133, VIASATA, ATA_SA150, "CX700" },
112 { ATA_VIAVX800, 0x00, VIA133, VIASATA, ATA_SA150, "VX800" },
113 { ATA_VIAVX855, 0x00, VIA133, 0x00, ATA_UDMA6, "VX855" },
114 { ATA_VIAVX900, 0x00, VIA133, VIASATA, ATA_SA300, "VX900" },
115 { 0, 0, 0, 0, 0, 0 }};
116 static const struct ata_chip_id new_ids[] =
117 {{ ATA_VIA6410, 0x00, 0, 0x00, ATA_UDMA6, "6410" },
118 { ATA_VIA6420, 0x00, 7, 0x00, ATA_SA150, "6420" },
119 { ATA_VIA6421, 0x00, 6, VIABAR, ATA_SA150, "6421" },
120 { ATA_VIA8237A, 0x00, 7, 0x00, ATA_SA150, "8237A" },
121 { ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" },
122 { ATA_VIA8237_5372, 0x00, 7, 0x00, ATA_SA300, "8237" },
123 { ATA_VIA8237_7372, 0x00, 7, 0x00, ATA_SA300, "8237" },
124 { 0, 0, 0, 0, 0, 0 }};
126 if (pci_get_vendor(dev) != ATA_VIA_ID)
129 if (pci_get_devid(dev) == ATA_VIA82C571 ||
130 pci_get_devid(dev) == ATA_VIACX700IDE ||
131 pci_get_devid(dev) == ATA_VIASATAIDE ||
132 pci_get_devid(dev) == ATA_VIASATAIDE2 ||
133 pci_get_devid(dev) == ATA_VIASATAIDE3) {
134 if (!(ctlr->chip = ata_find_chip(dev, ids, -99)))
138 if (!(ctlr->chip = ata_match_chip(dev, new_ids)))
143 ctlr->chipinit = ata_via_chipinit;
144 return (BUS_PROBE_LOW_PRIORITY);
148 ata_via_chipinit(device_t dev)
150 struct ata_pci_controller *ctlr = device_get_softc(dev);
152 if (ata_setup_interrupt(dev, ata_generic_intr))
155 /* 2 SATA with "SATA registers" at PCI config space + PATA on secondary */
156 if (ctlr->chip->cfg2 & VIASATA) {
157 ctlr->ch_attach = ata_via_sata_ch_attach;
158 ctlr->setmode = ata_via_sata_setmode;
159 ctlr->getrev = ata_via_sata_getrev;
160 ctlr->reset = ata_via_sata_reset;
163 /* Legacy SATA/SATA+PATA with SATA registers in BAR(5). */
164 if (ctlr->chip->max_dma >= ATA_SA150) {
165 ctlr->r_type2 = SYS_RES_IOPORT;
166 ctlr->r_rid2 = PCIR_BAR(5);
167 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
168 &ctlr->r_rid2, RF_ACTIVE))) {
169 ctlr->ch_attach = ata_via_ch_attach;
170 ctlr->ch_detach = ata_via_ch_detach;
171 ctlr->reset = ata_via_reset;
173 if (ctlr->chip->cfg2 & VIABAR) {
175 ctlr->setmode = ata_via_new_setmode;
177 ctlr->setmode = ata_sata_setmode;
178 ctlr->getrev = ata_sata_getrev;
182 /* prepare for ATA-66 on the 82C686a and 82C596b */
183 if (ctlr->chip->cfg2 & VIACLK)
184 pci_write_config(dev, 0x50, 0x030b030b, 4);
186 /* the southbridge might need the data corruption fix */
187 if (ctlr->chip->cfg2 & VIABUG)
188 ata_via_southbridge_fixup(dev);
190 /* set fifo configuration half'n'half */
191 pci_write_config(dev, 0x43,
192 (pci_read_config(dev, 0x43, 1) & 0x90) | 0x2a, 1);
194 /* set status register read retry */
195 pci_write_config(dev, 0x44, pci_read_config(dev, 0x44, 1) | 0x08, 1);
197 /* set DMA read & end-of-sector fifo flush */
198 pci_write_config(dev, 0x46,
199 (pci_read_config(dev, 0x46, 1) & 0x0c) | 0xf0, 1);
201 /* set sector size */
202 pci_write_config(dev, 0x60, DEV_BSIZE, 2);
203 pci_write_config(dev, 0x68, DEV_BSIZE, 2);
205 ctlr->setmode = ata_via_old_setmode;
210 ata_via_ch_attach(device_t dev)
212 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
213 struct ata_channel *ch = device_get_softc(dev);
215 /* newer SATA chips has resources in one BAR for each channel */
216 if (ctlr->chip->cfg2 & VIABAR) {
217 struct resource *r_io;
220 ata_pci_dmainit(dev);
222 rid = PCIR_BAR(ch->unit);
223 if (!(r_io = bus_alloc_resource_any(device_get_parent(dev),
228 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
229 ch->r_io[i].res = r_io;
230 ch->r_io[i].offset = i;
232 ch->r_io[ATA_CONTROL].res = r_io;
233 ch->r_io[ATA_CONTROL].offset = 2 + ATA_IOSIZE;
234 ch->r_io[ATA_IDX_ADDR].res = r_io;
235 ata_default_registers(dev);
236 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
237 ch->r_io[i].res = ctlr->r_res1;
238 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
245 /* setup the usual register normal pci style */
246 if (ata_pci_ch_attach(dev))
250 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
251 ch->r_io[ATA_SSTATUS].offset = (ch->unit << ctlr->chip->cfg1);
252 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
253 ch->r_io[ATA_SERROR].offset = 0x04 + (ch->unit << ctlr->chip->cfg1);
254 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
255 ch->r_io[ATA_SCONTROL].offset = 0x08 + (ch->unit << ctlr->chip->cfg1);
256 ch->hw.status = ata_via_status;
257 ch->flags |= ATA_NO_SLAVE;
258 ch->flags |= ATA_SATA;
259 ch->flags |= ATA_PERIODIC_POLL;
261 ata_sata_scr_write(ch, -1, ATA_SERROR, 0xffffffff);
267 ata_via_ch_detach(device_t dev)
269 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
270 struct ata_channel *ch = device_get_softc(dev);
272 /* newer SATA chips has resources in one BAR for each channel */
273 if (ctlr->chip->cfg2 & VIABAR) {
276 rid = PCIR_BAR(ch->unit);
277 bus_release_resource(device_get_parent(dev),
278 SYS_RES_IOPORT, rid, ch->r_io[ATA_CONTROL].res);
280 ata_pci_dmafini(dev);
283 /* setup the usual register normal pci style */
284 if (ata_pci_ch_detach(dev))
292 ata_via_reset(device_t dev)
294 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
295 struct ata_channel *ch = device_get_softc(dev);
297 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1))
298 ata_generic_reset(dev);
300 if (ata_sata_phy_reset(dev, -1, 1))
301 ata_generic_reset(dev);
308 ata_via_status(device_t dev)
311 ata_sata_phy_check_events(dev, -1);
312 return (ata_pci_status(dev));
316 ata_via_new_setmode(device_t dev, int target, int mode)
318 device_t parent = device_get_parent(dev);
319 struct ata_pci_controller *ctlr = device_get_softc(parent);
320 struct ata_channel *ch = device_get_softc(dev);
322 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) {
324 static const uint8_t pio_timings[] =
325 { 0xa8, 0x65, 0x65, 0x32, 0x20 };
326 static const uint8_t dma_timings[] =
327 { 0xee, 0xe8, 0xe6, 0xe4, 0xe2, 0xe1, 0xe0 };
329 /* This chip can't do WDMA. */
330 if (mode >= ATA_WDMA0 && mode < ATA_UDMA0)
332 if (mode >= ATA_UDMA0) {
333 pci_write_config(parent, 0xb3,
334 dma_timings[mode & ATA_MODE_MASK], 1);
338 pci_write_config(parent, 0xab, pio_timings[ata_mode2idx(piomode)], 1);
340 mode = ata_sata_setmode(dev, target, mode);
345 ata_via_old_setmode(device_t dev, int target, int mode)
347 device_t parent = device_get_parent(dev);
348 struct ata_pci_controller *ctlr = device_get_softc(parent);
349 struct ata_channel *ch = device_get_softc(dev);
350 int devno = (ch->unit << 1) + target;
351 int reg = 0x53 - devno;
353 static const uint8_t timings[] =
354 { 0xa8, 0x65, 0x42, 0x22, 0x20, 0xa8, 0x22, 0x20 };
355 static const uint8_t modes[][7] = {
356 { 0xc2, 0xc1, 0xc0, 0x00, 0x00, 0x00, 0x00 }, /* VIA ATA33 */
357 { 0xee, 0xec, 0xea, 0xe9, 0xe8, 0x00, 0x00 }, /* VIA ATA66 */
358 { 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0, 0x00 }, /* VIA ATA100 */
359 { 0xf7, 0xf7, 0xf6, 0xf4, 0xf2, 0xf1, 0xf0 } }; /* VIA ATA133 */
361 mode = min(mode, ctlr->chip->max_dma);
362 /* Set UDMA timings */
363 if (mode >= ATA_UDMA0) {
364 pci_write_config(parent, reg,
365 modes[ctlr->chip->cfg1][mode & ATA_MODE_MASK], 1);
368 pci_write_config(parent, reg, 0x8b, 1);
371 /* Set WDMA/PIO timings */
372 pci_write_config(parent, reg - 0x08,timings[ata_mode2idx(piomode)], 1);
377 ata_via_southbridge_fixup(device_t dev)
382 if (device_get_children(device_get_parent(dev), &children, &nchildren))
385 for (i = 0; i < nchildren; i++) {
386 if (pci_get_devid(children[i]) == ATA_VIA8363 ||
387 pci_get_devid(children[i]) == ATA_VIA8371 ||
388 pci_get_devid(children[i]) == ATA_VIA8662 ||
389 pci_get_devid(children[i]) == ATA_VIA8361) {
390 u_int8_t reg76 = pci_read_config(children[i], 0x76, 1);
392 if ((reg76 & 0xf0) != 0xd0) {
394 "Correcting VIA config for southbridge data corruption bug\n");
395 pci_write_config(children[i], 0x75, 0x80, 1);
396 pci_write_config(children[i], 0x76, (reg76 & 0x0f) | 0xd0, 1);
401 free(children, M_TEMP);
405 ata_via_sata_ch_attach(device_t dev)
407 struct ata_channel *ch = device_get_softc(dev);
409 if (ata_pci_ch_attach(dev))
412 ch->hw.status = ata_via_sata_status;
413 ch->hw.pm_read = ata_via_sata_scr_read;
414 ch->hw.pm_write = ata_via_sata_scr_write;
415 ch->flags |= ATA_PERIODIC_POLL;
416 ch->flags |= ATA_SATA;
417 ata_sata_scr_write(ch, 0, ATA_SERROR, 0xffffffff);
418 ata_sata_scr_write(ch, 1, ATA_SERROR, 0xffffffff);
424 ata_via_sata_getrev(device_t dev, int target)
426 device_t parent = device_get_parent(dev);
427 struct ata_channel *ch = device_get_softc(dev);
430 if (pci_read_config(parent, 0xa0 + target, 1) & 0x10)
439 ata_via_sata_setmode(device_t dev, int target, int mode)
441 struct ata_channel *ch = device_get_softc(dev);
445 return (ata_via_old_setmode(dev, target, mode));
449 ata_via_sata_reset(device_t dev)
451 struct ata_channel *ch = device_get_softc(dev);
456 devs = ata_sata_phy_reset(dev, 0, 0);
459 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA |
460 ATA_DEV(ATA_MASTER));
462 status = ATA_IDX_INB(ch, ATA_STATUS);
464 } while (status & ATA_S_BUSY && count < 100);
466 devs += ata_sata_phy_reset(dev, 1, 0);
469 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_D_LBA |
472 status = ATA_IDX_INB(ch, ATA_STATUS);
474 } while (status & ATA_S_BUSY && count < 100);
478 ata_generic_reset(dev);
484 ata_via_sata_scr_read(device_t dev, int port, int reg, u_int32_t *result)
489 parent = device_get_parent(dev);
490 port = (port == 1) ? 1 : 0;
493 val = pci_read_config(parent, 0xa0 + port, 1);
494 *result = val & 0x03;
495 if (*result != ATA_SS_DET_NO_DEVICE) {
497 *result |= ATA_SS_IPM_PARTIAL;
499 *result |= ATA_SS_IPM_SLUMBER;
501 *result |= ATA_SS_IPM_ACTIVE;
503 *result |= ATA_SS_SPD_GEN2;
505 *result |= ATA_SS_SPD_GEN1;
509 *result = pci_read_config(parent, 0xa8 + port * 4, 4);
512 val = pci_read_config(parent, 0xa4 + port, 1);
515 *result |= ATA_SC_DET_RESET;
517 *result |= ATA_SC_DET_DISABLE;
519 *result |= ATA_SC_IPM_DIS_PARTIAL;
521 *result |= ATA_SC_IPM_DIS_SLUMBER;
530 ata_via_sata_scr_write(device_t dev, int port, int reg, u_int32_t value)
535 parent = device_get_parent(dev);
536 port = (port == 1) ? 1 : 0;
539 pci_write_config(parent, 0xa8 + port * 4, value, 4);
543 if (value & ATA_SC_DET_RESET)
545 if (value & ATA_SC_DET_DISABLE)
547 if (value & ATA_SC_IPM_DIS_PARTIAL)
549 if (value & ATA_SC_IPM_DIS_SLUMBER)
551 pci_write_config(parent, 0xa4 + port, val, 1);
560 ata_via_sata_status(device_t dev)
563 ata_sata_phy_check_events(dev, 0);
564 ata_sata_phy_check_events(dev, 1);
565 return (ata_pci_status(dev));
568 ATA_DECLARE_DRIVER(ata_via);