2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
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9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
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13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
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19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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31 #ifndef _ATH_AH_OSDEP_H_
32 #define _ATH_AH_OSDEP_H_
34 * Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/endian.h>
40 #include <machine/bus.h>
43 * Delay n microseconds.
45 extern void ath_hal_delay(int);
46 #define OS_DELAY(_n) ath_hal_delay(_n)
48 #define OS_INLINE __inline
49 #define OS_MEMZERO(_a, _n) ath_hal_memzero((_a), (_n))
50 extern void ath_hal_memzero(void *, size_t);
51 #define OS_MEMCPY(_d, _s, _n) ath_hal_memcpy(_d,_s,_n)
52 extern void *ath_hal_memcpy(void *, const void *, size_t);
54 #define abs(_a) __builtin_abs(_a)
57 extern u_int32_t ath_hal_getuptime(struct ath_hal *);
58 #define OS_GETUPTIME(_ah) ath_hal_getuptime(_ah)
61 * Register read/write operations are either handled through
62 * platform-dependent routines (or when debugging is enabled
63 * with AH_DEBUG); or they are inline expanded using the macros
64 * defined below. For public builds we inline expand only for
65 * platforms where it is certain what the requirements are to
66 * read/write registers--typically they are memory-mapped and
67 * no explicit synchronization or memory invalidation operations
68 * are required (e.g. i386).
70 #if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ)
71 #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
72 #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
74 extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
75 extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
78 * The hardware registers are native little-endian byte order.
79 * Big-endian hosts are handled by enabling hardware byte-swap
80 * of register reads and writes at reset. But the PCI clock
81 * domain registers are not byte swapped! Thus, on big-endian
82 * platforms we have to explicitly byte-swap those registers.
83 * Most of this code is collapsed at compile time because the
84 * register values are constants.
86 #define AH_LITTLE_ENDIAN 1234
87 #define AH_BIG_ENDIAN 4321
89 #if _BYTE_ORDER == _BIG_ENDIAN
90 #define OS_REG_UNSWAPPED(_reg) \
91 (((_reg) >= 0x4000 && (_reg) < 0x5000) || \
92 ((_reg) >= 0x7000 && (_reg) < 0x8000))
93 #define OS_REG_WRITE(_ah, _reg, _val) do { \
94 if (OS_REG_UNSWAPPED(_reg)) \
95 bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
96 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \
98 bus_space_write_stream_4((bus_space_tag_t)(_ah)->ah_st, \
99 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val)); \
101 #define OS_REG_READ(_ah, _reg) \
102 (OS_REG_UNSWAPPED(_reg) ? \
103 bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \
104 (bus_space_handle_t)(_ah)->ah_sh, (_reg)) : \
105 bus_space_read_stream_4((bus_space_tag_t)(_ah)->ah_st, \
106 (bus_space_handle_t)(_ah)->ah_sh, (_reg)))
107 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */
108 #define OS_REG_UNSWAPPED(_reg) (0)
109 #define OS_REG_WRITE(_ah, _reg, _val) \
110 bus_space_write_4((bus_space_tag_t)(_ah)->ah_st, \
111 (bus_space_handle_t)(_ah)->ah_sh, (_reg), (_val))
112 #define OS_REG_READ(_ah, _reg) \
113 bus_space_read_4((bus_space_tag_t)(_ah)->ah_st, \
114 (bus_space_handle_t)(_ah)->ah_sh, (_reg))
115 #endif /* _BYTE_ORDER */
116 #endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */
119 extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
121 #define OS_MARK(_ah, _id, _v)
124 #endif /* _ATH_AH_OSDEP_H_ */