2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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31 #ifndef _ATH_AH_OSDEP_H_
32 #define _ATH_AH_OSDEP_H_
34 * Atheros Hardware Access Layer (HAL) OS Dependent Definitions.
36 #include <sys/cdefs.h>
37 #include <sys/param.h>
38 #include <sys/systm.h>
39 #include <sys/endian.h>
40 #include <sys/linker_set.h>
42 #include <machine/bus.h>
45 * Bus i/o type definitions.
47 typedef void *HAL_SOFTC;
48 typedef bus_space_tag_t HAL_BUS_TAG;
49 typedef bus_space_handle_t HAL_BUS_HANDLE;
52 * Although the underlying hardware may support 64 bit DMA, the
53 * current Atheros hardware only supports 32 bit addressing.
55 typedef uint32_t HAL_DMA_ADDR;
58 * Linker set writearounds for chip and RF backend registration.
60 #define OS_DATA_SET(set, item) DATA_SET(set, item)
61 #define OS_SET_DECLARE(set, ptype) SET_DECLARE(set, ptype)
62 #define OS_SET_FOREACH(pvar, set) SET_FOREACH(pvar, set)
65 * Delay n microseconds.
67 #define OS_DELAY(_n) DELAY(_n)
69 #define OS_INLINE __inline
70 #define OS_MEMZERO(_a, _n) bzero((_a), (_n))
71 #define OS_MEMCPY(_d, _s, _n) memcpy(_d,_s,_n)
72 #define OS_MEMCMP(_a, _b, _l) memcmp((_a), (_b), (_l))
74 #define abs(_a) __builtin_abs(_a)
79 * The hardware registers are native little-endian byte order.
80 * Big-endian hosts are handled by enabling hardware byte-swap
81 * of register reads and writes at reset. But the PCI clock
82 * domain registers are not byte swapped! Thus, on big-endian
83 * platforms we have to explicitly byte-swap those registers.
84 * OS_REG_UNSWAPPED identifies the registers that need special handling.
86 * This is not currently used by the FreeBSD HAL osdep code; the HAL
87 * currently does not configure hardware byteswapping for register space
88 * accesses and instead does it through the FreeBSD bus space code.
90 #if _BYTE_ORDER == _BIG_ENDIAN
91 #define OS_REG_UNSWAPPED(_reg) \
92 (((_reg) >= 0x4000 && (_reg) < 0x5000) || \
93 ((_reg) >= 0x7000 && (_reg) < 0x8000))
94 #else /* _BYTE_ORDER == _LITTLE_ENDIAN */
95 #define OS_REG_UNSWAPPED(_reg) (0)
96 #endif /* _BYTE_ORDER */
99 * For USB/SDIO support (where access latencies are quite high);
100 * some write accesses may be buffered and then flushed when
101 * either a read is done, or an explicit flush is done.
103 * These are simply placeholders for now.
105 #define OS_REG_WRITE_BUFFER_ENABLE(_ah) \
107 #define OS_REG_WRITE_BUFFER_DISABLE(_ah) \
109 #define OS_REG_WRITE_BUFFER_FLUSH(_ah) \
113 * Read and write barriers. Some platforms require more strongly ordered
114 * operations and unfortunately most of the HAL is written assuming everything
115 * is either an x86 or the bus layer will do the barriers for you.
117 * Read barriers should occur before each read, and write barriers
118 * occur after each write.
120 * Later on for SDIO/USB parts we will methodize this and make them no-ops;
121 * register accesses will go via USB commands.
123 #define OS_BUS_BARRIER_READ BUS_SPACE_BARRIER_READ
124 #define OS_BUS_BARRIER_WRITE BUS_SPACE_BARRIER_WRITE
125 #define OS_BUS_BARRIER_RW \
126 (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
127 #define OS_BUS_BARRIER(_ah, _start, _len, _t) \
128 bus_space_barrier((bus_space_tag_t)(_ah)->ah_st, \
129 (bus_space_handle_t)(_ah)->ah_sh, (_start), (_len), (_t))
130 #define OS_BUS_BARRIER_REG(_ah, _reg, _t) \
131 OS_BUS_BARRIER((_ah), (_reg), 4, (_t))
134 * Register read/write operations are handled through
135 * platform-dependent routines.
137 #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val)
138 #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg)
140 extern void ath_hal_reg_write(struct ath_hal *ah, u_int reg, u_int32_t val);
141 extern u_int32_t ath_hal_reg_read(struct ath_hal *ah, u_int reg);
144 extern void OS_MARK(struct ath_hal *, u_int id, u_int32_t value);
146 #define OS_MARK(_ah, _id, _v)
149 #endif /* _ATH_AH_OSDEP_H_ */