2 * Copyright (c) 2014 Qualcomm Atheros, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #ifndef __ATH_HAL_BTCOEX_H__
20 #define __ATH_HAL_BTCOEX_H__
23 * General BT coexistence definitions.
26 HAL_BT_MODULE_CSR_BC4 = 0, /* CSR BlueCore v4 */
27 HAL_BT_MODULE_JANUS = 1, /* Kite + Valkyrie combo */
28 HAL_BT_MODULE_HELIUS = 2, /* Kiwi + Valkyrie combo */
33 HAL_BT_MODULE bt_module;
34 u_int8_t bt_coex_config;
35 u_int8_t bt_gpio_bt_active;
36 u_int8_t bt_gpio_bt_priority;
37 u_int8_t bt_gpio_wlan_active;
38 u_int8_t bt_active_polarity;
39 HAL_BOOL bt_single_ant;
40 u_int8_t bt_isolation;
44 HAL_BT_COEX_MODE_LEGACY = 0, /* legacy rx_clear mode */
45 HAL_BT_COEX_MODE_UNSLOTTED = 1, /* untimed/unslotted mode */
46 HAL_BT_COEX_MODE_SLOTTED = 2, /* slotted mode */
47 HAL_BT_COEX_MODE_DISALBED = 3, /* coexistence disabled */
51 HAL_BT_COEX_CFG_NONE, /* No bt coex enabled */
52 HAL_BT_COEX_CFG_2WIRE_2CH, /* 2-wire with 2 chains */
53 HAL_BT_COEX_CFG_2WIRE_CH1, /* 2-wire with ch1 */
54 HAL_BT_COEX_CFG_2WIRE_CH0, /* 2-wire with ch0 */
55 HAL_BT_COEX_CFG_3WIRE, /* 3-wire */
56 HAL_BT_COEX_CFG_MCI /* MCI */
60 HAL_BT_COEX_SET_ACK_PWR = 0, /* Change ACK power setting */
61 HAL_BT_COEX_LOWER_TX_PWR, /* Change transmit power */
62 HAL_BT_COEX_ANTENNA_DIVERSITY, /* Enable RX diversity for Kite */
63 HAL_BT_COEX_MCI_MAX_TX_PWR, /* Set max tx power for concurrent tx */
64 HAL_BT_COEX_MCI_FTP_STOMP_RX, /* Use a different weight for stomp low */
65 } HAL_BT_COEX_SET_PARAMETER;
68 * MCI specific coexistence definitions.
71 #define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
72 #define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
73 /* Check Rx Diversity is allowed */
74 #define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004
75 /* Check Diversity is on or off */
76 #define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008
78 #define HAL_BT_COEX_ANTDIV_CONTROL1_ENABLE 0x0b
79 /* main: LNA1, alt: LNA2 */
80 #define HAL_BT_COEX_ANTDIV_CONTROL2_ENABLE 0x09
81 #define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_A 0x04
82 #define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_A 0x09
83 #define HAL_BT_COEX_ANTDIV_CONTROL1_FIXED_B 0x02
84 #define HAL_BT_COEX_ANTDIV_CONTROL2_FIXED_B 0x06
86 #define HAL_BT_COEX_ISOLATION_FOR_NO_COEX 30
88 #define HAL_BT_COEX_ANT_DIV_SWITCH_COM 0x66666666
90 #define HAL_BT_COEX_HELIUS_CHAINMASK 0x02
92 #define HAL_BT_COEX_LOW_ACK_POWER 0x0
93 #define HAL_BT_COEX_HIGH_ACK_POWER 0x3f3f3f
96 HAL_BT_COEX_NO_STOMP = 0,
97 HAL_BT_COEX_STOMP_ALL,
98 HAL_BT_COEX_STOMP_LOW,
99 HAL_BT_COEX_STOMP_NONE,
100 HAL_BT_COEX_STOMP_ALL_FORCE,
101 HAL_BT_COEX_STOMP_LOW_FORCE,
102 HAL_BT_COEX_STOMP_AUDIO,
103 } HAL_BT_COEX_STOMP_TYPE;
106 /* extend rx_clear after tx/rx to protect the burst (in usec). */
107 u_int8_t bt_time_extend;
110 * extend rx_clear as long as txsm is
111 * transmitting or waiting for ack.
113 HAL_BOOL bt_txstate_extend;
116 * extend rx_clear so that when tx_frame
117 * is asserted, rx_clear will drop.
119 HAL_BOOL bt_txframe_extend;
124 HAL_BT_COEX_MODE bt_mode;
127 * treat BT high priority traffic as
130 HAL_BOOL bt_quiet_collision;
133 * invert rx_clear as WLAN_ACTIVE
135 HAL_BOOL bt_rxclear_polarity;
138 * slotted mode only. indicate the time in usec
139 * from the rising edge of BT_ACTIVE to the time
140 * BT_PRIORITY can be sampled to indicate priority.
142 u_int8_t bt_priority_time;
145 * slotted mode only. indicate the time in usec
146 * from the rising edge of BT_ACTIVE to the time
147 * BT_PRIORITY can be sampled to indicate tx/rx and
148 * BT_FREQ is sampled.
150 u_int8_t bt_first_slot_time;
153 * slotted mode only. rx_clear and bt_ant decision
154 * will be held the entire time that BT_ACTIVE is asserted,
155 * otherwise the decision is made before every slot boundary.
157 HAL_BOOL bt_hold_rxclear;
158 } HAL_BT_COEX_CONFIG;
160 #define HAL_BT_COEX_FLAG_LOW_ACK_PWR 0x00000001
161 #define HAL_BT_COEX_FLAG_LOWER_TX_PWR 0x00000002
162 #define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW 0x00000004 /* Check Rx Diversity is allowed */
163 #define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE 0x00000008 /* Check Diversity is on or off */
164 #define HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR 0x00000010
165 #define HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX 0x00000020
167 #define HAL_MCI_FLAG_DISABLE_TIMESTAMP 0x00000001 /* Disable time stamp */
169 typedef enum mci_message_header {
170 MCI_LNA_CTRL = 0x10, /* len = 0 */
171 MCI_CONT_NACK = 0x20, /* len = 0 */
172 MCI_CONT_INFO = 0x30, /* len = 4 */
173 MCI_CONT_RST = 0x40, /* len = 0 */
174 MCI_SCHD_INFO = 0x50, /* len = 16 */
175 MCI_CPU_INT = 0x60, /* len = 4 */
176 MCI_SYS_WAKING = 0x70, /* len = 0 */
177 MCI_GPM = 0x80, /* len = 16 */
178 MCI_LNA_INFO = 0x90, /* len = 1 */
179 MCI_LNA_STATE = 0x94,
181 MCI_LNA_TRANS = 0x9c,
182 MCI_SYS_SLEEPING = 0xa0, /* len = 0 */
183 MCI_REQ_WAKE = 0xc0, /* len = 0 */
184 MCI_DEBUG_16 = 0xfe, /* len = 2 */
185 MCI_REMOTE_RESET = 0xff /* len = 16 */
186 } MCI_MESSAGE_HEADER;
188 /* Default remote BT device MCI COEX version */
189 #define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT 3
190 #define MCI_GPM_COEX_MINOR_VERSION_DEFAULT 0
191 /* Local WLAN MCI COEX version */
192 #define MCI_GPM_COEX_MAJOR_VERSION_WLAN 3
193 #define MCI_GPM_COEX_MINOR_VERSION_WLAN 0
195 typedef enum mci_gpm_subtype {
196 MCI_GPM_BT_CAL_REQ = 0,
197 MCI_GPM_BT_CAL_GRANT = 1,
198 MCI_GPM_BT_CAL_DONE = 2,
199 MCI_GPM_WLAN_CAL_REQ = 3,
200 MCI_GPM_WLAN_CAL_GRANT = 4,
201 MCI_GPM_WLAN_CAL_DONE = 5,
202 MCI_GPM_COEX_AGENT = 0x0C,
203 MCI_GPM_RSVD_PATTERN = 0xFE,
204 MCI_GPM_RSVD_PATTERN32 = 0xFEFEFEFE,
205 MCI_GPM_BT_DEBUG = 0xFF
208 typedef enum mci_gpm_coex_opcode {
209 MCI_GPM_COEX_VERSION_QUERY = 0,
210 MCI_GPM_COEX_VERSION_RESPONSE = 1,
211 MCI_GPM_COEX_STATUS_QUERY = 2,
212 MCI_GPM_COEX_HALT_BT_GPM = 3,
213 MCI_GPM_COEX_WLAN_CHANNELS = 4,
214 MCI_GPM_COEX_BT_PROFILE_INFO = 5,
215 MCI_GPM_COEX_BT_STATUS_UPDATE = 6,
216 MCI_GPM_COEX_BT_UPDATE_FLAGS = 7
217 } MCI_GPM_COEX_OPCODE_T;
219 typedef enum mci_gpm_coex_query_type {
220 /* WLAN information */
221 MCI_GPM_COEX_QUERY_WLAN_ALL_INFO = 0x01,
223 MCI_GPM_COEX_QUERY_BT_ALL_INFO = 0x01,
224 MCI_GPM_COEX_QUERY_BT_TOPOLOGY = 0x02,
225 MCI_GPM_COEX_QUERY_BT_DEBUG = 0x04
226 } MCI_GPM_COEX_QUERY_TYPE_T;
228 typedef enum mci_gpm_coex_halt_bt_gpm {
229 MCI_GPM_COEX_BT_GPM_UNHALT = 0,
230 MCI_GPM_COEX_BT_GPM_HALT = 1
231 } MCI_GPM_COEX_HALT_BT_GPM_T;
233 typedef enum mci_gpm_coex_profile_type {
234 MCI_GPM_COEX_PROFILE_UNKNOWN = 0,
235 MCI_GPM_COEX_PROFILE_RFCOMM = 1,
236 MCI_GPM_COEX_PROFILE_A2DP = 2,
237 MCI_GPM_COEX_PROFILE_HID = 3,
238 MCI_GPM_COEX_PROFILE_BNEP = 4,
239 MCI_GPM_COEX_PROFILE_VOICE = 5,
240 MCI_GPM_COEX_PROFILE_MAX
241 } MCI_GPM_COEX_PROFILE_TYPE_T;
243 typedef enum mci_gpm_coex_profile_state {
244 MCI_GPM_COEX_PROFILE_STATE_END = 0,
245 MCI_GPM_COEX_PROFILE_STATE_START = 1
246 } MCI_GPM_COEX_PROFILE_STATE_T;
248 typedef enum mci_gpm_coex_profile_role {
249 MCI_GPM_COEX_PROFILE_SLAVE = 0,
250 MCI_GPM_COEX_PROFILE_MASTER = 1
251 } MCI_GPM_COEX_PROFILE_ROLE_T;
253 typedef enum mci_gpm_coex_bt_status_type {
254 MCI_GPM_COEX_BT_NONLINK_STATUS = 0,
255 MCI_GPM_COEX_BT_LINK_STATUS = 1
256 } MCI_GPM_COEX_BT_STATUS_TYPE_T;
258 typedef enum mci_gpm_coex_bt_status_state {
259 MCI_GPM_COEX_BT_NORMAL_STATUS = 0,
260 MCI_GPM_COEX_BT_CRITICAL_STATUS = 1
261 } MCI_GPM_COEX_BT_STATUS_STATE_T;
263 #define MCI_GPM_INVALID_PROFILE_HANDLE 0xff
265 typedef enum mci_gpm_coex_bt_updata_flags_op {
266 MCI_GPM_COEX_BT_FLAGS_READ = 0x00,
267 MCI_GPM_COEX_BT_FLAGS_SET = 0x01,
268 MCI_GPM_COEX_BT_FLAGS_CLEAR = 0x02
269 } MCI_GPM_COEX_BT_FLAGS_OP_T;
271 /* MCI GPM/Coex opcode/type definitions */
273 MCI_GPM_COEX_W_GPM_PAYLOAD = 1,
274 MCI_GPM_COEX_B_GPM_TYPE = 4,
275 MCI_GPM_COEX_B_GPM_OPCODE = 5,
276 /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */
277 MCI_GPM_WLAN_CAL_W_SEQUENCE = 2,
278 /* MCI_GPM_COEX_VERSION_QUERY */
279 /* MCI_GPM_COEX_VERSION_RESPONSE */
280 MCI_GPM_COEX_B_MAJOR_VERSION = 6,
281 MCI_GPM_COEX_B_MINOR_VERSION = 7,
282 /* MCI_GPM_COEX_STATUS_QUERY */
283 MCI_GPM_COEX_B_BT_BITMAP = 6,
284 MCI_GPM_COEX_B_WLAN_BITMAP = 7,
285 /* MCI_GPM_COEX_HALT_BT_GPM */
286 MCI_GPM_COEX_B_HALT_STATE = 6,
287 /* MCI_GPM_COEX_WLAN_CHANNELS */
288 MCI_GPM_COEX_B_CHANNEL_MAP = 6,
289 /* MCI_GPM_COEX_BT_PROFILE_INFO */
290 MCI_GPM_COEX_B_PROFILE_TYPE = 6,
291 MCI_GPM_COEX_B_PROFILE_LINKID = 7,
292 MCI_GPM_COEX_B_PROFILE_STATE = 8,
293 MCI_GPM_COEX_B_PROFILE_ROLE = 9,
294 MCI_GPM_COEX_B_PROFILE_RATE = 10,
295 MCI_GPM_COEX_B_PROFILE_VOTYPE = 11,
296 MCI_GPM_COEX_H_PROFILE_T = 12,
297 MCI_GPM_COEX_B_PROFILE_W = 14,
298 MCI_GPM_COEX_B_PROFILE_A = 15,
299 /* MCI_GPM_COEX_BT_STATUS_UPDATE */
300 MCI_GPM_COEX_B_STATUS_TYPE = 6,
301 MCI_GPM_COEX_B_STATUS_LINKID = 7,
302 MCI_GPM_COEX_B_STATUS_STATE = 8,
303 /* MCI_GPM_COEX_BT_UPDATE_FLAGS */
304 MCI_GPM_COEX_B_BT_FLAGS_OP = 10,
305 MCI_GPM_COEX_W_BT_FLAGS = 6
308 #define MCI_GPM_RECYCLE(_p_gpm) \
310 *(((u_int32_t *)(_p_gpm)) + MCI_GPM_COEX_W_GPM_PAYLOAD) = MCI_GPM_RSVD_PATTERN32; \
312 #define MCI_GPM_TYPE(_p_gpm) \
313 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff)
314 #define MCI_GPM_OPCODE(_p_gpm) \
315 (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff)
317 #define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type) \
319 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff; \
321 #define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode) \
323 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff; \
324 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff; \
326 #define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE)
328 #define MCI_NUM_BT_CHANNELS 79
330 #define MCI_GPM_SET_CHANNEL_BIT(_p_gpm, _bt_chan) \
332 if (_bt_chan < MCI_NUM_BT_CHANNELS) { \
333 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \
334 (_bt_chan / 8)) |= 1 << (_bt_chan & 7); \
338 #define MCI_GPM_CLR_CHANNEL_BIT(_p_gpm, _bt_chan) \
340 if (_bt_chan < MCI_NUM_BT_CHANNELS) { \
341 *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \
342 (_bt_chan / 8)) &= ~(1 << (_bt_chan & 7)); \
346 #define HAL_MCI_INTERRUPT_SW_MSG_DONE 0x00000001
347 #define HAL_MCI_INTERRUPT_CPU_INT_MSG 0x00000002
348 #define HAL_MCI_INTERRUPT_RX_CHKSUM_FAIL 0x00000004
349 #define HAL_MCI_INTERRUPT_RX_INVALID_HDR 0x00000008
350 #define HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL 0x00000010
351 #define HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL 0x00000020
352 #define HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL 0x00000080
353 #define HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL 0x00000100
354 #define HAL_MCI_INTERRUPT_RX_MSG 0x00000200
355 #define HAL_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE 0x00000400
356 #define HAL_MCI_INTERRUPT_CONT_INFO_TIMEOUT 0x80000000
357 #define HAL_MCI_INTERRUPT_MSG_FAIL_MASK ( HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL | \
358 HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL | \
359 HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL | \
360 HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL )
362 #define HAL_MCI_INTERRUPT_RX_MSG_REMOTE_RESET 0x00000001
363 #define HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL 0x00000002
364 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK 0x00000004
365 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO 0x00000008
366 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_RST 0x00000010
367 #define HAL_MCI_INTERRUPT_RX_MSG_SCHD_INFO 0x00000020
368 #define HAL_MCI_INTERRUPT_RX_MSG_CPU_INT 0x00000040
369 #define HAL_MCI_INTERRUPT_RX_MSG_GPM 0x00000100
370 #define HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO 0x00000200
371 #define HAL_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING 0x00000400
372 #define HAL_MCI_INTERRUPT_RX_MSG_SYS_WAKING 0x00000800
373 #define HAL_MCI_INTERRUPT_RX_MSG_REQ_WAKE 0x00001000
374 #define HAL_MCI_INTERRUPT_RX_MSG_MONITOR (HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \
375 HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO | \
376 HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK | \
377 HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO | \
378 HAL_MCI_INTERRUPT_RX_MSG_CONT_RST)
380 typedef enum mci_bt_state {
387 /* Type of state query */
388 typedef enum mci_state_type {
389 HAL_MCI_STATE_ENABLE,
390 HAL_MCI_STATE_INIT_GPM_OFFSET,
391 HAL_MCI_STATE_NEXT_GPM_OFFSET,
392 HAL_MCI_STATE_LAST_GPM_OFFSET,
394 HAL_MCI_STATE_SET_BT_SLEEP,
395 HAL_MCI_STATE_SET_BT_AWAKE,
396 HAL_MCI_STATE_SET_BT_CAL_START,
397 HAL_MCI_STATE_SET_BT_CAL,
398 HAL_MCI_STATE_LAST_SCHD_MSG_OFFSET,
399 HAL_MCI_STATE_REMOTE_SLEEP,
400 HAL_MCI_STATE_CONT_RSSI_POWER,
401 HAL_MCI_STATE_CONT_PRIORITY,
402 HAL_MCI_STATE_CONT_TXRX,
403 HAL_MCI_STATE_RESET_REQ_WAKE,
404 HAL_MCI_STATE_SEND_WLAN_COEX_VERSION,
405 HAL_MCI_STATE_SET_BT_COEX_VERSION,
406 HAL_MCI_STATE_SEND_WLAN_CHANNELS,
407 HAL_MCI_STATE_SEND_VERSION_QUERY,
408 HAL_MCI_STATE_SEND_STATUS_QUERY,
409 HAL_MCI_STATE_NEED_FLUSH_BT_INFO,
410 HAL_MCI_STATE_SET_CONCUR_TX_PRI,
411 HAL_MCI_STATE_RECOVER_RX,
412 HAL_MCI_STATE_NEED_FTP_STOMP,
413 HAL_MCI_STATE_NEED_TUNING,
414 HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX,
417 } HAL_MCI_STATE_TYPE;
419 #define HAL_MCI_STATE_DEBUG_REQ_BT_DEBUG 1
421 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR 0x00000002
422 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR 0x00000004
423 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD 0x00000008
424 #define HAL_MCI_BT_MCI_FLAGS_LNA_CTRL 0x00000010
425 #define HAL_MCI_BT_MCI_FLAGS_DEBUG 0x00000020
426 #define HAL_MCI_BT_MCI_FLAGS_SCHED_MSG 0x00000040
427 #define HAL_MCI_BT_MCI_FLAGS_CONT_MSG 0x00000080
428 #define HAL_MCI_BT_MCI_FLAGS_COEX_GPM 0x00000100
429 #define HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG 0x00000200
430 #define HAL_MCI_BT_MCI_FLAGS_MCI_MODE 0x00000400
431 #define HAL_MCI_BT_MCI_FLAGS_EGRET_MODE 0x00000800
432 #define HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE 0x00001000
433 #define HAL_MCI_BT_MCI_FLAGS_OTHER 0x00010000
435 #define HAL_MCI_DEFAULT_BT_MCI_FLAGS 0x00011dde
437 HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR = 1
438 HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR = 1
439 HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD = 1
440 HAL_MCI_BT_MCI_FLAGS_LNA_CTRL = 1
441 HAL_MCI_BT_MCI_FLAGS_DEBUG = 0
442 HAL_MCI_BT_MCI_FLAGS_SCHED_MSG = 1
443 HAL_MCI_BT_MCI_FLAGS_CONT_MSG = 1
444 HAL_MCI_BT_MCI_FLAGS_COEX_GPM = 1
445 HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG = 0
446 HAL_MCI_BT_MCI_FLAGS_MCI_MODE = 1
447 HAL_MCI_BT_MCI_FLAGS_EGRET_MODE = 1
448 HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE = 1
449 HAL_MCI_BT_MCI_FLAGS_OTHER = 1
452 #define HAL_MCI_TOGGLE_BT_MCI_FLAGS \
453 ( HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR | \
454 HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR | \
455 HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD | \
456 HAL_MCI_BT_MCI_FLAGS_MCI_MODE )
458 #define HAL_MCI_2G_FLAGS_CLEAR_MASK 0x00000000
459 #define HAL_MCI_2G_FLAGS_SET_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS
460 #define HAL_MCI_2G_FLAGS HAL_MCI_DEFAULT_BT_MCI_FLAGS
462 #define HAL_MCI_5G_FLAGS_CLEAR_MASK HAL_MCI_TOGGLE_BT_MCI_FLAGS
463 #define HAL_MCI_5G_FLAGS_SET_MASK 0x00000000
464 #define HAL_MCI_5G_FLAGS (HAL_MCI_DEFAULT_BT_MCI_FLAGS & \
465 ~HAL_MCI_TOGGLE_BT_MCI_FLAGS)
467 #define HAL_MCI_GPM_NOMORE 0
468 #define HAL_MCI_GPM_MORE 1
469 #define HAL_MCI_GPM_INVALID 0xffffffff
471 #define ATH_AIC_MAX_BT_CHANNEL 79
474 * Default value for Jupiter is 0x00002201
475 * Default value for Aphrodite is 0x00002282
477 #define ATH_MCI_CONFIG_CONCUR_TX 0x00000003
478 #define ATH_MCI_CONFIG_MCI_OBS_MCI 0x00000004
479 #define ATH_MCI_CONFIG_MCI_OBS_TXRX 0x00000008
480 #define ATH_MCI_CONFIG_MCI_OBS_BT 0x00000010
481 #define ATH_MCI_CONFIG_DISABLE_MCI_CAL 0x00000020
482 #define ATH_MCI_CONFIG_DISABLE_OSLA 0x00000040
483 #define ATH_MCI_CONFIG_DISABLE_FTP_STOMP 0x00000080
484 #define ATH_MCI_CONFIG_AGGR_THRESH 0x00000700
485 #define ATH_MCI_CONFIG_AGGR_THRESH_S 8
486 #define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH 0x00000800
487 #define ATH_MCI_CONFIG_CLK_DIV 0x00003000
488 #define ATH_MCI_CONFIG_CLK_DIV_S 12
489 #define ATH_MCI_CONFIG_DISABLE_TUNING 0x00004000
490 #define ATH_MCI_CONFIG_DISABLE_AIC 0x00008000
491 #define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN 0x007f0000
492 #define ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN_S 16
493 #define ATH_MCI_CONFIG_NO_QUIET_ACK 0x00800000
494 #define ATH_MCI_CONFIG_NO_QUIET_ACK_S 23
495 #define ATH_MCI_CONFIG_ANT_ARCH 0x07000000
496 #define ATH_MCI_CONFIG_ANT_ARCH_S 24
497 #define ATH_MCI_CONFIG_FORCE_QUIET_ACK 0x08000000
498 #define ATH_MCI_CONFIG_FORCE_QUIET_ACK_S 27
499 #define ATH_MCI_CONFIG_FORCE_2CHAIN_ACK 0x10000000
500 #define ATH_MCI_CONFIG_MCI_STAT_DBG 0x20000000
501 #define ATH_MCI_CONFIG_MCI_WEIGHT_DBG 0x40000000
502 #define ATH_MCI_CONFIG_DISABLE_MCI 0x80000000
504 #define ATH_MCI_CONFIG_MCI_OBS_MASK ( ATH_MCI_CONFIG_MCI_OBS_MCI | \
505 ATH_MCI_CONFIG_MCI_OBS_TXRX | \
506 ATH_MCI_CONFIG_MCI_OBS_BT )
507 #define ATH_MCI_CONFIG_MCI_OBS_GPIO 0x0000002F
509 #define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_NON_SHARED 0x00
510 #define ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED 0x01
511 #define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_NON_SHARED 0x02
512 #define ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED 0x03
513 #define ATH_MCI_ANT_ARCH_3_ANT 0x04
515 #define MCI_ANT_ARCH_PA_LNA_SHARED(c) \
516 ((MS(c, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_1_ANT_PA_LNA_SHARED) || \
517 (MS(c, ATH_MCI_CONFIG_ANT_ARCH) == ATH_MCI_ANT_ARCH_2_ANT_PA_LNA_SHARED))
519 #define ATH_MCI_CONCUR_TX_SHARED_CHN 0x01
520 #define ATH_MCI_CONCUR_TX_UNSHARED_CHN 0x02
521 #define ATH_MCI_CONCUR_TX_DEBUG 0x03