2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #ifndef _ATH_AH_DECODE_H_
22 #define _ATH_AH_DECODE_H_
24 * Register tracing support.
26 * Setting hw.ath.hal.alq=1 enables tracing of all register reads and
27 * writes to the file /tmp/ath_hal.log. The file format is a simple
28 * fixed-size array of records. When done logging set hw.ath.hal.alq=0
29 * and then decode the file with the arcode program (that is part of the
30 * HAL). If you start+stop tracing the data will be appended to an
41 OP_READ = 0, /* register read */
42 OP_WRITE = 1, /* register write */
43 OP_DEVICE = 2, /* device identification */
44 OP_MARK = 3, /* application marker */
48 AH_MARK_RESET, /* ar*Reset entry, bChannelChange */
49 AH_MARK_RESET_LINE, /* ar*_reset.c, line %d */
50 AH_MARK_RESET_DONE, /* ar*Reset exit, error code */
51 AH_MARK_CHIPRESET, /* ar*ChipReset, channel num */
52 AH_MARK_PERCAL, /* ar*PerCalibration, channel num */
53 AH_MARK_SETCHANNEL, /* ar*SetChannel, channel num */
54 AH_MARK_ANI_RESET, /* ar*AniReset, opmode */
55 AH_MARK_ANI_POLL, /* ar*AniReset, listen time */
56 AH_MARK_ANI_CONTROL, /* ar*AniReset, cmd */
57 AH_MARK_RX_CTL, /* RX DMA control */
58 AH_MARK_CHIP_POWER, /* chip power control, mode */
59 AH_MARK_CHIP_POWER_DONE, /* chip power control done, status */
63 AH_MARK_RX_CTL_PCU_START,
64 AH_MARK_RX_CTL_PCU_STOP,
65 AH_MARK_RX_CTL_DMA_START,
66 AH_MARK_RX_CTL_DMA_STOP,
67 AH_MARK_RX_CTL_DMA_STOP_ERR,
68 AH_MARK_RX_CTL_DMA_STOP_OK,
71 #endif /* _ATH_AH_DECODE_H_ */