2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #ifndef _DEV_ATH_DESC_H
21 #define _DEV_ATH_DESC_H
23 #include "opt_ah.h" /* NB: required for AH_SUPPORT_AR5416 */
26 * For now, define this for the structure definitions.
27 * Because of how the HAL / driver module currently builds,
28 * it's not very feasible to build the module without
29 * this defined. The rest of the code (eg in the driver
30 * body) can work fine with these fields being uninitialised;
31 * they'll be initialised to 0 anyway.
34 #ifndef AH_SUPPORT_AR5416
35 #define AH_SUPPORT_AR5416 1
39 * Transmit descriptor status. This structure is filled
40 * in only after the tx descriptor process method finds a
41 * ``done'' descriptor; at which point it returns something
42 * other than HAL_EINPROGRESS.
44 * Note that ts_antenna may not be valid for all h/w. It
45 * should be used only if non-zero.
47 struct ath_tx_status {
48 uint16_t ts_seqnum; /* h/w assigned sequence number */
49 uint16_t ts_tstamp; /* h/w assigned timestamp */
50 uint8_t ts_status; /* frame status, 0 => xmit ok */
51 uint8_t ts_rate; /* h/w transmit rate index */
52 int8_t ts_rssi; /* tx ack RSSI */
53 uint8_t ts_shortretry; /* # short retries */
54 uint8_t ts_longretry; /* # long retries */
55 uint8_t ts_virtcol; /* virtual collision count */
56 uint8_t ts_antenna; /* antenna information */
57 uint8_t ts_finaltsi; /* final transmit series index */
58 #ifdef AH_SUPPORT_AR5416
60 uint8_t ts_flags; /* misc flags */
61 int8_t ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */
62 int8_t ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */
63 /* #define ts_rssi ts_rssi_combined */
64 uint32_t ts_ba_low; /* blockack bitmap low */
65 uint32_t ts_ba_high; /* blockack bitmap high */
66 uint8_t ts_tid; /* TID */
67 uint32_t ts_evm0; /* evm bytes */
70 #endif /* AH_SUPPORT_AR5416 */
73 /* bits found in ts_status */
74 #define HAL_TXERR_XRETRY 0x01 /* excessive retries */
75 #define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */
76 #define HAL_TXERR_FIFO 0x04 /* fifo underrun */
77 #define HAL_TXERR_XTXOP 0x08 /* txop exceeded */
78 #define HAL_TXERR_TIMER_EXPIRED 0x10 /* Tx timer expired */
80 /* bits found in ts_flags */
81 #define HAL_TX_BA 0x01 /* Block Ack seen */
82 #define HAL_TX_AGGR 0x02 /* Aggregate */
83 #define HAL_TX_DESC_CFG_ERR 0x10 /* Error in 20/40 desc config */
84 #define HAL_TX_DATA_UNDERRUN 0x20 /* Tx buffer underrun */
85 #define HAL_TX_DELIM_UNDERRUN 0x40 /* Tx delimiter underrun */
88 * Receive descriptor status. This structure is filled
89 * in only after the rx descriptor process method finds a
90 * ``done'' descriptor; at which point it returns something
91 * other than HAL_EINPROGRESS.
93 * If rx_status is zero, then the frame was received ok;
94 * otherwise the error information is indicated and rs_phyerr
95 * contains a phy error code if HAL_RXERR_PHY is set. In general
96 * the frame contents is undefined when an error occurred thought
97 * for some errors (e.g. a decryption error), it may be meaningful.
99 * Note that the receive timestamp is expanded using the TSF to
100 * at least 15 bits (regardless of what the h/w provides directly).
101 * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to
102 * find out if the hardware is capable.
104 * rx_rssi is in units of dbm above the noise floor. This value
105 * is measured during the preamble and PLCP; i.e. with the initial
106 * 4us of detection. The noise floor is typically a consistent
107 * -96dBm absolute power in a 20MHz channel.
109 struct ath_rx_status {
110 uint16_t rs_datalen; /* rx frame length */
111 uint8_t rs_status; /* rx status, 0 => recv ok */
112 uint8_t rs_phyerr; /* phy error code */
113 int8_t rs_rssi; /* rx frame RSSI (combined for 11n) */
114 uint8_t rs_keyix; /* key cache index */
115 uint8_t rs_rate; /* h/w receive rate index */
116 uint8_t rs_more; /* more descriptors follow */
117 uint32_t rs_tstamp; /* h/w assigned timestamp */
118 uint32_t rs_antenna; /* antenna information */
119 #ifdef AH_SUPPORT_AR5416
121 int8_t rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */
122 int8_t rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */
123 uint8_t rs_isaggr; /* is part of the aggregate */
124 uint8_t rs_moreaggr; /* more frames in aggr to follow */
125 uint16_t rs_flags; /* misc flags */
126 uint8_t rs_num_delims; /* number of delims in aggr */
127 uint8_t rs_spare0; /* padding */
128 uint32_t rs_evm0; /* evm bytes */
131 uint32_t rs_evm3; /* needed for ar9300 and later */
132 uint32_t rs_evm4; /* needed for ar9300 and later */
133 #endif /* AH_SUPPORT_AR5416 */
136 /* bits found in rs_status */
137 #define HAL_RXERR_CRC 0x01 /* CRC error on frame */
138 #define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */
139 #define HAL_RXERR_FIFO 0x04 /* fifo overrun */
140 #define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */
141 #define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */
142 #define HAL_RXERR_INCOMP 0x20 /* Rx Desc processing is incomplete */
143 #define HAL_RXERR_KEYMISS 0x40 /* Key not found in keycache */
145 /* bits found in rs_flags */
146 #define HAL_RX_MORE 0x0001 /* more descriptors follow */
147 #define HAL_RX_MORE_AGGR 0x0002 /* more frames in aggr */
148 #define HAL_RX_GI 0x0004 /* full gi */
149 #define HAL_RX_2040 0x0008 /* 40 Mhz */
150 #define HAL_RX_DELIM_CRC_PRE 0x0010 /* crc error in delimiter pre */
151 #define HAL_RX_DELIM_CRC_POST 0x0020 /* crc error in delim after */
152 #define HAL_RX_DECRYPT_BUSY 0x0040 /* decrypt was too slow */
153 #define HAL_RX_HI_RX_CHAIN 0x0080 /* SM power save: hi Rx chain control */
154 #define HAL_RX_IS_APSD 0x0100 /* Is ASPD trigger frame */
157 HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */
158 HAL_PHYERR_TIMING = 1, /* Timing error */
159 HAL_PHYERR_PARITY = 2, /* Illegal parity */
160 HAL_PHYERR_RATE = 3, /* Illegal rate */
161 HAL_PHYERR_LENGTH = 4, /* Illegal length */
162 HAL_PHYERR_RADAR = 5, /* Radar detect */
163 HAL_PHYERR_SERVICE = 6, /* Illegal service */
164 HAL_PHYERR_TOR = 7, /* Transmit override receive */
165 /* NB: these are specific to the 5212 and later */
166 HAL_PHYERR_OFDM_TIMING = 17, /* */
167 HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */
168 HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */
169 HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */
170 HAL_PHYERR_OFDM_POWER_DROP = 21, /* */
171 HAL_PHYERR_OFDM_SERVICE = 22, /* */
172 HAL_PHYERR_OFDM_RESTART = 23, /* */
173 HAL_PHYERR_FALSE_RADAR_EXT = 24, /* */
174 HAL_PHYERR_CCK_TIMING = 25, /* */
175 HAL_PHYERR_CCK_HEADER_CRC = 26, /* */
176 HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */
177 HAL_PHYERR_CCK_SERVICE = 30, /* */
178 HAL_PHYERR_CCK_RESTART = 31, /* */
179 HAL_PHYERR_CCK_LENGTH_ILLEGAL = 32, /* */
180 HAL_PHYERR_CCK_POWER_DROP = 33, /* */
181 /* AR5416 and later */
182 HAL_PHYERR_HT_CRC_ERROR = 34, /* */
183 HAL_PHYERR_HT_LENGTH_ILLEGAL = 35, /* */
184 HAL_PHYERR_HT_RATE_ILLEGAL = 36, /* */
186 HAL_PHYERR_SPECTRAL = 38,
189 /* value found in rs_keyix to mark invalid entries */
190 #define HAL_RXKEYIX_INVALID ((uint8_t) -1)
191 /* value used to specify no encryption key for xmit */
192 #define HAL_TXKEYIX_INVALID ((u_int) -1)
194 /* XXX rs_antenna definitions */
197 * Definitions for the software frame/packet descriptors used by
198 * the Atheros HAL. This definition obscures hardware-specific
199 * details from the driver. Drivers are expected to fillin the
200 * portions of a descriptor that are not opaque then use HAL calls
201 * to complete the work. Status for completed frames is returned
202 * in a device-independent format.
204 #ifdef AH_SUPPORT_AR5416
205 #define HAL_DESC_HW_SIZE 20
207 #define HAL_DESC_HW_SIZE 4
208 #endif /* AH_SUPPORT_AR5416 */
212 * The following definitions are passed directly
213 * the hardware and managed by the HAL. Drivers
214 * should not touch those elements marked opaque.
216 uint32_t ds_link; /* phys address of next descriptor */
217 uint32_t ds_data; /* phys address of data buffer */
218 uint32_t ds_ctl0; /* opaque DMA control 0 */
219 uint32_t ds_ctl1; /* opaque DMA control 1 */
220 uint32_t ds_hw[HAL_DESC_HW_SIZE]; /* opaque h/w region */
223 struct ath_desc_status {
225 struct ath_tx_status tx;/* xmit status */
226 struct ath_rx_status rx;/* recv status */
230 #define ds_txstat ds_us.tx
231 #define ds_rxstat ds_us.rx
233 /* flags passed to tx descriptor setup methods */
234 /* This is a uint16_t field in ath_buf, just be warned! */
235 #define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */
236 #define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */
237 #define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */
238 #define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */
239 #define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */
240 #define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */
241 /* NB: this only affects frame, not any RTS/CTS */
242 #define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */
243 #define HAL_TXDESC_EXT_ONLY 0x0080 /* send on ext channel only (11n) */
244 #define HAL_TXDESC_EXT_AND_CTL 0x0100 /* send on ext + ctl channels (11n) */
245 #define HAL_TXDESC_VMF 0x0200 /* virtual more frag */
247 /* flags passed to rx descriptor setup methods */
248 #define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */
249 #endif /* _DEV_ATH_DESC_H */