sys/dev/ath/ath_hal/ah_eeprom_v4k.h

   1 /*-
   2  * SPDX-License-Identifier: ISC
   3  *
   4  * Copyright (c) 2009 Rui Paulo <rpaulo@FreeBSD.org>
   5  * Copyright (c) 2008 Sam Leffler, Errno Consulting
   6  * Copyright (c) 2008 Atheros Communications, Inc.
   7  *
   8  * Permission to use, copy, modify, and/or distribute this software for any
   9  * purpose with or without fee is hereby granted, provided that the above
  10  * copyright notice and this permission notice appear in all copies.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  19  *
  20  * $FreeBSD$
  21  */
  22 #ifndef _AH_EEPROM_V4K_H_
  23 #define _AH_EEPROM_V4K_H_
  24
  25 #include "ah_eeprom.h"
  26 #include "ah_eeprom_v14.h"
  27
  28 #if     _BYTE_ORDER == _BIG_ENDIAN
  29 #define __BIG_ENDIAN_BITFIELD
  30 #endif
  31
  32 #define AR9285_RDEXT_DEFAULT    0x1F
  33
  34 #define AR5416_4K_EEP_PD_GAIN_BOUNDARY_DEFAULT  58
  35
  36 #undef owl_eep_start_loc
  37 #ifdef __LINUX_ARM_ARCH__ /* AP71 */
  38 #define owl_eep_start_loc               0
  39 #else
  40 #define owl_eep_start_loc               64
  41 #endif
  42
  43 // 16-bit offset location start of calibration struct
  44 #define AR5416_4K_EEP_START_LOC         64
  45 #define AR5416_4K_NUM_2G_CAL_PIERS      3
  46 #define AR5416_4K_NUM_2G_CCK_TARGET_POWERS 3
  47 #define AR5416_4K_NUM_2G_20_TARGET_POWERS  3
  48 #define AR5416_4K_NUM_2G_40_TARGET_POWERS  3
  49 #define AR5416_4K_NUM_CTLS              12
  50 #define AR5416_4K_NUM_BAND_EDGES        4
  51 #define AR5416_4K_NUM_PD_GAINS          2
  52 #define AR5416_4K_MAX_CHAINS            1
  53
  54 /*
  55  * NB: The format in EEPROM has words 0 and 2 swapped (i.e. version
  56  * and length are swapped).  We reverse their position after reading
  57  * the data into host memory so the version field is at the same
  58  * offset as in previous EEPROM layouts.  This makes utilities that
  59  * inspect the EEPROM contents work without looking at the PCI device
  60  * id which may or may not be reliable.
  61  */
  62 typedef struct BaseEepHeader4k {
  63         uint16_t        version;        /* NB: length in EEPROM */
  64         uint16_t        checksum;
  65         uint16_t        length;         /* NB: version in EEPROM */
  66         uint8_t         opCapFlags;
  67         uint8_t         eepMisc;
  68         uint16_t        regDmn[2];
  69         uint8_t         macAddr[6];
  70         uint8_t         rxMask;
  71         uint8_t         txMask;
  72         uint16_t        rfSilent;
  73         uint16_t        blueToothOptions;
  74         uint16_t        deviceCap;
  75         uint32_t        binBuildNumber;
  76         uint8_t         deviceType;
  77         uint8_t         txGainType;     /* high power tx gain table support */
  78 } __packed BASE_EEP4K_HEADER; // 32 B
  79
  80 typedef struct ModalEepHeader4k {
  81         uint32_t        antCtrlChain[AR5416_4K_MAX_CHAINS];     // 4
  82         uint32_t        antCtrlCommon;                          // 4
  83         int8_t          antennaGainCh[AR5416_4K_MAX_CHAINS];    // 1
  84         uint8_t         switchSettling;                         // 1
  85         uint8_t         txRxAttenCh[AR5416_4K_MAX_CHAINS];      // 1
  86         uint8_t         rxTxMarginCh[AR5416_4K_MAX_CHAINS];     // 1
  87         uint8_t         adcDesiredSize;                         // 1
  88         int8_t          pgaDesiredSize;                         // 1
  89         uint8_t         xlnaGainCh[AR5416_4K_MAX_CHAINS];       // 1
  90         uint8_t         txEndToXpaOff;                          // 1
  91         uint8_t         txEndToRxOn;                            // 1
  92         uint8_t         txFrameToXpaOn;                         // 1
  93         uint8_t         thresh62;                               // 1
  94         uint8_t         noiseFloorThreshCh[AR5416_4K_MAX_CHAINS];       // 1
  95         uint8_t         xpdGain;                                // 1
  96         uint8_t         xpd;                                    // 1
  97         int8_t          iqCalICh[AR5416_4K_MAX_CHAINS];         // 1
  98         int8_t          iqCalQCh[AR5416_4K_MAX_CHAINS];         // 1
  99
 100         uint8_t         pdGainOverlap;                          // 1
 101
 102 #ifdef __BIG_ENDIAN_BITFIELD
 103         uint8_t         ob_1:4, ob_0:4;                         // 1
 104         uint8_t         db1_1:4, db1_0:4;                       // 1
 105 #else
 106         uint8_t         ob_0:4, ob_1:4;
 107         uint8_t         db1_0:4, db1_1:4;
 108 #endif
 109
 110         uint8_t         xpaBiasLvl;                             // 1
 111         uint8_t         txFrameToDataStart;                     // 1
 112         uint8_t         txFrameToPaOn;                          // 1
 113         uint8_t         ht40PowerIncForPdadc;                   // 1
 114         uint8_t         bswAtten[AR5416_4K_MAX_CHAINS];         // 1
 115         uint8_t         bswMargin[AR5416_4K_MAX_CHAINS];        // 1
 116         uint8_t         swSettleHt40;                           // 1
 117         uint8_t         xatten2Db[AR5416_4K_MAX_CHAINS];        // 1
 118         uint8_t         xatten2Margin[AR5416_4K_MAX_CHAINS];    // 1
 119
 120 #ifdef __BIG_ENDIAN_BITFIELD
 121         uint8_t         db2_1:4, db2_0:4;                       // 1
 122 #else
 123         uint8_t         db2_0:4, db2_1:4;                       // 1
 124 #endif
 125
 126         uint8_t         version;                                // 1
 127
 128 #ifdef __BIG_ENDIAN_BITFIELD
 129         uint8_t         ob_3:4, ob_2:4;                         // 1
 130         uint8_t         antdiv_ctl1:4, ob_4:4;                  // 1
 131         uint8_t         db1_3:4, db1_2:4;                       // 1
 132         uint8_t         antdiv_ctl2:4, db1_4:4;                 // 1
 133         uint8_t         db2_2:4, db2_3:4;                       // 1
 134         uint8_t         reserved:4, db2_4:4;                    // 1
 135 #else
 136         uint8_t         ob_2:4, ob_3:4;
 137         uint8_t         ob_4:4, antdiv_ctl1:4;
 138         uint8_t         db1_2:4, db1_3:4;
 139         uint8_t         db1_4:4, antdiv_ctl2:4;
 140         uint8_t         db2_2:4, db2_3:4;
 141         uint8_t         db2_4:4, reserved:4;
 142 #endif
 143         uint8_t         tx_diversity;
 144         uint8_t         flc_pwr_thresh;
 145         uint8_t         bb_scale_smrt_antenna;
 146 #define EEP_4K_BB_DESIRED_SCALE_MASK    0x1f
 147         uint8_t         futureModal[1];
 148
 149         SPUR_CHAN spurChans[AR5416_EEPROM_MODAL_SPURS]; // 20 B
 150 } __packed MODAL_EEP4K_HEADER;                          // == 68 B
 151
 152 typedef struct CalCtlData4k {
 153         CAL_CTL_EDGES           ctlEdges[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_BAND_EDGES];
 154 } __packed CAL_CTL_DATA_4K;
 155
 156 typedef struct calDataPerFreq4k {
 157         uint8_t         pwrPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 158         uint8_t         vpdPdg[AR5416_4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
 159 } __packed CAL_DATA_PER_FREQ_4K;
 160
 161 struct ar5416eeprom_4k {
 162         BASE_EEP4K_HEADER       baseEepHeader;         // 32 B
 163         uint8_t                 custData[20];          // 20 B
 164         MODAL_EEP4K_HEADER      modalHeader;           // 68 B
 165         uint8_t                 calFreqPier2G[AR5416_4K_NUM_2G_CAL_PIERS];
 166         CAL_DATA_PER_FREQ_4K    calPierData2G[AR5416_4K_MAX_CHAINS][AR5416_4K_NUM_2G_CAL_PIERS];
 167         CAL_TARGET_POWER_LEG    calTargetPowerCck[AR5416_4K_NUM_2G_CCK_TARGET_POWERS];
 168         CAL_TARGET_POWER_LEG    calTargetPower2G[AR5416_4K_NUM_2G_20_TARGET_POWERS];
 169         CAL_TARGET_POWER_HT     calTargetPower2GHT20[AR5416_4K_NUM_2G_20_TARGET_POWERS];
 170         CAL_TARGET_POWER_HT     calTargetPower2GHT40[AR5416_4K_NUM_2G_40_TARGET_POWERS];
 171         uint8_t                 ctlIndex[AR5416_4K_NUM_CTLS];
 172         CAL_CTL_DATA_4K         ctlData[AR5416_4K_NUM_CTLS];
 173         uint8_t                 padding;
 174 } __packed;
 175
 176 typedef struct {
 177         struct ar5416eeprom_4k ee_base;
 178 #define NUM_EDGES        8
 179         uint16_t        ee_numCtls;
 180         RD_EDGES_POWER  ee_rdEdgesPower[NUM_EDGES*AR5416_4K_NUM_CTLS];
 181         /* XXX these are dynamically calculated for use by shared code */
 182         int8_t          ee_antennaGainMax;
 183 } HAL_EEPROM_v4k;
 184 #endif /* _AH_EEPROM_V4K_H_ */