2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #ifndef _ATH_AH_INTERAL_H_
20 #define _ATH_AH_INTERAL_H_
22 * Atheros Device Hardware Access Layer (HAL).
24 * Internal definitions.
27 #define AH_MIN(a,b) ((a)<(b)?(a):(b))
28 #define AH_MAX(a,b) ((a)>(b)?(a):(b))
30 #include <net80211/_ieee80211.h>
31 #include "opt_ah.h" /* needed for AH_SUPPORT_AR5416 */
33 #ifndef AH_SUPPORT_AR5416
34 #define AH_SUPPORT_AR5416 1
38 #define NBBY 8 /* number of bits/byte */
42 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y)) /* to any y */
45 #define howmany(x, y) (((x)+((y)-1))/(y))
49 #define offsetof(type, field) ((size_t)(&((type *)0)->field))
53 uint16_t start; /* first register */
54 uint16_t end; /* ending register or zero */
58 uint32_t addr; /* regiser address/offset */
59 uint32_t value; /* value to write */
63 * Transmit power scale factor.
65 * NB: This is not public because we want to discourage the use of
66 * scaling; folks should use the tx power limit interface.
69 HAL_TP_SCALE_MAX = 0, /* no scaling (default) */
70 HAL_TP_SCALE_50 = 1, /* 50% of max (-3 dBm) */
71 HAL_TP_SCALE_25 = 2, /* 25% of max (-6 dBm) */
72 HAL_TP_SCALE_12 = 3, /* 12% of max (-9 dBm) */
73 HAL_TP_SCALE_MIN = 4, /* min, but still on */
77 HAL_CAP_RADAR = 0, /* Radar capability */
78 HAL_CAP_AR = 1, /* AR capability */
82 * Enable/disable strong signal fast diversity
84 #define HAL_CAP_STRONG_DIV 2
87 * Each chip or class of chips registers to offer support.
91 const char *(*probe)(uint16_t vendorid, uint16_t devid);
92 struct ath_hal *(*attach)(uint16_t devid, HAL_SOFTC,
93 HAL_BUS_TAG, HAL_BUS_HANDLE, uint16_t *eepromdata,
97 #define AH_CHIP(_name, _probe, _attach) \
98 static struct ath_hal_chip _name##_chip = { \
103 OS_DATA_SET(ah_chips, _name##_chip)
107 * Each RF backend registers to offer support; this is mostly
108 * used by multi-chip 5212 solutions. Single-chip solutions
109 * have a fixed idea about which RF to use.
113 HAL_BOOL (*probe)(struct ath_hal *ah);
114 HAL_BOOL (*attach)(struct ath_hal *ah, HAL_STATUS *ecode);
117 #define AH_RF(_name, _probe, _attach) \
118 static struct ath_hal_rf _name##_rf = { \
119 .name = __STRING(_name), \
123 OS_DATA_SET(ah_rfs, _name##_rf)
126 struct ath_hal_rf *ath_hal_rfprobe(struct ath_hal *ah, HAL_STATUS *ecode);
129 * Maximum number of internal channels. Entries are per unique
130 * frequency so this might be need to be increased to handle all
131 * usage cases; typically no more than 32 are really needed but
132 * dynamically allocating the data structures is a bit painful
136 #define AH_MAXCHAN 96
139 #define HAL_NF_CAL_HIST_LEN_FULL 5
140 #define HAL_NF_CAL_HIST_LEN_SMALL 1
141 #define HAL_NUM_NF_READINGS 6 /* 3 chains * (ctl + ext) */
142 #define HAL_NF_LOAD_DELAY 1000
145 * PER_CHAN doesn't work for now, as it looks like the device layer
146 * has to pre-populate the per-channel list with nominal values.
148 //#define ATH_NF_PER_CHAN 1
152 int8_t invalidNFcount; /* TO DO: REMOVE THIS! */
153 int16_t priv_nf[HAL_NUM_NF_READINGS];
158 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_FULL][HAL_NUM_NF_READINGS];
159 } HAL_NFCAL_HIST_FULL;
163 int16_t nf_cal_buffer[HAL_NF_CAL_HIST_LEN_SMALL][HAL_NUM_NF_READINGS];
164 } HAL_NFCAL_HIST_SMALL;
166 #ifdef ATH_NF_PER_CHAN
167 typedef HAL_NFCAL_HIST_FULL HAL_CHAN_NFCAL_HIST;
168 #define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (ichan ? &ichan->nf_cal_hist: NULL)
170 typedef HAL_NFCAL_HIST_SMALL HAL_CHAN_NFCAL_HIST;
171 #define AH_HOME_CHAN_NFCAL_HIST(ah, ichan) (&AH_PRIVATE(ah)->nf_cal_hist)
172 #endif /* ATH_NF_PER_CHAN */
175 * Internal per-channel state. These are found
176 * using ic_devdata in the ieee80211_channel.
179 uint16_t channel; /* h/w frequency, NB: may be mapped */
181 #define CHANNEL_IQVALID 0x01 /* IQ calibration valid */
182 #define CHANNEL_ANI_INIT 0x02 /* ANI state initialized */
183 #define CHANNEL_ANI_SETUP 0x04 /* ANI state setup */
184 #define CHANNEL_MIMO_NF_VALID 0x04 /* Mimo NF values are valid */
185 uint8_t calValid; /* bitmask of cal types */
188 int16_t rawNoiseFloor;
189 int16_t noiseFloorAdjust;
190 #ifdef AH_SUPPORT_AR5416
191 int16_t noiseFloorCtl[AH_MAX_CHAINS];
192 int16_t noiseFloorExt[AH_MAX_CHAINS];
193 #endif /* AH_SUPPORT_AR5416 */
194 uint16_t mainSpur; /* cached spur value for this channel */
196 /*XXX TODO: make these part of privFlags */
197 uint8_t paprd_done:1, /* 1: PAPRD DONE, 0: PAPRD Cal not done */
198 paprd_table_write_done:1; /* 1: DONE, 0: Cal data write not done */
199 int one_time_cals_done;
200 HAL_CHAN_NFCAL_HIST nf_cal_hist;
201 } HAL_CHANNEL_INTERNAL;
203 /* channel requires noise floor check */
204 #define CHANNEL_NFCREQUIRED IEEE80211_CHAN_PRIV0
206 /* all full-width channels */
207 #define IEEE80211_CHAN_ALLFULL \
208 (IEEE80211_CHAN_ALL - (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
209 #define IEEE80211_CHAN_ALLTURBOFULL \
210 (IEEE80211_CHAN_ALLTURBO - \
211 (IEEE80211_CHAN_HALF | IEEE80211_CHAN_QUARTER))
214 uint32_t halChanSpreadSupport : 1,
215 halSleepAfterBeaconBroken : 1,
216 halCompressSupport : 1,
218 halFastFramesSupport : 1,
219 halChapTuningSupport : 1,
220 halTurboGSupport : 1,
221 halTurboPrimeSupport : 1,
222 halMicAesCcmSupport : 1,
223 halMicCkipSupport : 1,
224 halMicTkipSupport : 1,
225 halTkipMicTxRxKeySupport : 1,
226 halCipherAesCcmSupport : 1,
227 halCipherCkipSupport : 1,
228 halCipherTkipSupport : 1,
231 halBssIdMaskSupport : 1,
232 halMcastKeySrchSupport : 1,
233 halTsfAddSupport : 1,
235 halChanQuarterRate : 1,
237 halHTSGI20Support : 1,
238 halRfSilentSupport : 1,
239 halHwPhyCounterSupport : 1,
241 halWowMatchPatternExact : 1,
242 halAutoSleepSupport : 1,
243 halFastCCSupport : 1,
244 halBtCoexSupport : 1;
245 uint32_t halRxStbcSupport : 1,
246 halTxStbcSupport : 1,
249 halRifsRxSupport : 1,
250 halRifsTxSupport : 1,
251 hal4AddrAggrSupport : 1,
252 halExtChanDfsSupport : 1,
253 halUseCombinedRadarRssi : 1,
254 halForcePpmSupport : 1,
255 halEnhancedPmSupport : 1,
256 halEnhancedDfsSupport : 1,
257 halMbssidAggrSupport : 1,
258 halBssidMatchSupport : 1,
259 hal4kbSplitTransSupport : 1,
260 halHasRxSelfLinkedTail : 1,
261 halSupportsFastClock5GHz : 1,
262 halHasLongRxDescTsf : 1,
264 halSerialiseRegWar : 1,
266 halRxTxAbortSupport : 1,
268 halHasUapsdSupport : 1,
269 halWpsPushButtonSupport : 1,
270 halBtCoexApsmWar : 1,
271 halGenTimerSupport : 1,
273 halHwBeaconProcSupport : 1,
274 halEnhancedDmaSupport : 1;
275 uint32_t halIsrRacSupport : 1,
277 halIntrMitigation : 1,
279 halAntDivCombSupport : 1,
280 halAntDivCombSupportOrg : 1,
281 halRadioRetentionSupport : 1;
283 uint32_t halWirelessModes;
284 uint16_t halTotalQueues;
285 uint16_t halKeyCacheSize;
286 uint16_t halLow5GhzChan, halHigh5GhzChan;
287 uint16_t halLow2GhzChan, halHigh2GhzChan;
288 int halTstampPrecision;
290 uint8_t halTxChainMask;
291 uint8_t halRxChainMask;
292 uint8_t halNumGpioPins;
293 uint8_t halNumAntCfg2GHz;
294 uint8_t halNumAntCfg5GHz;
295 uint32_t halIntrMask;
296 uint8_t halTxStreams;
297 uint8_t halRxStreams;
298 HAL_MFP_OPT_T halMfpSupport;
300 /* AR9300 HAL porting capabilities */
301 int hal_paprd_enabled;
302 int hal_pcie_lcr_offset;
303 int hal_pcie_lcr_extsync_en;
308 int halRxHpFifoDepth;
309 int halRxLpFifoDepth;
310 uint32_t halRegCap; /* XXX needed? */
312 int hal_ani_poll_interval;
313 int hal_channel_switch_time_usec;
319 * Definitions for ah_flags in ath_hal_private
321 #define AH_USE_EEPROM 0x1
322 #define AH_IS_HB63 0x2
325 * The ``private area'' follows immediately after the ``public area''
326 * in the data structure returned by ath_hal_attach. Private data are
327 * used by device-independent code such as the regulatory domain support.
328 * In general, code within the HAL should never depend on data in the
329 * public area. Instead any public data needed internally should be
332 * When declaring a device-specific ath_hal data structure this structure
333 * is assumed to at the front; e.g.
335 * struct ath_hal_5212 {
336 * struct ath_hal_private ah_priv;
340 * It might be better to manage the method pointers in this structure
341 * using an indirect pointer to a read-only data structure but this would
342 * disallow class-style method overriding.
344 struct ath_hal_private {
345 struct ath_hal h; /* public area */
347 /* NB: all methods go first to simplify initialization */
348 HAL_BOOL (*ah_getChannelEdges)(struct ath_hal*,
349 uint16_t channelFlags,
350 uint16_t *lowChannel, uint16_t *highChannel);
351 u_int (*ah_getWirelessModes)(struct ath_hal*);
352 HAL_BOOL (*ah_eepromRead)(struct ath_hal *, u_int off,
354 HAL_BOOL (*ah_eepromWrite)(struct ath_hal *, u_int off,
356 HAL_BOOL (*ah_getChipPowerLimits)(struct ath_hal *,
357 struct ieee80211_channel *);
358 int16_t (*ah_getNfAdjust)(struct ath_hal *,
359 const HAL_CHANNEL_INTERNAL*);
360 void (*ah_getNoiseFloor)(struct ath_hal *,
363 void *ah_eeprom; /* opaque EEPROM state */
364 uint16_t ah_eeversion; /* EEPROM version */
365 void (*ah_eepromDetach)(struct ath_hal *);
366 HAL_STATUS (*ah_eepromGet)(struct ath_hal *, int, void *);
367 HAL_STATUS (*ah_eepromSet)(struct ath_hal *, int, int);
368 uint16_t (*ah_getSpurChan)(struct ath_hal *, int, HAL_BOOL);
369 HAL_BOOL (*ah_eepromDiag)(struct ath_hal *, int request,
370 const void *args, uint32_t argsize,
371 void **result, uint32_t *resultsize);
374 * Device revision information.
376 uint16_t ah_devid; /* PCI device ID */
377 uint16_t ah_subvendorid; /* PCI subvendor ID */
378 uint32_t ah_macVersion; /* MAC version id */
379 uint16_t ah_macRev; /* MAC revision */
380 uint16_t ah_phyRev; /* PHY revision */
381 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
382 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
383 uint32_t ah_flags; /* misc flags */
384 uint8_t ah_ispcie; /* PCIE, special treatment */
385 uint8_t ah_devType; /* card type - CB, PCI, PCIe */
387 HAL_OPMODE ah_opmode; /* operating mode from reset */
388 const struct ieee80211_channel *ah_curchan;/* operating channel */
389 HAL_CAPABILITIES ah_caps; /* device capabilities */
390 uint32_t ah_diagreg; /* user-specified AR_DIAG_SW */
391 int16_t ah_powerLimit; /* tx power cap */
392 uint16_t ah_maxPowerLevel; /* calculated max tx power */
393 u_int ah_tpScale; /* tx power scale factor */
394 uint32_t ah_11nCompat; /* 11n compat controls */
397 * State for regulatory domain handling.
399 HAL_REG_DOMAIN ah_currentRD; /* EEPROM regulatory domain */
400 HAL_REG_DOMAIN ah_currentRDext; /* EEPROM extended regdomain flags */
401 HAL_DFS_DOMAIN ah_dfsDomain; /* current DFS domain */
402 HAL_CHANNEL_INTERNAL ah_channels[AH_MAXCHAN]; /* private chan state */
403 u_int ah_nchan; /* valid items in ah_channels */
404 const struct regDomain *ah_rd2GHz; /* reg state for 2G band */
405 const struct regDomain *ah_rd5GHz; /* reg state for 5G band */
407 uint8_t ah_coverageClass; /* coverage class */
409 * RF Silent handling; setup according to the EEPROM.
411 uint16_t ah_rfsilent; /* GPIO pin + polarity */
412 HAL_BOOL ah_rfkillEnabled; /* enable/disable RfKill */
414 * Diagnostic support for discriminating HIUERR reports.
416 uint32_t ah_fatalState[6]; /* AR_ISR+shadow regs */
417 int ah_rxornIsFatal; /* how to treat HAL_INT_RXORN */
419 #ifndef ATH_NF_PER_CHAN
420 HAL_NFCAL_HIST_FULL nf_cal_hist;
421 #endif /* ! ATH_NF_PER_CHAN */
424 #define AH_PRIVATE(_ah) ((struct ath_hal_private *)(_ah))
426 #define ath_hal_getChannelEdges(_ah, _cf, _lc, _hc) \
427 AH_PRIVATE(_ah)->ah_getChannelEdges(_ah, _cf, _lc, _hc)
428 #define ath_hal_getWirelessModes(_ah) \
429 AH_PRIVATE(_ah)->ah_getWirelessModes(_ah)
430 #define ath_hal_eepromRead(_ah, _off, _data) \
431 AH_PRIVATE(_ah)->ah_eepromRead(_ah, _off, _data)
432 #define ath_hal_eepromWrite(_ah, _off, _data) \
433 AH_PRIVATE(_ah)->ah_eepromWrite(_ah, _off, _data)
434 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
435 (_ah)->ah_gpioCfgOutput(_ah, _gpio, _type)
436 #define ath_hal_gpioCfgInput(_ah, _gpio) \
437 (_ah)->ah_gpioCfgInput(_ah, _gpio)
438 #define ath_hal_gpioGet(_ah, _gpio) \
439 (_ah)->ah_gpioGet(_ah, _gpio)
440 #define ath_hal_gpioSet(_ah, _gpio, _val) \
441 (_ah)->ah_gpioSet(_ah, _gpio, _val)
442 #define ath_hal_gpioSetIntr(_ah, _gpio, _ilevel) \
443 (_ah)->ah_gpioSetIntr(_ah, _gpio, _ilevel)
444 #define ath_hal_getpowerlimits(_ah, _chan) \
445 AH_PRIVATE(_ah)->ah_getChipPowerLimits(_ah, _chan)
446 #define ath_hal_getNfAdjust(_ah, _c) \
447 AH_PRIVATE(_ah)->ah_getNfAdjust(_ah, _c)
448 #define ath_hal_getNoiseFloor(_ah, _nfArray) \
449 AH_PRIVATE(_ah)->ah_getNoiseFloor(_ah, _nfArray)
450 #define ath_hal_configPCIE(_ah, _reset, _poweroff) \
451 (_ah)->ah_configPCIE(_ah, _reset, _poweroff)
452 #define ath_hal_disablePCIE(_ah) \
453 (_ah)->ah_disablePCIE(_ah)
454 #define ath_hal_setInterrupts(_ah, _mask) \
455 (_ah)->ah_setInterrupts(_ah, _mask)
457 #define ath_hal_isrfkillenabled(_ah) \
458 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, AH_NULL) == HAL_OK)
459 #define ath_hal_enable_rfkill(_ah, _v) \
460 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _v, AH_NULL)
461 #define ath_hal_hasrfkill_int(_ah) \
462 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 3, AH_NULL) == HAL_OK)
464 #define ath_hal_eepromDetach(_ah) do { \
465 if (AH_PRIVATE(_ah)->ah_eepromDetach != AH_NULL) \
466 AH_PRIVATE(_ah)->ah_eepromDetach(_ah); \
468 #define ath_hal_eepromGet(_ah, _param, _val) \
469 AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, _val)
470 #define ath_hal_eepromSet(_ah, _param, _val) \
471 AH_PRIVATE(_ah)->ah_eepromSet(_ah, _param, _val)
472 #define ath_hal_eepromGetFlag(_ah, _param) \
473 (AH_PRIVATE(_ah)->ah_eepromGet(_ah, _param, AH_NULL) == HAL_OK)
474 #define ath_hal_getSpurChan(_ah, _ix, _is2G) \
475 AH_PRIVATE(_ah)->ah_getSpurChan(_ah, _ix, _is2G)
476 #define ath_hal_eepromDiag(_ah, _request, _a, _asize, _r, _rsize) \
477 AH_PRIVATE(_ah)->ah_eepromDiag(_ah, _request, _a, _asize, _r, _rsize)
479 #ifndef _NET_IF_IEEE80211_H_
481 * Stuff that would naturally come from _ieee80211.h
483 #define IEEE80211_ADDR_LEN 6
485 #define IEEE80211_WEP_IVLEN 3 /* 24bit */
486 #define IEEE80211_WEP_KIDLEN 1 /* 1 octet */
487 #define IEEE80211_WEP_CRCLEN 4 /* CRC-32 */
489 #define IEEE80211_CRC_LEN 4
491 #define IEEE80211_MAX_LEN (2300 + IEEE80211_CRC_LEN + \
492 (IEEE80211_WEP_IVLEN + IEEE80211_WEP_KIDLEN + IEEE80211_WEP_CRCLEN))
493 #endif /* _NET_IF_IEEE80211_H_ */
495 #define HAL_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001
498 #define INIT_CWMIN 15
499 #define INIT_CWMIN_11B 31
500 #define INIT_CWMAX 1023
501 #define INIT_SH_RETRY 10
502 #define INIT_LG_RETRY 10
503 #define INIT_SSH_RETRY 32
504 #define INIT_SLG_RETRY 32
507 uint32_t tqi_ver; /* HAL TXQ verson */
508 HAL_TX_QUEUE tqi_type; /* hw queue type*/
509 HAL_TX_QUEUE_SUBTYPE tqi_subtype; /* queue subtype, if applicable */
510 HAL_TX_QUEUE_FLAGS tqi_qflags; /* queue flags */
511 uint32_t tqi_priority;
512 uint32_t tqi_aifs; /* aifs */
513 uint32_t tqi_cwmin; /* cwMin */
514 uint32_t tqi_cwmax; /* cwMax */
515 uint16_t tqi_shretry; /* frame short retry limit */
516 uint16_t tqi_lgretry; /* frame long retry limit */
517 uint32_t tqi_cbrPeriod;
518 uint32_t tqi_cbrOverflowLimit;
519 uint32_t tqi_burstTime;
520 uint32_t tqi_readyTime;
521 uint32_t tqi_physCompBuf;
522 uint32_t tqi_intFlags; /* flags for internal use */
525 extern HAL_BOOL ath_hal_setTxQProps(struct ath_hal *ah,
526 HAL_TX_QUEUE_INFO *qi, const HAL_TXQ_INFO *qInfo);
527 extern HAL_BOOL ath_hal_getTxQProps(struct ath_hal *ah,
528 HAL_TXQ_INFO *qInfo, const HAL_TX_QUEUE_INFO *qi);
530 #define HAL_SPUR_VAL_MASK 0x3FFF
531 #define HAL_SPUR_CHAN_WIDTH 87
532 #define HAL_BIN_WIDTH_BASE_100HZ 3125
533 #define HAL_BIN_WIDTH_TURBO_100HZ 6250
534 #define HAL_MAX_BINS_ALLOWED 28
536 #define IS_CHAN_5GHZ(_c) ((_c)->channel > 4900)
537 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
539 #define IS_CHAN_IN_PUBLIC_SAFETY_BAND(_c) ((_c) > 4940 && (_c) < 4990)
542 * Deduce if the host cpu has big- or litt-endian byte order.
544 static __inline__ int
552 return (u.c[0] == 0);
555 /* unalligned little endian access */
556 #define LE_READ_2(p) \
558 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8)))
559 #define LE_READ_4(p) \
561 ((((const uint8_t *)(p))[0] ) | (((const uint8_t *)(p))[1]<< 8) |\
562 (((const uint8_t *)(p))[2]<<16) | (((const uint8_t *)(p))[3]<<24)))
565 * Register manipulation macros that expect bit field defines
566 * to follow the convention that an _S suffix is appended for
567 * a shift count, while the field mask has no suffix.
569 #define SM(_v, _f) (((_v) << _f##_S) & (_f))
570 #define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
571 #define OS_REG_RMW(_a, _r, _set, _clr) \
572 OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) & ~(_clr)) | (_set))
573 #define OS_REG_RMW_FIELD(_a, _r, _f, _v) \
574 OS_REG_WRITE(_a, _r, \
575 (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f)))
576 #define OS_REG_SET_BIT(_a, _r, _f) \
577 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) | (_f))
578 #define OS_REG_CLR_BIT(_a, _r, _f) \
579 OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))
580 #define OS_REG_IS_BIT_SET(_a, _r, _f) \
581 ((OS_REG_READ(_a, _r) & (_f)) != 0)
582 #define OS_REG_RMW_FIELD_ALT(_a, _r, _f, _v) \
583 OS_REG_WRITE(_a, _r, \
584 (OS_REG_READ(_a, _r) &~(_f<<_f##_S)) | \
585 (((_v) << _f##_S) & (_f<<_f##_S)))
586 #define OS_REG_READ_FIELD(_a, _r, _f) \
587 (((OS_REG_READ(_a, _r) & _f) >> _f##_S))
588 #define OS_REG_READ_FIELD_ALT(_a, _r, _f) \
589 ((OS_REG_READ(_a, _r) >> (_f##_S))&(_f))
591 /* Analog register writes may require a delay between each one (eg Merlin?) */
592 #define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \
593 do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | \
594 (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0)
595 #define OS_A_REG_WRITE(_a, _r, _v) \
596 do { OS_REG_WRITE(_a, _r, _v); OS_DELAY(100); } while (0)
598 /* wait for the register contents to have the specified value */
599 extern HAL_BOOL ath_hal_wait(struct ath_hal *, u_int reg,
600 uint32_t mask, uint32_t val);
601 extern HAL_BOOL ath_hal_waitfor(struct ath_hal *, u_int reg,
602 uint32_t mask, uint32_t val, uint32_t timeout);
604 /* return the first n bits in val reversed */
605 extern uint32_t ath_hal_reverseBits(uint32_t val, uint32_t n);
607 /* printf interfaces */
608 extern void ath_hal_printf(struct ath_hal *, const char*, ...)
610 extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
612 extern const char* ath_hal_ether_sprintf(const uint8_t *mac);
614 /* allocate and free memory */
615 extern void *ath_hal_malloc(size_t);
616 extern void ath_hal_free(void *);
618 /* common debugging interfaces */
620 #include "ah_debug.h"
621 extern int ath_hal_debug; /* Global debug flags */
624 * The typecast is purely because some callers will pass in
625 * AH_NULL directly rather than using a NULL ath_hal pointer.
627 #define HALDEBUG(_ah, __m, ...) \
629 if ((__m) == HAL_DEBUG_UNMASKABLE || \
630 ath_hal_debug & (__m) || \
632 ((struct ath_hal *) (_ah))->ah_config.ah_debug & (__m))) { \
633 DO_HALDEBUG((_ah), (__m), __VA_ARGS__); \
637 extern void DO_HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
640 #define HALDEBUG(_ah, __m, ...)
641 #endif /* AH_DEBUG */
644 * Register logging definitions shared with ardecode.
646 #include "ah_decode.h"
649 * Common assertion interface. Note: it is a bad idea to generate
650 * an assertion failure for any recoverable event. Instead catch
651 * the violation and, if possible, fix it up or recover from it; either
652 * with an error return value or a diagnostic messages. System software
653 * does not panic unless the situation is hopeless.
656 extern void ath_hal_assert_failed(const char* filename,
657 int lineno, const char* msg);
659 #define HALASSERT(_x) do { \
661 ath_hal_assert_failed(__FILE__, __LINE__, #_x); \
665 #define HALASSERT(_x)
666 #endif /* AH_ASSERT */
669 * Regulatory domain support.
673 * Return the max allowed antenna gain and apply any regulatory
674 * domain specific changes.
676 u_int ath_hal_getantennareduction(struct ath_hal *ah,
677 const struct ieee80211_channel *chan, u_int twiceGain);
680 * Return the test group for the specific channel based on
681 * the current regulatory setup.
683 u_int ath_hal_getctl(struct ath_hal *, const struct ieee80211_channel *);
686 * Map a public channel definition to the corresponding
687 * internal data structure. This implicitly specifies
688 * whether or not the specified channel is ok to use
689 * based on the current regulatory domain constraints.
692 static OS_INLINE HAL_CHANNEL_INTERNAL *
693 ath_hal_checkchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
695 HAL_CHANNEL_INTERNAL *cc;
697 HALASSERT(c->ic_devdata < AH_PRIVATE(ah)->ah_nchan);
698 cc = &AH_PRIVATE(ah)->ah_channels[c->ic_devdata];
699 HALASSERT(c->ic_freq == cc->channel || IEEE80211_IS_CHAN_GSM(c));
703 /* NB: non-inline version that checks state */
704 HAL_CHANNEL_INTERNAL *ath_hal_checkchannel(struct ath_hal *,
705 const struct ieee80211_channel *);
706 #endif /* AH_DEBUG */
709 * Return the h/w frequency for a channel. This may be
710 * different from ic_freq if this is a GSM device that
711 * takes 2.4GHz frequencies and down-converts them.
713 static OS_INLINE uint16_t
714 ath_hal_gethwchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
716 return ath_hal_checkchannel(ah, c)->channel;
720 * Convert between microseconds and core system clocks.
722 extern u_int ath_hal_mac_clks(struct ath_hal *ah, u_int usecs);
723 extern u_int ath_hal_mac_usec(struct ath_hal *ah, u_int clks);
726 * Generic get/set capability support. Each chip overrides
727 * this routine to support chip-specific capabilities.
729 extern HAL_STATUS ath_hal_getcapability(struct ath_hal *ah,
730 HAL_CAPABILITY_TYPE type, uint32_t capability,
732 extern HAL_BOOL ath_hal_setcapability(struct ath_hal *ah,
733 HAL_CAPABILITY_TYPE type, uint32_t capability,
734 uint32_t setting, HAL_STATUS *status);
736 /* The diagnostic codes used to be internally defined here -adrian */
737 #include "ah_diagcodes.h"
740 * The AR5416 and later HALs have MAC and baseband hang checking.
743 uint32_t hang_reg_offset;
746 uint32_t hang_offset;
747 } hal_hw_hang_check_t;
757 dcu_chain_state = 0x1,
758 dcu_complete_state = 0x2,
761 qcu_fsp_state = 0x10,
762 qcu_stitch_state = 0x20,
763 qcu_fetch_state = 0x40,
764 qcu_complete_state = 0x80
769 uint8_t dcu_chain_state;
770 uint8_t dcu_complete_state;
773 uint8_t qcu_fsp_state;
774 uint8_t qcu_stitch_state;
775 uint8_t qcu_fetch_state;
776 uint8_t qcu_complete_state;
777 } hal_mac_hang_check_t;
780 HAL_BB_HANG_DFS = 0x0001,
781 HAL_BB_HANG_RIFS = 0x0002,
782 HAL_BB_HANG_RX_CLEAR = 0x0004,
783 HAL_BB_HANG_UNKNOWN = 0x0080,
785 HAL_MAC_HANG_SIG1 = 0x0100,
786 HAL_MAC_HANG_SIG2 = 0x0200,
787 HAL_MAC_HANG_UNKNOWN = 0x8000,
789 HAL_BB_HANGS = HAL_BB_HANG_DFS
791 | HAL_BB_HANG_RX_CLEAR
792 | HAL_BB_HANG_UNKNOWN,
793 HAL_MAC_HANGS = HAL_MAC_HANG_SIG1
795 | HAL_MAC_HANG_UNKNOWN,
798 /* Merge these with above */
799 typedef enum hal_hw_hangs {
800 HAL_DFS_BB_HANG_WAR = 0x1,
801 HAL_RIFS_BB_HANG_WAR = 0x2,
802 HAL_RX_STUCK_LOW_BB_HANG_WAR = 0x4,
803 HAL_MAC_HANG_WAR = 0x8,
804 HAL_PHYRESTART_CLR_WAR = 0x10,
805 HAL_MAC_HANG_DETECTED = 0x40000000,
806 HAL_BB_HANG_DETECTED = 0x80000000
810 * Device revision information.
813 uint16_t ah_devid; /* PCI device ID */
814 uint16_t ah_subvendorid; /* PCI subvendor ID */
815 uint32_t ah_macVersion; /* MAC version id */
816 uint16_t ah_macRev; /* MAC revision */
817 uint16_t ah_phyRev; /* PHY revision */
818 uint16_t ah_analog5GhzRev; /* 2GHz radio revision */
819 uint16_t ah_analog2GhzRev; /* 5GHz radio revision */
823 * Argument payload for HAL_DIAG_SETKEY.
826 HAL_KEYVAL dk_keyval;
827 uint16_t dk_keyix; /* key index */
828 uint8_t dk_mac[IEEE80211_ADDR_LEN];
829 int dk_xor; /* XOR key data */
833 * Argument payload for HAL_DIAG_EEWRITE.
836 uint16_t ee_off; /* eeprom offset */
837 uint16_t ee_data; /* write data */
842 u_int offset; /* reg offset */
843 uint32_t val; /* reg value */
847 * 11n compatibility tweaks.
849 #define HAL_DIAG_11N_SERVICES 0x00000003
850 #define HAL_DIAG_11N_SERVICES_S 0
851 #define HAL_DIAG_11N_TXSTOMP 0x0000000c
852 #define HAL_DIAG_11N_TXSTOMP_S 2
855 int maxNoiseImmunityLevel; /* [0..4] */
856 int totalSizeDesired[5];
861 int maxSpurImmunityLevel; /* [0..7] */
864 int maxFirstepLevel; /* [0..2] */
867 uint32_t ofdmTrigHigh;
868 uint32_t ofdmTrigLow;
874 int period; /* update listen period */
877 extern HAL_BOOL ath_hal_getdiagstate(struct ath_hal *ah, int request,
878 const void *args, uint32_t argsize,
879 void **result, uint32_t *resultsize);
882 * Setup a h/w rate table for use.
884 extern void ath_hal_setupratetable(struct ath_hal *ah, HAL_RATE_TABLE *rt);
887 * Common routine for implementing getChanNoise api.
889 int16_t ath_hal_getChanNoise(struct ath_hal *, const struct ieee80211_channel *);
892 * Initialization support.
895 const uint32_t *data;
899 #define HAL_INI_INIT(_ia, _data, _cols) do { \
900 (_ia)->data = (const uint32_t *)(_data); \
901 (_ia)->rows = sizeof(_data) / sizeof((_data)[0]); \
902 (_ia)->cols = (_cols); \
904 #define HAL_INI_VAL(_ia, _r, _c) \
905 ((_ia)->data[((_r)*(_ia)->cols) + (_c)])
908 * OS_DELAY() does a PIO READ on the PCI bus which allows
909 * other cards' DMA reads to complete in the middle of our reset.
911 #define DMA_YIELD(x) do { \
912 if ((++(x) % 64) == 0) \
916 #define HAL_INI_WRITE_ARRAY(ah, regArray, col, regWr) do { \
918 for (r = 0; r < N(regArray); r++) { \
919 OS_REG_WRITE(ah, (regArray)[r][0], (regArray)[r][col]); \
924 #define HAL_INI_WRITE_BANK(ah, regArray, bankData, regWr) do { \
926 for (r = 0; r < N(regArray); r++) { \
927 OS_REG_WRITE(ah, (regArray)[r][0], (bankData)[r]); \
932 extern int ath_hal_ini_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
934 extern void ath_hal_ini_bank_setup(uint32_t data[], const HAL_INI_ARRAY *ia,
936 extern int ath_hal_ini_bank_write(struct ath_hal *ah, const HAL_INI_ARRAY *ia,
937 const uint32_t data[], int regWr);
939 #define CCK_SIFS_TIME 10
940 #define CCK_PREAMBLE_BITS 144
941 #define CCK_PLCP_BITS 48
943 #define OFDM_SIFS_TIME 16
944 #define OFDM_PREAMBLE_TIME 20
945 #define OFDM_PLCP_BITS 22
946 #define OFDM_SYMBOL_TIME 4
948 #define OFDM_HALF_SIFS_TIME 32
949 #define OFDM_HALF_PREAMBLE_TIME 40
950 #define OFDM_HALF_PLCP_BITS 22
951 #define OFDM_HALF_SYMBOL_TIME 8
953 #define OFDM_QUARTER_SIFS_TIME 64
954 #define OFDM_QUARTER_PREAMBLE_TIME 80
955 #define OFDM_QUARTER_PLCP_BITS 22
956 #define OFDM_QUARTER_SYMBOL_TIME 16
958 #define TURBO_SIFS_TIME 8
959 #define TURBO_PREAMBLE_TIME 14
960 #define TURBO_PLCP_BITS 22
961 #define TURBO_SYMBOL_TIME 4
963 #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) /* ACK+FCS */
965 /* Generic EEPROM board value functions */
966 extern HAL_BOOL ath_ee_getLowerUpperIndex(uint8_t target, uint8_t *pList,
967 uint16_t listSize, uint16_t *indexL, uint16_t *indexR);
968 extern HAL_BOOL ath_ee_FillVpdTable(uint8_t pwrMin, uint8_t pwrMax,
969 uint8_t *pPwrList, uint8_t *pVpdList, uint16_t numIntercepts,
970 uint8_t *pRetVpdList);
971 extern int16_t ath_ee_interpolate(uint16_t target, uint16_t srcLeft,
972 uint16_t srcRight, int16_t targetLeft, int16_t targetRight);
974 /* Whether 5ghz fast clock is needed */
976 * The chipset (Merlin, AR9300/later) should set the capability flag below;
977 * this flag simply says that the hardware can do it, not that the EEPROM
980 * Merlin 2.0/2.1 chips with an EEPROM version > 16 do 5ghz fast clock
981 * if the relevant eeprom flag is set.
982 * Merlin 2.0/2.1 chips with an EEPROM version <= 16 do 5ghz fast clock
985 #define IS_5GHZ_FAST_CLOCK_EN(_ah, _c) \
986 (IEEE80211_IS_CHAN_5GHZ(_c) && \
987 AH_PRIVATE((_ah))->ah_caps.halSupportsFastClock5GHz && \
988 ath_hal_eepromGetFlag((_ah), AR_EEP_FSTCLK_5G))
991 * Fetch the maximum regulatory domain power for the given channel
995 ath_hal_get_twice_max_regpower(struct ath_hal_private *ahp,
996 const HAL_CHANNEL_INTERNAL *ichan, const struct ieee80211_channel *chan)
998 struct ath_hal *ah = &ahp->h;
1001 ath_hal_printf(ah, "%s: called with chan=NULL!\n", __func__);
1004 return (chan->ic_maxpower);
1008 * Get the maximum antenna gain allowed, in 1/2dBm steps.
1011 ath_hal_getantennaallowed(struct ath_hal *ah,
1012 const struct ieee80211_channel *chan)
1018 return (chan->ic_maxantgain);
1022 #endif /* _ATH_AH_INTERAL_H_ */