2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2006 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include "ah_internal.h"
25 #include "ar5211/ar5211.h"
26 #include "ar5211/ar5211reg.h"
27 #include "ar5211/ar5211desc.h"
33 ar5211GetRxDP(struct ath_hal *ah, HAL_RX_QUEUE qtype)
36 HALASSERT(qtype == HAL_RX_QUEUE_HP);
37 return OS_REG_READ(ah, AR_RXDP);
44 ar5211SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype)
47 HALASSERT(qtype == HAL_RX_QUEUE_HP);
48 OS_REG_WRITE(ah, AR_RXDP, rxdp);
49 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
54 * Set Receive Enable bits.
57 ar5211EnableReceive(struct ath_hal *ah)
59 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
63 * Stop Receive at the DMA engine
66 ar5211StopDmaReceive(struct ath_hal *ah)
68 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
69 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
71 ath_hal_printf(ah, "%s failed to stop in 10ms\n"
72 "AR_CR=0x%08X\nAR_DIAG_SW=0x%08X\n"
74 , OS_REG_READ(ah, AR_CR)
75 , OS_REG_READ(ah, AR_DIAG_SW)
85 * Start Transmit at the PCU engine (unpause receive)
88 ar5211StartPcuReceive(struct ath_hal *ah)
90 OS_REG_WRITE(ah, AR_DIAG_SW,
91 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX));
95 * Stop Transmit at the PCU engine (pause receive)
98 ar5211StopPcuReceive(struct ath_hal *ah)
100 OS_REG_WRITE(ah, AR_DIAG_SW,
101 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX);
105 * Set multicast filter 0 (lower 32-bits)
106 * filter 1 (upper 32-bits)
109 ar5211SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
111 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
112 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
116 * Clear multicast filter by index
119 ar5211ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
126 val = OS_REG_READ(ah, AR_MCAST_FIL1);
127 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
129 val = OS_REG_READ(ah, AR_MCAST_FIL0);
130 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
136 * Set multicast filter by index
139 ar5211SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
146 val = OS_REG_READ(ah, AR_MCAST_FIL1);
147 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
149 val = OS_REG_READ(ah, AR_MCAST_FIL0);
150 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
156 * Get receive filter.
159 ar5211GetRxFilter(struct ath_hal *ah)
161 return OS_REG_READ(ah, AR_RX_FILTER);
165 * Set receive filter.
168 ar5211SetRxFilter(struct ath_hal *ah, uint32_t bits)
170 OS_REG_WRITE(ah, AR_RX_FILTER, bits);
174 * Initialize RX descriptor, by clearing the status and clearing
175 * the size. This is not strictly HW dependent, but we want the
176 * control and status words to be opaque above the hal.
179 ar5211SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
180 uint32_t size, u_int flags)
182 struct ar5211_desc *ads = AR5211DESC(ds);
185 ads->ds_ctl1 = size & AR_BufLen;
186 if (ads->ds_ctl1 != size) {
187 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: buffer size %u too large\n",
191 if (flags & HAL_RXDESC_INTREQ)
192 ads->ds_ctl1 |= AR_RxInterReq;
193 ads->ds_status0 = ads->ds_status1 = 0;
199 * Process an RX descriptor, and return the status to the caller.
200 * Copy some hardware specific items into the software portion
203 * NB: the caller is responsible for validating the memory contents
204 * of the descriptor (e.g. flushing any cached copy).
207 ar5211ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
208 uint32_t pa, struct ath_desc *nds, uint64_t tsf,
209 struct ath_rx_status *rs)
211 struct ar5211_desc *ads = AR5211DESC(ds);
212 struct ar5211_desc *ands = AR5211DESC(nds);
214 if ((ads->ds_status1 & AR_Done) == 0)
215 return HAL_EINPROGRESS;
217 * Given the use of a self-linked tail be very sure that the hw is
218 * done with this descriptor; the hw may have done this descriptor
219 * once and picked it up again...make sure the hw has moved on.
221 if ((ands->ds_status1 & AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
222 return HAL_EINPROGRESS;
224 rs->rs_datalen = ads->ds_status0 & AR_DataLen;
225 rs->rs_tstamp = MS(ads->ds_status1, AR_RcvTimestamp);
227 if ((ads->ds_status1 & AR_FrmRcvOK) == 0) {
228 if (ads->ds_status1 & AR_CRCErr)
229 rs->rs_status |= HAL_RXERR_CRC;
230 else if (ads->ds_status1 & AR_DecryptCRCErr)
231 rs->rs_status |= HAL_RXERR_DECRYPT;
233 rs->rs_status |= HAL_RXERR_PHY;
234 rs->rs_phyerr = MS(ads->ds_status1, AR_PHYErr);
237 /* XXX what about KeyCacheMiss? */
238 rs->rs_rssi = MS(ads->ds_status0, AR_RcvSigStrength);
239 if (ads->ds_status1 & AR_KeyIdxValid)
240 rs->rs_keyix = MS(ads->ds_status1, AR_KeyIdx);
242 rs->rs_keyix = HAL_RXKEYIX_INVALID;
243 /* NB: caller expected to do rate table mapping */
244 rs->rs_rate = MS(ads->ds_status0, AR_RcvRate);
245 rs->rs_antenna = MS(ads->ds_status0, AR_RcvAntenna);
246 rs->rs_more = (ads->ds_status0 & AR_More) ? 1 : 0;