2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #ifndef _ATH_AR5212_H_
20 #define _ATH_AR5212_H_
22 #include "ah_eeprom.h"
24 #define AR5212_MAGIC 0x19541014
26 /* DCU Transmit Filter macros */
27 #define CALC_MMR(dcu, idx) \
28 ( (4 * dcu) + (idx < 32 ? 0 : (idx < 64 ? 1 : (idx < 96 ? 2 : 3))) )
29 #define TXBLK_FROM_MMR(mmr) \
30 (AR_D_TXBLK_BASE + ((mmr & 0x1f) << 6) + ((mmr & 0x20) >> 3))
31 #define CALC_TXBLK_ADDR(dcu, idx) (TXBLK_FROM_MMR(CALC_MMR(dcu, idx)))
32 #define CALC_TXBLK_VALUE(idx) (1 << (idx & 0x1f))
34 /* MAC register values */
36 #define INIT_INTERRUPT_MASK \
37 ( AR_IMR_TXERR | AR_IMR_TXOK | AR_IMR_RXORN | \
38 AR_IMR_RXERR | AR_IMR_RXOK | AR_IMR_TXURN | \
40 #define INIT_BEACON_CONTROL \
41 ((INIT_RESET_TSF << 24) | (INIT_BEACON_EN << 23) | \
42 (INIT_TIM_OFFSET << 16) | INIT_BEACON_PERIOD)
44 #define INIT_CONFIG_STATUS 0x00000000
45 #define INIT_RSSI_THR 0x00000781 /* Missed beacon counter initialized to 0x7 (max is 0xff) */
46 #define INIT_IQCAL_LOG_COUNT_MAX 0xF
47 #define INIT_BCON_CNTRL_REG 0x00000000
50 #define HALF_RATE_USEC 19 /* ((40 / 2) - 1 ) */
51 #define QUARTER_RATE_USEC 9 /* ((40 / 4) - 1 ) */
53 #define RX_NON_FULL_RATE_LATENCY 63
54 #define TX_HALF_RATE_LATENCY 108
55 #define TX_QUARTER_RATE_LATENCY 216
57 #define IFS_SLOT_FULL_RATE 0x168 /* 9 us half, 40 MHz core clock (9*40) */
58 #define IFS_SLOT_HALF_RATE 0x104 /* 13 us half, 20 MHz core clock (13*20) */
59 #define IFS_SLOT_QUARTER_RATE 0xD2 /* 21 us quarter, 10 MHz core clock (21*10) */
60 #define IFS_EIFS_FULL_RATE 0xE60 /* (74 + (2 * 9)) * 40MHz core clock */
61 #define IFS_EIFS_HALF_RATE 0xDAC /* (149 + (2 * 13)) * 20MHz core clock */
62 #define IFS_EIFS_QUARTER_RATE 0xD48 /* (298 + (2 * 21)) * 10MHz core clock */
64 #define ACK_CTS_TIMEOUT_11A 0x3E8 /* ACK timeout in 11a core clocks */
66 /* Tx frame start to tx data start delay */
67 #define TX_FRAME_D_START_HALF_RATE 0xc
68 #define TX_FRAME_D_START_QUARTER_RATE 0xd
71 * Various fifo fill before Tx start, in 64-byte units
72 * i.e. put the frame in the air while still DMAing
74 #define MIN_TX_FIFO_THRESHOLD 0x1
75 #define MAX_TX_FIFO_THRESHOLD ((IEEE80211_MAX_LEN / 64) + 1)
76 #define INIT_TX_FIFO_THRESHOLD MIN_TX_FIFO_THRESHOLD
78 #define HAL_DECOMP_MASK_SIZE 128 /* 1 byte per key */
83 #define NUM_CORNER_FIX_BITS 4
84 #define NUM_CORNER_FIX_BITS_5112 7
85 #define DYN_ADJ_UP_MARGIN 15
86 #define DYN_ADJ_LO_MARGIN 20
87 #define PHY_PROBE_CCK_CORRECTION 5
88 #define CCK_OFDM_GAIN_DELTA 15
97 enum GAIN_PARAMS_5112 {
107 typedef struct _gainOptStep {
108 int16_t paramVal[NUM_CORNER_FIX_BITS_5112];
111 } GAIN_OPTIMIZATION_STEP;
114 uint32_t numStepsInLadder;
115 uint32_t defaultStepNum;
116 GAIN_OPTIMIZATION_STEP optStep[10];
117 } GAIN_OPTIMIZATION_LADDER;
120 uint32_t currStepNum;
126 const GAIN_OPTIMIZATION_STEP *currStep;
129 /* RF HAL structures */
130 typedef struct RfHalFuncs {
131 void *priv; /* private state */
133 void (*rfDetach)(struct ath_hal *ah);
134 void (*writeRegs)(struct ath_hal *,
135 u_int modeIndex, u_int freqIndex, int regWrites);
136 uint32_t *(*getRfBank)(struct ath_hal *ah, int bank);
137 HAL_BOOL (*setChannel)(struct ath_hal *,
138 const struct ieee80211_channel *);
139 HAL_BOOL (*setRfRegs)(struct ath_hal *,
140 const struct ieee80211_channel *, uint16_t modesIndex,
141 uint16_t *rfXpdGain);
142 HAL_BOOL (*setPowerTable)(struct ath_hal *ah,
143 int16_t *minPower, int16_t *maxPower,
144 const struct ieee80211_channel *, uint16_t *rfXpdGain);
145 HAL_BOOL (*getChannelMaxMinPower)(struct ath_hal *ah,
146 const struct ieee80211_channel *,
147 int16_t *maxPow, int16_t *minPow);
148 int16_t (*getNfAdjust)(struct ath_hal *, const HAL_CHANNEL_INTERNAL*);
151 struct ar5212AniParams {
152 int maxNoiseImmunityLevel; /* [0..4] */
153 int totalSizeDesired[5];
158 int maxSpurImmunityLevel; /* [0..7] */
161 int maxFirstepLevel; /* [0..2] */
164 uint32_t ofdmTrigHigh;
165 uint32_t ofdmTrigLow;
166 uint32_t cckTrigHigh;
169 uint32_t rssiThrHigh;
171 int period; /* update listen period */
173 /* NB: intentionally ordered so data exported to user space is first */
174 uint32_t ofdmPhyErrBase; /* Base value for ofdm err counter */
175 uint32_t cckPhyErrBase; /* Base value for cck err counters */
179 * Per-channel ANI state private to the driver.
181 struct ar5212AniState {
182 uint8_t noiseImmunityLevel;
183 uint8_t spurImmunityLevel;
184 uint8_t firstepLevel;
185 uint8_t ofdmWeakSigDetectOff;
186 uint8_t cckWeakSigThreshold;
189 /* NB: intentionally ordered so data exported to user space is first */
190 uint32_t txFrameCount; /* Last txFrameCount */
191 uint32_t rxFrameCount; /* Last rx Frame count */
192 uint32_t cycleCount; /* Last cycleCount
193 (to detect wrap-around) */
194 uint32_t ofdmPhyErrCount;/* OFDM err count since last reset */
195 uint32_t cckPhyErrCount; /* CCK err count since last reset */
197 const struct ar5212AniParams *params;
200 #define HAL_ANI_ENA 0x00000001 /* ANI operation enabled */
201 #define HAL_RSSI_ANI_ENA 0x00000002 /* rssi-based processing ena'd*/
205 uint32_t ast_ani_niup; /* ANI increased noise immunity */
206 uint32_t ast_ani_nidown; /* ANI decreased noise immunity */
207 uint32_t ast_ani_spurup; /* ANI increased spur immunity */
208 uint32_t ast_ani_spurdown;/* ANI descreased spur immunity */
209 uint32_t ast_ani_ofdmon; /* ANI OFDM weak signal detect on */
210 uint32_t ast_ani_ofdmoff;/* ANI OFDM weak signal detect off */
211 uint32_t ast_ani_cckhigh;/* ANI CCK weak signal threshold high */
212 uint32_t ast_ani_ccklow; /* ANI CCK weak signal threshold low */
213 uint32_t ast_ani_stepup; /* ANI increased first step level */
214 uint32_t ast_ani_stepdown;/* ANI decreased first step level */
215 uint32_t ast_ani_ofdmerrs;/* ANI cumulative ofdm phy err count */
216 uint32_t ast_ani_cckerrs;/* ANI cumulative cck phy err count */
217 uint32_t ast_ani_reset; /* ANI parameters zero'd for non-STA */
218 uint32_t ast_ani_lzero; /* ANI listen time forced to zero */
219 uint32_t ast_ani_lneg; /* ANI listen time calculated < 0 */
220 HAL_MIB_STATS ast_mibstats; /* MIB counter stats */
221 HAL_NODE_STATS ast_nodestats; /* Latest rssi stats from driver */
226 * NF Cal history buffer
228 #define AR5212_CCA_MAX_GOOD_VALUE -95
229 #define AR5212_CCA_MAX_HIGH_VALUE -62
230 #define AR5212_CCA_MIN_BAD_VALUE -125
232 #define AR512_NF_CAL_HIST_MAX 5
234 struct ar5212NfCalHist {
235 int16_t nfCalBuffer[AR512_NF_CAL_HIST_MAX];
239 uint8_t invalidNFcount;
242 struct ath_hal_5212 {
243 struct ath_hal_private ah_priv; /* base class */
246 * Per-chip common Initialization data.
247 * NB: RF backends have their own ini data.
249 HAL_INI_ARRAY ah_ini_modes;
250 HAL_INI_ARRAY ah_ini_common;
252 GAIN_VALUES ah_gainValues;
254 uint8_t ah_macaddr[IEEE80211_ADDR_LEN];
255 uint8_t ah_bssid[IEEE80211_ADDR_LEN];
256 uint8_t ah_bssidmask[IEEE80211_ADDR_LEN];
262 uint32_t ah_maskReg; /* copy of AR_IMR */
263 HAL_ANI_STATS ah_stats; /* various statistics */
264 RF_HAL_FUNCS *ah_rfHal;
265 uint32_t ah_txDescMask; /* mask for TXDESC */
266 uint32_t ah_txOkInterruptMask;
267 uint32_t ah_txErrInterruptMask;
268 uint32_t ah_txDescInterruptMask;
269 uint32_t ah_txEolInterruptMask;
270 uint32_t ah_txUrnInterruptMask;
271 HAL_TX_QUEUE_INFO ah_txq[HAL_NUM_TX_QUEUES];
272 uint32_t ah_intrTxqs; /* tx q interrupt state */
273 /* decomp mask array */
274 uint8_t ah_decompMask[HAL_DECOMP_MASK_SIZE];
275 HAL_ANT_SETTING ah_antControl; /* antenna setting */
276 HAL_BOOL ah_diversity; /* fast diversity setting */
281 } ah_bIQCalibration; /* IQ calibrate state */
282 HAL_RFGAIN ah_rfgainState; /* RF gain calibrartion state */
283 uint32_t ah_tx6PowerInHalfDbm; /* power output for 6Mb tx */
284 uint32_t ah_staId1Defaults; /* STA_ID1 default settings */
285 uint32_t ah_miscMode; /* MISC_MODE settings */
286 uint32_t ah_rssiThr; /* RSSI_THR settings */
287 HAL_BOOL ah_cwCalRequire; /* for ap51 */
288 HAL_BOOL ah_tpcEnabled; /* per-packet tpc enabled */
289 HAL_BOOL ah_phyPowerOn; /* PHY power state */
290 HAL_BOOL ah_isHb63; /* cached HB63 check */
291 uint32_t ah_macTPC; /* tpc register */
292 uint32_t ah_beaconInterval; /* XXX */
294 AUTO_32KHZ, /* use it if 32kHz crystal present */
295 USE_32KHZ, /* do it regardless */
296 DONT_USE_32KHZ, /* don't use it regardless */
297 } ah_enable32kHzClock; /* whether to sleep at 32kHz */
298 uint32_t ah_ofdmTxPower;
299 int16_t ah_txPowerIndexOffset;
301 * Noise floor cal histogram support.
303 struct ar5212NfCalHist ah_nfCalHist;
305 u_int ah_slottime; /* user-specified slot time */
306 u_int ah_acktimeout; /* user-specified ack timeout */
307 u_int ah_ctstimeout; /* user-specified cts timeout */
308 u_int ah_sifstime; /* user-specified sifs time */
310 * RF Silent handling; setup according to the EEPROM.
312 uint32_t ah_gpioSelect; /* GPIO pin to use */
313 uint32_t ah_polarity; /* polarity to disable RF */
314 uint32_t ah_gpioBit; /* after init, prev value */
318 uint32_t ah_procPhyErr; /* Process Phy errs */
319 HAL_BOOL ah_hasHwPhyCounters; /* Hardware has phy counters */
320 struct ar5212AniParams ah_aniParams24; /* 2.4GHz parameters */
321 struct ar5212AniParams ah_aniParams5; /* 5GHz parameters */
322 struct ar5212AniState *ah_curani; /* cached last reference */
323 struct ar5212AniState ah_ani[AH_MAXCHAN]; /* per-channel state */
325 /* AR5416 uses some of the AR5212 ANI code; these are the ANI methods */
326 HAL_BOOL (*ah_aniControl) (struct ath_hal *, HAL_ANI_CMD cmd, int param);
329 * Transmit power state. Note these are maintained
330 * here so they can be retrieved by diagnostic tools.
332 uint16_t *ah_pcdacTable;
333 u_int ah_pcdacTableSize;
334 uint16_t ah_ratesArray[37];
336 uint8_t ah_txTrigLev; /* current Tx trigger level */
337 uint8_t ah_maxTxTrigLev; /* max tx trigger level */
340 * Channel Tx, Rx, Rx Clear State
342 uint32_t ah_cycleCount;
346 uint32_t ah_rx_chainmask;
347 uint32_t ah_tx_chainmask;
349 /* Used to return ANI statistics to the diagnostic API */
350 HAL_ANI_STATS ext_ani_stats;
352 #define AH5212(_ah) ((struct ath_hal_5212 *)(_ah))
355 * IS_XXXX macros test the MAC version
356 * IS_RADXXX macros test the radio/RF version (matching both 2G-only and 2/5G)
358 * Some single chip radios have equivalent radio/RF (e.g. 5112)
359 * for those use IS_RADXXX_ANY macros.
361 #define IS_2317(ah) \
362 ((AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV1) || \
363 (AH_PRIVATE(ah)->ah_devid == AR5212_AR2317_REV2))
364 #define IS_2316(ah) \
365 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2415)
366 #define IS_2413(ah) \
367 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2413 || IS_2316(ah))
368 #define IS_5424(ah) \
369 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5424 || \
370 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 && \
371 AH_PRIVATE(ah)->ah_macRev <= AR_SREV_D2PLUS_MS))
372 #define IS_5413(ah) \
373 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_5413 || IS_5424(ah))
374 #define IS_2425(ah) \
375 (AH_PRIVATE(ah)->ah_macVersion == AR_SREV_2425)
376 #define IS_2417(ah) \
377 ((AH_PRIVATE(ah)->ah_macVersion) == AR_SREV_2417)
378 #define IS_HB63(ah) (AH5212(ah)->ah_isHb63 == AH_TRUE)
380 #define AH_RADIO_MAJOR(ah) \
381 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)
382 #define AH_RADIO_MINOR(ah) \
383 (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MINOR)
384 #define IS_RAD5111(ah) \
385 (AH_RADIO_MAJOR(ah) == AR_RAD5111_SREV_MAJOR || \
386 AH_RADIO_MAJOR(ah) == AR_RAD2111_SREV_MAJOR)
387 #define IS_RAD5112(ah) \
388 (AH_RADIO_MAJOR(ah) == AR_RAD5112_SREV_MAJOR || \
389 AH_RADIO_MAJOR(ah) == AR_RAD2112_SREV_MAJOR)
390 /* NB: does not include 5413 as Atheros' IS_5112 macro does */
391 #define IS_RAD5112_ANY(ah) \
392 (AR_RAD5112_SREV_MAJOR <= AH_RADIO_MAJOR(ah) && \
393 AH_RADIO_MAJOR(ah) <= AR_RAD2413_SREV_MAJOR)
394 #define IS_RAD5112_REV1(ah) \
396 AH_RADIO_MINOR(ah) < (AR_RAD5112_SREV_2_0 & AR_RADIO_SREV_MINOR))
397 #define IS_RADX112_REV2(ah) \
398 (AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_0 || \
399 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_0 || \
400 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD2112_SREV_2_1 || \
401 AH_PRIVATE(ah)->ah_analog5GhzRev == AR_RAD5112_SREV_2_1)
403 #define ar5212RfDetach(ah) do { \
404 if (AH5212(ah)->ah_rfHal != AH_NULL) \
405 AH5212(ah)->ah_rfHal->rfDetach(ah); \
407 #define ar5212GetRfBank(ah, b) \
408 AH5212(ah)->ah_rfHal->getRfBank(ah, b)
411 * Hack macros for Nala/San: 11b is handled
412 * using 11g; flip the channel flags to accomplish this.
414 #define SAVE_CCK(_ah, _chan, _flag) do { \
415 if ((IS_2425(_ah) || IS_2417(_ah)) && \
416 (((_chan)->ic_flags) & IEEE80211_CHAN_CCK)) { \
417 (_chan)->ic_flags &= ~IEEE80211_CHAN_CCK; \
418 (_chan)->ic_flags |= IEEE80211_CHAN_DYN; \
421 (_flag) = AH_FALSE; \
423 #define RESTORE_CCK(_ah, _chan, _flag) do { \
424 if ((_flag) && (IS_2425(_ah) || IS_2417(_ah))) { \
425 (_chan)->ic_flags &= ~IEEE80211_CHAN_DYN; \
426 (_chan)->ic_flags |= IEEE80211_CHAN_CCK; \
432 extern uint32_t ar5212GetRadioRev(struct ath_hal *ah);
433 extern void ar5212InitState(struct ath_hal_5212 *, uint16_t devid, HAL_SOFTC,
434 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status);
435 extern void ar5212Detach(struct ath_hal *ah);
436 extern HAL_BOOL ar5212ChipTest(struct ath_hal *ah);
437 extern HAL_BOOL ar5212GetChannelEdges(struct ath_hal *ah,
438 uint16_t flags, uint16_t *low, uint16_t *high);
439 extern HAL_BOOL ar5212FillCapabilityInfo(struct ath_hal *ah);
441 extern void ar5212SetBeaconTimers(struct ath_hal *ah,
442 const HAL_BEACON_TIMERS *);
443 extern void ar5212BeaconInit(struct ath_hal *ah,
444 uint32_t next_beacon, uint32_t beacon_period);
445 extern void ar5212ResetStaBeaconTimers(struct ath_hal *ah);
446 extern void ar5212SetStaBeaconTimers(struct ath_hal *ah,
447 const HAL_BEACON_STATE *);
448 extern uint64_t ar5212GetNextTBTT(struct ath_hal *);
450 extern HAL_BOOL ar5212IsInterruptPending(struct ath_hal *ah);
451 extern HAL_BOOL ar5212GetPendingInterrupts(struct ath_hal *ah, HAL_INT *);
452 extern HAL_INT ar5212GetInterrupts(struct ath_hal *ah);
453 extern HAL_INT ar5212SetInterrupts(struct ath_hal *ah, HAL_INT ints);
455 extern uint32_t ar5212GetKeyCacheSize(struct ath_hal *);
456 extern HAL_BOOL ar5212IsKeyCacheEntryValid(struct ath_hal *, uint16_t entry);
457 extern HAL_BOOL ar5212ResetKeyCacheEntry(struct ath_hal *ah, uint16_t entry);
458 extern HAL_BOOL ar5212SetKeyCacheEntryMac(struct ath_hal *,
459 uint16_t entry, const uint8_t *mac);
460 extern HAL_BOOL ar5212SetKeyCacheEntry(struct ath_hal *ah, uint16_t entry,
461 const HAL_KEYVAL *k, const uint8_t *mac, int xorKey);
463 extern void ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac);
464 extern HAL_BOOL ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *);
465 extern void ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mac);
466 extern HAL_BOOL ar5212SetBssIdMask(struct ath_hal *, const uint8_t *);
467 extern HAL_BOOL ar5212EepromRead(struct ath_hal *, u_int off, uint16_t *data);
468 extern HAL_BOOL ar5212EepromWrite(struct ath_hal *, u_int off, uint16_t data);
469 extern HAL_BOOL ar5212SetRegulatoryDomain(struct ath_hal *ah,
470 uint16_t regDomain, HAL_STATUS *stats);
471 extern u_int ar5212GetWirelessModes(struct ath_hal *ah);
472 extern void ar5212EnableRfKill(struct ath_hal *);
473 extern HAL_BOOL ar5212GpioCfgOutput(struct ath_hal *, uint32_t gpio,
475 extern HAL_BOOL ar5212GpioCfgInput(struct ath_hal *, uint32_t gpio);
476 extern HAL_BOOL ar5212GpioSet(struct ath_hal *, uint32_t gpio, uint32_t val);
477 extern uint32_t ar5212GpioGet(struct ath_hal *ah, uint32_t gpio);
478 extern void ar5212GpioSetIntr(struct ath_hal *ah, u_int, uint32_t ilevel);
479 extern void ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state);
480 extern void ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid,
482 extern uint32_t ar5212GetTsf32(struct ath_hal *ah);
483 extern uint64_t ar5212GetTsf64(struct ath_hal *ah);
484 extern void ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64);
485 extern void ar5212ResetTsf(struct ath_hal *ah);
486 extern void ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *pSet);
487 extern uint32_t ar5212GetRandomSeed(struct ath_hal *ah);
488 extern HAL_BOOL ar5212DetectCardPresent(struct ath_hal *ah);
489 extern void ar5212EnableMibCounters(struct ath_hal *);
490 extern void ar5212DisableMibCounters(struct ath_hal *);
491 extern void ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats);
492 extern HAL_BOOL ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah);
493 extern uint32_t ar5212GetCurRssi(struct ath_hal *ah);
494 extern u_int ar5212GetDefAntenna(struct ath_hal *ah);
495 extern void ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna);
496 extern HAL_ANT_SETTING ar5212GetAntennaSwitch(struct ath_hal *);
497 extern HAL_BOOL ar5212SetAntennaSwitch(struct ath_hal *, HAL_ANT_SETTING);
498 extern HAL_BOOL ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah);
499 extern HAL_BOOL ar5212SetSifsTime(struct ath_hal *, u_int);
500 extern u_int ar5212GetSifsTime(struct ath_hal *);
501 extern HAL_BOOL ar5212SetSlotTime(struct ath_hal *, u_int);
502 extern u_int ar5212GetSlotTime(struct ath_hal *);
503 extern HAL_BOOL ar5212SetAckTimeout(struct ath_hal *, u_int);
504 extern u_int ar5212GetAckTimeout(struct ath_hal *);
505 extern HAL_BOOL ar5212SetAckCTSRate(struct ath_hal *, u_int);
506 extern u_int ar5212GetAckCTSRate(struct ath_hal *);
507 extern HAL_BOOL ar5212SetCTSTimeout(struct ath_hal *, u_int);
508 extern u_int ar5212GetCTSTimeout(struct ath_hal *);
509 extern HAL_BOOL ar5212SetDecompMask(struct ath_hal *, uint16_t, int);
510 void ar5212SetCoverageClass(struct ath_hal *, uint8_t, int);
511 extern void ar5212SetPCUConfig(struct ath_hal *);
512 extern HAL_BOOL ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode);
513 extern void ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode);
514 extern void ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode);
515 extern int16_t ar5212GetNfAdjust(struct ath_hal *,
516 const HAL_CHANNEL_INTERNAL *);
517 extern void ar5212SetCompRegs(struct ath_hal *ah);
518 extern HAL_STATUS ar5212GetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
519 uint32_t, uint32_t *);
520 extern HAL_BOOL ar5212SetCapability(struct ath_hal *, HAL_CAPABILITY_TYPE,
521 uint32_t, uint32_t, HAL_STATUS *);
522 extern HAL_BOOL ar5212GetDiagState(struct ath_hal *ah, int request,
523 const void *args, uint32_t argsize,
524 void **result, uint32_t *resultsize);
525 extern HAL_STATUS ar5212SetQuiet(struct ath_hal *ah, uint32_t period,
526 uint32_t duration, uint32_t nextStart, HAL_QUIET_FLAG flag);
527 extern HAL_BOOL ar5212GetMibCycleCounts(struct ath_hal *,
528 HAL_SURVEY_SAMPLE *);
529 extern void ar5212SetChainMasks(struct ath_hal *, uint32_t, uint32_t);
531 extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
533 extern HAL_POWER_MODE ar5212GetPowerMode(struct ath_hal *ah);
534 extern HAL_BOOL ar5212GetPowerStatus(struct ath_hal *ah);
536 extern uint32_t ar5212GetRxDP(struct ath_hal *ath, HAL_RX_QUEUE);
537 extern void ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE);
538 extern void ar5212EnableReceive(struct ath_hal *ah);
539 extern HAL_BOOL ar5212StopDmaReceive(struct ath_hal *ah);
540 extern void ar5212StartPcuReceive(struct ath_hal *ah);
541 extern void ar5212StopPcuReceive(struct ath_hal *ah);
542 extern void ar5212SetMulticastFilter(struct ath_hal *ah,
543 uint32_t filter0, uint32_t filter1);
544 extern HAL_BOOL ar5212ClrMulticastFilterIndex(struct ath_hal *, uint32_t ix);
545 extern HAL_BOOL ar5212SetMulticastFilterIndex(struct ath_hal *, uint32_t ix);
546 extern uint32_t ar5212GetRxFilter(struct ath_hal *ah);
547 extern void ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits);
548 extern HAL_BOOL ar5212SetupRxDesc(struct ath_hal *,
549 struct ath_desc *, uint32_t size, u_int flags);
550 extern HAL_STATUS ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *,
551 uint32_t, struct ath_desc *, uint64_t,
552 struct ath_rx_status *);
554 extern HAL_BOOL ar5212Reset(struct ath_hal *ah, HAL_OPMODE opmode,
555 struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
556 HAL_RESET_TYPE, HAL_STATUS *status);
557 extern HAL_BOOL ar5212SetChannel(struct ath_hal *,
558 const struct ieee80211_channel *);
559 extern void ar5212SetOperatingMode(struct ath_hal *ah, int opmode);
560 extern HAL_BOOL ar5212PhyDisable(struct ath_hal *ah);
561 extern HAL_BOOL ar5212Disable(struct ath_hal *ah);
562 extern HAL_BOOL ar5212ChipReset(struct ath_hal *ah,
563 const struct ieee80211_channel *);
564 extern HAL_BOOL ar5212PerCalibration(struct ath_hal *ah,
565 struct ieee80211_channel *chan, HAL_BOOL *isIQdone);
566 extern HAL_BOOL ar5212PerCalibrationN(struct ath_hal *ah,
567 struct ieee80211_channel *chan, u_int chainMask,
568 HAL_BOOL longCal, HAL_BOOL *isCalDone);
569 extern HAL_BOOL ar5212ResetCalValid(struct ath_hal *ah,
570 const struct ieee80211_channel *);
571 extern int16_t ar5212GetNoiseFloor(struct ath_hal *ah);
572 extern void ar5212InitNfCalHistBuffer(struct ath_hal *);
573 extern int16_t ar5212GetNfHistMid(const int16_t calData[]);
574 extern void ar5212SetSpurMitigation(struct ath_hal *,
575 const struct ieee80211_channel *);
576 extern HAL_BOOL ar5212SetAntennaSwitchInternal(struct ath_hal *ah,
577 HAL_ANT_SETTING settings, const struct ieee80211_channel *);
578 extern HAL_BOOL ar5212SetTxPowerLimit(struct ath_hal *ah, uint32_t limit);
579 extern HAL_BOOL ar5212GetChipPowerLimits(struct ath_hal *ah,
580 struct ieee80211_channel *chan);
581 extern void ar5212InitializeGainValues(struct ath_hal *);
582 extern HAL_RFGAIN ar5212GetRfgain(struct ath_hal *ah);
583 extern void ar5212RequestRfgain(struct ath_hal *);
585 extern HAL_BOOL ar5212UpdateTxTrigLevel(struct ath_hal *,
586 HAL_BOOL IncTrigLevel);
587 extern HAL_BOOL ar5212SetTxQueueProps(struct ath_hal *ah, int q,
588 const HAL_TXQ_INFO *qInfo);
589 extern HAL_BOOL ar5212GetTxQueueProps(struct ath_hal *ah, int q,
590 HAL_TXQ_INFO *qInfo);
591 extern int ar5212SetupTxQueue(struct ath_hal *ah, HAL_TX_QUEUE type,
592 const HAL_TXQ_INFO *qInfo);
593 extern HAL_BOOL ar5212ReleaseTxQueue(struct ath_hal *ah, u_int q);
594 extern HAL_BOOL ar5212ResetTxQueue(struct ath_hal *ah, u_int q);
595 extern uint32_t ar5212GetTxDP(struct ath_hal *ah, u_int q);
596 extern HAL_BOOL ar5212SetTxDP(struct ath_hal *ah, u_int q, uint32_t txdp);
597 extern HAL_BOOL ar5212StartTxDma(struct ath_hal *ah, u_int q);
598 extern uint32_t ar5212NumTxPending(struct ath_hal *ah, u_int q);
599 extern HAL_BOOL ar5212StopTxDma(struct ath_hal *ah, u_int q);
600 extern HAL_BOOL ar5212SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
601 u_int pktLen, u_int hdrLen, HAL_PKT_TYPE type, u_int txPower,
602 u_int txRate0, u_int txTries0,
603 u_int keyIx, u_int antMode, u_int flags,
604 u_int rtsctsRate, u_int rtsctsDuration,
605 u_int compicvLen, u_int compivLen, u_int comp);
606 extern HAL_BOOL ar5212SetupXTxDesc(struct ath_hal *, struct ath_desc *,
607 u_int txRate1, u_int txRetries1,
608 u_int txRate2, u_int txRetries2,
609 u_int txRate3, u_int txRetries3);
610 extern HAL_BOOL ar5212FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
611 HAL_DMA_ADDR *bufAddrList, uint32_t *segLenList,
612 u_int descId, u_int qcuId, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
613 const struct ath_desc *ds0);
614 extern HAL_STATUS ar5212ProcTxDesc(struct ath_hal *ah,
615 struct ath_desc *, struct ath_tx_status *);
616 extern void ar5212GetTxIntrQueue(struct ath_hal *ah, uint32_t *);
617 extern void ar5212IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *);
618 extern HAL_BOOL ar5212GetTxCompletionRates(struct ath_hal *ah,
619 const struct ath_desc *ds0, int *rates, int *tries);
620 extern void ar5212SetTxDescLink(struct ath_hal *ah, void *ds,
622 extern void ar5212GetTxDescLink(struct ath_hal *ah, void *ds,
624 extern void ar5212GetTxDescLinkPtr(struct ath_hal *ah, void *ds,
627 extern const HAL_RATE_TABLE *ar5212GetRateTable(struct ath_hal *, u_int mode);
629 extern void ar5212AniAttach(struct ath_hal *, const struct ar5212AniParams *,
630 const struct ar5212AniParams *, HAL_BOOL ena);
631 extern void ar5212AniDetach(struct ath_hal *);
632 extern struct ar5212AniState *ar5212AniGetCurrentState(struct ath_hal *);
633 extern HAL_ANI_STATS *ar5212AniGetCurrentStats(struct ath_hal *);
634 extern HAL_BOOL ar5212AniControl(struct ath_hal *, HAL_ANI_CMD cmd, int param);
635 extern HAL_BOOL ar5212AniSetParams(struct ath_hal *,
636 const struct ar5212AniParams *, const struct ar5212AniParams *);
637 struct ath_rx_status;
638 extern void ar5212AniPhyErrReport(struct ath_hal *ah,
639 const struct ath_rx_status *rs);
640 extern void ar5212ProcessMibIntr(struct ath_hal *, const HAL_NODE_STATS *);
641 extern void ar5212RxMonitor(struct ath_hal *, const HAL_NODE_STATS *,
642 const struct ieee80211_channel *);
643 extern void ar5212AniPoll(struct ath_hal *, const struct ieee80211_channel *);
644 extern void ar5212AniReset(struct ath_hal *, const struct ieee80211_channel *,
647 extern HAL_BOOL ar5212IsNFCalInProgress(struct ath_hal *ah);
648 extern HAL_BOOL ar5212WaitNFCalComplete(struct ath_hal *ah, int i);
649 extern void ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
650 extern HAL_BOOL ar5212GetDfsDefaultThresh(struct ath_hal *ah,
651 HAL_PHYERR_PARAM *pe);
652 extern void ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe);
653 extern HAL_BOOL ar5212ProcessRadarEvent(struct ath_hal *ah,
654 struct ath_rx_status *rxs, uint64_t fulltsf, const char *buf,
655 HAL_DFS_EVENT *event);
656 extern HAL_BOOL ar5212IsFastClockEnabled(struct ath_hal *ah);
657 extern uint32_t ar5212Get11nExtBusy(struct ath_hal *ah);
659 #endif /* _ATH_AR5212_H_ */