2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #ifndef _ATH_AR5212_DESC_H_
22 #define _ATH_AR5212_DESC_H_
25 * Hardware-specific descriptor structures.
29 * AR5212-specific tx/rx descriptor definition.
32 uint32_t ds_link; /* link pointer */
33 uint32_t ds_data; /* data buffer pointer */
34 uint32_t ds_ctl0; /* DMA control 0 */
35 uint32_t ds_ctl1; /* DMA control 1 */
37 struct { /* xmit format */
38 uint32_t ctl2; /* DMA control 2 */
39 uint32_t ctl3; /* DMA control 3 */
40 uint32_t status0;/* DMA status 0 */
41 uint32_t status1;/* DMA status 1 */
43 struct { /* recv format */
44 uint32_t status0;/* DMA status 0 */
45 uint32_t status1;/* DMA status 1 */
49 #define AR5212DESC(_ds) ((struct ar5212_desc *)(_ds))
50 #define AR5212DESC_CONST(_ds) ((const struct ar5212_desc *)(_ds))
52 #define ds_ctl2 u.tx.ctl2
53 #define ds_ctl3 u.tx.ctl3
54 #define ds_txstatus0 u.tx.status0
55 #define ds_txstatus1 u.tx.status1
56 #define ds_rxstatus0 u.rx.status0
57 #define ds_rxstatus1 u.rx.status1
60 #define AR_FrameLen 0x00000fff /* frame length */
61 /* bits 12-15 are reserved */
62 #define AR_XmitPower 0x003f0000 /* transmit power control */
63 #define AR_XmitPower_S 16
64 #define AR_RTSCTSEnable 0x00400000 /* RTS/CTS protocol enable */
65 #define AR_VEOL 0x00800000 /* virtual end-of-list */
66 #define AR_ClearDestMask 0x01000000 /* Clear destination mask bit */
67 #define AR_AntModeXmit 0x1e000000 /* TX antenna seslection */
68 #define AR_AntModeXmit_S 25
69 #define AR_TxInterReq 0x20000000 /* TX interrupt request */
70 #define AR_DestIdxValid 0x40000000 /* destination index valid */
71 #define AR_CTSEnable 0x80000000 /* precede frame with CTS */
74 #define AR_BufLen 0x00000fff /* data buffer length */
75 #define AR_More 0x00001000 /* more desc in this frame */
76 #define AR_DestIdx 0x000fe000 /* destination table index */
77 #define AR_DestIdx_S 13
78 #define AR_FrmType 0x00f00000 /* frame type indication */
79 #define AR_FrmType_S 20
80 #define AR_NoAck 0x01000000 /* No ACK flag */
81 #define AR_CompProc 0x06000000 /* compression processing */
82 #define AR_CompProc_S 25
83 #define AR_CompIVLen 0x18000000 /* length of frame IV */
84 #define AR_CompIVLen_S 27
85 #define AR_CompICVLen 0x60000000 /* length of frame ICV */
86 #define AR_CompICVLen_S 29
87 /* bit 31 is reserved */
90 #define AR_RTSCTSDuration 0x00007fff /* RTS/CTS duration */
91 #define AR_RTSCTSDuration_S 0
92 #define AR_DurUpdateEna 0x00008000 /* frame duration update ctl */
93 #define AR_XmitDataTries0 0x000f0000 /* series 0 max attempts */
94 #define AR_XmitDataTries0_S 16
95 #define AR_XmitDataTries1 0x00f00000 /* series 1 max attempts */
96 #define AR_XmitDataTries1_S 20
97 #define AR_XmitDataTries2 0x0f000000 /* series 2 max attempts */
98 #define AR_XmitDataTries2_S 24
99 #define AR_XmitDataTries3 0xf0000000 /* series 3 max attempts */
100 #define AR_XmitDataTries3_S 28
103 #define AR_XmitRate0 0x0000001f /* series 0 tx rate */
104 #define AR_XmitRate0_S 0
105 #define AR_XmitRate1 0x000003e0 /* series 1 tx rate */
106 #define AR_XmitRate1_S 5
107 #define AR_XmitRate2 0x00007c00 /* series 2 tx rate */
108 #define AR_XmitRate2_S 10
109 #define AR_XmitRate3 0x000f8000 /* series 3 tx rate */
110 #define AR_XmitRate3_S 15
111 #define AR_RTSCTSRate 0x01f00000 /* RTS or CTS rate */
112 #define AR_RTSCTSRate_S 20
113 /* bits 25-31 are reserved */
116 /* AR_BufLen 0x00000fff data buffer length */
117 /* bit 12 is reserved */
118 #define AR_RxInterReq 0x00002000 /* RX interrupt request */
119 /* bits 14-31 are reserved */
121 /* TX ds_txstatus0 */
122 #define AR_FrmXmitOK 0x00000001 /* TX success */
123 #define AR_ExcessiveRetries 0x00000002 /* excessive retries */
124 #define AR_FIFOUnderrun 0x00000004 /* TX FIFO underrun */
125 #define AR_Filtered 0x00000008 /* TX filter indication */
126 #define AR_RTSFailCnt 0x000000f0 /* RTS failure count */
127 #define AR_RTSFailCnt_S 4
128 #define AR_DataFailCnt 0x00000f00 /* Data failure count */
129 #define AR_DataFailCnt_S 8
130 #define AR_VirtCollCnt 0x0000f000 /* virtual collision count */
131 #define AR_VirtCollCnt_S 12
132 #define AR_SendTimestamp 0xffff0000 /* TX timestamp */
133 #define AR_SendTimestamp_S 16
135 /* RX ds_rxstatus0 */
136 #define AR_DataLen 0x00000fff /* RX data length */
137 /* AR_More 0x00001000 more desc in this frame */
138 #define AR_DecompCRCErr 0x00002000 /* decompression CRC error */
139 /* bit 14 is reserved */
140 #define AR_RcvRate 0x000f8000 /* reception rate */
141 #define AR_RcvRate_S 15
142 #define AR_RcvSigStrength 0x0ff00000 /* receive signal strength */
143 #define AR_RcvSigStrength_S 20
144 #define AR_RcvAntenna 0xf0000000 /* receive antenaa */
145 #define AR_RcvAntenna_S 28
147 /* TX ds_txstatus1 */
148 #define AR_Done 0x00000001 /* descripter complete */
149 #define AR_SeqNum 0x00001ffe /* TX sequence number */
150 #define AR_SeqNum_S 1
151 #define AR_AckSigStrength 0x001fe000 /* strength of ACK */
152 #define AR_AckSigStrength_S 13
153 #define AR_FinalTSIndex 0x00600000 /* final TX attempt series ix */
154 #define AR_FinalTSIndex_S 21
155 #define AR_CompSuccess 0x00800000 /* compression status */
156 #define AR_XmitAtenna 0x01000000 /* transmit antenna */
157 /* bits 25-31 are reserved */
159 /* RX ds_rxstatus1 */
160 /* AR_Done 0x00000001 descripter complete */
161 #define AR_FrmRcvOK 0x00000002 /* frame reception success */
162 #define AR_CRCErr 0x00000004 /* CRC error */
163 #define AR_DecryptCRCErr 0x00000008 /* Decryption CRC fiailure */
164 #define AR_PHYErr 0x00000010 /* PHY error */
165 #define AR_MichaelErr 0x00000020 /* Michae MIC decrypt error */
166 /* bits 6-7 are reserved */
167 #define AR_KeyIdxValid 0x00000100 /* decryption key index valid */
168 #define AR_KeyIdx 0x0000fe00 /* Decryption key index */
169 #define AR_KeyIdx_S 9
170 #define AR_RcvTimestamp 0x7fff0000 /* timestamp */
171 #define AR_RcvTimestamp_S 16
172 #define AR_KeyCacheMiss 0x80000000 /* key cache miss indication */
174 /* NB: phy error code overlays key index and valid fields */
175 #define AR_PHYErrCode 0x0000ff00 /* PHY error code */
176 #define AR_PHYErrCode_S 8
178 #endif /* _ATH_AR5212_DESC_H_ */