2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24 #include "ah_internal.h"
27 #include "ah_eeprom_v14.h"
29 #include "ar5416/ar5416.h"
30 #include "ar5416/ar5416reg.h"
31 #include "ar5416/ar5416phy.h"
33 #include "ar5416/ar5416.ini"
35 static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
37 static void ar5416DisablePCIE(struct ath_hal *ah);
38 static void ar5416WriteIni(struct ath_hal *ah,
39 const struct ieee80211_channel *chan);
40 static void ar5416SpurMitigate(struct ath_hal *ah,
41 const struct ieee80211_channel *chan);
44 ar5416AniSetup(struct ath_hal *ah)
46 static const struct ar5212AniParams aniparams = {
47 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
48 .totalSizeDesired = { -55, -55, -55, -55, -62 },
49 .coarseHigh = { -14, -14, -14, -14, -12 },
50 .coarseLow = { -64, -64, -64, -64, -70 },
51 .firpwr = { -78, -78, -78, -78, -80 },
52 .maxSpurImmunityLevel = 7,
53 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 },
54 .maxFirstepLevel = 2, /* levels 0..2 */
55 .firstep = { 0, 4, 8 },
64 /* NB: disable ANI noise immmunity for reliable RIFS rx */
65 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL);
66 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
70 * AR5416 doesn't do OLC or temperature compensation.
73 ar5416olcInit(struct ath_hal *ah)
78 ar5416olcTempCompensation(struct ath_hal *ah)
83 * Attach for an AR5416 part.
86 ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
87 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status)
89 struct ath_hal_5212 *ahp;
92 ahp = &ahp5416->ah_5212;
93 ar5212InitState(ahp, devid, sc, st, sh, status);
96 /* override 5212 methods for our needs */
97 ah->ah_magic = AR5416_MAGIC;
98 ah->ah_getRateTable = ar5416GetRateTable;
99 ah->ah_detach = ar5416Detach;
101 /* Reset functions */
102 ah->ah_reset = ar5416Reset;
103 ah->ah_phyDisable = ar5416PhyDisable;
104 ah->ah_disable = ar5416Disable;
105 ah->ah_configPCIE = ar5416ConfigPCIE;
106 ah->ah_disablePCIE = ar5416DisablePCIE;
107 ah->ah_perCalibration = ar5416PerCalibration;
108 ah->ah_perCalibrationN = ar5416PerCalibrationN;
109 ah->ah_resetCalValid = ar5416ResetCalValid;
110 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit;
111 ah->ah_setTxPower = ar5416SetTransmitPower;
112 ah->ah_setBoardValues = ar5416SetBoardValues;
114 /* Transmit functions */
115 ah->ah_stopTxDma = ar5416StopTxDma;
116 ah->ah_setupTxDesc = ar5416SetupTxDesc;
117 ah->ah_setupXTxDesc = ar5416SetupXTxDesc;
118 ah->ah_fillTxDesc = ar5416FillTxDesc;
119 ah->ah_procTxDesc = ar5416ProcTxDesc;
120 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates;
121 ah->ah_setupTxQueue = ar5416SetupTxQueue;
122 ah->ah_resetTxQueue = ar5416ResetTxQueue;
124 /* Receive Functions */
125 ah->ah_getRxFilter = ar5416GetRxFilter;
126 ah->ah_setRxFilter = ar5416SetRxFilter;
127 ah->ah_stopDmaReceive = ar5416StopDmaReceive;
128 ah->ah_startPcuReceive = ar5416StartPcuReceive;
129 ah->ah_stopPcuReceive = ar5416StopPcuReceive;
130 ah->ah_setupRxDesc = ar5416SetupRxDesc;
131 ah->ah_procRxDesc = ar5416ProcRxDesc;
132 ah->ah_rxMonitor = ar5416RxMonitor;
133 ah->ah_aniPoll = ar5416AniPoll;
134 ah->ah_procMibEvent = ar5416ProcessMibIntr;
137 ah->ah_getCapability = ar5416GetCapability;
138 ah->ah_setCapability = ar5416SetCapability;
139 ah->ah_getDiagState = ar5416GetDiagState;
140 ah->ah_setLedState = ar5416SetLedState;
141 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput;
142 ah->ah_gpioCfgInput = ar5416GpioCfgInput;
143 ah->ah_gpioGet = ar5416GpioGet;
144 ah->ah_gpioSet = ar5416GpioSet;
145 ah->ah_gpioSetIntr = ar5416GpioSetIntr;
146 ah->ah_getTsf64 = ar5416GetTsf64;
147 ah->ah_setTsf64 = ar5416SetTsf64;
148 ah->ah_resetTsf = ar5416ResetTsf;
149 ah->ah_getRfGain = ar5416GetRfgain;
150 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch;
151 ah->ah_setDecompMask = ar5416SetDecompMask;
152 ah->ah_setCoverageClass = ar5416SetCoverageClass;
153 ah->ah_setQuiet = ar5416SetQuiet;
154 ah->ah_getMibCycleCounts = ar5416GetMibCycleCounts;
155 ah->ah_setChainMasks = ar5416SetChainMasks;
157 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry;
158 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry;
161 ah->ah_enableDfs = ar5416EnableDfs;
162 ah->ah_getDfsThresh = ar5416GetDfsThresh;
163 ah->ah_getDfsDefaultThresh = ar5416GetDfsDefaultThresh;
164 ah->ah_procRadarEvent = ar5416ProcessRadarEvent;
165 ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled;
167 /* Spectral Scan Functions */
168 ah->ah_spectralConfigure = ar5416ConfigureSpectralScan;
169 ah->ah_spectralGetConfig = ar5416GetSpectralParams;
170 ah->ah_spectralStart = ar5416StartSpectralScan;
171 ah->ah_spectralStop = ar5416StopSpectralScan;
172 ah->ah_spectralIsEnabled = ar5416IsSpectralEnabled;
173 ah->ah_spectralIsActive = ar5416IsSpectralActive;
175 /* Power Management Functions */
176 ah->ah_setPowerMode = ar5416SetPowerMode;
178 /* Beacon Management Functions */
179 ah->ah_setBeaconTimers = ar5416SetBeaconTimers;
180 ah->ah_beaconInit = ar5416BeaconInit;
181 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers;
182 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers;
183 ah->ah_getNextTBTT = ar5416GetNextTBTT;
185 /* 802.11n Functions */
186 ah->ah_chainTxDesc = ar5416ChainTxDesc;
187 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc;
188 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc;
189 ah->ah_set11nRateScenario = ar5416Set11nRateScenario;
190 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst;
191 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle;
192 ah->ah_set11nAggrLast = ar5416Set11nAggrLast;
193 ah->ah_clr11nAggr = ar5416Clr11nAggr;
194 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration;
195 ah->ah_get11nExtBusy = ar5416Get11nExtBusy;
196 ah->ah_set11nMac2040 = ar5416Set11nMac2040;
197 ah->ah_get11nRxClear = ar5416Get11nRxClear;
198 ah->ah_set11nRxClear = ar5416Set11nRxClear;
199 ah->ah_set11nVirtMoreFrag = ar5416Set11nVirtualMoreFrag;
201 /* Interrupt functions */
202 ah->ah_isInterruptPending = ar5416IsInterruptPending;
203 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts;
204 ah->ah_setInterrupts = ar5416SetInterrupts;
206 /* Bluetooth Coexistence functions */
207 ah->ah_btCoexSetInfo = ar5416SetBTCoexInfo;
208 ah->ah_btCoexSetConfig = ar5416BTCoexConfig;
209 ah->ah_btCoexSetQcuThresh = ar5416BTCoexSetQcuThresh;
210 ah->ah_btCoexSetWeights = ar5416BTCoexSetWeights;
211 ah->ah_btCoexSetBmissThresh = ar5416BTCoexSetupBmissThresh;
212 ah->ah_btCoexSetParameter = ar5416BTCoexSetParameter;
213 ah->ah_btCoexDisable = ar5416BTCoexDisable;
214 ah->ah_btCoexEnable = ar5416BTCoexEnable;
215 AH5416(ah)->ah_btCoexSetDiversity = ar5416BTCoexAntennaDiversity;
217 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes;
218 ahp->ah_priv.ah_eepromRead = ar5416EepromRead;
219 #ifdef AH_SUPPORT_WRITE_EEPROM
220 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite;
222 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits;
225 AH5416(ah)->ah_writeIni = ar5416WriteIni;
226 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate;
228 /* Internal baseband ops */
229 AH5416(ah)->ah_initPLL = ar5416InitPLL;
231 /* Internal calibration ops */
232 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware;
234 /* Internal TX power control related operations */
235 AH5416(ah)->ah_olcInit = ar5416olcInit;
236 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation;
237 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable;
240 * Start by setting all Owl devices to 2x2
242 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK;
243 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK;
245 /* Enable all ANI functions to begin with */
246 AH5416(ah)->ah_ani_function = 0xffffffff;
248 /* Set overridable ANI methods */
249 AH5212(ah)->ah_aniControl = ar5416AniControl;
252 * Default FIFO Trigger levels
254 * These define how filled the TX FIFO needs to be before
255 * the baseband begins to be given some data.
257 * To be paranoid, we ensure that the TX trigger level always
258 * has at least enough space for two TX DMA to occur.
259 * The TX DMA size is currently hard-coded to AR_TXCFG_DMASZ_128B.
260 * That means we need to leave at least 256 bytes available in
263 #define AR_FTRIG_512B 0x00000080 // 5 bits total
265 * AR9285/AR9271 have half the size TX FIFO compared to
268 if (AR_SREV_KITE(ah) || AR_SREV_9271(ah)) {
269 AH5212(ah)->ah_txTrigLev = (AR_FTRIG_256B >> AR_FTRIG_S);
270 AH5212(ah)->ah_maxTxTrigLev = ((2048 / 64) - 1);
272 AH5212(ah)->ah_txTrigLev = (AR_FTRIG_512B >> AR_FTRIG_S);
273 AH5212(ah)->ah_maxTxTrigLev = ((4096 / 64) - 1);
277 /* And now leave some headspace - 256 bytes */
278 AH5212(ah)->ah_maxTxTrigLev -= 4;
282 ar5416GetRadioRev(struct ath_hal *ah)
287 /* Read Radio Chip Rev Extract */
288 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
289 for (i = 0; i < 8; i++)
290 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
291 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
292 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
293 return ath_hal_reverseBits(val, 8);
297 * Attach for an AR5416 part.
299 static struct ath_hal *
300 ar5416Attach(uint16_t devid, HAL_SOFTC sc,
301 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
302 HAL_OPS_CONFIG *ah_config, HAL_STATUS *status)
304 struct ath_hal_5416 *ahp5416;
305 struct ath_hal_5212 *ahp;
311 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
312 __func__, sc, (void*) st, (void*) sh);
314 /* NB: memory is returned zero'd */
315 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) +
316 /* extra space for Owl 2.1/2.2 WAR */
319 if (ahp5416 == AH_NULL) {
320 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
321 "%s: cannot allocate memory for state block\n", __func__);
322 *status = HAL_ENOMEM;
325 ar5416InitState(ahp5416, devid, sc, st, sh, status);
326 ahp = &ahp5416->ah_5212;
327 ah = &ahp->ah_priv.h;
329 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
331 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__);
336 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
337 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__);
341 /* Read Revisions from Chips before taking out of reset */
342 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
343 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S;
344 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION;
345 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE);
347 /* setup common ini data; rf backends handle remainder */
348 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6);
349 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2);
351 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3);
352 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2);
353 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2);
354 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2);
355 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3);
356 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3);
357 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2);
358 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2);
360 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */
361 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n");
363 uint32_t *data; /* NB: !const */
366 /* override CLKDRV value */
367 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac));
368 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1];
369 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0;
372 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2);
373 ar5416AttachPCIE(ah);
375 ecode = ath_hal_v14EepromAttach(ah);
379 if (!ar5416ChipReset(ah, AH_NULL, HAL_RESET_NORMAL)) { /* reset chip */
380 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
386 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
388 if (!ar5212ChipTest(ah)) {
389 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
391 ecode = HAL_ESELFTEST;
396 * Set correct Baseband to analog shift
397 * setting to access analog chips.
399 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
401 /* Read Radio Chip Rev Extract */
402 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
403 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
404 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */
405 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */
406 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */
407 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */
410 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
412 * When RF_Silen is used the analog chip is reset.
413 * So when the system boots with radio switch off
414 * the RF chip rev reads back as zero and we need
415 * to use the mac+phy revs to set the radio rev.
417 AH_PRIVATE(ah)->ah_analog5GhzRev =
418 AR_RAD5133_SREV_MAJOR;
421 /* NB: silently accept anything in release code per Atheros */
423 HALDEBUG(ah, HAL_DEBUG_ANY,
424 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
425 "this driver\n", __func__,
426 AH_PRIVATE(ah)->ah_analog5GhzRev);
427 ecode = HAL_ENOTSUPP;
433 * Got everything we need now to setup the capabilities.
435 if (!ar5416FillCapabilityInfo(ah)) {
440 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
441 if (ecode != HAL_OK) {
442 HALDEBUG(ah, HAL_DEBUG_ANY,
443 "%s: error getting mac address from EEPROM\n", __func__);
446 /* XXX How about the serial number ? */
447 /* Read Reg Domain */
448 AH_PRIVATE(ah)->ah_currentRD =
449 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
450 AH_PRIVATE(ah)->ah_currentRDext =
451 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL);
454 * ah_miscMode is populated by ar5416FillCapabilityInfo()
455 * starting from griffin. Set here to make sure that
456 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
457 * placed into hardware.
459 if (ahp->ah_miscMode != 0)
460 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
462 rfStatus = ar2133RfAttach(ah, &ecode);
464 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
469 ar5416AniSetup(ah); /* Anti Noise Immunity */
471 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
472 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
473 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
474 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
475 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
476 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
478 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
480 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
485 ar5416Detach((struct ath_hal *) ahp);
492 ar5416Detach(struct ath_hal *ah)
494 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__);
496 HALASSERT(ah != AH_NULL);
497 HALASSERT(ah->ah_magic == AR5416_MAGIC);
499 /* Make sure that chip is awake before writing to it */
500 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
501 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
502 "%s: failed to wake up chip\n",
508 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE);
509 ath_hal_eepromDetach(ah);
514 ar5416AttachPCIE(struct ath_hal *ah)
516 if (AH_PRIVATE(ah)->ah_ispcie)
517 ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE);
519 ath_hal_disablePCIE(ah);
523 ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
526 /* This is only applicable for AR5418 (AR5416 PCIe) */
527 if (! AH_PRIVATE(ah)->ah_ispcie)
531 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
535 if (power_off) { /* Power-off */
536 /* clear bit 19 to disable L1 */
537 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
538 } else { /* Power-on */
539 /* Set default WAR values for Owl */
540 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
542 /* set bit 19 to allow forcing of pcie core into L1 state */
543 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
548 * Disable PCIe PHY if PCIe isn't used.
551 ar5416DisablePCIE(struct ath_hal *ah)
555 if (AH_PRIVATE(ah)->ah_ispcie)
558 /* .. Only applicable for AR5416v2 or later */
559 if (! (AR_SREV_OWL(ah) && AR_SREV_OWL_20_OR_LATER(ah)))
562 OS_REG_WRITE_BUFFER_ENABLE(ah);
565 * Disable the PCIe PHY.
567 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
568 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
569 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
570 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
571 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
572 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
573 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
574 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
575 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
577 /* Load the new settings */
578 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
580 OS_REG_WRITE_BUFFER_FLUSH(ah);
581 OS_REG_WRITE_BUFFER_DISABLE(ah);
585 ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
587 u_int modesIndex, freqIndex;
590 /* Setup the indices for the next set of register array writes */
591 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
592 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
594 if (IEEE80211_IS_CHAN_HT40(chan))
596 else if (IEEE80211_IS_CHAN_108G(chan))
602 if (IEEE80211_IS_CHAN_HT40(chan) ||
603 IEEE80211_IS_CHAN_TURBO(chan))
609 /* Set correct Baseband to analog shift setting to access analog chips. */
610 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
615 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
617 /* NB: only required for Sowl */
618 if (AR_SREV_SOWL(ah))
619 ar5416EepromSetAddac(ah, chan);
621 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1,
623 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
625 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes,
626 modesIndex, regWrites);
627 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common,
630 /* XXX updated regWrites? */
631 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
635 * Convert to baseband spur frequency given input channel frequency
636 * and compute register settings below.
640 ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan)
642 uint16_t freq = ath_hal_gethwchannel(ah, chan);
643 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
644 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 };
645 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
646 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 };
647 static const int inc[4] = { 0, 100, 0, 0 };
649 int bb_spur = AR_NO_SPUR;
652 int spur_delta_phase;
654 int upper, lower, cur_vit_mask;
663 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan);
665 OS_MEMZERO(mask_m, sizeof(mask_m));
666 OS_MEMZERO(mask_p, sizeof(mask_p));
669 * Need to verify range +/- 9.5 for static ht20, otherwise spur
670 * is out-of-band and can be ignored.
672 /* XXX ath9k changes */
673 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
674 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz);
675 if (AR_NO_SPUR == cur_bb_spur)
677 cur_bb_spur = cur_bb_spur - (freq * 10);
678 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
679 bb_spur = cur_bb_spur;
683 if (AR_NO_SPUR == bb_spur)
688 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0));
689 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
690 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
691 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
692 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
694 OS_REG_WRITE_BUFFER_ENABLE(ah);
696 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new);
698 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
699 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
700 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
701 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
702 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
703 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new);
705 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz
706 * config, no offset for HT20.
707 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20,
710 spur_delta_phase = ((bb_spur * 524288) / 100) &
711 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
713 * in 11A mode the denominator of spur_freq_sd should be 40 and
714 * it should be 44 in 11G
716 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400;
717 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
719 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
720 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
721 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
722 OS_REG_WRITE(ah, AR_PHY_TIMING11, new);
725 * ============================================
726 * pilot mask 1 [31:0] = +6..-26, no 0 bin
727 * pilot mask 2 [19:0] = +26..+7
729 * channel mask 1 [31:0] = +6..-26, no 0 bin
730 * channel mask 2 [19:0] = +26..+7
737 for (i = 0; i < 4; i++) {
741 for (bp = 0; bp < 30; bp++) {
742 if ((cur_bin > lower) && (cur_bin < upper)) {
743 pilot_mask = pilot_mask | 0x1 << bp;
744 chan_mask = chan_mask | 0x1 << bp;
749 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
750 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask);
753 /* =================================================
754 * viterbi mask 1 based on channel magnitude
756 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c)
757 * [1 2 2 1] for -9.6 or [1 2 1] for +16
758 * - enable_mask_ppm, all bins move with freq
760 * - mask_select, 8 bits for rates (reg 67,0x990c)
761 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c)
762 * choose which mask to use mask or mask2
766 * viterbi mask 2 2nd set for per data rate puncturing
768 * - mask_select, 8 bits for rates (reg 67)
769 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994)
770 * [1 2 2 1] for -9.6 or [1 2 1] for +16
776 for (i = 0; i < 123; i++) {
777 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
778 if ((abs(cur_vit_mask - bin)) < 75) {
783 if (cur_vit_mask < 0) {
784 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
786 mask_p[cur_vit_mask / 100] = mask_amt;
792 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
793 | (mask_m[48] << 26) | (mask_m[49] << 24)
794 | (mask_m[50] << 22) | (mask_m[51] << 20)
795 | (mask_m[52] << 18) | (mask_m[53] << 16)
796 | (mask_m[54] << 14) | (mask_m[55] << 12)
797 | (mask_m[56] << 10) | (mask_m[57] << 8)
798 | (mask_m[58] << 6) | (mask_m[59] << 4)
799 | (mask_m[60] << 2) | (mask_m[61] << 0);
800 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
801 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
803 tmp_mask = (mask_m[31] << 28)
804 | (mask_m[32] << 26) | (mask_m[33] << 24)
805 | (mask_m[34] << 22) | (mask_m[35] << 20)
806 | (mask_m[36] << 18) | (mask_m[37] << 16)
807 | (mask_m[48] << 14) | (mask_m[39] << 12)
808 | (mask_m[40] << 10) | (mask_m[41] << 8)
809 | (mask_m[42] << 6) | (mask_m[43] << 4)
810 | (mask_m[44] << 2) | (mask_m[45] << 0);
811 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
812 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
814 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
815 | (mask_m[18] << 26) | (mask_m[18] << 24)
816 | (mask_m[20] << 22) | (mask_m[20] << 20)
817 | (mask_m[22] << 18) | (mask_m[22] << 16)
818 | (mask_m[24] << 14) | (mask_m[24] << 12)
819 | (mask_m[25] << 10) | (mask_m[26] << 8)
820 | (mask_m[27] << 6) | (mask_m[28] << 4)
821 | (mask_m[29] << 2) | (mask_m[30] << 0);
822 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
823 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
825 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28)
826 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24)
827 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20)
828 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16)
829 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12)
830 | (mask_m[10] << 10) | (mask_m[11] << 8)
831 | (mask_m[12] << 6) | (mask_m[13] << 4)
832 | (mask_m[14] << 2) | (mask_m[15] << 0);
833 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
834 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
836 tmp_mask = (mask_p[15] << 28)
837 | (mask_p[14] << 26) | (mask_p[13] << 24)
838 | (mask_p[12] << 22) | (mask_p[11] << 20)
839 | (mask_p[10] << 18) | (mask_p[ 9] << 16)
840 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12)
841 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8)
842 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4)
843 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0);
844 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
845 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
847 tmp_mask = (mask_p[30] << 28)
848 | (mask_p[29] << 26) | (mask_p[28] << 24)
849 | (mask_p[27] << 22) | (mask_p[26] << 20)
850 | (mask_p[25] << 18) | (mask_p[24] << 16)
851 | (mask_p[23] << 14) | (mask_p[22] << 12)
852 | (mask_p[21] << 10) | (mask_p[20] << 8)
853 | (mask_p[19] << 6) | (mask_p[18] << 4)
854 | (mask_p[17] << 2) | (mask_p[16] << 0);
855 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
856 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
858 tmp_mask = (mask_p[45] << 28)
859 | (mask_p[44] << 26) | (mask_p[43] << 24)
860 | (mask_p[42] << 22) | (mask_p[41] << 20)
861 | (mask_p[40] << 18) | (mask_p[39] << 16)
862 | (mask_p[38] << 14) | (mask_p[37] << 12)
863 | (mask_p[36] << 10) | (mask_p[35] << 8)
864 | (mask_p[34] << 6) | (mask_p[33] << 4)
865 | (mask_p[32] << 2) | (mask_p[31] << 0);
866 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
867 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
869 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
870 | (mask_p[59] << 26) | (mask_p[58] << 24)
871 | (mask_p[57] << 22) | (mask_p[56] << 20)
872 | (mask_p[55] << 18) | (mask_p[54] << 16)
873 | (mask_p[53] << 14) | (mask_p[52] << 12)
874 | (mask_p[51] << 10) | (mask_p[50] << 8)
875 | (mask_p[49] << 6) | (mask_p[48] << 4)
876 | (mask_p[47] << 2) | (mask_p[46] << 0);
877 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
878 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
880 OS_REG_WRITE_BUFFER_FLUSH(ah);
881 OS_REG_WRITE_BUFFER_DISABLE(ah);
885 * Fill all software cached or static hardware state information.
886 * Return failure if capabilities are to come from EEPROM and
890 ar5416FillCapabilityInfo(struct ath_hal *ah)
892 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
893 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps;
896 /* Construct wireless mode from EEPROM */
897 pCap->halWirelessModes = 0;
898 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
899 pCap->halWirelessModes |= HAL_MODE_11A
901 | HAL_MODE_11NA_HT40PLUS
902 | HAL_MODE_11NA_HT40MINUS
905 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) {
906 pCap->halWirelessModes |= HAL_MODE_11G
908 | HAL_MODE_11NG_HT40PLUS
909 | HAL_MODE_11NG_HT40MINUS
911 pCap->halWirelessModes |= HAL_MODE_11A
913 | HAL_MODE_11NA_HT40PLUS
914 | HAL_MODE_11NA_HT40MINUS
918 pCap->halLow2GhzChan = 2312;
919 pCap->halHigh2GhzChan = 2732;
921 pCap->halLow5GhzChan = 4915;
922 pCap->halHigh5GhzChan = 6100;
924 pCap->halCipherCkipSupport = AH_FALSE;
925 pCap->halCipherTkipSupport = AH_TRUE;
926 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
928 pCap->halMicCkipSupport = AH_FALSE;
929 pCap->halMicTkipSupport = AH_TRUE;
930 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES);
932 * Starting with Griffin TX+RX mic keys can be combined
933 * in one key cache slot.
935 pCap->halTkipMicTxRxKeySupport = AH_TRUE;
936 pCap->halChanSpreadSupport = AH_TRUE;
937 pCap->halSleepAfterBeaconBroken = AH_TRUE;
939 pCap->halCompressSupport = AH_FALSE;
940 pCap->halBurstSupport = AH_TRUE;
941 pCap->halFastFramesSupport = AH_TRUE;
942 pCap->halChapTuningSupport = AH_TRUE;
943 pCap->halTurboPrimeSupport = AH_TRUE;
945 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G;
947 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */
948 pCap->halNumMRRetries = 4; /* Hardware supports 4 MRR */
949 pCap->halNumTxMaps = 1; /* Single TX ptr per descr */
950 pCap->halVEOLSupport = AH_TRUE;
951 pCap->halBssIdMaskSupport = AH_TRUE;
952 pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */
953 pCap->halTsfAddSupport = AH_TRUE;
954 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */
955 pCap->halSpectralScanSupport = AH_FALSE; /* AR9280 and later */
957 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK)
958 pCap->halTotalQueues = val;
960 pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
962 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK)
963 pCap->halKeyCacheSize = val;
965 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE;
967 /* XXX Which chips? */
968 pCap->halChanHalfRate = AH_TRUE;
969 pCap->halChanQuarterRate = AH_TRUE;
971 pCap->halTxTstampPrecision = 32;
972 pCap->halRxTstampPrecision = 32;
973 pCap->halHwPhyCounterSupport = AH_TRUE;
974 pCap->halIntrMask = HAL_INT_COMMON
986 pCap->halFastCCSupport = AH_TRUE;
987 pCap->halNumGpioPins = 14;
988 pCap->halWowSupport = AH_FALSE;
989 pCap->halWowMatchPatternExact = AH_FALSE;
990 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */
991 pCap->halAutoSleepSupport = AH_FALSE;
992 pCap->hal4kbSplitTransSupport = AH_TRUE;
993 /* Disable this so Block-ACK works correctly */
994 pCap->halHasRxSelfLinkedTail = AH_FALSE;
995 #if 0 /* XXX not yet */
996 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ);
997 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ);
999 pCap->halHTSupport = AH_TRUE;
1000 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL);
1001 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */
1002 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL);
1003 /* AR5416 may have 3 antennas but is a 2x2 stream device */
1004 pCap->halTxStreams = 2;
1005 pCap->halRxStreams = 2;
1008 * If the TX or RX chainmask has less than 2 chains active,
1009 * mark it as a 1-stream device for the relevant stream.
1011 if (owl_get_ntxchains(pCap->halTxChainMask) == 1)
1012 pCap->halTxStreams = 1;
1014 if (owl_get_ntxchains(pCap->halRxChainMask) == 1)
1015 pCap->halRxStreams = 1;
1016 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */
1017 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */
1018 pCap->halForcePpmSupport = AH_TRUE;
1019 pCap->halEnhancedPmSupport = AH_TRUE;
1020 pCap->halBssidMatchSupport = AH_TRUE;
1021 pCap->halGTTSupport = AH_TRUE;
1022 pCap->halCSTSupport = AH_TRUE;
1023 pCap->halEnhancedDfsSupport = AH_FALSE;
1025 * BB Read WAR: this is only for AR5008/AR9001 NICs
1026 * It is also set individually in the AR91xx attach functions.
1028 if (AR_SREV_OWL(ah))
1029 pCap->halHasBBReadWar = AH_TRUE;
1031 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
1032 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
1033 /* NB: enabled by default */
1034 ahpriv->ah_rfkillEnabled = AH_TRUE;
1035 pCap->halRfSilentSupport = AH_TRUE;
1039 * The MAC will mark frames as RXed if there's a descriptor
1040 * to write them to. So if it hits a self-linked final descriptor,
1041 * it'll keep ACKing frames even though they're being silently
1042 * dropped. Thus, this particular feature of the driver can't
1043 * be used for 802.11n devices.
1045 ahpriv->ah_rxornIsFatal = AH_FALSE;
1048 * If it's a PCI NIC, ask the HAL OS layer to serialise
1049 * register access, or SMP machines may cause the hardware
1050 * to hang. This is applicable to AR5416 and AR9220; I'm not
1051 * sure about AR9160 or AR9227.
1053 if (! AH_PRIVATE(ah)->ah_ispcie)
1054 pCap->halSerialiseRegWar = 1;
1057 * AR5416 and later NICs support MYBEACON filtering.
1059 pCap->halRxDoMyBeacon = AH_TRUE;
1065 ar5416Probe(uint16_t vendorid, uint16_t devid)
1067 if (vendorid == ATHEROS_VENDOR_ID) {
1068 if (devid == AR5416_DEVID_PCI)
1069 return "Atheros 5416";
1070 if (devid == AR5416_DEVID_PCIE)
1071 return "Atheros 5418";
1075 AH_CHIP(AR5416, ar5416Probe, ar5416Attach);