2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2008 Atheros Communications, Inc.
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
24 #include "ah_internal.h"
27 #include "ah_eeprom_v14.h" /* XXX for tx/rx gain */
28 #include "ah_eeprom_9287.h"
30 #include "ar9002/ar9280.h"
31 #include "ar9002/ar9287.h"
32 #include "ar5416/ar5416reg.h"
33 #include "ar5416/ar5416phy.h"
35 #include "ar9002/ar9287_cal.h"
36 #include "ar9002/ar9287_reset.h"
37 #include "ar9002/ar9287_olc.h"
39 #include "ar9002/ar9287.ini"
41 static const HAL_PERCAL_DATA ar9287_iq_cal = { /* single sample */
42 .calName = "IQ", .calType = IQ_MISMATCH_CAL,
43 .calNumSamples = MIN_CAL_SAMPLES,
44 .calCountMax = PER_MAX_LOG_COUNT,
45 .calCollect = ar5416IQCalCollect,
46 .calPostProc = ar5416IQCalibration
48 static const HAL_PERCAL_DATA ar9287_adc_gain_cal = { /* single sample */
49 .calName = "ADC Gain", .calType = ADC_GAIN_CAL,
50 .calNumSamples = MIN_CAL_SAMPLES,
51 .calCountMax = PER_MIN_LOG_COUNT,
52 .calCollect = ar5416AdcGainCalCollect,
53 .calPostProc = ar5416AdcGainCalibration
55 static const HAL_PERCAL_DATA ar9287_adc_dc_cal = { /* single sample */
56 .calName = "ADC DC", .calType = ADC_DC_CAL,
57 .calNumSamples = MIN_CAL_SAMPLES,
58 .calCountMax = PER_MIN_LOG_COUNT,
59 .calCollect = ar5416AdcDcCalCollect,
60 .calPostProc = ar5416AdcDcCalibration
62 static const HAL_PERCAL_DATA ar9287_adc_init_dc_cal = {
63 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL,
64 .calNumSamples = MIN_CAL_SAMPLES,
65 .calCountMax = INIT_LOG_COUNT,
66 .calCollect = ar5416AdcDcCalCollect,
67 .calPostProc = ar5416AdcDcCalibration
70 static void ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore,
72 static void ar9287DisablePCIE(struct ath_hal *ah);
73 static HAL_BOOL ar9287FillCapabilityInfo(struct ath_hal *ah);
74 static void ar9287WriteIni(struct ath_hal *ah,
75 const struct ieee80211_channel *chan);
78 ar9287AniSetup(struct ath_hal *ah)
81 * These are the parameters from the AR5416 ANI code;
82 * they likely need quite a bit of adjustment for the
85 static const struct ar5212AniParams aniparams = {
86 .maxNoiseImmunityLevel = 4, /* levels 0..4 */
87 .totalSizeDesired = { -55, -55, -55, -55, -62 },
88 .coarseHigh = { -14, -14, -14, -14, -12 },
89 .coarseLow = { -64, -64, -64, -64, -70 },
90 .firpwr = { -78, -78, -78, -78, -80 },
91 .maxSpurImmunityLevel = 7,
92 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 },
93 .maxFirstepLevel = 2, /* levels 0..2 */
94 .firstep = { 0, 4, 8 },
103 /* NB: disable ANI noise immmunity for reliable RIFS rx */
104 AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL;
106 /* NB: ANI is not enabled yet */
107 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE);
111 * Attach for an AR9287 part.
113 static struct ath_hal *
114 ar9287Attach(uint16_t devid, HAL_SOFTC sc,
115 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata,
116 HAL_OPS_CONFIG *ah_config,
119 struct ath_hal_9287 *ahp9287;
120 struct ath_hal_5212 *ahp;
125 int8_t pwr_table_offset;
127 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n",
128 __func__, sc, (void*) st, (void*) sh);
130 /* NB: memory is returned zero'd */
131 ahp9287 = ath_hal_malloc(sizeof (struct ath_hal_9287));
132 if (ahp9287 == AH_NULL) {
133 HALDEBUG(AH_NULL, HAL_DEBUG_ANY,
134 "%s: cannot allocate memory for state block\n", __func__);
135 *status = HAL_ENOMEM;
138 ahp = AH5212(ahp9287);
139 ah = &ahp->ah_priv.h;
141 ar5416InitState(AH5416(ah), devid, sc, st, sh, status);
143 if (eepromdata != AH_NULL) {
144 AH_PRIVATE(ah)->ah_eepromRead = ath_hal_EepromDataRead;
145 AH_PRIVATE(ah)->ah_eepromWrite = NULL;
146 ah->ah_eepromdata = eepromdata;
150 /* XXX override with 9280 specific state */
151 /* override 5416 methods for our needs */
152 AH5416(ah)->ah_initPLL = ar9280InitPLL;
154 ah->ah_setAntennaSwitch = ar9287SetAntennaSwitch;
155 ah->ah_configPCIE = ar9287ConfigPCIE;
156 ah->ah_disablePCIE = ar9287DisablePCIE;
158 AH5416(ah)->ah_cal.iqCalData.calData = &ar9287_iq_cal;
159 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9287_adc_gain_cal;
160 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9287_adc_dc_cal;
161 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9287_adc_init_dc_cal;
162 /* Better performance without ADC Gain Calibration */
163 AH5416(ah)->ah_cal.suppCals = ADC_DC_CAL | IQ_MISMATCH_CAL;
165 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate;
166 AH5416(ah)->ah_writeIni = ar9287WriteIni;
168 ah->ah_setTxPower = ar9287SetTransmitPower;
169 ah->ah_setBoardValues = ar9287SetBoardValues;
171 AH5416(ah)->ah_olcInit = ar9287olcInit;
172 AH5416(ah)->ah_olcTempCompensation = ar9287olcTemperatureCompensation;
173 //AH5416(ah)->ah_setPowerCalTable = ar9287SetPowerCalTable;
174 AH5416(ah)->ah_cal_initcal = ar9287InitCalHardware;
175 AH5416(ah)->ah_cal_pacal = ar9287PACal;
177 /* XXX NF calibration */
178 /* XXX Ini override? (IFS vars - since the kiwi mac clock is faster?) */
179 /* XXX what else is kiwi-specific in the radio/calibration pathway? */
181 AH5416(ah)->ah_rx_chainmask = AR9287_DEFAULT_RXCHAINMASK;
182 AH5416(ah)->ah_tx_chainmask = AR9287_DEFAULT_TXCHAINMASK;
184 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) {
186 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n",
192 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) {
193 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n",
198 /* Read Revisions from Chips before taking out of reset */
199 val = OS_REG_READ(ah, AR_SREV);
200 HALDEBUG(ah, HAL_DEBUG_ATTACH,
201 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n",
202 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION),
203 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION));
204 /* NB: include chip type to differentiate from pre-Sowl versions */
205 AH_PRIVATE(ah)->ah_macVersion =
206 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S;
207 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION);
208 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0;
210 /* Don't support Kiwi < 1.2; those are pre-release chips */
211 if (! AR_SREV_KIWI_12_OR_LATER(ah)) {
212 ath_hal_printf(ah, "[ath]: Kiwi < 1.2 is not supported\n");
217 /* setup common ini data; rf backends handle remainder */
218 HAL_INI_INIT(&ahp->ah_ini_modes, ar9287Modes_9287_1_1, 6);
219 HAL_INI_INIT(&ahp->ah_ini_common, ar9287Common_9287_1_1, 2);
221 /* If pcie_clock_req */
222 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
223 ar9287PciePhy_clkreq_always_on_L1_9287_1_1, 2);
225 /* XXX WoW ini values */
229 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes,
230 ar9287PciePhy_clkreq_off_L1_9287_1_1, 2);
233 /* Initialise Japan arrays */
234 HAL_INI_INIT(&ahp9287->ah_ini_cckFirNormal,
235 ar9287Common_normal_cck_fir_coeff_9287_1_1, 2);
236 HAL_INI_INIT(&ahp9287->ah_ini_cckFirJapan2484,
237 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1, 2);
239 ar5416AttachPCIE(ah);
241 ecode = ath_hal_9287EepromAttach(ah);
245 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */
246 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__);
251 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID);
253 if (!ar5212ChipTest(ah)) {
254 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n",
256 ecode = HAL_ESELFTEST;
261 * Set correct Baseband to analog shift
262 * setting to access analog chips.
264 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
266 /* Read Radio Chip Rev Extract */
267 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah);
268 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) {
269 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */
270 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */
273 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) {
274 AH_PRIVATE(ah)->ah_analog5GhzRev =
275 AR_RAD5133_SREV_MAJOR;
279 HALDEBUG(ah, HAL_DEBUG_ANY,
280 "%s: 5G Radio Chip Rev 0x%02X is not supported by "
281 "this driver\n", __func__,
282 AH_PRIVATE(ah)->ah_analog5GhzRev);
283 ecode = HAL_ENOTSUPP;
287 rfStatus = ar9287RfAttach(ah, &ecode);
289 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n",
295 * We only implement open-loop TX power control
296 * for the AR9287 in this codebase.
298 if (! ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) {
299 ath_hal_printf(ah, "[ath] AR9287 w/ closed-loop TX power control"
300 " isn't supported.\n");
301 ecode = HAL_ENOTSUPP;
306 * Check whether the power table offset isn't the default.
307 * This can occur with eeprom minor V21 or greater on Merlin.
309 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset);
310 if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB)
311 ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n",
312 AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset);
314 /* setup rxgain table */
315 HAL_INI_INIT(&ahp9287->ah_ini_rxgain, ar9287Modes_rx_gain_9287_1_1, 6);
317 /* setup txgain table */
318 HAL_INI_INIT(&ahp9287->ah_ini_txgain, ar9287Modes_tx_gain_9287_1_1, 6);
321 * Got everything we need now to setup the capabilities.
323 if (!ar9287FillCapabilityInfo(ah)) {
328 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr);
329 if (ecode != HAL_OK) {
330 HALDEBUG(ah, HAL_DEBUG_ANY,
331 "%s: error getting mac address from EEPROM\n", __func__);
334 /* XXX How about the serial number ? */
335 /* Read Reg Domain */
336 AH_PRIVATE(ah)->ah_currentRD =
337 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL);
338 AH_PRIVATE(ah)->ah_currentRDext = AR9287_RDEXT_DEFAULT;
341 * ah_miscMode is populated by ar5416FillCapabilityInfo()
342 * starting from griffin. Set here to make sure that
343 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is
344 * placed into hardware.
346 if (ahp->ah_miscMode != 0)
347 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
349 ar9287AniSetup(ah); /* Anti Noise Immunity */
351 /* Setup noise floor min/max/nominal values */
352 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
353 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
354 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
355 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_5GHZ;
356 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_5GHZ;
357 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9287_5GHZ;
359 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist);
361 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__);
373 ar9287ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off)
375 if (AH_PRIVATE(ah)->ah_ispcie && !restore) {
376 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0);
378 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
379 /* Yes, Kiwi uses the Kite PCIe PHY WA */
380 OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
385 ar9287DisablePCIE(struct ath_hal *ah)
391 ar9287WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan)
393 u_int modesIndex, freqIndex;
396 /* Setup the indices for the next set of register array writes */
397 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */
398 if (IEEE80211_IS_CHAN_2GHZ(chan)) {
400 if (IEEE80211_IS_CHAN_HT40(chan))
402 else if (IEEE80211_IS_CHAN_108G(chan))
408 if (IEEE80211_IS_CHAN_HT40(chan) ||
409 IEEE80211_IS_CHAN_TURBO(chan))
415 /* Set correct Baseband to analog shift setting to access analog chips. */
416 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
417 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
419 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, modesIndex, regWrites);
420 regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_rxgain, modesIndex, regWrites);
421 regWrites = ath_hal_ini_write(ah, &AH9287(ah)->ah_ini_txgain, modesIndex, regWrites);
422 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 1, regWrites);
426 * Fill all software cached or static hardware state information.
427 * Return failure if capabilities are to come from EEPROM and
431 ar9287FillCapabilityInfo(struct ath_hal *ah)
433 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
435 if (!ar5416FillCapabilityInfo(ah))
437 pCap->halNumGpioPins = 10;
438 pCap->halWowSupport = AH_TRUE;
439 pCap->halWowMatchPatternExact = AH_TRUE;
441 pCap->halWowMatchPatternDword = AH_TRUE;
444 pCap->halCSTSupport = AH_TRUE;
445 pCap->halRifsRxSupport = AH_TRUE;
446 pCap->halRifsTxSupport = AH_TRUE;
447 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */
448 pCap->halExtChanDfsSupport = AH_TRUE;
449 pCap->halUseCombinedRadarRssi = AH_TRUE;
452 pCap->halBtCoexSupport = AH_TRUE;
454 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
455 pCap->hal4kbSplitTransSupport = AH_FALSE;
456 /* Disable this so Block-ACK works correctly */
457 pCap->halHasRxSelfLinkedTail = AH_FALSE;
458 pCap->halPSPollBroken = AH_FALSE;
459 pCap->halSpectralScanSupport = AH_TRUE;
461 /* Hardware supports (at least) single-stream STBC TX/RX */
462 pCap->halRxStbcSupport = 1;
463 pCap->halTxStbcSupport = 1;
465 /* Hardware supports short-GI w/ 20MHz */
466 pCap->halHTSGI20Support = 1;
468 pCap->halEnhancedDfsSupport = AH_TRUE;
474 * This has been disabled - having the HAL flip chainmasks on/off
475 * when attempting to implement 11n disrupts things. For now, just
476 * leave this flipped off and worry about implementing TX diversity
477 * for legacy and MCS0-15 when 11n is fully functioning.
480 ar9287SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings)
486 ar9287Probe(uint16_t vendorid, uint16_t devid)
488 if (vendorid == ATHEROS_VENDOR_ID) {
489 if (devid == AR9287_DEVID_PCI)
490 return "Atheros 9227";
491 if (devid == AR9287_DEVID_PCIE)
492 return "Atheros 9287";
496 AH_CHIP(AR9287, ar9287Probe, ar9287Attach);