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38 #ifndef __AR9300_DEVID_H__
39 #define __AR9300_DEVID_H__
42 * AR9380 HAL device IDs.
46 * MAC Version and Revision
48 #define AR_SREV_VERSION_AR9380 0x1C0
49 #define AR_SREV_VERSION_AR9580 0x1C0
50 #define AR_SREV_VERSION_AR9460 0x280
51 #define AR_SREV_VERSION_QCA9565 0x2c0
53 #define AR_SREV_VERSION_AR9330 0x200
54 #define AR_SREV_VERSION_AR9340 0x300
55 #define AR_SREV_VERSION_QCA9550 0x400
56 #define AR_SREV_VERSION_AR9485 0x240
58 #define AR_SREV_REVISION_AR9380_10 0 /* AR9380 1.0 */
59 #define AR_SREV_REVISION_AR9380_20 2 /* AR9380 2.0/2.1 */
60 #define AR_SREV_REVISION_AR9380_22 3 /* AR9380 2.2 */
61 #define AR_SREV_REVISION_AR9580_10 4 /* AR9580/Peacock 1.0 */
63 #define AR_SREV_REVISION_AR9330_10 0 /* AR9330 1.0 */
64 #define AR_SREV_REVISION_AR9330_11 1 /* AR9330 1.1 */
65 #define AR_SREV_REVISION_AR9330_12 2 /* AR9330 1.2 */
66 #define AR_SREV_REVISION_AR9330_11_MASK 0xf /* AR9330 1.1 revision mask */
68 #define AR_SREV_REVISION_AR9485_10 0 /* AR9485 1.0 */
69 #define AR_SREV_REVISION_AR9485_11 1 /* AR9485 1.1 */
71 #define AR_SREV_REVISION_AR9340_10 0 /* AR9340 1.0 */
72 #define AR_SREV_REVISION_AR9340_11 1 /* AR9340 1.1 */
73 #define AR_SREV_REVISION_AR9340_12 2 /* AR9340 1.2 */
74 #define AR_SREV_REVISION_AR9340_MASK 0xf /* AR9340 revision mask */
76 #define AR_SREV_REVISION_AR9460_10 0 /* AR946x 1.0 */
78 #endif /* __AR9300_DEVID_H__ */