2 * SPDX-License-Identifier: BSD-3-Clause
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5 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
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42 #ifndef _DEV_ATH_RATE_AMRR_H
43 #define _DEV_ATH_RATE_AMRR_H
45 /* per-device state */
47 struct ath_ratectrl arc; /* base state */
52 int amn_rix; /* current rate index */
53 int amn_ticks; /* time of last update */
54 int amn_interval; /* update interval (ticks) */
55 /* AMRR statistics for this node */
56 u_int amn_tx_try0_cnt;
57 u_int amn_tx_try1_cnt;
58 u_int amn_tx_try2_cnt;
59 u_int amn_tx_try3_cnt;
60 u_int amn_tx_failure_cnt;
61 /* AMRR algorithm state for this node */
62 u_int amn_success_threshold;
65 /* rate index et al. */
66 u_int8_t amn_tx_rix0; /* series 0 rate index */
67 u_int8_t amn_tx_rate0; /* series 0 h/w rate */
68 u_int8_t amn_tx_rate1; /* series 1 h/w rate */
69 u_int8_t amn_tx_rate2; /* series 2 h/w rate */
70 u_int8_t amn_tx_rate3; /* series 3 h/w rate */
71 u_int8_t amn_tx_rate0sp; /* series 0 short preamble h/w rate */
72 u_int8_t amn_tx_rate1sp; /* series 1 short preamble h/w rate */
73 u_int8_t amn_tx_rate2sp; /* series 2 short preamble h/w rate */
74 u_int8_t amn_tx_rate3sp; /* series 3 short preamble h/w rate */
75 u_int8_t amn_tx_try0; /* series 0 try count */
76 u_int amn_tx_try1; /* series 1 try count */
77 u_int amn_tx_try2; /* series 2 try count */
78 u_int amn_tx_try3; /* series 3 try count */
80 #define ATH_NODE_AMRR(an) ((struct amrr_node *)&an[1])
81 #endif /* _DEV_ATH_RATE_AMRR_H */