2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
15 * redistribution must be conditioned upon including a substantially
16 * similar Disclaimer requirement for further binary redistribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGES.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 * Driver for the Atheros Wireless LAN controller.
38 * This software is derived from work of Atsushi Onoe; his contribution
39 * is greatly appreciated.
45 * This is needed for register operations which are performed
46 * by the driver - eg, calls to ath_hal_gettsf32().
48 * It's also required for any AH_DEBUG checks in here, eg the
49 * module dependencies.
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/sysctl.h>
58 #include <sys/malloc.h>
60 #include <sys/mutex.h>
61 #include <sys/kernel.h>
62 #include <sys/socket.h>
63 #include <sys/sockio.h>
64 #include <sys/errno.h>
65 #include <sys/callout.h>
67 #include <sys/endian.h>
68 #include <sys/kthread.h>
69 #include <sys/taskqueue.h>
71 #include <sys/module.h>
73 #include <sys/smp.h> /* for mp_ncpus */
75 #include <machine/bus.h>
78 #include <net/if_var.h>
79 #include <net/if_dl.h>
80 #include <net/if_media.h>
81 #include <net/if_types.h>
82 #include <net/if_arp.h>
83 #include <net/ethernet.h>
84 #include <net/if_llc.h>
86 #include <net80211/ieee80211_var.h>
87 #include <net80211/ieee80211_regdomain.h>
88 #ifdef IEEE80211_SUPPORT_SUPERG
89 #include <net80211/ieee80211_superg.h>
91 #ifdef IEEE80211_SUPPORT_TDMA
92 #include <net80211/ieee80211_tdma.h>
98 #include <netinet/in.h>
99 #include <netinet/if_ether.h>
102 #include <dev/ath/if_athvar.h>
103 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
104 #include <dev/ath/ath_hal/ah_diagcodes.h>
106 #include <dev/ath/if_ath_debug.h>
107 #include <dev/ath/if_ath_misc.h>
108 #include <dev/ath/if_ath_tsf.h>
109 #include <dev/ath/if_ath_tx.h>
110 #include <dev/ath/if_ath_sysctl.h>
111 #include <dev/ath/if_ath_led.h>
112 #include <dev/ath/if_ath_keycache.h>
113 #include <dev/ath/if_ath_rx.h>
114 #include <dev/ath/if_ath_rx_edma.h>
115 #include <dev/ath/if_ath_tx_edma.h>
116 #include <dev/ath/if_ath_beacon.h>
117 #include <dev/ath/if_ath_btcoex.h>
118 #include <dev/ath/if_ath_btcoex_mci.h>
119 #include <dev/ath/if_ath_spectral.h>
120 #include <dev/ath/if_ath_lna_div.h>
121 #include <dev/ath/if_athdfs.h>
122 #include <dev/ath/if_ath_ioctl.h>
123 #include <dev/ath/if_ath_descdma.h>
126 #include <dev/ath/ath_tx99/ath_tx99.h>
130 #include <dev/ath/if_ath_alq.h>
134 * Only enable this if you're working on PS-POLL support.
139 * ATH_BCBUF determines the number of vap's that can transmit
140 * beacons and also (currently) the number of vap's that can
141 * have unique mac addresses/bssid. When staggering beacons
142 * 4 is probably a good max as otherwise the beacons become
143 * very closely spaced and there is limited time for cab q traffic
144 * to go out. You can burst beacons instead but that is not good
145 * for stations in power save and at some point you really want
146 * another radio (and channel).
148 * The limit on the number of mac addresses is tied to our use of
149 * the U/L bit and tracking addresses in a byte; it would be
150 * worthwhile to allow more for applications like proxy sta.
152 CTASSERT(ATH_BCBUF <= 8);
154 static struct ieee80211vap *ath_vap_create(struct ieee80211com *,
155 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
156 const uint8_t [IEEE80211_ADDR_LEN],
157 const uint8_t [IEEE80211_ADDR_LEN]);
158 static void ath_vap_delete(struct ieee80211vap *);
159 static int ath_init(struct ath_softc *);
160 static void ath_stop(struct ath_softc *);
161 static int ath_reset_vap(struct ieee80211vap *, u_long);
162 static int ath_transmit(struct ieee80211com *, struct mbuf *);
163 static int ath_media_change(struct ifnet *);
164 static void ath_watchdog(void *);
165 static void ath_parent(struct ieee80211com *);
166 static void ath_fatal_proc(void *, int);
167 static void ath_bmiss_vap(struct ieee80211vap *);
168 static void ath_bmiss_proc(void *, int);
169 static void ath_key_update_begin(struct ieee80211vap *);
170 static void ath_key_update_end(struct ieee80211vap *);
171 static void ath_update_mcast_hw(struct ath_softc *);
172 static void ath_update_mcast(struct ieee80211com *);
173 static void ath_update_promisc(struct ieee80211com *);
174 static void ath_updateslot(struct ieee80211com *);
175 static void ath_bstuck_proc(void *, int);
176 static void ath_reset_proc(void *, int);
177 static int ath_desc_alloc(struct ath_softc *);
178 static void ath_desc_free(struct ath_softc *);
179 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *,
180 const uint8_t [IEEE80211_ADDR_LEN]);
181 static void ath_node_cleanup(struct ieee80211_node *);
182 static void ath_node_free(struct ieee80211_node *);
183 static void ath_node_getsignal(const struct ieee80211_node *,
185 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int);
186 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
187 static int ath_tx_setup(struct ath_softc *, int, int);
188 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
189 static void ath_tx_cleanup(struct ath_softc *);
190 static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq,
192 static void ath_tx_proc_q0(void *, int);
193 static void ath_tx_proc_q0123(void *, int);
194 static void ath_tx_proc(void *, int);
195 static void ath_txq_sched_tasklet(void *, int);
196 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
197 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
198 static void ath_scan_start(struct ieee80211com *);
199 static void ath_scan_end(struct ieee80211com *);
200 static void ath_set_channel(struct ieee80211com *);
201 #ifdef ATH_ENABLE_11N
202 static void ath_update_chw(struct ieee80211com *);
203 #endif /* ATH_ENABLE_11N */
204 static int ath_set_quiet_ie(struct ieee80211_node *, uint8_t *);
205 static void ath_calibrate(void *);
206 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int);
207 static void ath_setup_stationkey(struct ieee80211_node *);
208 static void ath_newassoc(struct ieee80211_node *, int);
209 static int ath_setregdomain(struct ieee80211com *,
210 struct ieee80211_regdomain *, int,
211 struct ieee80211_channel []);
212 static void ath_getradiocaps(struct ieee80211com *, int, int *,
213 struct ieee80211_channel []);
214 static int ath_getchannels(struct ath_softc *);
216 static int ath_rate_setup(struct ath_softc *, u_int mode);
217 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
219 static void ath_announce(struct ath_softc *);
221 static void ath_dfs_tasklet(void *, int);
222 static void ath_node_powersave(struct ieee80211_node *, int);
223 static int ath_node_set_tim(struct ieee80211_node *, int);
224 static void ath_node_recv_pspoll(struct ieee80211_node *, struct mbuf *);
226 #ifdef IEEE80211_SUPPORT_TDMA
227 #include <dev/ath/if_ath_tdma.h>
230 SYSCTL_DECL(_hw_ath);
232 /* XXX validate sysctl values */
233 static int ath_longcalinterval = 30; /* long cals every 30 secs */
234 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval,
235 0, "long chip calibration interval (secs)");
236 static int ath_shortcalinterval = 100; /* short cals every 100 ms */
237 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval,
238 0, "short chip calibration interval (msecs)");
239 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */
240 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval,
241 0, "reset chip calibration results (secs)");
242 static int ath_anicalinterval = 100; /* ANI calibration - 100 msec */
243 SYSCTL_INT(_hw_ath, OID_AUTO, anical, CTLFLAG_RW, &ath_anicalinterval,
244 0, "ANI calibration (msecs)");
246 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
247 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RWTUN, &ath_rxbuf,
248 0, "rx buffers allocated");
249 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
250 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RWTUN, &ath_txbuf,
251 0, "tx buffers allocated");
252 int ath_txbuf_mgmt = ATH_MGMT_TXBUF; /* # mgmt tx buffers to allocate */
253 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf_mgmt, CTLFLAG_RWTUN, &ath_txbuf_mgmt,
254 0, "tx (mgmt) buffers allocated");
256 int ath_bstuck_threshold = 4; /* max missed beacons */
257 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold,
258 0, "max missed beacon xmits before chip reset");
260 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
263 ath_legacy_attach_comp_func(struct ath_softc *sc)
267 * Special case certain configurations. Note the
268 * CAB queue is handled by these specially so don't
269 * include them when checking the txq setup mask.
271 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
273 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
276 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
279 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
285 * Set the target power mode.
287 * If this is called during a point in time where
288 * the hardware is being programmed elsewhere, it will
289 * simply store it away and update it when all current
290 * uses of the hardware are completed.
292 * If the chip is going into network sleep or power off, then
293 * we will wait until all uses of the chip are done before
294 * going into network sleep or power off.
296 * If the chip is being programmed full-awake, then immediately
297 * program it full-awake so we can actually stay awake rather than
298 * the chip potentially going to sleep underneath us.
301 _ath_power_setpower(struct ath_softc *sc, int power_state, int selfgen,
302 const char *file, int line)
306 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d, target=%d, cur=%d\n",
311 sc->sc_powersave_refcnt,
312 sc->sc_target_powerstate,
313 sc->sc_cur_powerstate);
315 sc->sc_target_powerstate = power_state;
318 * Don't program the chip into network sleep if the chip
319 * is being programmed elsewhere.
321 * However, if the chip is being programmed /awake/, force
322 * the chip awake so we stay awake.
324 if ((sc->sc_powersave_refcnt == 0 || power_state == HAL_PM_AWAKE) &&
325 power_state != sc->sc_cur_powerstate) {
326 sc->sc_cur_powerstate = power_state;
327 ath_hal_setpower(sc->sc_ah, power_state);
330 * If the NIC is force-awake, then set the
331 * self-gen frame state appropriately.
333 * If the nic is in network sleep or full-sleep,
334 * we let the above call leave the self-gen
338 sc->sc_cur_powerstate == HAL_PM_AWAKE &&
339 sc->sc_target_selfgen_state != HAL_PM_AWAKE) {
340 ath_hal_setselfgenpower(sc->sc_ah,
341 sc->sc_target_selfgen_state);
347 * Set the current self-generated frames state.
349 * This is separate from the target power mode. The chip may be
350 * awake but the desired state is "sleep", so frames sent to the
351 * destination has PWRMGT=1 in the 802.11 header. The NIC also
352 * needs to know to set PWRMGT=1 in self-generated frames.
355 _ath_power_set_selfgen(struct ath_softc *sc, int power_state, const char *file, int line)
360 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n",
365 sc->sc_target_selfgen_state);
367 sc->sc_target_selfgen_state = power_state;
370 * If the NIC is force-awake, then set the power state.
371 * Network-state and full-sleep will already transition it to
372 * mark self-gen frames as sleeping - and we can't
373 * guarantee the NIC is awake to program the self-gen frame
376 if (sc->sc_cur_powerstate == HAL_PM_AWAKE) {
377 ath_hal_setselfgenpower(sc->sc_ah, power_state);
382 * Set the hardware power mode and take a reference.
384 * This doesn't update the target power mode in the driver;
385 * it just updates the hardware power state.
387 * XXX it should only ever force the hardware awake; it should
388 * never be called to set it asleep.
391 _ath_power_set_power_state(struct ath_softc *sc, int power_state, const char *file, int line)
395 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n",
400 sc->sc_powersave_refcnt);
402 sc->sc_powersave_refcnt++;
405 * Only do the power state change if we're not programming
408 if (power_state != sc->sc_cur_powerstate) {
409 ath_hal_setpower(sc->sc_ah, power_state);
410 sc->sc_cur_powerstate = power_state;
412 * Adjust the self-gen powerstate if appropriate.
414 if (sc->sc_cur_powerstate == HAL_PM_AWAKE &&
415 sc->sc_target_selfgen_state != HAL_PM_AWAKE) {
416 ath_hal_setselfgenpower(sc->sc_ah,
417 sc->sc_target_selfgen_state);
423 * Restore the power save mode to what it once was.
425 * This will decrement the reference counter and once it hits
426 * zero, it'll restore the powersave state.
429 _ath_power_restore_power_state(struct ath_softc *sc, const char *file, int line)
434 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) refcnt=%d, target state=%d\n",
438 sc->sc_powersave_refcnt,
439 sc->sc_target_powerstate);
441 if (sc->sc_powersave_refcnt == 0)
442 device_printf(sc->sc_dev, "%s: refcnt=0?\n", __func__);
444 sc->sc_powersave_refcnt--;
446 if (sc->sc_powersave_refcnt == 0 &&
447 sc->sc_target_powerstate != sc->sc_cur_powerstate) {
448 sc->sc_cur_powerstate = sc->sc_target_powerstate;
449 ath_hal_setpower(sc->sc_ah, sc->sc_target_powerstate);
453 * Adjust the self-gen powerstate if appropriate.
455 if (sc->sc_cur_powerstate == HAL_PM_AWAKE &&
456 sc->sc_target_selfgen_state != HAL_PM_AWAKE) {
457 ath_hal_setselfgenpower(sc->sc_ah,
458 sc->sc_target_selfgen_state);
464 * Configure the initial HAL configuration values based on bus
465 * specific parameters.
467 * Some PCI IDs and other information may need tweaking.
469 * XXX TODO: ath9k and the Atheros HAL only program comm2g_switch_enable
470 * if BT antenna diversity isn't enabled.
472 * So, let's also figure out how to enable BT diversity for AR9485.
475 ath_setup_hal_config(struct ath_softc *sc, HAL_OPS_CONFIG *ah_config)
477 /* XXX TODO: only for PCI devices? */
479 if (sc->sc_pci_devinfo & (ATH_PCI_CUS198 | ATH_PCI_CUS230)) {
480 ah_config->ath_hal_ext_lna_ctl_gpio = 0x200; /* bit 9 */
481 ah_config->ath_hal_ext_atten_margin_cfg = AH_TRUE;
482 ah_config->ath_hal_min_gainidx = AH_TRUE;
483 ah_config->ath_hal_ant_ctrl_comm2g_switch_enable = 0x000bbb88;
484 /* XXX low_rssi_thresh */
485 /* XXX fast_div_bias */
486 device_printf(sc->sc_dev, "configuring for %s\n",
487 (sc->sc_pci_devinfo & ATH_PCI_CUS198) ?
488 "CUS198" : "CUS230");
491 if (sc->sc_pci_devinfo & ATH_PCI_CUS217)
492 device_printf(sc->sc_dev, "CUS217 card detected\n");
494 if (sc->sc_pci_devinfo & ATH_PCI_CUS252)
495 device_printf(sc->sc_dev, "CUS252 card detected\n");
497 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_1ANT)
498 device_printf(sc->sc_dev, "WB335 1-ANT card detected\n");
500 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_2ANT)
501 device_printf(sc->sc_dev, "WB335 2-ANT card detected\n");
503 if (sc->sc_pci_devinfo & ATH_PCI_BT_ANT_DIV)
504 device_printf(sc->sc_dev,
505 "Bluetooth Antenna Diversity card detected\n");
507 if (sc->sc_pci_devinfo & ATH_PCI_KILLER)
508 device_printf(sc->sc_dev, "Killer Wireless card detected\n");
512 * Some WB335 cards do not support antenna diversity. Since
513 * we use a hardcoded value for AR9565 instead of using the
514 * EEPROM/OTP data, remove the combining feature from
515 * the HW capabilities bitmap.
517 if (sc->sc_pci_devinfo & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
518 if (!(sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV))
519 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
522 if (sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV) {
523 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
524 device_printf(sc->sc_dev, "Set BT/WLAN RX diversity capability\n");
528 if (sc->sc_pci_devinfo & ATH_PCI_D3_L1_WAR) {
529 ah_config->ath_hal_pcie_waen = 0x0040473b;
530 device_printf(sc->sc_dev, "Enable WAR for ASPM D3/L1\n");
534 if (sc->sc_pci_devinfo & ATH9K_PCI_NO_PLL_PWRSAVE) {
535 ah->config.no_pll_pwrsave = true;
536 device_printf(sc->sc_dev, "Disable PLL PowerSave\n");
543 * Attempt to fetch the MAC address from the kernel environment.
545 * Returns 0, macaddr in macaddr if successful; -1 otherwise.
548 ath_fetch_mac_kenv(struct ath_softc *sc, uint8_t *macaddr)
555 * Fetch from the kenv rather than using hints.
557 * Hints would be nice but the transition to dynamic
558 * hints/kenv doesn't happen early enough for this
559 * to work reliably (eg on anything embedded.)
561 snprintf(devid_str, 32, "hint.%s.%d.macaddr",
562 device_get_name(sc->sc_dev),
563 device_get_unit(sc->sc_dev));
565 if ((local_macstr = kern_getenv(devid_str)) != NULL) {
566 uint32_t tmpmac[ETHER_ADDR_LEN];
570 /* Have a MAC address; should use it */
571 device_printf(sc->sc_dev,
572 "Overriding MAC address from environment: '%s'\n",
575 /* Extract out the MAC address */
576 count = sscanf(local_macstr, "%x%*c%x%*c%x%*c%x%*c%x%*c%x",
577 &tmpmac[0], &tmpmac[1],
578 &tmpmac[2], &tmpmac[3],
579 &tmpmac[4], &tmpmac[5]);
583 for (i = 0; i < ETHER_ADDR_LEN; i++)
584 macaddr[i] = tmpmac[i];
587 freeenv(local_macstr);
596 #define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20)
597 #define HAL_MODE_HT40 \
598 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS | \
599 HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)
601 ath_attach(u_int16_t devid, struct ath_softc *sc)
603 struct ieee80211com *ic = &sc->sc_ic;
604 struct ath_hal *ah = NULL;
608 int rx_chainmask, tx_chainmask;
609 HAL_OPS_CONFIG ah_config;
611 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
614 ic->ic_name = device_get_nameunit(sc->sc_dev);
617 * Configure the initial configuration data.
619 * This is stuff that may be needed early during attach
620 * rather than done via configuration calls later.
622 bzero(&ah_config, sizeof(ah_config));
623 ath_setup_hal_config(sc, &ah_config);
625 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh,
626 sc->sc_eepromdata, &ah_config, &status);
628 device_printf(sc->sc_dev,
629 "unable to attach hardware; HAL status %u\n", status);
634 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
636 sc->sc_debug = ath_debug;
640 * Force the chip awake during setup, just to keep
641 * the HAL/driver power tracking happy.
643 * There are some methods (eg ath_hal_setmac())
644 * that poke the hardware.
647 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
651 * Setup the DMA/EDMA functions based on the current
654 * This is required before the descriptors are allocated.
656 if (ath_hal_hasedma(sc->sc_ah)) {
658 ath_recv_setup_edma(sc);
659 ath_xmit_setup_edma(sc);
661 ath_recv_setup_legacy(sc);
662 ath_xmit_setup_legacy(sc);
665 if (ath_hal_hasmybeacon(sc->sc_ah)) {
666 sc->sc_do_mybeacon = 1;
670 * Check if the MAC has multi-rate retry support.
671 * We do this by trying to setup a fake extended
672 * descriptor. MAC's that don't have support will
673 * return false w/o doing anything. MAC's that do
674 * support it will return true w/o doing anything.
676 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
679 * Check if the device has hardware counters for PHY
680 * errors. If so we need to enable the MIB interrupt
681 * so we can act on stat triggers.
683 if (ath_hal_hwphycounters(ah))
687 * Get the hardware key cache size.
689 sc->sc_keymax = ath_hal_keycachesize(ah);
690 if (sc->sc_keymax > ATH_KEYMAX) {
691 device_printf(sc->sc_dev,
692 "Warning, using only %u of %u key cache slots\n",
693 ATH_KEYMAX, sc->sc_keymax);
694 sc->sc_keymax = ATH_KEYMAX;
697 * Reset the key cache since some parts do not
698 * reset the contents on initial power up.
700 for (i = 0; i < sc->sc_keymax; i++)
701 ath_hal_keyreset(ah, i);
704 * Collect the default channel list.
706 error = ath_getchannels(sc);
711 * Setup rate tables for all potential media types.
713 ath_rate_setup(sc, IEEE80211_MODE_11A);
714 ath_rate_setup(sc, IEEE80211_MODE_11B);
715 ath_rate_setup(sc, IEEE80211_MODE_11G);
716 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
717 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
718 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A);
719 ath_rate_setup(sc, IEEE80211_MODE_11NA);
720 ath_rate_setup(sc, IEEE80211_MODE_11NG);
721 ath_rate_setup(sc, IEEE80211_MODE_HALF);
722 ath_rate_setup(sc, IEEE80211_MODE_QUARTER);
724 /* NB: setup here so ath_rate_update is happy */
725 ath_setcurmode(sc, IEEE80211_MODE_11A);
728 * Allocate TX descriptors and populate the lists.
730 error = ath_desc_alloc(sc);
732 device_printf(sc->sc_dev,
733 "failed to allocate TX descriptors: %d\n", error);
736 error = ath_txdma_setup(sc);
738 device_printf(sc->sc_dev,
739 "failed to allocate TX descriptors: %d\n", error);
744 * Allocate RX descriptors and populate the lists.
746 error = ath_rxdma_setup(sc);
748 device_printf(sc->sc_dev,
749 "failed to allocate RX descriptors: %d\n", error);
753 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0);
754 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0);
756 ATH_TXBUF_LOCK_INIT(sc);
758 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT,
759 taskqueue_thread_enqueue, &sc->sc_tq);
760 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
761 device_get_nameunit(sc->sc_dev));
763 TASK_INIT(&sc->sc_rxtask, 0, sc->sc_rx.recv_tasklet, sc);
764 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
765 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc);
766 TASK_INIT(&sc->sc_resettask,0, ath_reset_proc, sc);
767 TASK_INIT(&sc->sc_txqtask, 0, ath_txq_sched_tasklet, sc);
768 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc);
771 * Allocate hardware transmit queues: one queue for
772 * beacon frames and one data queue for each QoS
773 * priority. Note that the hal handles resetting
774 * these queues at the needed time.
778 sc->sc_bhalq = ath_beaconq_setup(sc);
779 if (sc->sc_bhalq == (u_int) -1) {
780 device_printf(sc->sc_dev,
781 "unable to setup a beacon xmit queue!\n");
785 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
786 if (sc->sc_cabq == NULL) {
787 device_printf(sc->sc_dev, "unable to setup CAB xmit queue!\n");
791 /* NB: insure BK queue is the lowest priority h/w queue */
792 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
793 device_printf(sc->sc_dev,
794 "unable to setup xmit queue for %s traffic!\n",
795 ieee80211_wme_acnames[WME_AC_BK]);
799 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
800 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
801 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
803 * Not enough hardware tx queues to properly do WME;
804 * just punt and assign them all to the same h/w queue.
805 * We could do a better job of this if, for example,
806 * we allocate queues when we switch from station to
809 if (sc->sc_ac2q[WME_AC_VI] != NULL)
810 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
811 if (sc->sc_ac2q[WME_AC_BE] != NULL)
812 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
813 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
814 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
815 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
819 * Attach the TX completion function.
821 * The non-EDMA chips may have some special case optimisations;
822 * this method gives everyone a chance to attach cleanly.
824 sc->sc_tx.xmit_attach_comp_func(sc);
827 * Setup rate control. Some rate control modules
828 * call back to change the anntena state so expose
829 * the necessary entry points.
830 * XXX maybe belongs in struct ath_ratectrl?
832 sc->sc_setdefantenna = ath_setdefantenna;
833 sc->sc_rc = ath_rate_attach(sc);
834 if (sc->sc_rc == NULL) {
839 /* Attach DFS module */
840 if (! ath_dfs_attach(sc)) {
841 device_printf(sc->sc_dev,
842 "%s: unable to attach DFS\n", __func__);
847 /* Attach spectral module */
848 if (ath_spectral_attach(sc) < 0) {
849 device_printf(sc->sc_dev,
850 "%s: unable to attach spectral\n", __func__);
855 /* Attach bluetooth coexistence module */
856 if (ath_btcoex_attach(sc) < 0) {
857 device_printf(sc->sc_dev,
858 "%s: unable to attach bluetooth coexistence\n", __func__);
863 /* Attach LNA diversity module */
864 if (ath_lna_div_attach(sc) < 0) {
865 device_printf(sc->sc_dev,
866 "%s: unable to attach LNA diversity\n", __func__);
871 /* Start DFS processing tasklet */
872 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc);
874 /* Configure LED state */
877 sc->sc_ledon = 0; /* low true */
878 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
879 callout_init(&sc->sc_ledtimer, 1);
882 * Don't setup hardware-based blinking.
884 * Although some NICs may have this configured in the
885 * default reset register values, the user may wish
886 * to alter which pins have which function.
888 * The reference driver attaches the MAC network LED to GPIO1 and
889 * the MAC power LED to GPIO2. However, the DWA-552 cardbus
890 * NIC has these reversed.
892 sc->sc_hardled = (1 == 0);
893 sc->sc_led_net_pin = -1;
894 sc->sc_led_pwr_pin = -1;
896 * Auto-enable soft led processing for IBM cards and for
897 * 5211 minipci cards. Users can also manually enable/disable
898 * support with a sysctl.
900 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
902 ath_hal_setledstate(ah, HAL_LED_INIT);
904 /* XXX not right but it's not used anywhere important */
905 ic->ic_phytype = IEEE80211_T_OFDM;
906 ic->ic_opmode = IEEE80211_M_STA;
908 IEEE80211_C_STA /* station mode */
909 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
910 | IEEE80211_C_HOSTAP /* hostap mode */
911 | IEEE80211_C_MONITOR /* monitor mode */
912 | IEEE80211_C_AHDEMO /* adhoc demo mode */
913 | IEEE80211_C_WDS /* 4-address traffic works */
914 | IEEE80211_C_MBSS /* mesh point link mode */
915 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
916 | IEEE80211_C_SHSLOT /* short slot time supported */
917 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
918 #ifndef ATH_ENABLE_11N
919 | IEEE80211_C_BGSCAN /* capable of bg scanning */
921 | IEEE80211_C_TXFRAG /* handle tx frags */
922 #ifdef ATH_ENABLE_DFS
923 | IEEE80211_C_DFS /* Enable radar detection */
925 | IEEE80211_C_PMGT /* Station side power mgmt */
926 | IEEE80211_C_SWSLEEP
929 * Query the hal to figure out h/w crypto support.
931 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
932 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP;
933 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
934 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB;
935 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
936 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM;
937 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
938 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP;
939 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
940 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP;
942 * Check if h/w does the MIC and/or whether the
943 * separate key cache entries are required to
944 * handle both tx+rx MIC keys.
946 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
947 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
949 * If the h/w supports storing tx+rx MIC keys
950 * in one cache slot automatically enable use.
952 if (ath_hal_hastkipsplit(ah) ||
953 !ath_hal_settkipsplit(ah, AH_FALSE))
956 * If the h/w can do TKIP MIC together with WME then
957 * we use it; otherwise we force the MIC to be done
958 * in software by the net80211 layer.
960 if (ath_hal_haswmetkipmic(ah))
961 sc->sc_wmetkipmic = 1;
963 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
965 * Check for multicast key search support.
967 if (ath_hal_hasmcastkeysearch(sc->sc_ah) &&
968 !ath_hal_getmcastkeysearch(sc->sc_ah)) {
969 ath_hal_setmcastkeysearch(sc->sc_ah, 1);
971 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
973 * Mark key cache slots associated with global keys
974 * as in use. If we knew TKIP was not to be used we
975 * could leave the +32, +64, and +32+64 slots free.
977 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
978 setbit(sc->sc_keymap, i);
979 setbit(sc->sc_keymap, i+64);
980 if (sc->sc_splitmic) {
981 setbit(sc->sc_keymap, i+32);
982 setbit(sc->sc_keymap, i+32+64);
986 * TPC support can be done either with a global cap or
987 * per-packet support. The latter is not available on
988 * all parts. We're a bit pedantic here as all parts
989 * support a global cap.
991 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
992 ic->ic_caps |= IEEE80211_C_TXPMGT;
995 * Mark WME capability only if we have sufficient
996 * hardware queues to do proper priority scheduling.
998 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
999 ic->ic_caps |= IEEE80211_C_WME;
1001 * Check for misc other capabilities.
1003 if (ath_hal_hasbursting(ah))
1004 ic->ic_caps |= IEEE80211_C_BURST;
1005 sc->sc_hasbmask = ath_hal_hasbssidmask(ah);
1006 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah);
1007 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah);
1008 sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah);
1010 /* XXX TODO: just make this a "store tx/rx timestamp length" operation */
1011 if (ath_hal_get_rx_tsf_prec(ah, &i)) {
1016 device_printf(sc->sc_dev, "RX timestamp: %d bits\n", i);
1018 if (ath_hal_get_tx_tsf_prec(ah, &i)) {
1020 device_printf(sc->sc_dev, "TX timestamp: %d bits\n", i);
1023 sc->sc_hasenforcetxop = ath_hal_hasenforcetxop(ah);
1024 sc->sc_rx_lnamixer = ath_hal_hasrxlnamixer(ah);
1025 sc->sc_hasdivcomb = ath_hal_hasdivantcomb(ah);
1028 * Some WB335 cards do not support antenna diversity. Since
1029 * we use a hardcoded value for AR9565 instead of using the
1030 * EEPROM/OTP data, remove the combining feature from
1031 * the HW capabilities bitmap.
1034 * XXX TODO: check reference driver and ath9k for what to do
1035 * here for WB335. I think we have to actually disable the
1036 * LNA div processing in the HAL and instead use the hard
1037 * coded values; and then use BT diversity.
1039 * .. but also need to setup MCI too for WB335..
1042 if (sc->sc_pci_devinfo & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
1043 device_printf(sc->sc_dev, "%s: WB335: disabling LNA mixer diversity\n",
1045 sc->sc_dolnadiv = 0;
1049 if (ath_hal_hasfastframes(ah))
1050 ic->ic_caps |= IEEE80211_C_FF;
1051 wmodes = ath_hal_getwirelessmodes(ah);
1052 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO))
1053 ic->ic_caps |= IEEE80211_C_TURBOP;
1054 #ifdef IEEE80211_SUPPORT_TDMA
1055 if (ath_hal_macversion(ah) > 0x78) {
1056 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */
1057 ic->ic_tdma_update = ath_tdma_update;
1062 * TODO: enforce that at least this many frames are available
1063 * in the txbuf list before allowing data frames (raw or
1064 * otherwise) to be transmitted.
1066 sc->sc_txq_data_minfree = 10;
1069 * Shorten this to 64 packets, or 1/4 ath_txbuf, whichever
1072 * Anything bigger can potentially see the cabq consume
1073 * almost all buffers, starving everything else, only to
1074 * see most fail to transmit in the given beacon interval.
1076 sc->sc_txq_mcastq_maxdepth = MIN(64, ath_txbuf / 4);
1079 * How deep can the node software TX queue get whilst it's asleep.
1081 sc->sc_txq_node_psq_maxdepth = 16;
1084 * Default the maximum queue to 1/4'th the TX buffers, or
1085 * 64, whichever is smaller.
1087 sc->sc_txq_node_maxdepth = MIN(64, ath_txbuf / 4);
1089 /* Enable CABQ by default */
1090 sc->sc_cabq_enable = 1;
1093 * Allow the TX and RX chainmasks to be overridden by
1094 * environment variables and/or device.hints.
1096 * This must be done early - before the hardware is
1097 * calibrated or before the 802.11n stream calculation
1100 if (resource_int_value(device_get_name(sc->sc_dev),
1101 device_get_unit(sc->sc_dev), "rx_chainmask",
1102 &rx_chainmask) == 0) {
1103 device_printf(sc->sc_dev, "Setting RX chainmask to 0x%x\n",
1105 (void) ath_hal_setrxchainmask(sc->sc_ah, rx_chainmask);
1107 if (resource_int_value(device_get_name(sc->sc_dev),
1108 device_get_unit(sc->sc_dev), "tx_chainmask",
1109 &tx_chainmask) == 0) {
1110 device_printf(sc->sc_dev, "Setting TX chainmask to 0x%x\n",
1112 (void) ath_hal_settxchainmask(sc->sc_ah, tx_chainmask);
1116 * Query the TX/RX chainmask configuration.
1118 * This is only relevant for 11n devices.
1120 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask);
1121 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask);
1124 * Disable MRR with protected frames by default.
1125 * Only 802.11n series NICs can handle this.
1127 sc->sc_mrrprot = 0; /* XXX should be a capability */
1130 * Query the enterprise mode information the HAL.
1132 if (ath_hal_getcapability(ah, HAL_CAP_ENTERPRISE_MODE, 0,
1133 &sc->sc_ent_cfg) == HAL_OK)
1136 #ifdef ATH_ENABLE_11N
1138 * Query HT capabilities
1140 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK &&
1141 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) {
1145 device_printf(sc->sc_dev, "[HT] enabling HT modes\n");
1147 sc->sc_mrrprot = 1; /* XXX should be a capability */
1149 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */
1150 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */
1151 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */
1152 | IEEE80211_HTCAP_MAXAMSDU_3839
1153 /* max A-MSDU length */
1154 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */
1157 * Enable short-GI for HT20 only if the hardware
1158 * advertises support.
1159 * Notably, anything earlier than the AR9287 doesn't.
1161 if ((ath_hal_getcapability(ah,
1162 HAL_CAP_HT20_SGI, 0, NULL) == HAL_OK) &&
1163 (wmodes & HAL_MODE_HT20)) {
1164 device_printf(sc->sc_dev,
1165 "[HT] enabling short-GI in 20MHz mode\n");
1166 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20;
1169 if (wmodes & HAL_MODE_HT40)
1170 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40
1171 | IEEE80211_HTCAP_SHORTGI40;
1174 * TX/RX streams need to be taken into account when
1175 * negotiating which MCS rates it'll receive and
1176 * what MCS rates are available for TX.
1178 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &txs);
1179 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &rxs);
1180 ic->ic_txstream = txs;
1181 ic->ic_rxstream = rxs;
1184 * Setup TX and RX STBC based on what the HAL allows and
1185 * the currently configured chainmask set.
1186 * Ie - don't enable STBC TX if only one chain is enabled.
1187 * STBC RX is fine on a single RX chain; it just won't
1188 * provide any real benefit.
1190 if (ath_hal_getcapability(ah, HAL_CAP_RX_STBC, 0,
1193 device_printf(sc->sc_dev,
1194 "[HT] 1 stream STBC receive enabled\n");
1195 ic->ic_htcaps |= IEEE80211_HTCAP_RXSTBC_1STREAM;
1197 if (txs > 1 && ath_hal_getcapability(ah, HAL_CAP_TX_STBC, 0,
1200 device_printf(sc->sc_dev,
1201 "[HT] 1 stream STBC transmit enabled\n");
1202 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC;
1205 (void) ath_hal_getcapability(ah, HAL_CAP_RTS_AGGR_LIMIT, 1,
1206 &sc->sc_rts_aggr_limit);
1207 if (sc->sc_rts_aggr_limit != (64 * 1024))
1208 device_printf(sc->sc_dev,
1209 "[HT] RTS aggregates limited to %d KiB\n",
1210 sc->sc_rts_aggr_limit / 1024);
1215 if ((ath_hal_getcapability(ah, HAL_CAP_LDPC, 0, &ldpc))
1216 == HAL_OK && (ldpc == 1)) {
1217 sc->sc_has_ldpc = 1;
1218 device_printf(sc->sc_dev,
1219 "[HT] LDPC transmit/receive enabled\n");
1220 ic->ic_htcaps |= IEEE80211_HTCAP_LDPC |
1221 IEEE80211_HTC_TXLDPC;
1225 device_printf(sc->sc_dev,
1226 "[HT] %d RX streams; %d TX streams\n", rxs, txs);
1231 * Initial aggregation settings.
1233 sc->sc_hwq_limit_aggr = ATH_AGGR_MIN_QDEPTH;
1234 sc->sc_hwq_limit_nonaggr = ATH_NONAGGR_MIN_QDEPTH;
1235 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW;
1236 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH;
1237 sc->sc_aggr_limit = ATH_AGGR_MAXSIZE;
1238 sc->sc_delim_min_pad = 0;
1241 * Check if the hardware requires PCI register serialisation.
1242 * Some of the Owl based MACs require this.
1245 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR,
1246 0, NULL) == HAL_OK) {
1247 sc->sc_ah->ah_config.ah_serialise_reg_war = 1;
1248 device_printf(sc->sc_dev,
1249 "Enabling register serialisation\n");
1253 * Initialise the deferred completed RX buffer list.
1255 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP]);
1256 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP]);
1259 * Indicate we need the 802.11 header padded to a
1260 * 32-bit boundary for 4-address and QoS frames.
1262 ic->ic_flags |= IEEE80211_F_DATAPAD;
1265 * Query the hal about antenna support.
1267 sc->sc_defant = ath_hal_getdefantenna(ah);
1270 * Not all chips have the VEOL support we want to
1271 * use with IBSS beacons; check here for it.
1273 sc->sc_hasveol = ath_hal_hasveol(ah);
1275 /* get mac address from kenv first, then hardware */
1276 if (ath_fetch_mac_kenv(sc, ic->ic_macaddr) == 0) {
1277 /* Tell the HAL now about the new MAC */
1278 ath_hal_setmac(ah, ic->ic_macaddr);
1280 ath_hal_getmac(ah, ic->ic_macaddr);
1283 if (sc->sc_hasbmask)
1284 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask);
1286 /* NB: used to size node table key mapping array */
1287 ic->ic_max_keyix = sc->sc_keymax;
1288 /* call MI attach routine. */
1289 ieee80211_ifattach(ic);
1290 ic->ic_setregdomain = ath_setregdomain;
1291 ic->ic_getradiocaps = ath_getradiocaps;
1292 sc->sc_opmode = HAL_M_STA;
1294 /* override default methods */
1295 ic->ic_ioctl = ath_ioctl;
1296 ic->ic_parent = ath_parent;
1297 ic->ic_transmit = ath_transmit;
1298 ic->ic_newassoc = ath_newassoc;
1299 ic->ic_updateslot = ath_updateslot;
1300 ic->ic_wme.wme_update = ath_wme_update;
1301 ic->ic_vap_create = ath_vap_create;
1302 ic->ic_vap_delete = ath_vap_delete;
1303 ic->ic_raw_xmit = ath_raw_xmit;
1304 ic->ic_update_mcast = ath_update_mcast;
1305 ic->ic_update_promisc = ath_update_promisc;
1306 ic->ic_node_alloc = ath_node_alloc;
1307 sc->sc_node_free = ic->ic_node_free;
1308 ic->ic_node_free = ath_node_free;
1309 sc->sc_node_cleanup = ic->ic_node_cleanup;
1310 ic->ic_node_cleanup = ath_node_cleanup;
1311 ic->ic_node_getsignal = ath_node_getsignal;
1312 ic->ic_scan_start = ath_scan_start;
1313 ic->ic_scan_end = ath_scan_end;
1314 ic->ic_set_channel = ath_set_channel;
1315 #ifdef ATH_ENABLE_11N
1316 /* 802.11n specific - but just override anyway */
1317 sc->sc_addba_request = ic->ic_addba_request;
1318 sc->sc_addba_response = ic->ic_addba_response;
1319 sc->sc_addba_stop = ic->ic_addba_stop;
1320 sc->sc_bar_response = ic->ic_bar_response;
1321 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout;
1323 ic->ic_addba_request = ath_addba_request;
1324 ic->ic_addba_response = ath_addba_response;
1325 ic->ic_addba_response_timeout = ath_addba_response_timeout;
1326 ic->ic_addba_stop = ath_addba_stop;
1327 ic->ic_bar_response = ath_bar_response;
1329 ic->ic_update_chw = ath_update_chw;
1330 #endif /* ATH_ENABLE_11N */
1331 ic->ic_set_quiet = ath_set_quiet_ie;
1333 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
1335 * There's one vendor bitmap entry in the RX radiotap
1336 * header; make sure that's taken into account.
1338 ieee80211_radiotap_attachv(ic,
1339 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 0,
1340 ATH_TX_RADIOTAP_PRESENT,
1341 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1,
1342 ATH_RX_RADIOTAP_PRESENT);
1345 * No vendor bitmap/extensions are present.
1347 ieee80211_radiotap_attach(ic,
1348 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
1349 ATH_TX_RADIOTAP_PRESENT,
1350 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
1351 ATH_RX_RADIOTAP_PRESENT);
1352 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
1355 * Setup the ALQ logging if required
1357 #ifdef ATH_DEBUG_ALQ
1358 if_ath_alq_init(&sc->sc_alq, device_get_nameunit(sc->sc_dev));
1359 if_ath_alq_setcfg(&sc->sc_alq,
1360 sc->sc_ah->ah_macVersion,
1361 sc->sc_ah->ah_macRev,
1362 sc->sc_ah->ah_phyRev,
1363 sc->sc_ah->ah_magic);
1367 * Setup dynamic sysctl's now that country code and
1368 * regdomain are available from the hal.
1370 ath_sysctlattach(sc);
1371 ath_sysctl_stats_attach(sc);
1372 ath_sysctl_hal_attach(sc);
1375 ieee80211_announce(ic);
1379 * Put it to sleep for now.
1382 ath_power_setpower(sc, HAL_PM_FULL_SLEEP, 1);
1389 ath_txdma_teardown(sc);
1390 ath_rxdma_teardown(sc);
1400 ath_detach(struct ath_softc *sc)
1404 * NB: the order of these is important:
1405 * o stop the chip so no more interrupts will fire
1406 * o call the 802.11 layer before detaching the hal to
1407 * insure callbacks into the driver to delete global
1408 * key cache entries can be handled
1409 * o free the taskqueue which drains any pending tasks
1410 * o reclaim the tx queue data structures after calling
1411 * the 802.11 layer as we'll get called back to reclaim
1412 * node state and potentially want to use them
1413 * o to cleanup the tx queues the hal is called, so detach
1415 * Other than that, it's straightforward...
1419 * XXX Wake the hardware up first. ath_stop() will still
1420 * wake it up first, but I'd rather do it here just to
1421 * ensure it's awake.
1424 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1425 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
1428 * Stop things cleanly.
1433 ieee80211_ifdetach(&sc->sc_ic);
1434 taskqueue_free(sc->sc_tq);
1435 #ifdef ATH_TX99_DIAG
1436 if (sc->sc_tx99 != NULL)
1437 sc->sc_tx99->detach(sc->sc_tx99);
1439 ath_rate_detach(sc->sc_rc);
1440 #ifdef ATH_DEBUG_ALQ
1441 if_ath_alq_tidyup(&sc->sc_alq);
1443 ath_lna_div_detach(sc);
1444 ath_btcoex_detach(sc);
1445 ath_spectral_detach(sc);
1448 ath_txdma_teardown(sc);
1449 ath_rxdma_teardown(sc);
1451 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */
1457 * MAC address handling for multiple BSS on the same radio.
1458 * The first vap uses the MAC address from the EEPROM. For
1459 * subsequent vap's we set the U/L bit (bit 1) in the MAC
1460 * address and use the next six bits as an index.
1463 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone)
1467 if (clone && sc->sc_hasbmask) {
1468 /* NB: we only do this if h/w supports multiple bssid */
1469 for (i = 0; i < 8; i++)
1470 if ((sc->sc_bssidmask & (1<<i)) == 0)
1473 mac[0] |= (i << 2)|0x2;
1476 sc->sc_bssidmask |= 1<<i;
1477 sc->sc_hwbssidmask[0] &= ~mac[0];
1483 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN])
1485 int i = mac[0] >> 2;
1488 if (i != 0 || --sc->sc_nbssid0 == 0) {
1489 sc->sc_bssidmask &= ~(1<<i);
1490 /* recalculate bssid mask from remaining addresses */
1492 for (i = 1; i < 8; i++)
1493 if (sc->sc_bssidmask & (1<<i))
1494 mask &= ~((i<<2)|0x2);
1495 sc->sc_hwbssidmask[0] |= mask;
1500 * Assign a beacon xmit slot. We try to space out
1501 * assignments so when beacons are staggered the
1502 * traffic coming out of the cab q has maximal time
1503 * to go out before the next beacon is scheduled.
1506 assign_bslot(struct ath_softc *sc)
1511 for (slot = 0; slot < ATH_BCBUF; slot++)
1512 if (sc->sc_bslot[slot] == NULL) {
1513 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL &&
1514 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL)
1517 /* NB: keep looking for a double slot */
1522 static struct ieee80211vap *
1523 ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1524 enum ieee80211_opmode opmode, int flags,
1525 const uint8_t bssid[IEEE80211_ADDR_LEN],
1526 const uint8_t mac0[IEEE80211_ADDR_LEN])
1528 struct ath_softc *sc = ic->ic_softc;
1529 struct ath_vap *avp;
1530 struct ieee80211vap *vap;
1531 uint8_t mac[IEEE80211_ADDR_LEN];
1532 int needbeacon, error;
1533 enum ieee80211_opmode ic_opmode;
1535 avp = malloc(sizeof(struct ath_vap), M_80211_VAP, M_WAITOK | M_ZERO);
1537 IEEE80211_ADDR_COPY(mac, mac0);
1540 ic_opmode = opmode; /* default to opmode of new vap */
1542 case IEEE80211_M_STA:
1543 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */
1544 device_printf(sc->sc_dev, "only 1 sta vap supported\n");
1549 * With multiple vaps we must fall back
1550 * to s/w beacon miss handling.
1552 flags |= IEEE80211_CLONE_NOBEACONS;
1554 if (flags & IEEE80211_CLONE_NOBEACONS) {
1556 * Station mode w/o beacons are implemented w/ AP mode.
1558 ic_opmode = IEEE80211_M_HOSTAP;
1561 case IEEE80211_M_IBSS:
1562 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */
1563 device_printf(sc->sc_dev,
1564 "only 1 ibss vap supported\n");
1569 case IEEE80211_M_AHDEMO:
1570 #ifdef IEEE80211_SUPPORT_TDMA
1571 if (flags & IEEE80211_CLONE_TDMA) {
1572 if (sc->sc_nvaps != 0) {
1573 device_printf(sc->sc_dev,
1574 "only 1 tdma vap supported\n");
1578 flags |= IEEE80211_CLONE_NOBEACONS;
1582 case IEEE80211_M_MONITOR:
1583 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) {
1585 * Adopt existing mode. Adding a monitor or ahdemo
1586 * vap to an existing configuration is of dubious
1587 * value but should be ok.
1589 /* XXX not right for monitor mode */
1590 ic_opmode = ic->ic_opmode;
1593 case IEEE80211_M_HOSTAP:
1594 case IEEE80211_M_MBSS:
1597 case IEEE80211_M_WDS:
1598 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) {
1599 device_printf(sc->sc_dev,
1600 "wds not supported in sta mode\n");
1604 * Silently remove any request for a unique
1605 * bssid; WDS vap's always share the local
1608 flags &= ~IEEE80211_CLONE_BSSID;
1609 if (sc->sc_nvaps == 0)
1610 ic_opmode = IEEE80211_M_HOSTAP;
1612 ic_opmode = ic->ic_opmode;
1615 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
1619 * Check that a beacon buffer is available; the code below assumes it.
1621 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) {
1622 device_printf(sc->sc_dev, "no beacon buffer available\n");
1627 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS || opmode == IEEE80211_M_STA) {
1628 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID);
1629 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1633 /* XXX can't hold mutex across if_alloc */
1635 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid);
1638 device_printf(sc->sc_dev, "%s: error %d creating vap\n",
1643 /* h/w crypto support */
1644 vap->iv_key_alloc = ath_key_alloc;
1645 vap->iv_key_delete = ath_key_delete;
1646 vap->iv_key_set = ath_key_set;
1647 vap->iv_key_update_begin = ath_key_update_begin;
1648 vap->iv_key_update_end = ath_key_update_end;
1650 /* override various methods */
1651 avp->av_recv_mgmt = vap->iv_recv_mgmt;
1652 vap->iv_recv_mgmt = ath_recv_mgmt;
1653 vap->iv_reset = ath_reset_vap;
1654 vap->iv_update_beacon = ath_beacon_update;
1655 avp->av_newstate = vap->iv_newstate;
1656 vap->iv_newstate = ath_newstate;
1657 avp->av_bmiss = vap->iv_bmiss;
1658 vap->iv_bmiss = ath_bmiss_vap;
1660 avp->av_node_ps = vap->iv_node_ps;
1661 vap->iv_node_ps = ath_node_powersave;
1663 avp->av_set_tim = vap->iv_set_tim;
1664 vap->iv_set_tim = ath_node_set_tim;
1666 avp->av_recv_pspoll = vap->iv_recv_pspoll;
1667 vap->iv_recv_pspoll = ath_node_recv_pspoll;
1669 /* Set default parameters */
1672 * Anything earlier than some AR9300 series MACs don't
1673 * support a smaller MPDU density.
1675 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8;
1677 * All NICs can handle the maximum size, however
1678 * AR5416 based MACs can only TX aggregates w/ RTS
1679 * protection when the total aggregate size is <= 8k.
1680 * However, for now that's enforced by the TX path.
1682 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K;
1683 vap->iv_ampdu_limit = IEEE80211_HTCAP_MAXRXAMPDU_64K;
1688 * Allocate beacon state and setup the q for buffered
1689 * multicast frames. We know a beacon buffer is
1690 * available because we checked above.
1692 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf);
1693 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list);
1694 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) {
1696 * Assign the vap to a beacon xmit slot. As above
1697 * this cannot fail to find a free one.
1699 avp->av_bslot = assign_bslot(sc);
1700 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL,
1701 ("beacon slot %u not empty", avp->av_bslot));
1702 sc->sc_bslot[avp->av_bslot] = vap;
1705 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) {
1707 * Multple vaps are to transmit beacons and we
1708 * have h/w support for TSF adjusting; enable
1709 * use of staggered beacons.
1711 sc->sc_stagbeacons = 1;
1713 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ);
1716 ic->ic_opmode = ic_opmode;
1717 if (opmode != IEEE80211_M_WDS) {
1719 if (opmode == IEEE80211_M_STA)
1721 if (opmode == IEEE80211_M_MBSS)
1724 switch (ic_opmode) {
1725 case IEEE80211_M_IBSS:
1726 sc->sc_opmode = HAL_M_IBSS;
1728 case IEEE80211_M_STA:
1729 sc->sc_opmode = HAL_M_STA;
1731 case IEEE80211_M_AHDEMO:
1732 #ifdef IEEE80211_SUPPORT_TDMA
1733 if (vap->iv_caps & IEEE80211_C_TDMA) {
1735 /* NB: disable tsf adjust */
1736 sc->sc_stagbeacons = 0;
1739 * NB: adhoc demo mode is a pseudo mode; to the hal it's
1744 case IEEE80211_M_HOSTAP:
1745 case IEEE80211_M_MBSS:
1746 sc->sc_opmode = HAL_M_HOSTAP;
1748 case IEEE80211_M_MONITOR:
1749 sc->sc_opmode = HAL_M_MONITOR;
1752 /* XXX should not happen */
1755 if (sc->sc_hastsfadd) {
1757 * Configure whether or not TSF adjust should be done.
1759 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons);
1761 if (flags & IEEE80211_CLONE_NOBEACONS) {
1763 * Enable s/w beacon miss handling.
1769 /* complete setup */
1770 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status,
1774 reclaim_address(sc, mac);
1775 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1777 free(avp, M_80211_VAP);
1783 ath_vap_delete(struct ieee80211vap *vap)
1785 struct ieee80211com *ic = vap->iv_ic;
1786 struct ath_softc *sc = ic->ic_softc;
1787 struct ath_hal *ah = sc->sc_ah;
1788 struct ath_vap *avp = ATH_VAP(vap);
1791 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1794 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
1795 if (sc->sc_running) {
1797 * Quiesce the hardware while we remove the vap. In
1798 * particular we need to reclaim all references to
1799 * the vap state by any frames pending on the tx queues.
1801 ath_hal_intrset(ah, 0); /* disable interrupts */
1802 /* XXX Do all frames from all vaps/nodes need draining here? */
1803 ath_stoprecv(sc, 1); /* stop recv side */
1805 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */
1808 /* .. leave the hardware awake for now. */
1810 ieee80211_vap_detach(vap);
1813 * XXX Danger Will Robinson! Danger!
1815 * Because ieee80211_vap_detach() can queue a frame (the station
1816 * diassociate message?) after we've drained the TXQ and
1817 * flushed the software TXQ, we will end up with a frame queued
1818 * to a node whose vap is about to be freed.
1820 * To work around this, flush the hardware/software again.
1821 * This may be racy - the ath task may be running and the packet
1822 * may be being scheduled between sw->hw txq. Tsk.
1824 * TODO: figure out why a new node gets allocated somewhere around
1825 * here (after the ath_tx_swq() call; and after an ath_stop()
1829 ath_draintxq(sc, ATH_RESET_DEFAULT);
1833 * Reclaim beacon state. Note this must be done before
1834 * the vap instance is reclaimed as we may have a reference
1835 * to it in the buffer for the beacon frame.
1837 if (avp->av_bcbuf != NULL) {
1838 if (avp->av_bslot != -1) {
1839 sc->sc_bslot[avp->av_bslot] = NULL;
1842 ath_beacon_return(sc, avp->av_bcbuf);
1843 avp->av_bcbuf = NULL;
1844 if (sc->sc_nbcnvaps == 0) {
1845 sc->sc_stagbeacons = 0;
1846 if (sc->sc_hastsfadd)
1847 ath_hal_settsfadjust(sc->sc_ah, 0);
1850 * Reclaim any pending mcast frames for the vap.
1852 ath_tx_draintxq(sc, &avp->av_mcastq);
1855 * Update bookkeeping.
1857 if (vap->iv_opmode == IEEE80211_M_STA) {
1859 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss)
1861 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
1862 vap->iv_opmode == IEEE80211_M_STA ||
1863 vap->iv_opmode == IEEE80211_M_MBSS) {
1864 reclaim_address(sc, vap->iv_myaddr);
1865 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask);
1866 if (vap->iv_opmode == IEEE80211_M_MBSS)
1869 if (vap->iv_opmode != IEEE80211_M_WDS)
1871 #ifdef IEEE80211_SUPPORT_TDMA
1872 /* TDMA operation ceases when the last vap is destroyed */
1873 if (sc->sc_tdma && sc->sc_nvaps == 0) {
1878 free(avp, M_80211_VAP);
1880 if (sc->sc_running) {
1882 * Restart rx+tx machines if still running (RUNNING will
1883 * be reset if we just destroyed the last vap).
1885 if (ath_startrecv(sc) != 0)
1886 device_printf(sc->sc_dev,
1887 "%s: unable to restart recv logic\n", __func__);
1888 if (sc->sc_beacons) { /* restart beacons */
1889 #ifdef IEEE80211_SUPPORT_TDMA
1891 ath_tdma_config(sc, NULL);
1894 ath_beacon_config(sc, NULL);
1896 ath_hal_intrset(ah, sc->sc_imask);
1899 /* Ok, let the hardware asleep. */
1900 ath_power_restore_power_state(sc);
1905 ath_suspend(struct ath_softc *sc)
1907 struct ieee80211com *ic = &sc->sc_ic;
1909 sc->sc_resume_up = ic->ic_nrunning != 0;
1911 ieee80211_suspend_all(ic);
1913 * NB: don't worry about putting the chip in low power
1914 * mode; pci will power off our socket on suspend and
1915 * CardBus detaches the device.
1917 * XXX TODO: well, that's great, except for non-cardbus
1922 * XXX This doesn't wait until all pending taskqueue
1923 * items and parallel transmit/receive/other threads
1926 ath_hal_intrset(sc->sc_ah, 0);
1927 taskqueue_block(sc->sc_tq);
1930 callout_stop(&sc->sc_cal_ch);
1934 * XXX ensure sc_invalid is 1
1937 /* Disable the PCIe PHY, complete with workarounds */
1938 ath_hal_enablepcie(sc->sc_ah, 1, 1);
1942 * Reset the key cache since some parts do not reset the
1943 * contents on resume. First we clear all entries, then
1944 * re-load keys that the 802.11 layer assumes are setup
1948 ath_reset_keycache(struct ath_softc *sc)
1950 struct ieee80211com *ic = &sc->sc_ic;
1951 struct ath_hal *ah = sc->sc_ah;
1955 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1956 for (i = 0; i < sc->sc_keymax; i++)
1957 ath_hal_keyreset(ah, i);
1958 ath_power_restore_power_state(sc);
1960 ieee80211_crypto_reload_keys(ic);
1964 * Fetch the current chainmask configuration based on the current
1965 * operating channel and options.
1968 ath_update_chainmasks(struct ath_softc *sc, struct ieee80211_channel *chan)
1972 * Set TX chainmask to the currently configured chainmask;
1973 * the TX chainmask depends upon the current operating mode.
1975 sc->sc_cur_rxchainmask = sc->sc_rxchainmask;
1976 if (IEEE80211_IS_CHAN_HT(chan)) {
1977 sc->sc_cur_txchainmask = sc->sc_txchainmask;
1979 sc->sc_cur_txchainmask = 1;
1982 DPRINTF(sc, ATH_DEBUG_RESET,
1983 "%s: TX chainmask is now 0x%x, RX is now 0x%x\n",
1985 sc->sc_cur_txchainmask,
1986 sc->sc_cur_rxchainmask);
1990 ath_resume(struct ath_softc *sc)
1992 struct ieee80211com *ic = &sc->sc_ic;
1993 struct ath_hal *ah = sc->sc_ah;
1996 ath_hal_enablepcie(ah, 0, 0);
1999 * Must reset the chip before we reload the
2000 * keycache as we were powered down on suspend.
2002 ath_update_chainmasks(sc,
2003 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan);
2004 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2005 sc->sc_cur_rxchainmask);
2007 /* Ensure we set the current power state to on */
2009 ath_power_setselfgen(sc, HAL_PM_AWAKE);
2010 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2011 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
2014 ath_hal_reset(ah, sc->sc_opmode,
2015 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan,
2016 AH_FALSE, HAL_RESET_NORMAL, &status);
2017 ath_reset_keycache(sc);
2020 sc->sc_rx_stopped = 1;
2021 sc->sc_rx_resetted = 1;
2024 /* Let DFS at it in case it's a DFS channel */
2025 ath_dfs_radar_enable(sc, ic->ic_curchan);
2027 /* Let spectral at in case spectral is enabled */
2028 ath_spectral_enable(sc, ic->ic_curchan);
2031 * Let bluetooth coexistence at in case it's needed for this channel
2033 ath_btcoex_enable(sc, ic->ic_curchan);
2036 * If we're doing TDMA, enforce the TXOP limitation for chips that
2039 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2040 ath_hal_setenforcetxop(sc->sc_ah, 1);
2042 ath_hal_setenforcetxop(sc->sc_ah, 0);
2044 /* Restore the LED configuration */
2046 ath_hal_setledstate(ah, HAL_LED_INIT);
2048 if (sc->sc_resume_up)
2049 ieee80211_resume_all(ic);
2052 ath_power_restore_power_state(sc);
2059 ath_shutdown(struct ath_softc *sc)
2065 /* NB: no point powering down chip as we're about to reboot */
2069 * Interrupt handler. Most of the actual processing is deferred.
2074 struct ath_softc *sc = arg;
2075 struct ath_hal *ah = sc->sc_ah;
2080 * If we're inside a reset path, just print a warning and
2081 * clear the ISR. The reset routine will finish it for us.
2084 if (sc->sc_inreset_cnt) {
2086 ath_hal_getisr(ah, &status); /* clear ISR */
2087 ath_hal_intrset(ah, 0); /* disable further intr's */
2088 DPRINTF(sc, ATH_DEBUG_ANY,
2089 "%s: in reset, ignoring: status=0x%x\n",
2095 if (sc->sc_invalid) {
2097 * The hardware is not ready/present, don't touch anything.
2098 * Note this can happen early on if the IRQ is shared.
2100 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
2104 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */
2110 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2113 if (sc->sc_ic.ic_nrunning == 0 && sc->sc_running == 0) {
2116 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_nrunning %d sc_running %d\n",
2117 __func__, sc->sc_ic.ic_nrunning, sc->sc_running);
2118 ath_hal_getisr(ah, &status); /* clear ISR */
2119 ath_hal_intrset(ah, 0); /* disable further intr's */
2123 ath_power_restore_power_state(sc);
2129 * Figure out the reason(s) for the interrupt. Note
2130 * that the hal returns a pseudo-ISR that may include
2131 * bits we haven't explicitly enabled so we mask the
2132 * value to insure we only process bits we requested.
2134 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
2135 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
2136 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1, "ath_intr: mask=0x%.8x", status);
2137 #ifdef ATH_DEBUG_ALQ
2138 if_ath_alq_post_intr(&sc->sc_alq, status, ah->ah_intrstate,
2140 #endif /* ATH_DEBUG_ALQ */
2141 #ifdef ATH_KTR_INTR_DEBUG
2142 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 5,
2143 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x",
2144 ah->ah_intrstate[0],
2145 ah->ah_intrstate[1],
2146 ah->ah_intrstate[2],
2147 ah->ah_intrstate[3],
2148 ah->ah_intrstate[6]);
2151 /* Squirrel away SYNC interrupt debugging */
2152 if (ah->ah_syncstate != 0) {
2154 for (i = 0; i < 32; i++)
2155 if (ah->ah_syncstate & (1 << i))
2156 sc->sc_intr_stats.sync_intr[i]++;
2159 status &= sc->sc_imask; /* discard unasked for bits */
2161 /* Short-circuit un-handled interrupts */
2162 if (status == 0x0) {
2166 ath_power_restore_power_state(sc);
2173 * Take a note that we're inside the interrupt handler, so
2174 * the reset routines know to wait.
2180 * Handle the interrupt. We won't run concurrent with the reset
2181 * or channel change routines as they'll wait for sc_intr_cnt
2182 * to be 0 before continuing.
2184 if (status & HAL_INT_FATAL) {
2185 sc->sc_stats.ast_hardware++;
2186 ath_hal_intrset(ah, 0); /* disable intr's until reset */
2187 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask);
2189 if (status & HAL_INT_SWBA) {
2191 * Software beacon alert--time to send a beacon.
2192 * Handle beacon transmission directly; deferring
2193 * this is too slow to meet timing constraints
2196 #ifdef IEEE80211_SUPPORT_TDMA
2198 if (sc->sc_tdmaswba == 0) {
2199 struct ieee80211com *ic = &sc->sc_ic;
2200 struct ieee80211vap *vap =
2201 TAILQ_FIRST(&ic->ic_vaps);
2202 ath_tdma_beacon_send(sc, vap);
2204 vap->iv_tdma->tdma_bintval;
2210 ath_beacon_proc(sc, 0);
2211 #ifdef IEEE80211_SUPPORT_SUPERG
2213 * Schedule the rx taskq in case there's no
2214 * traffic so any frames held on the staging
2215 * queue are aged and potentially flushed.
2217 sc->sc_rx.recv_sched(sc, 1);
2221 if (status & HAL_INT_RXEOL) {
2223 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXEOL");
2224 if (! sc->sc_isedma) {
2227 * NB: the hardware should re-read the link when
2228 * RXE bit is written, but it doesn't work at
2229 * least on older hardware revs.
2231 sc->sc_stats.ast_rxeol++;
2233 * Disable RXEOL/RXORN - prevent an interrupt
2234 * storm until the PCU logic can be reset.
2235 * In case the interface is reset some other
2236 * way before "sc_kickpcu" is called, don't
2237 * modify sc_imask - that way if it is reset
2238 * by a call to ath_reset() somehow, the
2239 * interrupt mask will be correctly reprogrammed.
2241 imask = sc->sc_imask;
2242 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN);
2243 ath_hal_intrset(ah, imask);
2245 * Only blank sc_rxlink if we've not yet kicked
2248 * This isn't entirely correct - the correct solution
2249 * would be to have a PCU lock and engage that for
2250 * the duration of the PCU fiddling; which would include
2251 * running the RX process. Otherwise we could end up
2252 * messing up the RX descriptor chain and making the
2253 * RX desc list much shorter.
2255 if (! sc->sc_kickpcu)
2256 sc->sc_rxlink = NULL;
2261 * Enqueue an RX proc to handle whatever
2262 * is in the RX queue.
2263 * This will then kick the PCU if required.
2265 sc->sc_rx.recv_sched(sc, 1);
2267 if (status & HAL_INT_TXURN) {
2268 sc->sc_stats.ast_txurn++;
2269 /* bump tx trigger level */
2270 ath_hal_updatetxtriglevel(ah, AH_TRUE);
2273 * Handle both the legacy and RX EDMA interrupt bits.
2274 * Note that HAL_INT_RXLP is also HAL_INT_RXDESC.
2276 if (status & (HAL_INT_RX | HAL_INT_RXHP | HAL_INT_RXLP)) {
2277 sc->sc_stats.ast_rx_intr++;
2278 sc->sc_rx.recv_sched(sc, 1);
2280 if (status & HAL_INT_TX) {
2281 sc->sc_stats.ast_tx_intr++;
2283 * Grab all the currently set bits in the HAL txq bitmap
2284 * and blank them. This is the only place we should be
2287 if (! sc->sc_isedma) {
2290 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs);
2291 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 3,
2292 "ath_intr: TX; txqs=0x%08x, txq_active was 0x%08x, now 0x%08x",
2295 sc->sc_txq_active | txqs);
2296 sc->sc_txq_active |= txqs;
2299 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
2301 if (status & HAL_INT_BMISS) {
2302 sc->sc_stats.ast_bmiss++;
2303 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
2305 if (status & HAL_INT_GTT)
2306 sc->sc_stats.ast_tx_timeout++;
2307 if (status & HAL_INT_CST)
2308 sc->sc_stats.ast_tx_cst++;
2309 if (status & HAL_INT_MIB) {
2310 sc->sc_stats.ast_mib++;
2313 * Disable interrupts until we service the MIB
2314 * interrupt; otherwise it will continue to fire.
2316 ath_hal_intrset(ah, 0);
2318 * Let the hal handle the event. We assume it will
2319 * clear whatever condition caused the interrupt.
2321 ath_hal_mibevent(ah, &sc->sc_halstats);
2323 * Don't reset the interrupt if we've just
2324 * kicked the PCU, or we may get a nested
2325 * RXEOL before the rxproc has had a chance
2328 if (sc->sc_kickpcu == 0)
2329 ath_hal_intrset(ah, sc->sc_imask);
2332 if (status & HAL_INT_RXORN) {
2333 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */
2334 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXORN");
2335 sc->sc_stats.ast_rxorn++;
2337 if (status & HAL_INT_TSFOOR) {
2338 /* out of range beacon - wake the chip up,
2339 * but don't modify self-gen frame config */
2340 device_printf(sc->sc_dev, "%s: TSFOOR\n", __func__);
2341 sc->sc_syncbeacon = 1;
2343 ath_power_setpower(sc, HAL_PM_AWAKE, 0);
2346 if (status & HAL_INT_MCI) {
2347 ath_btcoex_mci_intr(sc);
2355 ath_power_restore_power_state(sc);
2360 ath_fatal_proc(void *arg, int pending)
2362 struct ath_softc *sc = arg;
2370 device_printf(sc->sc_dev, "hardware error; resetting\n");
2372 * Fatal errors are unrecoverable. Typically these
2373 * are caused by DMA errors. Collect h/w state from
2374 * the hal so we can diagnose what's going on.
2376 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) {
2377 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len));
2379 device_printf(sc->sc_dev,
2380 "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n", state[0],
2381 state[1] , state[2], state[3], state[4], state[5]);
2383 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_FORCE_COLD);
2387 ath_bmiss_vap(struct ieee80211vap *vap)
2389 struct ath_softc *sc = vap->iv_ic->ic_softc;
2392 * Workaround phantom bmiss interrupts by sanity-checking
2393 * the time of our last rx'd frame. If it is within the
2394 * beacon miss interval then ignore the interrupt. If it's
2395 * truly a bmiss we'll get another interrupt soon and that'll
2396 * be dispatched up for processing. Note this applies only
2397 * for h/w beacon miss events.
2401 * XXX TODO: Just read the TSF during the interrupt path;
2402 * that way we don't have to wake up again just to read it
2406 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2409 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) {
2410 u_int64_t lastrx = sc->sc_lastrx;
2411 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
2412 /* XXX should take a locked ref to iv_bss */
2413 u_int bmisstimeout =
2414 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024;
2416 DPRINTF(sc, ATH_DEBUG_BEACON,
2417 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
2418 __func__, (unsigned long long) tsf,
2419 (unsigned long long)(tsf - lastrx),
2420 (unsigned long long) lastrx, bmisstimeout);
2422 if (tsf - lastrx <= bmisstimeout) {
2423 sc->sc_stats.ast_bmiss_phantom++;
2426 ath_power_restore_power_state(sc);
2434 * Keep the hardware awake if it's asleep (and leave self-gen
2435 * frame config alone) until the next beacon, so we can resync
2436 * against the next beacon.
2438 * This handles three common beacon miss cases in STA powersave mode -
2439 * (a) the beacon TBTT isnt a multiple of bintval;
2440 * (b) the beacon was missed; and
2441 * (c) the beacons are being delayed because the AP is busy and
2442 * isn't reliably able to meet its TBTT.
2445 ath_power_setpower(sc, HAL_PM_AWAKE, 0);
2446 ath_power_restore_power_state(sc);
2448 DPRINTF(sc, ATH_DEBUG_BEACON,
2449 "%s: forced awake; force syncbeacon=1\n", __func__);
2452 * Attempt to force a beacon resync.
2454 sc->sc_syncbeacon = 1;
2456 ATH_VAP(vap)->av_bmiss(vap);
2459 /* XXX this needs a force wakeup! */
2461 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs)
2466 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize))
2468 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize));
2469 *hangs = *(uint32_t *)sp;
2474 ath_bmiss_proc(void *arg, int pending)
2476 struct ath_softc *sc = arg;
2479 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
2482 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2485 ath_beacon_miss(sc);
2488 * Do a reset upon any becaon miss event.
2490 * It may be a non-recognised RX clear hang which needs a reset
2493 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) {
2494 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_BBPANIC);
2495 device_printf(sc->sc_dev,
2496 "bb hang detected (0x%x), resetting\n", hangs);
2498 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_FORCE_COLD);
2499 ieee80211_beacon_miss(&sc->sc_ic);
2502 /* Force a beacon resync, in case they've drifted */
2503 sc->sc_syncbeacon = 1;
2506 ath_power_restore_power_state(sc);
2511 * Handle TKIP MIC setup to deal hardware that doesn't do MIC
2512 * calcs together with WME. If necessary disable the crypto
2513 * hardware and mark the 802.11 state so keys will be setup
2514 * with the MIC work done in software.
2517 ath_settkipmic(struct ath_softc *sc)
2519 struct ieee80211com *ic = &sc->sc_ic;
2521 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) {
2522 if (ic->ic_flags & IEEE80211_F_WME) {
2523 ath_hal_settkipmic(sc->sc_ah, AH_FALSE);
2524 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC;
2526 ath_hal_settkipmic(sc->sc_ah, AH_TRUE);
2527 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
2533 ath_vap_clear_quiet_ie(struct ath_softc *sc)
2535 struct ieee80211com *ic = &sc->sc_ic;
2536 struct ieee80211vap *vap;
2537 struct ath_vap *avp;
2539 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
2541 /* Quiet time handling - ensure we resync */
2542 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie));
2547 ath_init(struct ath_softc *sc)
2549 struct ieee80211com *ic = &sc->sc_ic;
2550 struct ath_hal *ah = sc->sc_ah;
2553 ATH_LOCK_ASSERT(sc);
2556 * Force the sleep state awake.
2558 ath_power_setselfgen(sc, HAL_PM_AWAKE);
2559 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2560 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
2563 * Stop anything previously setup. This is safe
2564 * whether this is the first time through or not.
2569 * The basic interface to setting the hardware in a good
2570 * state is ``reset''. On return the hardware is known to
2571 * be powered up and with interrupts disabled. This must
2572 * be followed by initialization of the appropriate bits
2573 * and then setup of the interrupt mask.
2576 ath_update_chainmasks(sc, ic->ic_curchan);
2577 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2578 sc->sc_cur_rxchainmask);
2580 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE,
2581 HAL_RESET_NORMAL, &status)) {
2582 device_printf(sc->sc_dev,
2583 "unable to reset hardware; hal status %u\n", status);
2588 sc->sc_rx_stopped = 1;
2589 sc->sc_rx_resetted = 1;
2592 /* Clear quiet IE state for each VAP */
2593 ath_vap_clear_quiet_ie(sc);
2595 ath_chan_change(sc, ic->ic_curchan);
2597 /* Let DFS at it in case it's a DFS channel */
2598 ath_dfs_radar_enable(sc, ic->ic_curchan);
2600 /* Let spectral at in case spectral is enabled */
2601 ath_spectral_enable(sc, ic->ic_curchan);
2604 * Let bluetooth coexistence at in case it's needed for this channel
2606 ath_btcoex_enable(sc, ic->ic_curchan);
2609 * If we're doing TDMA, enforce the TXOP limitation for chips that
2612 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2613 ath_hal_setenforcetxop(sc->sc_ah, 1);
2615 ath_hal_setenforcetxop(sc->sc_ah, 0);
2618 * Likewise this is set during reset so update
2619 * state cached in the driver.
2621 sc->sc_diversity = ath_hal_getdiversity(ah);
2622 sc->sc_lastlongcal = ticks;
2623 sc->sc_resetcal = 1;
2624 sc->sc_lastcalreset = 0;
2625 sc->sc_lastani = ticks;
2626 sc->sc_lastshortcal = ticks;
2627 sc->sc_doresetcal = AH_FALSE;
2629 * Beacon timers were cleared here; give ath_newstate()
2630 * a hint that the beacon timers should be poked when
2631 * things transition to the RUN state.
2636 * Setup the hardware after reset: the key cache
2637 * is filled as needed and the receive engine is
2638 * set going. Frame transmit is handled entirely
2639 * in the frame output path; there's nothing to do
2640 * here except setup the interrupt mask.
2642 if (ath_startrecv(sc) != 0) {
2643 device_printf(sc->sc_dev, "unable to start recv logic\n");
2644 ath_power_restore_power_state(sc);
2649 * Enable interrupts.
2651 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
2652 | HAL_INT_RXORN | HAL_INT_TXURN
2653 | HAL_INT_FATAL | HAL_INT_GLOBAL;
2656 * Enable RX EDMA bits. Note these overlap with
2657 * HAL_INT_RX and HAL_INT_RXDESC respectively.
2660 sc->sc_imask |= (HAL_INT_RXHP | HAL_INT_RXLP);
2663 * If we're an EDMA NIC, we don't care about RXEOL.
2664 * Writing a new descriptor in will simply restart
2667 if (! sc->sc_isedma)
2668 sc->sc_imask |= HAL_INT_RXEOL;
2671 * Enable MCI interrupt for MCI devices.
2673 if (sc->sc_btcoex_mci)
2674 sc->sc_imask |= HAL_INT_MCI;
2677 * Enable MIB interrupts when there are hardware phy counters.
2678 * Note we only do this (at the moment) for station mode.
2680 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
2681 sc->sc_imask |= HAL_INT_MIB;
2684 * XXX add capability for this.
2686 * If we're in STA mode (and maybe IBSS?) then register for
2687 * TSFOOR interrupts.
2689 if (ic->ic_opmode == IEEE80211_M_STA)
2690 sc->sc_imask |= HAL_INT_TSFOOR;
2692 /* Enable global TX timeout and carrier sense timeout if available */
2693 if (ath_hal_gtxto_supported(ah))
2694 sc->sc_imask |= HAL_INT_GTT;
2696 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n",
2697 __func__, sc->sc_imask);
2700 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc);
2701 ath_hal_intrset(ah, sc->sc_imask);
2703 ath_power_restore_power_state(sc);
2709 ath_stop(struct ath_softc *sc)
2711 struct ath_hal *ah = sc->sc_ah;
2713 ATH_LOCK_ASSERT(sc);
2716 * Wake the hardware up before fiddling with it.
2718 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2720 if (sc->sc_running) {
2722 * Shutdown the hardware and driver:
2723 * reset 802.11 state machine
2725 * disable interrupts
2726 * turn off the radio
2727 * clear transmit machinery
2728 * clear receive machinery
2729 * drain and release tx queues
2730 * reclaim beacon resources
2731 * power down hardware
2733 * Note that some of this work is not possible if the
2734 * hardware is gone (invalid).
2736 #ifdef ATH_TX99_DIAG
2737 if (sc->sc_tx99 != NULL)
2738 sc->sc_tx99->stop(sc->sc_tx99);
2740 callout_stop(&sc->sc_wd_ch);
2741 sc->sc_wd_timer = 0;
2743 if (!sc->sc_invalid) {
2744 if (sc->sc_softled) {
2745 callout_stop(&sc->sc_ledtimer);
2746 ath_hal_gpioset(ah, sc->sc_ledpin,
2748 sc->sc_blinking = 0;
2750 ath_hal_intrset(ah, 0);
2752 /* XXX we should stop RX regardless of whether it's valid */
2753 if (!sc->sc_invalid) {
2754 ath_stoprecv(sc, 1);
2755 ath_hal_phydisable(ah);
2757 sc->sc_rxlink = NULL;
2758 ath_draintxq(sc, ATH_RESET_DEFAULT);
2759 ath_beacon_free(sc); /* XXX not needed */
2762 /* And now, restore the current power state */
2763 ath_power_restore_power_state(sc);
2767 * Wait until all pending TX/RX has completed.
2769 * This waits until all existing transmit, receive and interrupts
2770 * have completed. It's assumed that the caller has first
2771 * grabbed the reset lock so it doesn't try to do overlapping
2774 #define MAX_TXRX_ITERATIONS 100
2776 ath_txrx_stop_locked(struct ath_softc *sc)
2778 int i = MAX_TXRX_ITERATIONS;
2780 ATH_UNLOCK_ASSERT(sc);
2781 ATH_PCU_LOCK_ASSERT(sc);
2784 * Sleep until all the pending operations have completed.
2786 * The caller must ensure that reset has been incremented
2787 * or the pending operations may continue being queued.
2789 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt ||
2790 sc->sc_txstart_cnt || sc->sc_intr_cnt) {
2793 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop",
2794 msecs_to_ticks(10));
2799 device_printf(sc->sc_dev,
2800 "%s: didn't finish after %d iterations\n",
2801 __func__, MAX_TXRX_ITERATIONS);
2803 #undef MAX_TXRX_ITERATIONS
2807 ath_txrx_stop(struct ath_softc *sc)
2809 ATH_UNLOCK_ASSERT(sc);
2810 ATH_PCU_UNLOCK_ASSERT(sc);
2813 ath_txrx_stop_locked(sc);
2819 ath_txrx_start(struct ath_softc *sc)
2822 taskqueue_unblock(sc->sc_tq);
2826 * Grab the reset lock, and wait around until no one else
2827 * is trying to do anything with it.
2829 * This is totally horrible but we can't hold this lock for
2830 * long enough to do TX/RX or we end up with net80211/ip stack
2831 * LORs and eventual deadlock.
2833 * "dowait" signals whether to spin, waiting for the reset
2834 * lock count to reach 0. This should (for now) only be used
2835 * during the reset path, as the rest of the code may not
2836 * be locking-reentrant enough to behave correctly.
2838 * Another, cleaner way should be found to serialise all of
2841 #define MAX_RESET_ITERATIONS 25
2843 ath_reset_grablock(struct ath_softc *sc, int dowait)
2846 int i = MAX_RESET_ITERATIONS;
2848 ATH_PCU_LOCK_ASSERT(sc);
2850 if (sc->sc_inreset_cnt == 0) {
2860 * 1 tick is likely not enough time for long calibrations
2861 * to complete. So we should wait quite a while.
2863 pause("ath_reset_grablock", msecs_to_ticks(100));
2869 * We always increment the refcounter, regardless
2870 * of whether we succeeded to get it in an exclusive
2873 sc->sc_inreset_cnt++;
2876 device_printf(sc->sc_dev,
2877 "%s: didn't finish after %d iterations\n",
2878 __func__, MAX_RESET_ITERATIONS);
2881 device_printf(sc->sc_dev,
2882 "%s: warning, recursive reset path!\n",
2887 #undef MAX_RESET_ITERATIONS
2890 * Reset the hardware w/o losing operational state. This is
2891 * basically a more efficient way of doing ath_stop, ath_init,
2892 * followed by state transitions to the current 802.11
2893 * operational state. Used to recover from various errors and
2894 * to reset or reload hardware state.
2897 ath_reset(struct ath_softc *sc, ATH_RESET_TYPE reset_type,
2898 HAL_RESET_TYPE ah_reset_type)
2900 struct ieee80211com *ic = &sc->sc_ic;
2901 struct ath_hal *ah = sc->sc_ah;
2905 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
2907 /* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */
2908 ATH_PCU_UNLOCK_ASSERT(sc);
2909 ATH_UNLOCK_ASSERT(sc);
2911 /* Try to (stop any further TX/RX from occurring */
2912 taskqueue_block(sc->sc_tq);
2915 * Wake the hardware up.
2918 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2924 * Grab the reset lock before TX/RX is stopped.
2926 * This is needed to ensure that when the TX/RX actually does finish,
2927 * no further TX/RX/reset runs in parallel with this.
2929 if (ath_reset_grablock(sc, 1) == 0) {
2930 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
2934 /* disable interrupts */
2935 ath_hal_intrset(ah, 0);
2938 * Now, ensure that any in progress TX/RX completes before we
2941 ath_txrx_stop_locked(sc);
2946 * Regardless of whether we're doing a no-loss flush or
2947 * not, stop the PCU and handle what's in the RX queue.
2948 * That way frames aren't dropped which shouldn't be.
2950 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS));
2954 * Should now wait for pending TX/RX to complete
2955 * and block future ones from occurring. This needs to be
2956 * done before the TX queue is drained.
2958 ath_draintxq(sc, reset_type); /* stop xmit side */
2960 ath_settkipmic(sc); /* configure TKIP MIC handling */
2961 /* NB: indicate channel change so we do a full reset */
2962 ath_update_chainmasks(sc, ic->ic_curchan);
2963 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2964 sc->sc_cur_rxchainmask);
2965 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE,
2966 ah_reset_type, &status))
2967 device_printf(sc->sc_dev,
2968 "%s: unable to reset hardware; hal status %u\n",
2970 sc->sc_diversity = ath_hal_getdiversity(ah);
2973 sc->sc_rx_stopped = 1;
2974 sc->sc_rx_resetted = 1;
2977 /* Quiet time handling - ensure we resync */
2978 ath_vap_clear_quiet_ie(sc);
2980 /* Let DFS at it in case it's a DFS channel */
2981 ath_dfs_radar_enable(sc, ic->ic_curchan);
2983 /* Let spectral at in case spectral is enabled */
2984 ath_spectral_enable(sc, ic->ic_curchan);
2987 * Let bluetooth coexistence at in case it's needed for this channel
2989 ath_btcoex_enable(sc, ic->ic_curchan);
2992 * If we're doing TDMA, enforce the TXOP limitation for chips that
2995 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2996 ath_hal_setenforcetxop(sc->sc_ah, 1);
2998 ath_hal_setenforcetxop(sc->sc_ah, 0);
3000 if (ath_startrecv(sc) != 0) /* restart recv */
3001 device_printf(sc->sc_dev,
3002 "%s: unable to start recv logic\n", __func__);
3004 * We may be doing a reset in response to an ioctl
3005 * that changes the channel so update any state that
3006 * might change as a result.
3008 ath_chan_change(sc, ic->ic_curchan);
3009 if (sc->sc_beacons) { /* restart beacons */
3010 #ifdef IEEE80211_SUPPORT_TDMA
3012 ath_tdma_config(sc, NULL);
3015 ath_beacon_config(sc, NULL);
3019 * Release the reset lock and re-enable interrupts here.
3020 * If an interrupt was being processed in ath_intr(),
3021 * it would disable interrupts at this point. So we have
3022 * to atomically enable interrupts and decrement the
3023 * reset counter - this way ath_intr() doesn't end up
3024 * disabling interrupts without a corresponding enable
3025 * in the rest or channel change path.
3027 * Grab the TX reference in case we need to transmit.
3028 * That way a parallel transmit doesn't.
3031 sc->sc_inreset_cnt--;
3032 sc->sc_txstart_cnt++;
3033 /* XXX only do this if sc_inreset_cnt == 0? */
3034 ath_hal_intrset(ah, sc->sc_imask);
3038 * TX and RX can be started here. If it were started with
3039 * sc_inreset_cnt > 0, the TX and RX path would abort.
3040 * Thus if this is a nested call through the reset or
3041 * channel change code, TX completion will occur but
3042 * RX completion and ath_start / ath_tx_start will not
3046 /* Restart TX/RX as needed */
3049 /* XXX TODO: we need to hold the tx refcount here! */
3051 /* Restart TX completion and pending TX */
3052 if (reset_type == ATH_RESET_NOLOSS) {
3053 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
3054 if (ATH_TXQ_SETUP(sc, i)) {
3055 ATH_TXQ_LOCK(&sc->sc_txq[i]);
3056 ath_txq_restart_dma(sc, &sc->sc_txq[i]);
3057 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
3060 ath_txq_sched(sc, &sc->sc_txq[i]);
3067 ath_power_restore_power_state(sc);
3071 sc->sc_txstart_cnt--;
3074 /* Handle any frames in the TX queue */
3076 * XXX should this be done by the caller, rather than
3079 ath_tx_kick(sc); /* restart xmit */
3084 ath_reset_vap(struct ieee80211vap *vap, u_long cmd)
3086 struct ieee80211com *ic = vap->iv_ic;
3087 struct ath_softc *sc = ic->ic_softc;
3088 struct ath_hal *ah = sc->sc_ah;
3091 case IEEE80211_IOC_TXPOWER:
3093 * If per-packet TPC is enabled, then we have nothing
3094 * to do; otherwise we need to force the global limit.
3095 * All this can happen directly; no need to reset.
3097 if (!ath_hal_gettpc(ah))
3098 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
3101 /* XXX? Full or NOLOSS? */
3102 return ath_reset(sc, ATH_RESET_FULL, HAL_RESET_NORMAL);
3106 _ath_getbuf_locked(struct ath_softc *sc, ath_buf_type_t btype)
3110 ATH_TXBUF_LOCK_ASSERT(sc);
3112 if (btype == ATH_BUFTYPE_MGMT)
3113 bf = TAILQ_FIRST(&sc->sc_txbuf_mgmt);
3115 bf = TAILQ_FIRST(&sc->sc_txbuf);
3118 sc->sc_stats.ast_tx_getnobuf++;
3120 if (bf->bf_flags & ATH_BUF_BUSY) {
3121 sc->sc_stats.ast_tx_getbusybuf++;
3126 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) {
3127 if (btype == ATH_BUFTYPE_MGMT)
3128 TAILQ_REMOVE(&sc->sc_txbuf_mgmt, bf, bf_list);
3130 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list);
3134 * This shuldn't happen; however just to be
3135 * safe print a warning and fudge the txbuf
3138 if (sc->sc_txbuf_cnt < 0) {
3139 device_printf(sc->sc_dev,
3140 "%s: sc_txbuf_cnt < 0?\n",
3142 sc->sc_txbuf_cnt = 0;
3149 /* XXX should check which list, mgmt or otherwise */
3150 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__,
3151 TAILQ_FIRST(&sc->sc_txbuf) == NULL ?
3152 "out of xmit buffers" : "xmit buffer busy");
3156 /* XXX TODO: should do this at buffer list initialisation */
3157 /* XXX (then, ensure the buffer has the right flag set) */
3159 if (btype == ATH_BUFTYPE_MGMT)
3160 bf->bf_flags |= ATH_BUF_MGMT;
3162 bf->bf_flags &= (~ATH_BUF_MGMT);
3164 /* Valid bf here; clear some basic fields */
3165 bf->bf_next = NULL; /* XXX just to be sure */
3166 bf->bf_last = NULL; /* XXX again, just to be sure */
3167 bf->bf_comp = NULL; /* XXX again, just to be sure */
3168 bzero(&bf->bf_state, sizeof(bf->bf_state));
3171 * Track the descriptor ID only if doing EDMA
3173 if (sc->sc_isedma) {
3174 bf->bf_descid = sc->sc_txbuf_descid;
3175 sc->sc_txbuf_descid++;
3182 * When retrying a software frame, buffers marked ATH_BUF_BUSY
3183 * can't be thrown back on the queue as they could still be
3184 * in use by the hardware.
3186 * This duplicates the buffer, or returns NULL.
3188 * The descriptor is also copied but the link pointers and
3189 * the DMA segments aren't copied; this frame should thus
3190 * be again passed through the descriptor setup/chain routines
3191 * so the link is correct.
3193 * The caller must free the buffer using ath_freebuf().
3196 ath_buf_clone(struct ath_softc *sc, struct ath_buf *bf)
3198 struct ath_buf *tbf;
3200 tbf = ath_getbuf(sc,
3201 (bf->bf_flags & ATH_BUF_MGMT) ?
3202 ATH_BUFTYPE_MGMT : ATH_BUFTYPE_NORMAL);
3204 return NULL; /* XXX failure? Why? */
3207 tbf->bf_next = NULL;
3208 tbf->bf_nseg = bf->bf_nseg;
3209 tbf->bf_flags = bf->bf_flags & ATH_BUF_FLAGS_CLONE;
3210 tbf->bf_status = bf->bf_status;
3211 tbf->bf_m = bf->bf_m;
3212 tbf->bf_node = bf->bf_node;
3213 KASSERT((bf->bf_node != NULL), ("%s: bf_node=NULL!", __func__));
3214 /* will be setup by the chain/setup function */
3215 tbf->bf_lastds = NULL;
3216 /* for now, last == self */
3218 tbf->bf_comp = bf->bf_comp;
3220 /* NOTE: DMA segments will be setup by the setup/chain functions */
3222 /* The caller has to re-init the descriptor + links */
3225 * Free the DMA mapping here, before we NULL the mbuf.
3226 * We must only call bus_dmamap_unload() once per mbuf chain
3227 * or behaviour is undefined.
3229 if (bf->bf_m != NULL) {
3231 * XXX is this POSTWRITE call required?
3233 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3234 BUS_DMASYNC_POSTWRITE);
3235 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3242 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state));
3248 ath_getbuf(struct ath_softc *sc, ath_buf_type_t btype)
3253 bf = _ath_getbuf_locked(sc, btype);
3255 * If a mgmt buffer was requested but we're out of those,
3256 * try requesting a normal one.
3258 if (bf == NULL && btype == ATH_BUFTYPE_MGMT)
3259 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL);
3260 ATH_TXBUF_UNLOCK(sc);
3262 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__);
3263 sc->sc_stats.ast_tx_qstop++;
3269 * Transmit a single frame.
3271 * net80211 will free the node reference if the transmit
3272 * fails, so don't free the node reference here.
3275 ath_transmit(struct ieee80211com *ic, struct mbuf *m)
3277 struct ath_softc *sc = ic->ic_softc;
3278 struct ieee80211_node *ni;
3285 * Tell the reset path that we're currently transmitting.
3288 if (sc->sc_inreset_cnt > 0) {
3289 DPRINTF(sc, ATH_DEBUG_XMIT,
3290 "%s: sc_inreset_cnt > 0; bailing\n", __func__);
3292 sc->sc_stats.ast_tx_qstop++;
3293 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: OACTIVE, finish");
3294 return (ENOBUFS); /* XXX should be EINVAL or? */
3296 sc->sc_txstart_cnt++;
3299 /* Wake the hardware up already */
3301 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3304 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: start");
3306 * Grab the TX lock - it's ok to do this here; we haven't
3307 * yet started transmitting.
3312 * Node reference, if there's one.
3314 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
3317 * Enforce how deep a node queue can get.
3319 * XXX it would be nicer if we kept an mbuf queue per
3320 * node and only whacked them into ath_bufs when we
3321 * are ready to schedule some traffic from them.
3322 * .. that may come later.
3324 * XXX we should also track the per-node hardware queue
3325 * depth so it is easy to limit the _SUM_ of the swq and
3326 * hwq frames. Since we only schedule two HWQ frames
3327 * at a time, this should be OK for now.
3329 if ((!(m->m_flags & M_EAPOL)) &&
3330 (ATH_NODE(ni)->an_swq_depth > sc->sc_txq_node_maxdepth)) {
3331 sc->sc_stats.ast_tx_nodeq_overflow++;
3337 * Check how many TX buffers are available.
3339 * If this is for non-EAPOL traffic, just leave some
3340 * space free in order for buffer cloning and raw
3341 * frame transmission to occur.
3343 * If it's for EAPOL traffic, ignore this for now.
3344 * Management traffic will be sent via the raw transmit
3345 * method which bypasses this check.
3347 * This is needed to ensure that EAPOL frames during
3348 * (re) keying have a chance to go out.
3350 * See kern/138379 for more information.
3352 if ((!(m->m_flags & M_EAPOL)) &&
3353 (sc->sc_txbuf_cnt <= sc->sc_txq_data_minfree)) {
3354 sc->sc_stats.ast_tx_nobuf++;
3360 * Grab a TX buffer and associated resources.
3362 * If it's an EAPOL frame, allocate a MGMT ath_buf.
3363 * That way even with temporary buffer exhaustion due to
3364 * the data path doesn't leave us without the ability
3365 * to transmit management frames.
3367 * Otherwise allocate a normal buffer.
3369 if (m->m_flags & M_EAPOL)
3370 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT);
3372 bf = ath_getbuf(sc, ATH_BUFTYPE_NORMAL);
3376 * If we failed to allocate a buffer, fail.
3378 * We shouldn't fail normally, due to the check
3381 sc->sc_stats.ast_tx_nobuf++;
3387 * At this point we have a buffer; so we need to free it
3388 * if we hit any error conditions.
3392 * Check for fragmentation. If this frame
3393 * has been broken up verify we have enough
3394 * buffers to send all the fragments so all
3398 if ((m->m_flags & M_FRAG) &&
3399 !ath_txfrag_setup(sc, &frags, m, ni)) {
3400 DPRINTF(sc, ATH_DEBUG_XMIT,
3401 "%s: out of txfrag buffers\n", __func__);
3402 sc->sc_stats.ast_tx_nofrag++;
3403 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1);
3405 * XXXGL: is mbuf valid after ath_txfrag_setup? If yes,
3406 * we shouldn't free it but return back.
3408 ieee80211_free_mbuf(m);
3414 * At this point if we have any TX fragments, then we will
3415 * have bumped the node reference once for each of those.
3419 * XXX Is there anything actually _enforcing_ that the
3420 * fragments are being transmitted in one hit, rather than
3421 * being interleaved with other transmissions on that
3424 * The ATH TX output lock is the only thing serialising this
3429 * Calculate the "next fragment" length field in ath_buf
3430 * in order to let the transmit path know enough about
3431 * what to next write to the hardware.
3433 if (m->m_flags & M_FRAG) {
3434 struct ath_buf *fbf = bf;
3435 struct ath_buf *n_fbf = NULL;
3436 struct mbuf *fm = m->m_nextpkt;
3439 * We need to walk the list of fragments and set
3440 * the next size to the following buffer.
3441 * However, the first buffer isn't in the frag
3442 * list, so we have to do some gymnastics here.
3444 TAILQ_FOREACH(n_fbf, &frags, bf_list) {
3445 fbf->bf_nextfraglen = fm->m_pkthdr.len;
3453 * Pass the frame to the h/w for transmission.
3454 * Fragmented frames have each frag chained together
3455 * with m_nextpkt. We know there are sufficient ath_buf's
3456 * to send all the frags because of work done by
3457 * ath_txfrag_setup. We leave m_nextpkt set while
3458 * calling ath_tx_start so it can use it to extend the
3459 * the tx duration to cover the subsequent frag and
3460 * so it can reclaim all the mbufs in case of an error;
3461 * ath_tx_start clears m_nextpkt once it commits to
3462 * handing the frame to the hardware.
3464 * Note: if this fails, then the mbufs are freed but
3465 * not the node reference.
3467 * So, we now have to free the node reference ourselves here
3468 * and return OK up to the stack.
3470 next = m->m_nextpkt;
3471 if (ath_tx_start(sc, ni, bf, m)) {
3473 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1);
3478 ath_returnbuf_head(sc, bf);
3480 * Free the rest of the node references and
3481 * buffers for the fragment list.
3483 ath_txfrag_cleanup(sc, &frags, ni);
3484 ATH_TXBUF_UNLOCK(sc);
3487 * XXX: And free the node/return OK; ath_tx_start() may have
3488 * modified the buffer. We currently have no way to
3489 * signify that the mbuf was freed but there was an error.
3491 ieee80211_free_node(ni);
3497 * Check here if the node is in power save state.
3499 ath_tx_update_tim(sc, ni, 1);
3503 * Beware of state changing between frags.
3504 * XXX check sta power-save state?
3506 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) {
3507 DPRINTF(sc, ATH_DEBUG_XMIT,
3508 "%s: flush fragmented packet, state %s\n",
3510 ieee80211_state_name[ni->ni_vap->iv_state]);
3512 ieee80211_free_mbuf(next);
3516 bf = TAILQ_FIRST(&frags);
3517 KASSERT(bf != NULL, ("no buf for txfrag"));
3518 TAILQ_REMOVE(&frags, bf, bf_list);
3523 * Bump watchdog timer.
3525 sc->sc_wd_timer = 5;
3531 * Finished transmitting!
3534 sc->sc_txstart_cnt--;
3537 /* Sleep the hardware if required */
3539 ath_power_restore_power_state(sc);
3542 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: finished");
3548 ath_media_change(struct ifnet *ifp)
3550 int error = ieee80211_media_change(ifp);
3551 /* NB: only the fixed rate can change and that doesn't need a reset */
3552 return (error == ENETRESET ? 0 : error);
3556 * Block/unblock tx+rx processing while a key change is done.
3557 * We assume the caller serializes key management operations
3558 * so we only need to worry about synchronization with other
3559 * uses that originate in the driver.
3562 ath_key_update_begin(struct ieee80211vap *vap)
3564 struct ath_softc *sc = vap->iv_ic->ic_softc;
3566 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
3567 taskqueue_block(sc->sc_tq);
3571 ath_key_update_end(struct ieee80211vap *vap)
3573 struct ath_softc *sc = vap->iv_ic->ic_softc;
3575 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
3576 taskqueue_unblock(sc->sc_tq);
3580 ath_update_promisc(struct ieee80211com *ic)
3582 struct ath_softc *sc = ic->ic_softc;
3585 /* configure rx filter */
3587 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3588 rfilt = ath_calcrxfilter(sc);
3589 ath_hal_setrxfilter(sc->sc_ah, rfilt);
3590 ath_power_restore_power_state(sc);
3593 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt);
3597 ath_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
3599 uint32_t val, *mfilt = arg;
3603 /* calculate XOR of eight 6bit values */
3605 val = le32dec(dl + 0);
3606 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3607 val = le32dec(dl + 3);
3608 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3610 mfilt[pos / 32] |= (1 << (pos % 32));
3616 * Driver-internal mcast update call.
3618 * Assumes the hardware is already awake.
3621 ath_update_mcast_hw(struct ath_softc *sc)
3623 struct ieee80211com *ic = &sc->sc_ic;
3626 /* calculate and install multicast filter */
3627 if (ic->ic_allmulti == 0) {
3628 struct ieee80211vap *vap;
3631 * Merge multicast addresses to form the hardware filter.
3633 mfilt[0] = mfilt[1] = 0;
3634 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next)
3635 if_foreach_llmaddr(vap->iv_ifp, ath_hash_maddr, &mfilt);
3637 mfilt[0] = mfilt[1] = ~0;
3639 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]);
3641 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n",
3642 __func__, mfilt[0], mfilt[1]);
3646 * Called from the net80211 layer - force the hardware
3647 * awake before operating.
3650 ath_update_mcast(struct ieee80211com *ic)
3652 struct ath_softc *sc = ic->ic_softc;
3655 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3658 ath_update_mcast_hw(sc);
3661 ath_power_restore_power_state(sc);
3666 ath_mode_init(struct ath_softc *sc)
3668 struct ieee80211com *ic = &sc->sc_ic;
3669 struct ath_hal *ah = sc->sc_ah;
3672 /* XXX power state? */
3674 /* configure rx filter */
3675 rfilt = ath_calcrxfilter(sc);
3676 ath_hal_setrxfilter(ah, rfilt);
3678 /* configure operational mode */
3679 ath_hal_setopmode(ah);
3681 /* handle any link-level address change */
3682 ath_hal_setmac(ah, ic->ic_macaddr);
3684 /* calculate and install multicast filter */
3685 ath_update_mcast_hw(sc);
3689 * Set the slot time based on the current setting.
3692 ath_setslottime(struct ath_softc *sc)
3694 struct ieee80211com *ic = &sc->sc_ic;
3695 struct ath_hal *ah = sc->sc_ah;
3698 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan))
3700 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan))
3702 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
3703 /* honor short/long slot time only in 11g */
3704 /* XXX shouldn't honor on pure g or turbo g channel */
3705 if (ic->ic_flags & IEEE80211_F_SHSLOT)
3706 usec = HAL_SLOT_TIME_9;
3708 usec = HAL_SLOT_TIME_20;
3710 usec = HAL_SLOT_TIME_9;
3712 DPRINTF(sc, ATH_DEBUG_RESET,
3713 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n",
3714 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags,
3715 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec);
3717 /* Wake up the hardware first before updating the slot time */
3719 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3720 ath_hal_setslottime(ah, usec);
3721 ath_power_restore_power_state(sc);
3722 sc->sc_updateslot = OK;
3727 * Callback from the 802.11 layer to update the
3728 * slot time based on the current setting.
3731 ath_updateslot(struct ieee80211com *ic)
3733 struct ath_softc *sc = ic->ic_softc;
3736 * When not coordinating the BSS, change the hardware
3737 * immediately. For other operation we defer the change
3738 * until beacon updates have propagated to the stations.
3740 * XXX sc_updateslot isn't changed behind a lock?
3742 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3743 ic->ic_opmode == IEEE80211_M_MBSS)
3744 sc->sc_updateslot = UPDATE;
3746 ath_setslottime(sc);
3750 * Append the contents of src to dst; both queues
3751 * are assumed to be locked.
3754 ath_txqmove(struct ath_txq *dst, struct ath_txq *src)
3757 ATH_TXQ_LOCK_ASSERT(src);
3758 ATH_TXQ_LOCK_ASSERT(dst);
3760 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list);
3761 dst->axq_link = src->axq_link;
3762 src->axq_link = NULL;
3763 dst->axq_depth += src->axq_depth;
3764 dst->axq_aggr_depth += src->axq_aggr_depth;
3766 src->axq_aggr_depth = 0;
3770 * Reset the hardware, with no loss.
3772 * This can't be used for a general case reset.
3775 ath_reset_proc(void *arg, int pending)
3777 struct ath_softc *sc = arg;
3780 device_printf(sc->sc_dev, "%s: resetting\n", __func__);
3782 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_FORCE_COLD);
3786 * Reset the hardware after detecting beacons have stopped.
3789 ath_bstuck_proc(void *arg, int pending)
3791 struct ath_softc *sc = arg;
3794 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0)
3795 device_printf(sc->sc_dev, "bb hang detected (0x%x)\n", hangs);
3797 #ifdef ATH_DEBUG_ALQ
3798 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_STUCK_BEACON))
3799 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_STUCK_BEACON, 0, NULL);
3802 device_printf(sc->sc_dev, "stuck beacon; resetting (bmiss count %u)\n",
3804 sc->sc_stats.ast_bstuck++;
3806 * This assumes that there's no simultaneous channel mode change
3809 ath_reset(sc, ATH_RESET_NOLOSS, HAL_RESET_FORCE_COLD);
3813 ath_desc_alloc(struct ath_softc *sc)
3817 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
3818 "tx", sc->sc_tx_desclen, ath_txbuf, ATH_MAX_SCATTER);
3822 sc->sc_txbuf_cnt = ath_txbuf;
3824 error = ath_descdma_setup(sc, &sc->sc_txdma_mgmt, &sc->sc_txbuf_mgmt,
3825 "tx_mgmt", sc->sc_tx_desclen, ath_txbuf_mgmt,
3828 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3833 * XXX mark txbuf_mgmt frames with ATH_BUF_MGMT, so the
3834 * flag doesn't have to be set in ath_getbuf_locked().
3837 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
3838 "beacon", sc->sc_tx_desclen, ATH_BCBUF, 1);
3840 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3841 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
3842 &sc->sc_txbuf_mgmt);
3849 ath_desc_free(struct ath_softc *sc)
3852 if (sc->sc_bdma.dd_desc_len != 0)
3853 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
3854 if (sc->sc_txdma.dd_desc_len != 0)
3855 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3856 if (sc->sc_txdma_mgmt.dd_desc_len != 0)
3857 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
3858 &sc->sc_txbuf_mgmt);
3861 static struct ieee80211_node *
3862 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
3864 struct ieee80211com *ic = vap->iv_ic;
3865 struct ath_softc *sc = ic->ic_softc;
3866 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
3867 struct ath_node *an;
3869 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
3874 ath_rate_node_init(sc, an);
3876 /* Setup the mutex - there's no associd yet so set the name to NULL */
3877 snprintf(an->an_name, sizeof(an->an_name), "%s: node %p",
3878 device_get_nameunit(sc->sc_dev), an);
3879 mtx_init(&an->an_mtx, an->an_name, NULL, MTX_DEF);
3881 /* XXX setup ath_tid */
3882 ath_tx_tid_init(sc, an);
3884 an->an_node_stats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
3885 an->an_node_stats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
3886 an->an_node_stats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
3888 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, mac, ":", an);
3889 return &an->an_node;
3893 ath_node_cleanup(struct ieee80211_node *ni)
3895 struct ieee80211com *ic = ni->ni_ic;
3896 struct ath_softc *sc = ic->ic_softc;
3898 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
3899 ni->ni_macaddr, ":", ATH_NODE(ni));
3901 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */
3902 ath_tx_node_flush(sc, ATH_NODE(ni));
3903 ath_rate_node_cleanup(sc, ATH_NODE(ni));
3904 sc->sc_node_cleanup(ni);
3908 ath_node_free(struct ieee80211_node *ni)
3910 struct ieee80211com *ic = ni->ni_ic;
3911 struct ath_softc *sc = ic->ic_softc;
3913 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
3914 ni->ni_macaddr, ":", ATH_NODE(ni));
3915 mtx_destroy(&ATH_NODE(ni)->an_mtx);
3916 sc->sc_node_free(ni);
3920 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise)
3922 struct ieee80211com *ic = ni->ni_ic;
3923 struct ath_softc *sc = ic->ic_softc;
3924 struct ath_hal *ah = sc->sc_ah;
3926 *rssi = ic->ic_node_getrssi(ni);
3927 if (ni->ni_chan != IEEE80211_CHAN_ANYC)
3928 *noise = ath_hal_getchannoise(ah, ni->ni_chan);
3930 *noise = -95; /* nominally correct */
3934 * Set the default antenna.
3937 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
3939 struct ath_hal *ah = sc->sc_ah;
3941 /* XXX block beacon interrupts */
3942 ath_hal_setdefantenna(ah, antenna);
3943 if (sc->sc_defant != antenna)
3944 sc->sc_stats.ast_ant_defswitch++;
3945 sc->sc_defant = antenna;
3946 sc->sc_rxotherant = 0;
3950 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
3952 txq->axq_qnum = qnum;
3955 txq->axq_aggr_depth = 0;
3956 txq->axq_intrcnt = 0;
3957 txq->axq_link = NULL;
3958 txq->axq_softc = sc;
3959 TAILQ_INIT(&txq->axq_q);
3960 TAILQ_INIT(&txq->axq_tidq);
3961 TAILQ_INIT(&txq->fifo.axq_q);
3962 ATH_TXQ_LOCK_INIT(sc, txq);
3966 * Setup a h/w transmit queue.
3968 static struct ath_txq *
3969 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
3971 struct ath_hal *ah = sc->sc_ah;
3975 memset(&qi, 0, sizeof(qi));
3976 qi.tqi_subtype = subtype;
3977 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
3978 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
3979 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
3981 * Enable interrupts only for EOL and DESC conditions.
3982 * We mark tx descriptors to receive a DESC interrupt
3983 * when a tx queue gets deep; otherwise waiting for the
3984 * EOL to reap descriptors. Note that this is done to
3985 * reduce interrupt load and this only defers reaping
3986 * descriptors, never transmitting frames. Aside from
3987 * reducing interrupts this also permits more concurrency.
3988 * The only potential downside is if the tx queue backs
3989 * up in which case the top half of the kernel may backup
3990 * due to a lack of tx descriptors.
3993 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE |
3994 HAL_TXQ_TXOKINT_ENABLE;
3996 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE |
3997 HAL_TXQ_TXDESCINT_ENABLE;
3999 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
4002 * NB: don't print a message, this happens
4003 * normally on parts with too few tx queues
4007 if (qnum >= nitems(sc->sc_txq)) {
4008 device_printf(sc->sc_dev,
4009 "hal qnum %u out of range, max %zu!\n",
4010 qnum, nitems(sc->sc_txq));
4011 ath_hal_releasetxqueue(ah, qnum);
4014 if (!ATH_TXQ_SETUP(sc, qnum)) {
4015 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
4016 sc->sc_txqsetup |= 1<<qnum;
4018 return &sc->sc_txq[qnum];
4022 * Setup a hardware data transmit queue for the specified
4023 * access control. The hal may not support all requested
4024 * queues in which case it will return a reference to a
4025 * previously setup queue. We record the mapping from ac's
4026 * to h/w queues for use by ath_tx_start and also track
4027 * the set of h/w queues being used to optimize work in the
4028 * transmit interrupt handler and related routines.
4031 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
4033 struct ath_txq *txq;
4035 if (ac >= nitems(sc->sc_ac2q)) {
4036 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
4037 ac, nitems(sc->sc_ac2q));
4040 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
4043 sc->sc_ac2q[ac] = txq;
4050 * Update WME parameters for a transmit queue.
4053 ath_txq_update(struct ath_softc *sc, int ac)
4055 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
4056 struct ieee80211com *ic = &sc->sc_ic;
4057 struct ath_txq *txq = sc->sc_ac2q[ac];
4058 struct chanAccParams chp;
4059 struct wmeParams *wmep;
4060 struct ath_hal *ah = sc->sc_ah;
4063 ieee80211_wme_ic_getparams(ic, &chp);
4064 wmep = &chp.cap_wmeParams[ac];
4066 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
4067 #ifdef IEEE80211_SUPPORT_TDMA
4070 * AIFS is zero so there's no pre-transmit wait. The
4071 * burst time defines the slot duration and is configured
4072 * through net80211. The QCU is setup to not do post-xmit
4073 * back off, lockout all lower-priority QCU's, and fire
4074 * off the DMA beacon alert timer which is setup based
4075 * on the slot configuration.
4077 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4078 | HAL_TXQ_TXERRINT_ENABLE
4079 | HAL_TXQ_TXURNINT_ENABLE
4080 | HAL_TXQ_TXEOLINT_ENABLE
4082 | HAL_TXQ_BACKOFF_DISABLE
4083 | HAL_TXQ_ARB_LOCKOUT_GLOBAL
4087 qi.tqi_readyTime = sc->sc_tdmaslotlen;
4088 qi.tqi_burstTime = qi.tqi_readyTime;
4092 * XXX shouldn't this just use the default flags
4093 * used in the previous queue setup?
4095 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4096 | HAL_TXQ_TXERRINT_ENABLE
4097 | HAL_TXQ_TXDESCINT_ENABLE
4098 | HAL_TXQ_TXURNINT_ENABLE
4099 | HAL_TXQ_TXEOLINT_ENABLE
4101 qi.tqi_aifs = wmep->wmep_aifsn;
4102 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
4103 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
4104 qi.tqi_readyTime = 0;
4105 qi.tqi_burstTime = IEEE80211_TXOP_TO_US(wmep->wmep_txopLimit);
4106 #ifdef IEEE80211_SUPPORT_TDMA
4110 DPRINTF(sc, ATH_DEBUG_RESET,
4111 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n",
4112 __func__, txq->axq_qnum, qi.tqi_qflags,
4113 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime);
4115 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
4116 device_printf(sc->sc_dev, "unable to update hardware queue "
4117 "parameters for %s traffic!\n", ieee80211_wme_acnames[ac]);
4120 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
4123 #undef ATH_EXPONENT_TO_VALUE
4127 * Callback from the 802.11 layer to update WME parameters.
4130 ath_wme_update(struct ieee80211com *ic)
4132 struct ath_softc *sc = ic->ic_softc;
4134 return !ath_txq_update(sc, WME_AC_BE) ||
4135 !ath_txq_update(sc, WME_AC_BK) ||
4136 !ath_txq_update(sc, WME_AC_VI) ||
4137 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
4141 * Reclaim resources for a setup queue.
4144 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
4147 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
4148 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
4149 ATH_TXQ_LOCK_DESTROY(txq);
4153 * Reclaim all tx queue resources.
4156 ath_tx_cleanup(struct ath_softc *sc)
4160 ATH_TXBUF_LOCK_DESTROY(sc);
4161 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4162 if (ATH_TXQ_SETUP(sc, i))
4163 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
4167 * Return h/w rate index for an IEEE rate (w/o basic rate bit)
4168 * using the current rates in sc_rixmap.
4171 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate)
4173 int rix = sc->sc_rixmap[rate];
4174 /* NB: return lowest rix for invalid rate */
4175 return (rix == 0xff ? 0 : rix);
4179 ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts,
4182 struct ieee80211_node *ni = bf->bf_node;
4183 struct ieee80211com *ic = &sc->sc_ic;
4186 if (ts->ts_status == 0) {
4187 u_int8_t txant = ts->ts_antenna;
4188 sc->sc_stats.ast_ant_tx[txant]++;
4189 sc->sc_ant_tx[txant]++;
4190 if (ts->ts_finaltsi != 0)
4191 sc->sc_stats.ast_tx_altrate++;
4193 /* XXX TODO: should do per-pri conuters */
4194 pri = M_WME_GETAC(bf->bf_m);
4195 if (pri >= WME_AC_VO)
4196 ic->ic_wme.wme_hipri_traffic++;
4198 if ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)
4199 ni->ni_inact = ni->ni_inact_reload;
4201 if (ts->ts_status & HAL_TXERR_XRETRY)
4202 sc->sc_stats.ast_tx_xretries++;
4203 if (ts->ts_status & HAL_TXERR_FIFO)
4204 sc->sc_stats.ast_tx_fifoerr++;
4205 if (ts->ts_status & HAL_TXERR_FILT)
4206 sc->sc_stats.ast_tx_filtered++;
4207 if (ts->ts_status & HAL_TXERR_XTXOP)
4208 sc->sc_stats.ast_tx_xtxop++;
4209 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED)
4210 sc->sc_stats.ast_tx_timerexpired++;
4212 if (bf->bf_m->m_flags & M_FF)
4213 sc->sc_stats.ast_ff_txerr++;
4215 /* XXX when is this valid? */
4216 if (ts->ts_flags & HAL_TX_DESC_CFG_ERR)
4217 sc->sc_stats.ast_tx_desccfgerr++;
4219 * This can be valid for successful frame transmission!
4220 * If there's a TX FIFO underrun during aggregate transmission,
4221 * the MAC will pad the rest of the aggregate with delimiters.
4222 * If a BA is returned, the frame is marked as "OK" and it's up
4223 * to the TX completion code to notice which frames weren't
4224 * successfully transmitted.
4226 if (ts->ts_flags & HAL_TX_DATA_UNDERRUN)
4227 sc->sc_stats.ast_tx_data_underrun++;
4228 if (ts->ts_flags & HAL_TX_DELIM_UNDERRUN)
4229 sc->sc_stats.ast_tx_delim_underrun++;
4231 sr = ts->ts_shortretry;
4232 lr = ts->ts_longretry;
4233 sc->sc_stats.ast_tx_shortretry += sr;
4234 sc->sc_stats.ast_tx_longretry += lr;
4239 * The default completion. If fail is 1, this means
4240 * "please don't retry the frame, and just return -1 status
4241 * to the net80211 stack.
4244 ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
4246 struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
4252 st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ?
4253 ts->ts_status : HAL_TXERR_XRETRY;
4256 if (bf->bf_state.bfs_dobaw)
4257 device_printf(sc->sc_dev,
4258 "%s: bf %p: seqno %d: dobaw should've been cleared!\n",
4261 SEQNO(bf->bf_state.bfs_seqno));
4263 if (bf->bf_next != NULL)
4264 device_printf(sc->sc_dev,
4265 "%s: bf %p: seqno %d: bf_next not NULL!\n",
4268 SEQNO(bf->bf_state.bfs_seqno));
4271 * Check if the node software queue is empty; if so
4272 * then clear the TIM.
4274 * This needs to be done before the buffer is freed as
4275 * otherwise the node reference will have been released
4276 * and the node may not actually exist any longer.
4278 * XXX I don't like this belonging here, but it's cleaner
4279 * to do it here right now then all the other places
4280 * where ath_tx_default_comp() is called.
4282 * XXX TODO: during drain, ensure that the callback is
4283 * being called so we get a chance to update the TIM.
4287 ath_tx_update_tim(sc, bf->bf_node, 0);
4292 * Do any tx complete callback. Note this must
4293 * be done before releasing the node reference.
4294 * This will free the mbuf, release the net80211
4295 * node and recycle the ath_buf.
4297 ath_tx_freebuf(sc, bf, st);
4301 * Update rate control with the given completion status.
4304 ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni,
4305 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen,
4306 int rc_framelen, int nframes, int nbad)
4308 struct ath_node *an;
4310 /* Only for unicast frames */
4315 ATH_NODE_UNLOCK_ASSERT(an);
4318 * XXX TODO: teach the rate control about TXERR_FILT and
4319 * see about handling it (eg see how many attempts were
4320 * made before it got filtered and account for that.)
4323 if ((ts->ts_status & HAL_TXERR_FILT) == 0) {
4325 ath_rate_tx_complete(sc, an, rc, ts, frmlen, rc_framelen,
4327 ATH_NODE_UNLOCK(an);
4332 * Process the completion of the given buffer.
4334 * This calls the rate control update and then the buffer completion.
4335 * This will either free the buffer or requeue it. In any case, the
4336 * bf pointer should be treated as invalid after this function is called.
4339 ath_tx_process_buf_completion(struct ath_softc *sc, struct ath_txq *txq,
4340 struct ath_tx_status *ts, struct ath_buf *bf)
4342 struct ieee80211_node *ni = bf->bf_node;
4344 ATH_TX_UNLOCK_ASSERT(sc);
4345 ATH_TXQ_UNLOCK_ASSERT(txq);
4347 /* If unicast frame, update general statistics */
4349 /* update statistics */
4350 ath_tx_update_stats(sc, ts, bf);
4354 * Call the completion handler.
4355 * The completion handler is responsible for
4356 * calling the rate control code.
4358 * Frames with no completion handler get the
4359 * rate control code called here.
4361 if (bf->bf_comp == NULL) {
4362 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
4363 (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) {
4365 * XXX assume this isn't an aggregate
4368 * XXX TODO: also do this for filtered frames?
4369 * Once rate control knows about them?
4371 ath_tx_update_ratectrl(sc, ni,
4372 bf->bf_state.bfs_rc, ts,
4373 bf->bf_state.bfs_pktlen,
4374 bf->bf_state.bfs_pktlen,
4376 (ts->ts_status == 0 ? 0 : 1));
4378 ath_tx_default_comp(sc, bf, 0);
4380 bf->bf_comp(sc, bf, 0);
4386 * Process completed xmit descriptors from the specified queue.
4387 * Kick the packet scheduler if needed. This can occur from this
4391 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched)
4393 struct ath_hal *ah = sc->sc_ah;
4395 struct ath_desc *ds;
4396 struct ath_tx_status *ts;
4397 struct ieee80211_node *ni;
4398 #ifdef IEEE80211_SUPPORT_SUPERG
4399 struct ieee80211com *ic = &sc->sc_ic;
4400 #endif /* IEEE80211_SUPPORT_SUPERG */
4404 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
4405 __func__, txq->axq_qnum,
4406 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4409 ATH_KTR(sc, ATH_KTR_TXCOMP, 4,
4410 "ath_tx_processq: txq=%u head %p link %p depth %p",
4412 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4419 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
4420 bf = TAILQ_FIRST(&txq->axq_q);
4422 ATH_TXQ_UNLOCK(txq);
4425 ds = bf->bf_lastds; /* XXX must be setup correctly! */
4426 ts = &bf->bf_status.ds_txstat;
4428 status = ath_hal_txprocdesc(ah, ds, ts);
4430 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
4431 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4433 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0))
4434 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4437 #ifdef ATH_DEBUG_ALQ
4438 if (if_ath_alq_checkdebug(&sc->sc_alq,
4439 ATH_ALQ_EDMA_TXSTATUS)) {
4440 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS,
4441 sc->sc_tx_statuslen,
4446 if (status == HAL_EINPROGRESS) {
4447 ATH_KTR(sc, ATH_KTR_TXCOMP, 3,
4448 "ath_tx_processq: txq=%u, bf=%p ds=%p, HAL_EINPROGRESS",
4449 txq->axq_qnum, bf, ds);
4450 ATH_TXQ_UNLOCK(txq);
4453 ATH_TXQ_REMOVE(txq, bf, bf_list);
4458 if (txq->axq_qnum != bf->bf_state.bfs_tx_queue) {
4459 device_printf(sc->sc_dev,
4460 "%s: TXQ=%d: bf=%p, bfs_tx_queue=%d\n",
4464 bf->bf_state.bfs_tx_queue);
4466 if (txq->axq_qnum != bf->bf_last->bf_state.bfs_tx_queue) {
4467 device_printf(sc->sc_dev,
4468 "%s: TXQ=%d: bf_last=%p, bfs_tx_queue=%d\n",
4472 bf->bf_last->bf_state.bfs_tx_queue);
4476 if (txq->axq_depth > 0) {
4478 * More frames follow. Mark the buffer busy
4479 * so it's not re-used while the hardware may
4480 * still re-read the link field in the descriptor.
4482 * Use the last buffer in an aggregate as that
4483 * is where the hardware may be - intermediate
4484 * descriptors won't be "busy".
4486 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
4488 txq->axq_link = NULL;
4490 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
4492 if (bf->bf_state.bfs_aggr)
4493 txq->axq_aggr_depth--;
4497 ATH_KTR(sc, ATH_KTR_TXCOMP, 5,
4498 "ath_tx_processq: txq=%u, bf=%p, ds=%p, ni=%p, ts_status=0x%08x",
4499 txq->axq_qnum, bf, ds, ni, ts->ts_status);
4501 * If unicast frame was ack'd update RSSI,
4502 * including the last rx time used to
4503 * workaround phantom bmiss interrupts.
4505 if (ni != NULL && ts->ts_status == 0 &&
4506 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) {
4508 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
4509 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
4511 ATH_RSSI_LPF(ATH_NODE(ni)->an_node_stats.ns_avgtxrssi,
4514 ATH_TXQ_UNLOCK(txq);
4517 * Update statistics and call completion
4519 ath_tx_process_buf_completion(sc, txq, ts, bf);
4521 /* XXX at this point, bf and ni may be totally invalid */
4523 #ifdef IEEE80211_SUPPORT_SUPERG
4525 * Flush fast-frame staging queue when traffic slows.
4527 if (txq->axq_depth <= 1)
4528 ieee80211_ff_flush(ic, txq->axq_ac);
4531 /* Kick the software TXQ scheduler */
4534 ath_txq_sched(sc, txq);
4538 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4539 "ath_tx_processq: txq=%u: done",
4545 #define TXQACTIVE(t, q) ( (t) & (1 << (q)))
4548 * Deferred processing of transmit interrupt; special-cased
4549 * for a single hardware transmit queue (e.g. 5210 and 5211).
4552 ath_tx_proc_q0(void *arg, int npending)
4554 struct ath_softc *sc = arg;
4558 sc->sc_txproc_cnt++;
4559 txqs = sc->sc_txq_active;
4560 sc->sc_txq_active &= ~txqs;
4564 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4567 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4568 "ath_tx_proc_q0: txqs=0x%08x", txqs);
4570 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1))
4571 /* XXX why is lastrx updated in tx code? */
4572 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4573 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4574 ath_tx_processq(sc, sc->sc_cabq, 1);
4575 sc->sc_wd_timer = 0;
4578 ath_led_event(sc, sc->sc_txrix);
4581 sc->sc_txproc_cnt--;
4585 ath_power_restore_power_state(sc);
4592 * Deferred processing of transmit interrupt; special-cased
4593 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
4596 ath_tx_proc_q0123(void *arg, int npending)
4598 struct ath_softc *sc = arg;
4603 sc->sc_txproc_cnt++;
4604 txqs = sc->sc_txq_active;
4605 sc->sc_txq_active &= ~txqs;
4609 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4612 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4613 "ath_tx_proc_q0123: txqs=0x%08x", txqs);
4616 * Process each active queue.
4619 if (TXQACTIVE(txqs, 0))
4620 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1);
4621 if (TXQACTIVE(txqs, 1))
4622 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1);
4623 if (TXQACTIVE(txqs, 2))
4624 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1);
4625 if (TXQACTIVE(txqs, 3))
4626 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1);
4627 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4628 ath_tx_processq(sc, sc->sc_cabq, 1);
4630 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4632 sc->sc_wd_timer = 0;
4635 ath_led_event(sc, sc->sc_txrix);
4638 sc->sc_txproc_cnt--;
4642 ath_power_restore_power_state(sc);
4649 * Deferred processing of transmit interrupt.
4652 ath_tx_proc(void *arg, int npending)
4654 struct ath_softc *sc = arg;
4659 sc->sc_txproc_cnt++;
4660 txqs = sc->sc_txq_active;
4661 sc->sc_txq_active &= ~txqs;
4665 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4668 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, "ath_tx_proc: txqs=0x%08x", txqs);
4671 * Process each active queue.
4674 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4675 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i))
4676 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1);
4678 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4680 sc->sc_wd_timer = 0;
4683 ath_led_event(sc, sc->sc_txrix);
4686 sc->sc_txproc_cnt--;
4690 ath_power_restore_power_state(sc);
4698 * Deferred processing of TXQ rescheduling.
4701 ath_txq_sched_tasklet(void *arg, int npending)
4703 struct ath_softc *sc = arg;
4706 /* XXX is skipping ok? */
4709 if (sc->sc_inreset_cnt > 0) {
4710 device_printf(sc->sc_dev,
4711 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
4716 sc->sc_txproc_cnt++;
4720 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4724 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
4725 if (ATH_TXQ_SETUP(sc, i)) {
4726 ath_txq_sched(sc, &sc->sc_txq[i]);
4732 ath_power_restore_power_state(sc);
4736 sc->sc_txproc_cnt--;
4741 ath_returnbuf_tail(struct ath_softc *sc, struct ath_buf *bf)
4744 ATH_TXBUF_LOCK_ASSERT(sc);
4746 if (bf->bf_flags & ATH_BUF_MGMT)
4747 TAILQ_INSERT_TAIL(&sc->sc_txbuf_mgmt, bf, bf_list);
4749 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
4751 if (sc->sc_txbuf_cnt > ath_txbuf) {
4752 device_printf(sc->sc_dev,
4753 "%s: sc_txbuf_cnt > %d?\n",
4756 sc->sc_txbuf_cnt = ath_txbuf;
4762 ath_returnbuf_head(struct ath_softc *sc, struct ath_buf *bf)
4765 ATH_TXBUF_LOCK_ASSERT(sc);
4767 if (bf->bf_flags & ATH_BUF_MGMT)
4768 TAILQ_INSERT_HEAD(&sc->sc_txbuf_mgmt, bf, bf_list);
4770 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
4772 if (sc->sc_txbuf_cnt > ATH_TXBUF) {
4773 device_printf(sc->sc_dev,
4774 "%s: sc_txbuf_cnt > %d?\n",
4777 sc->sc_txbuf_cnt = ATH_TXBUF;
4783 * Free the holding buffer if it exists
4786 ath_txq_freeholdingbuf(struct ath_softc *sc, struct ath_txq *txq)
4788 ATH_TXBUF_UNLOCK_ASSERT(sc);
4789 ATH_TXQ_LOCK_ASSERT(txq);
4791 if (txq->axq_holdingbf == NULL)
4794 txq->axq_holdingbf->bf_flags &= ~ATH_BUF_BUSY;
4797 ath_returnbuf_tail(sc, txq->axq_holdingbf);
4798 ATH_TXBUF_UNLOCK(sc);
4800 txq->axq_holdingbf = NULL;
4804 * Add this buffer to the holding queue, freeing the previous
4808 ath_txq_addholdingbuf(struct ath_softc *sc, struct ath_buf *bf)
4810 struct ath_txq *txq;
4812 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
4814 ATH_TXBUF_UNLOCK_ASSERT(sc);
4815 ATH_TXQ_LOCK_ASSERT(txq);
4817 /* XXX assert ATH_BUF_BUSY is set */
4819 /* XXX assert the tx queue is under the max number */
4820 if (bf->bf_state.bfs_tx_queue > HAL_NUM_TX_QUEUES) {
4821 device_printf(sc->sc_dev, "%s: bf=%p: invalid tx queue (%d)\n",
4824 bf->bf_state.bfs_tx_queue);
4825 bf->bf_flags &= ~ATH_BUF_BUSY;
4826 ath_returnbuf_tail(sc, bf);
4829 ath_txq_freeholdingbuf(sc, txq);
4830 txq->axq_holdingbf = bf;
4834 * Return a buffer to the pool and update the 'busy' flag on the
4835 * previous 'tail' entry.
4837 * This _must_ only be called when the buffer is involved in a completed
4838 * TX. The logic is that if it was part of an active TX, the previous
4839 * buffer on the list is now not involved in a halted TX DMA queue, waiting
4840 * for restart (eg for TDMA.)
4842 * The caller must free the mbuf and recycle the node reference.
4844 * XXX This method of handling busy / holding buffers is insanely stupid.
4845 * It requires bf_state.bfs_tx_queue to be correctly assigned. It would
4846 * be much nicer if buffers in the processq() methods would instead be
4847 * always completed there (pushed onto a txq or ath_bufhead) so we knew
4848 * exactly what hardware queue they came from in the first place.
4851 ath_freebuf(struct ath_softc *sc, struct ath_buf *bf)
4853 struct ath_txq *txq;
4855 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
4857 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__));
4858 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__));
4861 * If this buffer is busy, push it onto the holding queue.
4863 if (bf->bf_flags & ATH_BUF_BUSY) {
4865 ath_txq_addholdingbuf(sc, bf);
4866 ATH_TXQ_UNLOCK(txq);
4871 * Not a busy buffer, so free normally
4874 ath_returnbuf_tail(sc, bf);
4875 ATH_TXBUF_UNLOCK(sc);
4879 * This is currently used by ath_tx_draintxq() and
4880 * ath_tx_tid_free_pkts().
4882 * It recycles a single ath_buf.
4885 ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status)
4887 struct ieee80211_node *ni = bf->bf_node;
4888 struct mbuf *m0 = bf->bf_m;
4891 * Make sure that we only sync/unload if there's an mbuf.
4892 * If not (eg we cloned a buffer), the unload will have already
4895 if (bf->bf_m != NULL) {
4896 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
4897 BUS_DMASYNC_POSTWRITE);
4898 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4904 /* Free the buffer, it's not needed any longer */
4905 ath_freebuf(sc, bf);
4907 /* Pass the buffer back to net80211 - completing it */
4908 ieee80211_tx_complete(ni, m0, status);
4911 static struct ath_buf *
4912 ath_tx_draintxq_get_one(struct ath_softc *sc, struct ath_txq *txq)
4916 ATH_TXQ_LOCK_ASSERT(txq);
4919 * Drain the FIFO queue first, then if it's
4920 * empty, move to the normal frame queue.
4922 bf = TAILQ_FIRST(&txq->fifo.axq_q);
4925 * Is it the last buffer in this set?
4926 * Decrement the FIFO counter.
4928 if (bf->bf_flags & ATH_BUF_FIFOEND) {
4929 if (txq->axq_fifo_depth == 0) {
4930 device_printf(sc->sc_dev,
4931 "%s: Q%d: fifo_depth=0, fifo.axq_depth=%d?\n",
4934 txq->fifo.axq_depth);
4936 txq->axq_fifo_depth--;
4938 ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list);
4945 if (txq->axq_fifo_depth != 0 || txq->fifo.axq_depth != 0) {
4946 device_printf(sc->sc_dev,
4947 "%s: Q%d: fifo_depth=%d, fifo.axq_depth=%d\n",
4950 txq->axq_fifo_depth,
4951 txq->fifo.axq_depth);
4955 * Now drain the pending queue.
4957 bf = TAILQ_FIRST(&txq->axq_q);
4959 txq->axq_link = NULL;
4962 ATH_TXQ_REMOVE(txq, bf, bf_list);
4967 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
4970 struct ath_hal *ah = sc->sc_ah;
4976 * NB: this assumes output has been stopped and
4977 * we do not need to block ath_tx_proc
4979 for (ix = 0;; ix++) {
4981 bf = ath_tx_draintxq_get_one(sc, txq);
4983 ATH_TXQ_UNLOCK(txq);
4986 if (bf->bf_state.bfs_aggr)
4987 txq->axq_aggr_depth--;
4989 if (sc->sc_debug & ATH_DEBUG_RESET) {
4990 struct ieee80211com *ic = &sc->sc_ic;
4994 * EDMA operation has a TX completion FIFO
4995 * separate from the TX descriptor, so this
4996 * method of checking the "completion" status
4999 if (! sc->sc_isedma) {
5000 status = (ath_hal_txprocdesc(ah,
5002 &bf->bf_status.ds_txstat) == HAL_OK);
5004 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, status);
5005 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *),
5006 bf->bf_m->m_len, 0, -1);
5008 #endif /* ATH_DEBUG */
5010 * Since we're now doing magic in the completion
5011 * functions, we -must- call it for aggregation
5012 * destinations or BAW tracking will get upset.
5015 * Clear ATH_BUF_BUSY; the completion handler
5016 * will free the buffer.
5018 ATH_TXQ_UNLOCK(txq);
5019 bf->bf_flags &= ~ATH_BUF_BUSY;
5021 bf->bf_comp(sc, bf, 1);
5023 ath_tx_default_comp(sc, bf, 1);
5027 * Free the holding buffer if it exists
5030 ath_txq_freeholdingbuf(sc, txq);
5031 ATH_TXQ_UNLOCK(txq);
5034 * Drain software queued frames which are on
5037 ath_tx_txq_drain(sc, txq);
5041 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
5043 struct ath_hal *ah = sc->sc_ah;
5045 ATH_TXQ_LOCK_ASSERT(txq);
5047 DPRINTF(sc, ATH_DEBUG_RESET,
5048 "%s: tx queue [%u] %p, active=%d, hwpending=%d, flags 0x%08x, "
5049 "link %p, holdingbf=%p\n",
5052 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
5053 (int) (!! ath_hal_txqenabled(ah, txq->axq_qnum)),
5054 (int) ath_hal_numtxpending(ah, txq->axq_qnum),
5057 txq->axq_holdingbf);
5059 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
5060 /* We've stopped TX DMA, so mark this as stopped. */
5061 txq->axq_flags &= ~ATH_TXQ_PUTRUNNING;
5064 if ((sc->sc_debug & ATH_DEBUG_RESET)
5065 && (txq->axq_holdingbf != NULL)) {
5066 ath_printtxbuf(sc, txq->axq_holdingbf, txq->axq_qnum, 0, 0);
5072 ath_stoptxdma(struct ath_softc *sc)
5074 struct ath_hal *ah = sc->sc_ah;
5077 /* XXX return value */
5081 if (!sc->sc_invalid) {
5082 /* don't touch the hardware if marked invalid */
5083 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
5084 __func__, sc->sc_bhalq,
5085 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq),
5088 /* stop the beacon queue */
5089 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
5091 /* Stop the data queues */
5092 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
5093 if (ATH_TXQ_SETUP(sc, i)) {
5094 ATH_TXQ_LOCK(&sc->sc_txq[i]);
5095 ath_tx_stopdma(sc, &sc->sc_txq[i]);
5096 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
5106 ath_tx_dump(struct ath_softc *sc, struct ath_txq *txq)
5108 struct ath_hal *ah = sc->sc_ah;
5112 if (! (sc->sc_debug & ATH_DEBUG_RESET))
5115 device_printf(sc->sc_dev, "%s: Q%d: begin\n",
5116 __func__, txq->axq_qnum);
5117 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) {
5118 ath_printtxbuf(sc, bf, txq->axq_qnum, i,
5119 ath_hal_txprocdesc(ah, bf->bf_lastds,
5120 &bf->bf_status.ds_txstat) == HAL_OK);
5123 device_printf(sc->sc_dev, "%s: Q%d: end\n",
5124 __func__, txq->axq_qnum);
5126 #endif /* ATH_DEBUG */
5129 * Drain the transmit queues and reclaim resources.
5132 ath_legacy_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
5134 struct ath_hal *ah = sc->sc_ah;
5135 struct ath_buf *bf_last;
5138 (void) ath_stoptxdma(sc);
5141 * Dump the queue contents
5143 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
5145 * XXX TODO: should we just handle the completed TX frames
5146 * here, whether or not the reset is a full one or not?
5148 if (ATH_TXQ_SETUP(sc, i)) {
5150 if (sc->sc_debug & ATH_DEBUG_RESET)
5151 ath_tx_dump(sc, &sc->sc_txq[i]);
5152 #endif /* ATH_DEBUG */
5153 if (reset_type == ATH_RESET_NOLOSS) {
5154 ath_tx_processq(sc, &sc->sc_txq[i], 0);
5155 ATH_TXQ_LOCK(&sc->sc_txq[i]);
5157 * Free the holding buffer; DMA is now
5160 ath_txq_freeholdingbuf(sc, &sc->sc_txq[i]);
5162 * Setup the link pointer to be the
5163 * _last_ buffer/descriptor in the list.
5164 * If there's nothing in the list, set it
5167 bf_last = ATH_TXQ_LAST(&sc->sc_txq[i],
5169 if (bf_last != NULL) {
5170 ath_hal_gettxdesclinkptr(ah,
5172 &sc->sc_txq[i].axq_link);
5174 sc->sc_txq[i].axq_link = NULL;
5176 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
5178 ath_tx_draintxq(sc, &sc->sc_txq[i]);
5182 if (sc->sc_debug & ATH_DEBUG_RESET) {
5183 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf);
5184 if (bf != NULL && bf->bf_m != NULL) {
5185 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0,
5186 ath_hal_txprocdesc(ah, bf->bf_lastds,
5187 &bf->bf_status.ds_txstat) == HAL_OK);
5188 ieee80211_dump_pkt(&sc->sc_ic,
5189 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len,
5193 #endif /* ATH_DEBUG */
5194 sc->sc_wd_timer = 0;
5198 * Update internal state after a channel change.
5201 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
5203 enum ieee80211_phymode mode;
5206 * Change channels and update the h/w rate map
5207 * if we're switching; e.g. 11a to 11b/g.
5209 mode = ieee80211_chan2mode(chan);
5210 if (mode != sc->sc_curmode)
5211 ath_setcurmode(sc, mode);
5212 sc->sc_curchan = chan;
5216 * Set/change channels. If the channel is really being changed,
5217 * it's done by resetting the chip. To accomplish this we must
5218 * first cleanup any pending DMA, then restart stuff after a la
5222 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
5224 struct ieee80211com *ic = &sc->sc_ic;
5225 struct ath_hal *ah = sc->sc_ah;
5228 /* Treat this as an interface reset */
5229 ATH_PCU_UNLOCK_ASSERT(sc);
5230 ATH_UNLOCK_ASSERT(sc);
5232 /* (Try to) stop TX/RX from occurring */
5233 taskqueue_block(sc->sc_tq);
5237 /* Disable interrupts */
5238 ath_hal_intrset(ah, 0);
5240 /* Stop new RX/TX/interrupt completion */
5241 if (ath_reset_grablock(sc, 1) == 0) {
5242 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
5246 /* Stop pending RX/TX completion */
5247 ath_txrx_stop_locked(sc);
5251 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n",
5252 __func__, ieee80211_chan2ieee(ic, chan),
5253 chan->ic_freq, chan->ic_flags);
5254 if (chan != sc->sc_curchan) {
5257 * To switch channels clear any pending DMA operations;
5258 * wait long enough for the RX fifo to drain, reset the
5259 * hardware at the new frequency, and then re-enable
5260 * the relevant bits of the h/w.
5263 ath_hal_intrset(ah, 0); /* disable interrupts */
5265 ath_stoprecv(sc, 1); /* turn off frame recv */
5267 * First, handle completed TX/RX frames.
5270 ath_draintxq(sc, ATH_RESET_NOLOSS);
5272 * Next, flush the non-scheduled frames.
5274 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */
5276 ath_update_chainmasks(sc, chan);
5277 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
5278 sc->sc_cur_rxchainmask);
5279 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE,
5280 HAL_RESET_NORMAL, &status)) {
5281 device_printf(sc->sc_dev, "%s: unable to reset "
5282 "channel %u (%u MHz, flags 0x%x), hal status %u\n",
5283 __func__, ieee80211_chan2ieee(ic, chan),
5284 chan->ic_freq, chan->ic_flags, status);
5288 sc->sc_diversity = ath_hal_getdiversity(ah);
5291 sc->sc_rx_stopped = 1;
5292 sc->sc_rx_resetted = 1;
5295 /* Quiet time handling - ensure we resync */
5296 ath_vap_clear_quiet_ie(sc);
5298 /* Let DFS at it in case it's a DFS channel */
5299 ath_dfs_radar_enable(sc, chan);
5301 /* Let spectral at in case spectral is enabled */
5302 ath_spectral_enable(sc, chan);
5305 * Let bluetooth coexistence at in case it's needed for this
5308 ath_btcoex_enable(sc, ic->ic_curchan);
5311 * If we're doing TDMA, enforce the TXOP limitation for chips
5314 if (sc->sc_hasenforcetxop && sc->sc_tdma)
5315 ath_hal_setenforcetxop(sc->sc_ah, 1);
5317 ath_hal_setenforcetxop(sc->sc_ah, 0);
5320 * Re-enable rx framework.
5322 if (ath_startrecv(sc) != 0) {
5323 device_printf(sc->sc_dev,
5324 "%s: unable to restart recv logic\n", __func__);
5330 * Change channels and update the h/w rate map
5331 * if we're switching; e.g. 11a to 11b/g.
5333 ath_chan_change(sc, chan);
5336 * Reset clears the beacon timers; reset them
5339 if (sc->sc_beacons) { /* restart beacons */
5340 #ifdef IEEE80211_SUPPORT_TDMA
5342 ath_tdma_config(sc, NULL);
5345 ath_beacon_config(sc, NULL);
5349 * Re-enable interrupts.
5352 ath_hal_intrset(ah, sc->sc_imask);
5358 sc->sc_inreset_cnt--;
5359 /* XXX only do this if sc_inreset_cnt == 0? */
5360 ath_hal_intrset(ah, sc->sc_imask);
5364 /* XXX ath_start? */
5370 * Periodically recalibrate the PHY to account
5371 * for temperature/environment changes.
5374 ath_calibrate(void *arg)
5376 struct ath_softc *sc = arg;
5377 struct ath_hal *ah = sc->sc_ah;
5378 struct ieee80211com *ic = &sc->sc_ic;
5379 HAL_BOOL longCal, isCalDone = AH_TRUE;
5380 HAL_BOOL aniCal, shortCal = AH_FALSE;
5383 ATH_LOCK_ASSERT(sc);
5386 * Force the hardware awake for ANI work.
5388 ath_power_set_power_state(sc, HAL_PM_AWAKE);
5390 /* Skip trying to do this if we're in reset */
5391 if (sc->sc_inreset_cnt)
5394 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */
5396 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz);
5397 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000);
5398 if (sc->sc_doresetcal)
5399 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000);
5401 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal);
5403 sc->sc_stats.ast_ani_cal++;
5404 sc->sc_lastani = ticks;
5405 ath_hal_ani_poll(ah, sc->sc_curchan);
5409 sc->sc_stats.ast_per_cal++;
5410 sc->sc_lastlongcal = ticks;
5411 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
5413 * Rfgain is out of bounds, reset the chip
5414 * to load new gain values.
5416 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5417 "%s: rfgain change\n", __func__);
5418 sc->sc_stats.ast_per_rfgain++;
5419 sc->sc_resetcal = 0;
5420 sc->sc_doresetcal = AH_TRUE;
5421 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
5422 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
5423 ath_power_restore_power_state(sc);
5427 * If this long cal is after an idle period, then
5428 * reset the data collection state so we start fresh.
5430 if (sc->sc_resetcal) {
5431 (void) ath_hal_calreset(ah, sc->sc_curchan);
5432 sc->sc_lastcalreset = ticks;
5433 sc->sc_lastshortcal = ticks;
5434 sc->sc_resetcal = 0;
5435 sc->sc_doresetcal = AH_TRUE;
5439 /* Only call if we're doing a short/long cal, not for ANI calibration */
5440 if (shortCal || longCal) {
5441 isCalDone = AH_FALSE;
5442 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) {
5445 * Calibrate noise floor data again in case of change.
5447 ath_hal_process_noisefloor(ah);
5450 DPRINTF(sc, ATH_DEBUG_ANY,
5451 "%s: calibration of channel %u failed\n",
5452 __func__, sc->sc_curchan->ic_freq);
5453 sc->sc_stats.ast_per_calfail++;
5456 * XXX TODO: get the NF calibration results from the HAL.
5457 * If we failed NF cal then schedule a hard reset to potentially
5458 * un-freeze the PHY.
5460 * Note we have to be careful here to not get stuck in an
5461 * infinite NIC restart. Ideally we'd not restart if we
5462 * failed the first NF cal - that /can/ fail sometimes in
5463 * a noisy environment.
5465 * Instead, we should likely temporarily shorten the longCal
5466 * period to happen pretty quickly and if a subsequent one
5467 * fails, do a full reset.
5470 sc->sc_lastshortcal = ticks;
5475 * Use a shorter interval to potentially collect multiple
5476 * data samples required to complete calibration. Once
5477 * we're told the work is done we drop back to a longer
5478 * interval between requests. We're more aggressive doing
5479 * work when operating as an AP to improve operation right
5482 sc->sc_lastshortcal = ticks;
5483 nextcal = ath_shortcalinterval*hz/1000;
5484 if (sc->sc_opmode != HAL_M_HOSTAP)
5486 sc->sc_doresetcal = AH_TRUE;
5488 /* nextcal should be the shortest time for next event */
5489 nextcal = ath_longcalinterval*hz;
5490 if (sc->sc_lastcalreset == 0)
5491 sc->sc_lastcalreset = sc->sc_lastlongcal;
5492 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz)
5493 sc->sc_resetcal = 1; /* setup reset next trip */
5494 sc->sc_doresetcal = AH_FALSE;
5496 /* ANI calibration may occur more often than short/long/resetcal */
5497 if (ath_anicalinterval > 0)
5498 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000);
5501 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n",
5502 __func__, nextcal, isCalDone ? "" : "!");
5503 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc);
5505 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n",
5507 /* NB: don't rearm timer */
5510 * Restore power state now that we're done.
5512 ath_power_restore_power_state(sc);
5516 ath_scan_start(struct ieee80211com *ic)
5518 struct ath_softc *sc = ic->ic_softc;
5519 struct ath_hal *ah = sc->sc_ah;
5522 /* XXX calibration timer? */
5523 /* XXXGL: is constant ieee80211broadcastaddr a correct choice? */
5526 sc->sc_scanning = 1;
5527 sc->sc_syncbeacon = 0;
5528 rfilt = ath_calcrxfilter(sc);
5532 ath_hal_setrxfilter(ah, rfilt);
5533 ath_hal_setassocid(ah, ieee80211broadcastaddr, 0);
5536 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n",
5537 __func__, rfilt, ether_sprintf(ieee80211broadcastaddr));
5541 ath_scan_end(struct ieee80211com *ic)
5543 struct ath_softc *sc = ic->ic_softc;
5544 struct ath_hal *ah = sc->sc_ah;
5548 sc->sc_scanning = 0;
5549 rfilt = ath_calcrxfilter(sc);
5553 ath_hal_setrxfilter(ah, rfilt);
5554 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5556 ath_hal_process_noisefloor(ah);
5559 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5560 __func__, rfilt, ether_sprintf(sc->sc_curbssid),
5564 #ifdef ATH_ENABLE_11N
5566 * For now, just do a channel change.
5568 * Later, we'll go through the hard slog of suspending tx/rx, changing rate
5569 * control state and resetting the hardware without dropping frames out
5572 * The unfortunate trouble here is making absolutely sure that the
5573 * channel width change has propagated enough so the hardware
5574 * absolutely isn't handed bogus frames for it's current operating
5575 * mode. (Eg, 40MHz frames in 20MHz mode.) Since TX and RX can and
5576 * does occur in parallel, we need to make certain we've blocked
5577 * any further ongoing TX (and RX, that can cause raw TX)
5578 * before we do this.
5581 ath_update_chw(struct ieee80211com *ic)
5583 struct ath_softc *sc = ic->ic_softc;
5585 //DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__);
5586 device_printf(sc->sc_dev, "%s: called\n", __func__);
5589 * XXX TODO: schedule a tasklet that stops things without freeing,
5590 * walks the now stopped TX queue(s) looking for frames to retry
5591 * as if we TX filtered them (whch may mean dropping non-ampdu frames!)
5592 * but okay) then place them back on the software queue so they
5593 * can have the rate control lookup done again.
5595 ath_set_channel(ic);
5597 #endif /* ATH_ENABLE_11N */
5600 * This is called by the beacon parsing routine in the receive
5601 * path to update the current quiet time information provided by
5604 * This is STA specific, it doesn't take the AP TBTT/beacon slot
5605 * offset into account.
5607 * The quiet IE doesn't control the /now/ beacon interval - it
5608 * controls the upcoming beacon interval. So, when tbtt=1,
5609 * the quiet element programming shall be for the next beacon
5610 * interval. There's no tbtt=0 behaviour defined, so don't.
5612 * Since we're programming the next quiet interval, we have
5613 * to keep in mind what we will see when the next beacon
5614 * is received with potentially a quiet IE. For example, if
5615 * quiet_period is 1, then we are always getting a quiet interval
5616 * each TBTT - so if we just program it in upon each beacon received,
5617 * it will constantly reflect the "next" TBTT and we will never
5618 * let the counter stay programmed correctly.
5621 * + the first time we see the quiet IE, program it and store
5622 * the details somewhere;
5623 * + if the quiet parameters don't change (ie, period/duration/offset)
5624 * then just leave the programming enabled;
5625 * + (we can "skip" beacons, so don't try to enforce tbttcount unless
5626 * you're willing to also do the skipped beacon math);
5627 * + if the quiet IE is removed, then halt quiet time.
5630 ath_set_quiet_ie(struct ieee80211_node *ni, uint8_t *ie)
5632 struct ieee80211_quiet_ie *q;
5633 struct ieee80211vap *vap = ni->ni_vap;
5634 struct ath_vap *avp = ATH_VAP(vap);
5635 struct ieee80211com *ic = vap->iv_ic;
5636 struct ath_softc *sc = ic->ic_softc;
5638 if (vap->iv_opmode != IEEE80211_M_STA)
5641 /* Verify we have a quiet time IE */
5643 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5644 "%s: called; NULL IE, disabling\n", __func__);
5646 ath_hal_set_quiet(sc->sc_ah, 0, 0, 0, HAL_QUIET_DISABLE);
5647 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie));
5651 /* If we do, verify it's actually legit */
5652 if (ie[0] != IEEE80211_ELEMID_QUIET)
5657 /* Note: this belongs in net80211, parsed out and everything */
5661 * Compare what we have stored to what we last saw.
5662 * If they're the same then don't program in anything.
5664 if ((q->period == avp->quiet_ie.period) &&
5665 (le16dec(&q->duration) == le16dec(&avp->quiet_ie.duration)) &&
5666 (le16dec(&q->offset) == le16dec(&avp->quiet_ie.offset)))
5669 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5670 "%s: called; tbttcount=%d, period=%d, duration=%d, offset=%d\n",
5674 (int) le16dec(&q->duration),
5675 (int) le16dec(&q->offset));
5678 * Don't program in garbage values.
5680 if ((le16dec(&q->duration) == 0) ||
5681 (le16dec(&q->duration) >= ni->ni_intval)) {
5682 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5683 "%s: invalid duration (%d)\n", __func__,
5684 le16dec(&q->duration));
5688 * Can have a 0 offset, but not a duration - so just check
5689 * they don't exceed the intval.
5691 if (le16dec(&q->duration) + le16dec(&q->offset) >= ni->ni_intval) {
5692 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5693 "%s: invalid duration + offset (%d+%d)\n", __func__,
5694 le16dec(&q->duration),
5695 le16dec(&q->offset));
5698 if (q->tbttcount == 0) {
5699 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5700 "%s: invalid tbttcount (0)\n", __func__);
5703 if (q->period == 0) {
5704 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5705 "%s: invalid period (0)\n", __func__);
5710 * This is a new quiet time IE config, so wait until tbttcount
5711 * is equal to 1, and program it in.
5713 if (q->tbttcount == 1) {
5714 DPRINTF(sc, ATH_DEBUG_QUIETIE,
5715 "%s: programming\n", __func__);
5716 ath_hal_set_quiet(sc->sc_ah,
5717 q->period * ni->ni_intval, /* convert to TU */
5718 le16dec(&q->duration), /* already in TU */
5719 le16dec(&q->offset) + ni->ni_intval,
5720 HAL_QUIET_ENABLE | HAL_QUIET_ADD_CURRENT_TSF);
5722 * Note: no HAL_QUIET_ADD_SWBA_RESP_TIME; as this is for
5726 /* Update local state */
5727 memcpy(&avp->quiet_ie, ie, sizeof(struct ieee80211_quiet_ie));
5734 ath_set_channel(struct ieee80211com *ic)
5736 struct ath_softc *sc = ic->ic_softc;
5739 ath_power_set_power_state(sc, HAL_PM_AWAKE);
5742 (void) ath_chan_set(sc, ic->ic_curchan);
5744 * If we are returning to our bss channel then mark state
5745 * so the next recv'd beacon's tsf will be used to sync the
5746 * beacon timers. Note that since we only hear beacons in
5747 * sta/ibss mode this has no effect in other operating modes.
5750 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan)
5751 sc->sc_syncbeacon = 1;
5752 ath_power_restore_power_state(sc);
5757 * Walk the vap list and check if there any vap's in RUN state.
5760 ath_isanyrunningvaps(struct ieee80211vap *this)
5762 struct ieee80211com *ic = this->iv_ic;
5763 struct ieee80211vap *vap;
5765 IEEE80211_LOCK_ASSERT(ic);
5767 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
5768 if (vap != this && vap->iv_state >= IEEE80211_S_RUN)
5775 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
5777 struct ieee80211com *ic = vap->iv_ic;
5778 struct ath_softc *sc = ic->ic_softc;
5779 struct ath_vap *avp = ATH_VAP(vap);
5780 struct ath_hal *ah = sc->sc_ah;
5781 struct ieee80211_node *ni = NULL;
5782 int i, error, stamode;
5784 int csa_run_transition = 0;
5785 enum ieee80211_state ostate = vap->iv_state;
5787 static const HAL_LED_STATE leds[] = {
5788 HAL_LED_INIT, /* IEEE80211_S_INIT */
5789 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
5790 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
5791 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
5792 HAL_LED_RUN, /* IEEE80211_S_CAC */
5793 HAL_LED_RUN, /* IEEE80211_S_RUN */
5794 HAL_LED_RUN, /* IEEE80211_S_CSA */
5795 HAL_LED_RUN, /* IEEE80211_S_SLEEP */
5798 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
5799 ieee80211_state_name[ostate],
5800 ieee80211_state_name[nstate]);
5803 * net80211 _should_ have the comlock asserted at this point.
5804 * There are some comments around the calls to vap->iv_newstate
5805 * which indicate that it (newstate) may end up dropping the
5806 * lock. This and the subsequent lock assert check after newstate
5807 * are an attempt to catch these and figure out how/why.
5809 IEEE80211_LOCK_ASSERT(ic);
5811 /* Before we touch the hardware - wake it up */
5814 * If the NIC is in anything other than SLEEP state,
5815 * we need to ensure that self-generated frames are
5816 * set for PWRMGT=0. Otherwise we may end up with
5817 * strange situations.
5819 * XXX TODO: is this actually the case? :-)
5821 if (nstate != IEEE80211_S_SLEEP)
5822 ath_power_setselfgen(sc, HAL_PM_AWAKE);
5825 * Now, wake the thing up.
5827 ath_power_set_power_state(sc, HAL_PM_AWAKE);
5830 * And stop the calibration callout whilst we have
5833 callout_stop(&sc->sc_cal_ch);
5836 if (ostate == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN)
5837 csa_run_transition = 1;
5839 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
5841 if (nstate == IEEE80211_S_SCAN) {
5843 * Scanning: turn off beacon miss and don't beacon.
5844 * Mark beacon state so when we reach RUN state we'll
5845 * [re]setup beacons. Unblock the task q thread so
5846 * deferred interrupt processing is done.
5849 /* Ensure we stay awake during scan */
5851 ath_power_setselfgen(sc, HAL_PM_AWAKE);
5852 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
5856 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
5857 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5859 taskqueue_unblock(sc->sc_tq);
5862 ni = ieee80211_ref_node(vap->iv_bss);
5863 rfilt = ath_calcrxfilter(sc);
5864 stamode = (vap->iv_opmode == IEEE80211_M_STA ||
5865 vap->iv_opmode == IEEE80211_M_AHDEMO ||
5866 vap->iv_opmode == IEEE80211_M_IBSS);
5869 * XXX Dont need to do this (and others) if we've transitioned
5872 if (stamode && nstate == IEEE80211_S_RUN) {
5873 sc->sc_curaid = ni->ni_associd;
5874 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid);
5875 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5877 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5878 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid);
5879 ath_hal_setrxfilter(ah, rfilt);
5881 /* XXX is this to restore keycache on resume? */
5882 if (vap->iv_opmode != IEEE80211_M_STA &&
5883 (vap->iv_flags & IEEE80211_F_PRIVACY)) {
5884 for (i = 0; i < IEEE80211_WEP_NKID; i++)
5885 if (ath_hal_keyisvalid(ah, i))
5886 ath_hal_keysetmac(ah, i, ni->ni_bssid);
5890 * Invoke the parent method to do net80211 work.
5892 error = avp->av_newstate(vap, nstate, arg);
5897 * See above: ensure av_newstate() doesn't drop the lock
5900 IEEE80211_LOCK_ASSERT(ic);
5903 * XXX TODO: if nstate is _S_CAC, then we should disable
5904 * ACK processing until CAC is completed.
5908 * XXX TODO: if we're on a passive channel, then we should
5909 * not allow any ACKs or self-generated frames until we hear
5910 * a beacon. Unfortunately there isn't a notification from
5911 * net80211 so perhaps we could slot that particular check
5912 * into the mgmt receive path and just ensure that we clear
5913 * it on RX of beacons in passive mode (and only clear it
5918 * XXX TODO: net80211 should be tracking whether channels
5919 * have heard beacons and are thus considered "OK" for
5920 * transmitting - and then inform the driver about this
5921 * state change. That way if we hear an AP go quiet
5922 * (and nothing else is beaconing on a channel) the
5923 * channel can go back to being passive until another
5928 * XXX TODO: if nstate is _S_CAC, then we should disable
5929 * ACK processing until CAC is completed.
5933 * XXX TODO: if we're on a passive channel, then we should
5934 * not allow any ACKs or self-generated frames until we hear
5935 * a beacon. Unfortunately there isn't a notification from
5936 * net80211 so perhaps we could slot that particular check
5937 * into the mgmt receive path and just ensure that we clear
5938 * it on RX of beacons in passive mode (and only clear it
5943 * XXX TODO: net80211 should be tracking whether channels
5944 * have heard beacons and are thus considered "OK" for
5945 * transmitting - and then inform the driver about this
5946 * state change. That way if we hear an AP go quiet
5947 * (and nothing else is beaconing on a channel) the
5948 * channel can go back to being passive until another
5952 if (nstate == IEEE80211_S_RUN) {
5953 /* NB: collect bss node again, it may have changed */
5954 ieee80211_free_node(ni);
5955 ni = ieee80211_ref_node(vap->iv_bss);
5957 DPRINTF(sc, ATH_DEBUG_STATE,
5958 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s "
5959 "capinfo 0x%04x chan %d\n", __func__,
5960 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid),
5961 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan));
5963 switch (vap->iv_opmode) {
5964 #ifdef IEEE80211_SUPPORT_TDMA
5965 case IEEE80211_M_AHDEMO:
5966 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0)
5970 case IEEE80211_M_HOSTAP:
5971 case IEEE80211_M_IBSS:
5972 case IEEE80211_M_MBSS:
5975 * TODO: Enable ACK processing (ie, clear AR_DIAG_ACK_DIS.)
5976 * For channels that are in CAC, we may have disabled
5977 * this during CAC to ensure we don't ACK frames
5982 * Allocate and setup the beacon frame.
5984 * Stop any previous beacon DMA. This may be
5985 * necessary, for example, when an ibss merge
5986 * causes reconfiguration; there will be a state
5987 * transition from RUN->RUN that means we may
5988 * be called with beacon transmission active.
5990 ath_hal_stoptxdma(ah, sc->sc_bhalq);
5992 error = ath_beacon_alloc(sc, ni);
5996 * If joining an adhoc network defer beacon timer
5997 * configuration to the next beacon frame so we
5998 * have a current TSF to use. Otherwise we're
5999 * starting an ibss/bss so there's no need to delay;
6000 * if this is the first vap moving to RUN state, then
6001 * beacon state needs to be [re]configured.
6003 if (vap->iv_opmode == IEEE80211_M_IBSS &&
6004 ni->ni_tstamp.tsf != 0) {
6005 sc->sc_syncbeacon = 1;
6006 } else if (!sc->sc_beacons) {
6007 #ifdef IEEE80211_SUPPORT_TDMA
6008 if (vap->iv_caps & IEEE80211_C_TDMA)
6009 ath_tdma_config(sc, vap);
6012 ath_beacon_config(sc, vap);
6016 case IEEE80211_M_STA:
6018 * Defer beacon timer configuration to the next
6019 * beacon frame so we have a current TSF to use
6020 * (any TSF collected when scanning is likely old).
6021 * However if it's due to a CSA -> RUN transition,
6022 * force a beacon update so we pick up a lack of
6023 * beacons from an AP in CAC and thus force a
6026 * And, there's also corner cases here where
6027 * after a scan, the AP may have disappeared.
6028 * In that case, we may not receive an actual
6029 * beacon to update the beacon timer and thus we
6030 * won't get notified of the missing beacons.
6032 if (ostate != IEEE80211_S_RUN &&
6033 ostate != IEEE80211_S_SLEEP) {
6034 DPRINTF(sc, ATH_DEBUG_BEACON,
6035 "%s: STA; syncbeacon=1\n", __func__);
6036 sc->sc_syncbeacon = 1;
6038 /* Quiet time handling - ensure we resync */
6039 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie));
6041 if (csa_run_transition)
6042 ath_beacon_config(sc, vap);
6047 * Reconfigure beacons during reset; as otherwise
6048 * we won't get the beacon timers reprogrammed
6049 * after a reset and thus we won't pick up a
6050 * beacon miss interrupt.
6052 * Hopefully we'll see a beacon before the BMISS
6053 * timer fires (too often), leading to a STA
6059 case IEEE80211_M_MONITOR:
6061 * Monitor mode vaps have only INIT->RUN and RUN->RUN
6062 * transitions so we must re-enable interrupts here to
6063 * handle the case of a single monitor mode vap.
6065 ath_hal_intrset(ah, sc->sc_imask);
6067 case IEEE80211_M_WDS:
6073 * Let the hal process statistics collected during a
6074 * scan so it can provide calibrated noise floor data.
6076 ath_hal_process_noisefloor(ah);
6078 * Reset rssi stats; maybe not the best place...
6080 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
6081 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
6082 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
6085 * Force awake for RUN mode.
6088 ath_power_setselfgen(sc, HAL_PM_AWAKE);
6089 ath_power_setpower(sc, HAL_PM_AWAKE, 1);
6092 * Finally, start any timers and the task q thread
6093 * (in case we didn't go through SCAN state).
6095 if (ath_longcalinterval != 0) {
6096 /* start periodic recalibration timer */
6097 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
6099 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
6100 "%s: calibration disabled\n", __func__);
6104 taskqueue_unblock(sc->sc_tq);
6105 } else if (nstate == IEEE80211_S_INIT) {
6107 /* Quiet time handling - ensure we resync */
6108 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie));
6111 * If there are no vaps left in RUN state then
6112 * shutdown host/driver operation:
6113 * o disable interrupts
6114 * o disable the task queue thread
6115 * o mark beacon processing as stopped
6117 if (!ath_isanyrunningvaps(vap)) {
6118 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
6119 /* disable interrupts */
6120 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
6121 taskqueue_block(sc->sc_tq);
6126 * For at least STA mode we likely should clear the ANI
6127 * and NF calibration state and allow the NIC/HAL to figure
6128 * out optimal parameters at runtime. Otherwise if we
6129 * disassociate due to interference / deafness it may persist
6130 * when we reconnect.
6132 * Note: may need to do this for other states too, not just
6135 #ifdef IEEE80211_SUPPORT_TDMA
6136 ath_hal_setcca(ah, AH_TRUE);
6138 } else if (nstate == IEEE80211_S_SLEEP) {
6139 /* We're going to sleep, so transition appropriately */
6140 /* For now, only do this if we're a single STA vap */
6141 if (sc->sc_nvaps == 1 &&
6142 vap->iv_opmode == IEEE80211_M_STA) {
6143 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: syncbeacon=%d\n", __func__, sc->sc_syncbeacon);
6146 * Always at least set the self-generated
6147 * frame config to set PWRMGT=1.
6149 ath_power_setselfgen(sc, HAL_PM_NETWORK_SLEEP);
6152 * If we're not syncing beacons, transition
6155 * We stay awake if syncbeacon > 0 in case
6156 * we need to listen for some beacons otherwise
6157 * our beacon timer config may be wrong.
6159 if (sc->sc_syncbeacon == 0) {
6160 ath_power_setpower(sc, HAL_PM_NETWORK_SLEEP, 1);
6166 * Note - the ANI/calibration timer isn't re-enabled during
6167 * network sleep for now. One unfortunate side-effect is that
6168 * the PHY/airtime statistics aren't gathered on the channel
6169 * but I haven't yet tested to see if reading those registers
6170 * CAN occur during network sleep.
6172 * This should be revisited in a future commit, even if it's
6173 * just to split out the airtime polling from ANI/calibration.
6175 } else if (nstate == IEEE80211_S_SCAN) {
6176 /* Quiet time handling - ensure we resync */
6177 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie));
6180 * If we're in scan mode then startpcureceive() is
6181 * hopefully being called with "reset ANI" for this channel;
6182 * but once we attempt to reassociate we program in the previous
6183 * ANI values and.. not do any calibration until we're running.
6184 * This may mean we stay deaf unless we can associate successfully.
6186 * So do kick off the cal timer to get NF/ANI going.
6189 if (ath_longcalinterval != 0) {
6190 /* start periodic recalibration timer */
6191 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
6193 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
6194 "%s: calibration disabled\n", __func__);
6199 ieee80211_free_node(ni);
6202 * Restore the power state - either to what it was, or
6203 * to network_sleep if it's alright.
6206 ath_power_restore_power_state(sc);
6212 * Allocate a key cache slot to the station so we can
6213 * setup a mapping from key index to node. The key cache
6214 * slot is needed for managing antenna state and for
6215 * compression when stations do not use crypto. We do
6216 * it uniliaterally here; if crypto is employed this slot
6217 * will be reassigned.
6220 ath_setup_stationkey(struct ieee80211_node *ni)
6222 struct ieee80211vap *vap = ni->ni_vap;
6223 struct ath_softc *sc = vap->iv_ic->ic_softc;
6224 ieee80211_keyix keyix, rxkeyix;
6226 /* XXX should take a locked ref to vap->iv_bss */
6227 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
6229 * Key cache is full; we'll fall back to doing
6230 * the more expensive lookup in software. Note
6231 * this also means no h/w compression.
6233 /* XXX msg+statistic */
6236 ni->ni_ucastkey.wk_keyix = keyix;
6237 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
6238 /* NB: must mark device key to get called back on delete */
6239 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY;
6240 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr);
6241 /* NB: this will create a pass-thru key entry */
6242 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss);
6247 * Setup driver-specific state for a newly associated node.
6248 * Note that we're called also on a re-associate, the isnew
6249 * param tells us if this is the first time or not.
6252 ath_newassoc(struct ieee80211_node *ni, int isnew)
6254 struct ath_node *an = ATH_NODE(ni);
6255 struct ieee80211vap *vap = ni->ni_vap;
6256 struct ath_softc *sc = vap->iv_ic->ic_softc;
6257 const struct ieee80211_txparam *tp = ni->ni_txparms;
6259 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate);
6260 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate);
6262 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: reassoc; isnew=%d, is_powersave=%d\n",
6267 an->an_is_powersave);
6270 ath_rate_newassoc(sc, an, isnew);
6271 ATH_NODE_UNLOCK(an);
6274 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey &&
6275 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
6276 ath_setup_stationkey(ni);
6279 * If we're reassociating, make sure that any paused queues
6282 * Now, we may have frames in the hardware queue for this node.
6283 * So if we are reassociating and there are frames in the queue,
6284 * we need to go through the cleanup path to ensure that they're
6285 * marked as non-aggregate.
6288 DPRINTF(sc, ATH_DEBUG_NODE,
6289 "%s: %6D: reassoc; is_powersave=%d\n",
6293 an->an_is_powersave);
6295 /* XXX for now, we can't hold the lock across assoc */
6296 ath_tx_node_reassoc(sc, an);
6298 /* XXX for now, we can't hold the lock across wakeup */
6299 if (an->an_is_powersave)
6300 ath_tx_node_wakeup(sc, an);
6305 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg,
6306 int nchans, struct ieee80211_channel chans[])
6308 struct ath_softc *sc = ic->ic_softc;
6309 struct ath_hal *ah = sc->sc_ah;
6312 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
6313 "%s: rd %u cc %u location %c%s\n",
6314 __func__, reg->regdomain, reg->country, reg->location,
6315 reg->ecm ? " ecm" : "");
6317 status = ath_hal_set_channels(ah, chans, nchans,
6318 reg->country, reg->regdomain);
6319 if (status != HAL_OK) {
6320 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n",
6322 return EINVAL; /* XXX */
6329 ath_getradiocaps(struct ieee80211com *ic,
6330 int maxchans, int *nchans, struct ieee80211_channel chans[])
6332 struct ath_softc *sc = ic->ic_softc;
6333 struct ath_hal *ah = sc->sc_ah;
6335 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n",
6336 __func__, SKU_DEBUG, CTRY_DEFAULT);
6338 /* XXX check return */
6339 (void) ath_hal_getchannels(ah, chans, maxchans, nchans,
6340 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE);
6345 ath_getchannels(struct ath_softc *sc)
6347 struct ieee80211com *ic = &sc->sc_ic;
6348 struct ath_hal *ah = sc->sc_ah;
6352 * Collect channel set based on EEPROM contents.
6354 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX,
6355 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE);
6356 if (status != HAL_OK) {
6357 device_printf(sc->sc_dev,
6358 "%s: unable to collect channel list from hal, status %d\n",
6362 (void) ath_hal_getregdomain(ah, &sc->sc_eerd);
6363 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */
6364 /* XXX map Atheros sku's to net80211 SKU's */
6365 /* XXX net80211 types too small */
6366 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd;
6367 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc;
6368 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */
6369 ic->ic_regdomain.isocc[1] = ' ';
6371 ic->ic_regdomain.ecm = 1;
6372 ic->ic_regdomain.location = 'I';
6374 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
6375 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n",
6376 __func__, sc->sc_eerd, sc->sc_eecc,
6377 ic->ic_regdomain.regdomain, ic->ic_regdomain.country,
6378 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : "");
6383 ath_rate_setup(struct ath_softc *sc, u_int mode)
6385 struct ath_hal *ah = sc->sc_ah;
6386 const HAL_RATE_TABLE *rt;
6389 case IEEE80211_MODE_11A:
6390 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
6392 case IEEE80211_MODE_HALF:
6393 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE);
6395 case IEEE80211_MODE_QUARTER:
6396 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE);
6398 case IEEE80211_MODE_11B:
6399 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
6401 case IEEE80211_MODE_11G:
6402 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
6404 case IEEE80211_MODE_TURBO_A:
6405 rt = ath_hal_getratetable(ah, HAL_MODE_108A);
6407 case IEEE80211_MODE_TURBO_G:
6408 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
6410 case IEEE80211_MODE_STURBO_A:
6411 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
6413 case IEEE80211_MODE_11NA:
6414 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20);
6416 case IEEE80211_MODE_11NG:
6417 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20);
6420 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
6424 sc->sc_rates[mode] = rt;
6425 return (rt != NULL);
6429 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
6431 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
6432 static const struct {
6433 u_int rate; /* tx/rx 802.11 rate */
6434 u_int16_t timeOn; /* LED on time (ms) */
6435 u_int16_t timeOff; /* LED off time (ms) */
6451 /* XXX half/quarter rates */
6453 const HAL_RATE_TABLE *rt;
6456 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
6457 rt = sc->sc_rates[mode];
6458 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
6459 for (i = 0; i < rt->rateCount; i++) {
6460 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
6461 if (rt->info[i].phy != IEEE80211_T_HT)
6462 sc->sc_rixmap[ieeerate] = i;
6464 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i;
6466 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
6467 for (i = 0; i < nitems(sc->sc_hwmap); i++) {
6468 if (i >= rt->rateCount) {
6469 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
6470 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
6473 sc->sc_hwmap[i].ieeerate =
6474 rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
6475 if (rt->info[i].phy == IEEE80211_T_HT)
6476 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS;
6477 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
6478 if (rt->info[i].shortPreamble ||
6479 rt->info[i].phy == IEEE80211_T_OFDM)
6480 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6481 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags;
6482 for (j = 0; j < nitems(blinkrates)-1; j++)
6483 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
6485 /* NB: this uses the last entry if the rate isn't found */
6486 /* XXX beware of overlow */
6487 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
6488 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
6490 sc->sc_currates = rt;
6491 sc->sc_curmode = mode;
6493 * All protection frames are transmitted at 2Mb/s for
6494 * 11g, otherwise at 1Mb/s.
6496 if (mode == IEEE80211_MODE_11G)
6497 sc->sc_protrix = ath_tx_findrix(sc, 2*2);
6499 sc->sc_protrix = ath_tx_findrix(sc, 2*1);
6500 /* NB: caller is responsible for resetting rate control state */
6504 ath_watchdog(void *arg)
6506 struct ath_softc *sc = arg;
6507 struct ieee80211com *ic = &sc->sc_ic;
6510 ATH_LOCK_ASSERT(sc);
6512 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) {
6515 ath_power_set_power_state(sc, HAL_PM_AWAKE);
6517 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) &&
6519 device_printf(sc->sc_dev, "%s hang detected (0x%x)\n",
6520 hangs & 0xff ? "bb" : "mac", hangs);
6522 device_printf(sc->sc_dev, "device timeout\n");
6524 counter_u64_add(ic->ic_oerrors, 1);
6525 sc->sc_stats.ast_watchdog++;
6527 ath_power_restore_power_state(sc);
6531 * We can't hold the lock across the ath_reset() call.
6533 * And since this routine can't hold a lock and sleep,
6534 * do the reset deferred.
6537 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
6540 callout_schedule(&sc->sc_wd_ch, hz);
6544 ath_parent(struct ieee80211com *ic)
6546 struct ath_softc *sc = ic->ic_softc;
6547 int error = EDOOFUS;
6550 if (ic->ic_nrunning > 0) {
6552 * To avoid rescanning another access point,
6553 * do not call ath_init() here. Instead,
6554 * only reflect promisc mode settings.
6556 if (sc->sc_running) {
6557 ath_power_set_power_state(sc, HAL_PM_AWAKE);
6559 ath_power_restore_power_state(sc);
6560 } else if (!sc->sc_invalid) {
6562 * Beware of being called during attach/detach
6563 * to reset promiscuous mode. In that case we
6564 * will still be marked UP but not RUNNING.
6565 * However trying to re-init the interface
6566 * is the wrong thing to do as we've already
6567 * torn down much of our state. There's
6568 * probably a better way to deal with this.
6570 error = ath_init(sc);
6574 if (!sc->sc_invalid)
6575 ath_power_setpower(sc, HAL_PM_FULL_SLEEP, 1);
6580 #ifdef ATH_TX99_DIAG
6581 if (sc->sc_tx99 != NULL)
6582 sc->sc_tx99->start(sc->sc_tx99);
6585 ieee80211_start_all(ic);
6590 * Announce various information on device/driver attach.
6593 ath_announce(struct ath_softc *sc)
6595 struct ath_hal *ah = sc->sc_ah;
6597 device_printf(sc->sc_dev, "%s mac %d.%d RF%s phy %d.%d\n",
6598 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev,
6599 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
6600 device_printf(sc->sc_dev, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n",
6601 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev);
6604 for (i = 0; i <= WME_AC_VO; i++) {
6605 struct ath_txq *txq = sc->sc_ac2q[i];
6606 device_printf(sc->sc_dev,
6607 "Use hw queue %u for %s traffic\n",
6608 txq->axq_qnum, ieee80211_wme_acnames[i]);
6610 device_printf(sc->sc_dev, "Use hw queue %u for CAB traffic\n",
6611 sc->sc_cabq->axq_qnum);
6612 device_printf(sc->sc_dev, "Use hw queue %u for beacons\n",
6615 if (ath_rxbuf != ATH_RXBUF)
6616 device_printf(sc->sc_dev, "using %u rx buffers\n", ath_rxbuf);
6617 if (ath_txbuf != ATH_TXBUF)
6618 device_printf(sc->sc_dev, "using %u tx buffers\n", ath_txbuf);
6619 if (sc->sc_mcastkey && bootverbose)
6620 device_printf(sc->sc_dev, "using multicast key search\n");
6624 ath_dfs_tasklet(void *p, int npending)
6626 struct ath_softc *sc = (struct ath_softc *) p;
6627 struct ieee80211com *ic = &sc->sc_ic;
6630 * If previous processing has found a radar event,
6631 * signal this to the net80211 layer to begin DFS
6634 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) {
6635 /* DFS event found, initiate channel change */
6638 * XXX TODO: immediately disable ACK processing
6639 * on the current channel. This would be done
6640 * by setting AR_DIAG_ACK_DIS (AR5212; may be
6641 * different for others) until we are out of
6646 * XXX doesn't currently tell us whether the event
6647 * XXX was found in the primary or extension
6651 ieee80211_dfs_notify_radar(ic, sc->sc_curchan);
6652 IEEE80211_UNLOCK(ic);
6657 * Enable/disable power save. This must be called with
6658 * no TX driver locks currently held, so it should only
6659 * be called from the RX path (which doesn't hold any
6663 ath_node_powersave(struct ieee80211_node *ni, int enable)
6666 struct ath_node *an = ATH_NODE(ni);
6667 struct ieee80211com *ic = ni->ni_ic;
6668 struct ath_softc *sc = ic->ic_softc;
6669 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6671 /* XXX and no TXQ locks should be held here */
6673 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, "%s: %6D: enable=%d\n",
6679 /* Suspend or resume software queue handling */
6681 ath_tx_node_sleep(sc, an);
6683 ath_tx_node_wakeup(sc, an);
6685 /* Update net80211 state */
6686 avp->av_node_ps(ni, enable);
6688 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6690 /* Update net80211 state */
6691 avp->av_node_ps(ni, enable);
6692 #endif/* ATH_SW_PSQ */
6696 * Notification from net80211 that the powersave queue state has
6699 * Since the software queue also may have some frames:
6701 * + if the node software queue has frames and the TID state
6702 * is 0, we set the TIM;
6703 * + if the node and the stack are both empty, we clear the TIM bit.
6704 * + If the stack tries to set the bit, always set it.
6705 * + If the stack tries to clear the bit, only clear it if the
6706 * software queue in question is also cleared.
6708 * TODO: this is called during node teardown; so let's ensure this
6709 * is all correctly handled and that the TIM bit is cleared.
6710 * It may be that the node flush is called _AFTER_ the net80211
6711 * stack clears the TIM.
6713 * Here is the racy part. Since it's possible >1 concurrent,
6714 * overlapping TXes will appear complete with a TX completion in
6715 * another thread, it's possible that the concurrent TIM calls will
6716 * clash. We can't hold the node lock here because setting the
6717 * TIM grabs the net80211 comlock and this may cause a LOR.
6718 * The solution is either to totally serialise _everything_ at
6719 * this point (ie, all TX, completion and any reset/flush go into
6720 * one taskqueue) or a new "ath TIM lock" needs to be created that
6721 * just wraps the driver state change and this call to avp->av_set_tim().
6723 * The same race exists in the net80211 power save queue handling
6724 * as well. Since multiple transmitting threads may queue frames
6725 * into the driver, as well as ps-poll and the driver transmitting
6726 * frames (and thus clearing the psq), it's quite possible that
6727 * a packet entering the PSQ and a ps-poll being handled will
6728 * race, causing the TIM to be cleared and not re-set.
6731 ath_node_set_tim(struct ieee80211_node *ni, int enable)
6734 struct ieee80211com *ic = ni->ni_ic;
6735 struct ath_softc *sc = ic->ic_softc;
6736 struct ath_node *an = ATH_NODE(ni);
6737 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6741 an->an_stack_psq = enable;
6744 * This will get called for all operating modes,
6745 * even if avp->av_set_tim is unset.
6746 * It's currently set for hostap/ibss modes; but
6747 * the same infrastructure is used for both STA
6748 * and AP/IBSS node power save.
6750 if (avp->av_set_tim == NULL) {
6756 * If setting the bit, always set it here.
6757 * If clearing the bit, only clear it if the
6758 * software queue is also empty.
6760 * If the node has left power save, just clear the TIM
6761 * bit regardless of the state of the power save queue.
6763 * XXX TODO: although atomics are used, it's quite possible
6764 * that a race will occur between this and setting/clearing
6765 * in another thread. TX completion will occur always in
6766 * one thread, however setting/clearing the TIM bit can come
6767 * from a variety of different process contexts!
6769 if (enable && an->an_tim_set == 1) {
6770 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6771 "%s: %6D: enable=%d, tim_set=1, ignoring\n",
6777 } else if (enable) {
6778 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6779 "%s: %6D: enable=%d, enabling TIM\n",
6786 changed = avp->av_set_tim(ni, enable);
6787 } else if (an->an_swq_depth == 0) {
6789 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6790 "%s: %6D: enable=%d, an_swq_depth == 0, disabling\n",
6797 changed = avp->av_set_tim(ni, enable);
6798 } else if (! an->an_is_powersave) {
6800 * disable regardless; the node isn't in powersave now
6802 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6803 "%s: %6D: enable=%d, an_pwrsave=0, disabling\n",
6810 changed = avp->av_set_tim(ni, enable);
6813 * psq disable, node is currently in powersave, node
6814 * software queue isn't empty, so don't clear the TIM bit
6818 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6819 "%s: %6D: enable=%d, an_swq_depth > 0, ignoring\n",
6829 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6832 * Some operating modes don't set av_set_tim(), so don't
6835 if (avp->av_set_tim == NULL)
6838 return (avp->av_set_tim(ni, enable));
6839 #endif /* ATH_SW_PSQ */
6843 * Set or update the TIM from the software queue.
6845 * Check the software queue depth before attempting to do lock
6846 * anything; that avoids trying to obtain the lock. Then,
6847 * re-check afterwards to ensure nothing has changed in the
6850 * set: This is designed to be called from the TX path, after
6851 * a frame has been queued; to see if the swq > 0.
6853 * clear: This is designed to be called from the buffer completion point
6854 * (right now it's ath_tx_default_comp()) where the state of
6855 * a software queue has changed.
6857 * It makes sense to place it at buffer free / completion rather
6858 * than after each software queue operation, as there's no real
6859 * point in churning the TIM bit as the last frames in the software
6860 * queue are transmitted. If they fail and we retry them, we'd
6861 * just be setting the TIM bit again anyway.
6864 ath_tx_update_tim(struct ath_softc *sc, struct ieee80211_node *ni,
6868 struct ath_node *an;
6869 struct ath_vap *avp;
6871 /* Don't do this for broadcast/etc frames */
6876 avp = ATH_VAP(ni->ni_vap);
6879 * And for operating modes without the TIM handler set, let's
6882 if (avp->av_set_tim == NULL)
6885 ATH_TX_LOCK_ASSERT(sc);
6888 if (an->an_is_powersave &&
6889 an->an_tim_set == 0 &&
6890 an->an_swq_depth != 0) {
6891 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6892 "%s: %6D: swq_depth>0, tim_set=0, set!\n",
6897 (void) avp->av_set_tim(ni, 1);
6901 * Don't bother grabbing the lock unless the queue is empty.
6903 if (an->an_swq_depth != 0)
6906 if (an->an_is_powersave &&
6907 an->an_stack_psq == 0 &&
6908 an->an_tim_set == 1 &&
6909 an->an_swq_depth == 0) {
6910 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6911 "%s: %6D: swq_depth=0, tim_set=1, psq_set=0,"
6917 (void) avp->av_set_tim(ni, 0);
6922 #endif /* ATH_SW_PSQ */
6926 * Received a ps-poll frame from net80211.
6928 * Here we get a chance to serve out a software-queued frame ourselves
6929 * before we punt it to net80211 to transmit us one itself - either
6930 * because there's traffic in the net80211 psq, or a NULL frame to
6931 * indicate there's nothing else.
6934 ath_node_recv_pspoll(struct ieee80211_node *ni, struct mbuf *m)
6937 struct ath_node *an;
6938 struct ath_vap *avp;
6939 struct ieee80211com *ic = ni->ni_ic;
6940 struct ath_softc *sc = ic->ic_softc;
6948 * Unassociated (temporary node) station.
6950 if (ni->ni_associd == 0)
6954 * We do have an active node, so let's begin looking into it.
6957 avp = ATH_VAP(ni->ni_vap);
6960 * For now, we just call the original ps-poll method.
6961 * Once we're ready to flip this on:
6963 * + Set leak to 1, as no matter what we're going to have
6965 * + Check the software queue and if there's something in it,
6966 * schedule the highest TID thas has traffic from this node.
6967 * Then make sure we schedule the software scheduler to
6968 * run so it picks up said frame.
6970 * That way whatever happens, we'll at least send _a_ frame
6971 * to the given node.
6973 * Again, yes, it's crappy QoS if the node has multiple
6974 * TIDs worth of traffic - but let's get it working first
6975 * before we optimise it.
6977 * Also yes, there's definitely latency here - we're not
6978 * direct dispatching to the hardware in this path (and
6979 * we're likely being called from the packet receive path,
6980 * so going back into TX may be a little hairy!) but again
6981 * I'd like to get this working first before optimising
6988 * Legacy - we're called and the node isn't asleep.
6991 if (! an->an_is_powersave) {
6992 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6993 "%s: %6D: not in powersave?\n",
6998 avp->av_recv_pspoll(ni, m);
7003 * We're in powersave.
7007 an->an_leak_count = 1;
7010 * Now, if there's no frames in the node, just punt to
7013 * Don't bother checking if the TIM bit is set, we really
7014 * only care if there are any frames here!
7016 if (an->an_swq_depth == 0) {
7018 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7019 "%s: %6D: SWQ empty; punting to net80211\n",
7023 avp->av_recv_pspoll(ni, m);
7028 * Ok, let's schedule the highest TID that has traffic
7029 * and then schedule something.
7031 for (tid = IEEE80211_TID_SIZE - 1; tid >= 0; tid--) {
7032 struct ath_tid *atid = &an->an_tid[tid];
7036 if (atid->axq_depth == 0)
7038 ath_tx_tid_sched(sc, atid);
7040 * XXX we could do a direct call to the TXQ
7041 * scheduler code here to optimise latency
7042 * at the expense of a REALLY deep callstack.
7045 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask);
7046 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7047 "%s: %6D: leaking frame to TID %d\n",
7058 * XXX nothing in the TIDs at this point? Eek.
7060 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7061 "%s: %6D: TIDs empty, but ath_node showed traffic?!\n",
7065 avp->av_recv_pspoll(ni, m);
7067 avp->av_recv_pspoll(ni, m);
7068 #endif /* ATH_SW_PSQ */
7071 MODULE_VERSION(ath_main, 1);
7072 MODULE_DEPEND(ath_main, wlan, 1, 1, 1); /* 802.11 media layer */
7073 MODULE_DEPEND(ath_main, ath_rate, 1, 1, 1);
7074 MODULE_DEPEND(ath_main, ath_dfs, 1, 1, 1);
7075 MODULE_DEPEND(ath_main, ath_hal, 1, 1, 1);
7076 #if defined(IEEE80211_ALQ) || defined(AH_DEBUG_ALQ) || defined(ATH_DEBUG_ALQ)
7077 MODULE_DEPEND(ath_main, alq, 1, 1, 1);