2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
41 * Driver for the Atheros Wireless LAN controller.
43 * This software is derived from work of Atsushi Onoe; his contribution
44 * is greatly appreciated.
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/sysctl.h>
53 #include <sys/malloc.h>
55 #include <sys/mutex.h>
56 #include <sys/kernel.h>
57 #include <sys/socket.h>
58 #include <sys/sockio.h>
59 #include <sys/errno.h>
60 #include <sys/callout.h>
62 #include <sys/endian.h>
64 #include <machine/bus.h>
67 #include <net/if_dl.h>
68 #include <net/if_media.h>
69 #include <net/if_types.h>
70 #include <net/if_arp.h>
71 #include <net/ethernet.h>
72 #include <net/if_llc.h>
74 #include <net80211/ieee80211_var.h>
79 #include <netinet/in.h>
80 #include <netinet/if_ether.h>
84 #include <dev/ath/if_athvar.h>
85 #include <contrib/dev/ath/ah_desc.h>
86 #include <contrib/dev/ath/ah_devid.h> /* XXX for softled */
88 /* unaligned little endian access */
89 #define LE_READ_2(p) \
91 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8)))
92 #define LE_READ_4(p) \
94 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \
95 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24)))
103 static void ath_init(void *);
104 static void ath_stop_locked(struct ifnet *);
105 static void ath_stop(struct ifnet *);
106 static void ath_start(struct ifnet *);
107 static int ath_reset(struct ifnet *);
108 static int ath_media_change(struct ifnet *);
109 static void ath_watchdog(struct ifnet *);
110 static int ath_ioctl(struct ifnet *, u_long, caddr_t);
111 static void ath_fatal_proc(void *, int);
112 static void ath_rxorn_proc(void *, int);
113 static void ath_bmiss_proc(void *, int);
114 static int ath_key_alloc(struct ieee80211com *,
115 const struct ieee80211_key *);
116 static int ath_key_delete(struct ieee80211com *,
117 const struct ieee80211_key *);
118 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *,
119 const u_int8_t mac[IEEE80211_ADDR_LEN]);
120 static void ath_key_update_begin(struct ieee80211com *);
121 static void ath_key_update_end(struct ieee80211com *);
122 static void ath_mode_init(struct ath_softc *);
123 static void ath_setslottime(struct ath_softc *);
124 static void ath_updateslot(struct ifnet *);
125 static int ath_beaconq_setup(struct ath_hal *);
126 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *);
127 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *);
128 static void ath_beacon_proc(void *, int);
129 static void ath_bstuck_proc(void *, int);
130 static void ath_beacon_free(struct ath_softc *);
131 static void ath_beacon_config(struct ath_softc *);
132 static void ath_descdma_cleanup(struct ath_softc *sc,
133 struct ath_descdma *, ath_bufhead *);
134 static int ath_desc_alloc(struct ath_softc *);
135 static void ath_desc_free(struct ath_softc *);
136 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *);
137 static void ath_node_free(struct ieee80211_node *);
138 static u_int8_t ath_node_getrssi(const struct ieee80211_node *);
139 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *);
140 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
141 struct ieee80211_node *ni,
142 int subtype, int rssi, u_int32_t rstamp);
143 static void ath_setdefantenna(struct ath_softc *, u_int);
144 static void ath_rx_proc(void *, int);
145 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
146 static int ath_tx_setup(struct ath_softc *, int, int);
147 static int ath_wme_update(struct ieee80211com *);
148 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
149 static void ath_tx_cleanup(struct ath_softc *);
150 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *,
151 struct ath_buf *, struct mbuf *);
152 static void ath_tx_proc_q0(void *, int);
153 static void ath_tx_proc_q0123(void *, int);
154 static void ath_tx_proc(void *, int);
155 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
156 static void ath_draintxq(struct ath_softc *);
157 static void ath_stoprecv(struct ath_softc *);
158 static int ath_startrecv(struct ath_softc *);
159 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
160 static void ath_next_scan(void *);
161 static void ath_calibrate(void *);
162 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int);
163 static void ath_setup_stationkey(struct ieee80211_node *);
164 static void ath_newassoc(struct ieee80211_node *, int);
165 static int ath_getchannels(struct ath_softc *, u_int cc,
166 HAL_BOOL outdoor, HAL_BOOL xchanmode);
167 static void ath_led_event(struct ath_softc *, int);
168 static void ath_update_txpow(struct ath_softc *);
170 static int ath_rate_setup(struct ath_softc *, u_int mode);
171 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
173 static void ath_sysctlattach(struct ath_softc *);
174 static void ath_bpfattach(struct ath_softc *);
175 static void ath_announce(struct ath_softc *);
177 SYSCTL_DECL(_hw_ath);
179 /* XXX validate sysctl values */
180 static int ath_dwelltime = 200; /* 5 channels/second */
181 SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime,
182 0, "channel dwell time (ms) for AP/station scanning");
183 static int ath_calinterval = 30; /* calibrate every 30 secs */
184 SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval,
185 0, "chip calibration interval (secs)");
186 static int ath_outdoor = AH_TRUE; /* outdoor operation */
187 SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor,
188 0, "outdoor operation");
189 TUNABLE_INT("hw.ath.outdoor", &ath_outdoor);
190 static int ath_xchanmode = AH_TRUE; /* extended channel use */
191 SYSCTL_INT(_hw_ath, OID_AUTO, xchanmode, CTLFLAG_RD, &ath_xchanmode,
192 0, "extended channel mode");
193 TUNABLE_INT("hw.ath.xchanmode", &ath_xchanmode);
194 static int ath_countrycode = CTRY_DEFAULT; /* country code */
195 SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode,
197 TUNABLE_INT("hw.ath.countrycode", &ath_countrycode);
198 static int ath_regdomain = 0; /* regulatory domain */
199 SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain,
200 0, "regulatory domain");
203 static int ath_debug = 0;
204 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug,
205 0, "control debugging printfs");
206 TUNABLE_INT("hw.ath.debug", &ath_debug);
208 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
209 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */
210 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */
211 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */
212 ATH_DEBUG_RATE = 0x00000010, /* rate control */
213 ATH_DEBUG_RESET = 0x00000020, /* reset processing */
214 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */
215 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */
216 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */
217 ATH_DEBUG_INTR = 0x00001000, /* ISR */
218 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */
219 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */
220 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */
221 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */
222 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */
223 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */
224 ATH_DEBUG_NODE = 0x00080000, /* node management */
225 ATH_DEBUG_LED = 0x00100000, /* led management */
226 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */
227 ATH_DEBUG_ANY = 0xffffffff
229 #define IFF_DUMPPKTS(sc, m) \
230 ((sc->sc_debug & (m)) || \
231 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
232 #define DPRINTF(sc, m, fmt, ...) do { \
233 if (sc->sc_debug & (m)) \
234 printf(fmt, __VA_ARGS__); \
236 #define KEYPRINTF(sc, ix, hk, mac) do { \
237 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \
238 ath_keyprint(__func__, ix, hk, mac); \
240 static void ath_printrxbuf(struct ath_buf *bf, int);
241 static void ath_printtxbuf(struct ath_buf *bf, int);
243 #define IFF_DUMPPKTS(sc, m) \
244 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
245 #define DPRINTF(m, fmt, ...)
246 #define KEYPRINTF(sc, k, ix, mac)
249 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
252 ath_attach(u_int16_t devid, struct ath_softc *sc)
255 struct ieee80211com *ic = &sc->sc_ic;
256 struct ath_hal *ah = NULL;
260 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
262 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
264 device_printf(sc->sc_dev, "can not if_alloc()\n");
269 /* set these up early for if_printf use */
270 if_initname(ifp, device_get_name(sc->sc_dev),
271 device_get_unit(sc->sc_dev));
273 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status);
275 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
280 if (ah->ah_abi != HAL_ABI_VERSION) {
281 if_printf(ifp, "HAL ABI mismatch detected "
282 "(HAL:0x%x != driver:0x%x)\n",
283 ah->ah_abi, HAL_ABI_VERSION);
288 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
291 * Check if the MAC has multi-rate retry support.
292 * We do this by trying to setup a fake extended
293 * descriptor. MAC's that don't have support will
294 * return false w/o doing anything. MAC's that do
295 * support it will return true w/o doing anything.
297 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
300 * Check if the device has hardware counters for PHY
301 * errors. If so we need to enable the MIB interrupt
302 * so we can act on stat triggers.
304 if (ath_hal_hwphycounters(ah))
308 * Get the hardware key cache size.
310 sc->sc_keymax = ath_hal_keycachesize(ah);
311 if (sc->sc_keymax > ATH_KEYMAX) {
312 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
313 ATH_KEYMAX, sc->sc_keymax);
314 sc->sc_keymax = ATH_KEYMAX;
317 * Reset the key cache since some parts do not
318 * reset the contents on initial power up.
320 for (i = 0; i < sc->sc_keymax; i++)
321 ath_hal_keyreset(ah, i);
323 * Mark key cache slots associated with global keys
324 * as in use. If we knew TKIP was not to be used we
325 * could leave the +32, +64, and +32+64 slots free.
326 * XXX only for splitmic.
328 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
329 setbit(sc->sc_keymap, i);
330 setbit(sc->sc_keymap, i+32);
331 setbit(sc->sc_keymap, i+64);
332 setbit(sc->sc_keymap, i+32+64);
336 * Collect the channel list using the default country
337 * code and including outdoor channels. The 802.11 layer
338 * is resposible for filtering this list based on settings
341 error = ath_getchannels(sc, ath_countrycode,
342 ath_outdoor, ath_xchanmode);
346 * Setup dynamic sysctl's now that country code and
347 * regdomain are available from the hal.
349 ath_sysctlattach(sc);
352 * Setup rate tables for all potential media types.
354 ath_rate_setup(sc, IEEE80211_MODE_11A);
355 ath_rate_setup(sc, IEEE80211_MODE_11B);
356 ath_rate_setup(sc, IEEE80211_MODE_11G);
357 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
358 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
359 /* NB: setup here so ath_rate_update is happy */
360 ath_setcurmode(sc, IEEE80211_MODE_11A);
363 * Allocate tx+rx descriptors and populate the lists.
365 error = ath_desc_alloc(sc);
367 if_printf(ifp, "failed to allocate descriptors: %d\n", error);
370 callout_init(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0);
371 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE);
373 ATH_TXBUF_LOCK_INIT(sc);
375 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc);
376 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc);
377 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc);
378 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
379 TASK_INIT(&sc->sc_bstucktask, 0, ath_bstuck_proc, sc);
382 * Allocate hardware transmit queues: one queue for
383 * beacon frames and one data queue for each QoS
384 * priority. Note that the hal handles reseting
385 * these queues at the needed time.
389 sc->sc_bhalq = ath_beaconq_setup(ah);
390 if (sc->sc_bhalq == (u_int) -1) {
391 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
395 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
396 if (sc->sc_cabq == NULL) {
397 if_printf(ifp, "unable to setup CAB xmit queue!\n");
401 /* NB: insure BK queue is the lowest priority h/w queue */
402 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
403 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
404 ieee80211_wme_acnames[WME_AC_BK]);
408 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
409 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
410 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
412 * Not enough hardware tx queues to properly do WME;
413 * just punt and assign them all to the same h/w queue.
414 * We could do a better job of this if, for example,
415 * we allocate queues when we switch from station to
418 if (sc->sc_ac2q[WME_AC_VI] != NULL)
419 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
420 if (sc->sc_ac2q[WME_AC_BE] != NULL)
421 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
422 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
423 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
424 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
428 * Special case certain configurations. Note the
429 * CAB queue is handled by these specially so don't
430 * include them when checking the txq setup mask.
432 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
434 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
437 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
440 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
445 * Setup rate control. Some rate control modules
446 * call back to change the anntena state so expose
447 * the necessary entry points.
448 * XXX maybe belongs in struct ath_ratectrl?
450 sc->sc_setdefantenna = ath_setdefantenna;
451 sc->sc_rc = ath_rate_attach(sc);
452 if (sc->sc_rc == NULL) {
459 sc->sc_ledon = 0; /* low true */
460 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
461 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE);
463 * Auto-enable soft led processing for IBM cards and for
464 * 5211 minipci cards. Users can also manually enable/disable
465 * support with a sysctl.
467 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
468 if (sc->sc_softled) {
469 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin);
470 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
474 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
475 ifp->if_start = ath_start;
476 ifp->if_watchdog = ath_watchdog;
477 ifp->if_ioctl = ath_ioctl;
478 ifp->if_init = ath_init;
479 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
480 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
481 IFQ_SET_READY(&ifp->if_snd);
484 ic->ic_reset = ath_reset;
485 ic->ic_newassoc = ath_newassoc;
486 ic->ic_updateslot = ath_updateslot;
487 ic->ic_wme.wme_update = ath_wme_update;
488 /* XXX not right but it's not used anywhere important */
489 ic->ic_phytype = IEEE80211_T_OFDM;
490 ic->ic_opmode = IEEE80211_M_STA;
492 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
493 | IEEE80211_C_HOSTAP /* hostap mode */
494 | IEEE80211_C_MONITOR /* monitor mode */
495 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
496 | IEEE80211_C_SHSLOT /* short slot time supported */
497 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
500 * Query the hal to figure out h/w crypto support.
502 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
503 ic->ic_caps |= IEEE80211_C_WEP;
504 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
505 ic->ic_caps |= IEEE80211_C_AES;
506 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
507 ic->ic_caps |= IEEE80211_C_AES_CCM;
508 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
509 ic->ic_caps |= IEEE80211_C_CKIP;
510 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
511 ic->ic_caps |= IEEE80211_C_TKIP;
513 * Check if h/w does the MIC and/or whether the
514 * separate key cache entries are required to
515 * handle both tx+rx MIC keys.
517 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
518 ic->ic_caps |= IEEE80211_C_TKIPMIC;
519 if (ath_hal_tkipsplit(ah))
522 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
523 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
525 * TPC support can be done either with a global cap or
526 * per-packet support. The latter is not available on
527 * all parts. We're a bit pedantic here as all parts
528 * support a global cap.
530 sc->sc_hastpc = ath_hal_hastpc(ah);
531 if (sc->sc_hastpc || ath_hal_hastxpowlimit(ah))
532 ic->ic_caps |= IEEE80211_C_TXPMGT;
535 * Mark WME capability only if we have sufficient
536 * hardware queues to do proper priority scheduling.
538 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
539 ic->ic_caps |= IEEE80211_C_WME;
541 * Check for misc other capabilities.
543 if (ath_hal_hasbursting(ah))
544 ic->ic_caps |= IEEE80211_C_BURST;
547 * Indicate we need the 802.11 header padded to a
548 * 32-bit boundary for 4-address and QoS frames.
550 ic->ic_flags |= IEEE80211_F_DATAPAD;
553 * Query the hal about antenna support.
555 if (ath_hal_hasdiversity(ah)) {
556 sc->sc_hasdiversity = 1;
557 sc->sc_diversity = ath_hal_getdiversity(ah);
559 sc->sc_defant = ath_hal_getdefantenna(ah);
562 * Not all chips have the VEOL support we want to
563 * use with IBSS beacons; check here for it.
565 sc->sc_hasveol = ath_hal_hasveol(ah);
567 /* get mac address from hardware */
568 ath_hal_getmac(ah, ic->ic_myaddr);
570 /* call MI attach routine. */
571 ieee80211_ifattach(ic);
572 /* override default methods */
573 ic->ic_node_alloc = ath_node_alloc;
574 sc->sc_node_free = ic->ic_node_free;
575 ic->ic_node_free = ath_node_free;
576 ic->ic_node_getrssi = ath_node_getrssi;
577 sc->sc_recv_mgmt = ic->ic_recv_mgmt;
578 ic->ic_recv_mgmt = ath_recv_mgmt;
579 sc->sc_newstate = ic->ic_newstate;
580 ic->ic_newstate = ath_newstate;
581 ic->ic_crypto.cs_key_alloc = ath_key_alloc;
582 ic->ic_crypto.cs_key_delete = ath_key_delete;
583 ic->ic_crypto.cs_key_set = ath_key_set;
584 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin;
585 ic->ic_crypto.cs_key_update_end = ath_key_update_end;
586 /* complete initialization */
587 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status);
592 ieee80211_announce(ic);
608 ath_detach(struct ath_softc *sc)
610 struct ifnet *ifp = sc->sc_ifp;
612 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
613 __func__, ifp->if_flags);
618 * NB: the order of these is important:
619 * o call the 802.11 layer before detaching the hal to
620 * insure callbacks into the driver to delete global
621 * key cache entries can be handled
622 * o reclaim the tx queue data structures after calling
623 * the 802.11 layer as we'll get called back to reclaim
624 * node state and potentially want to use them
625 * o to cleanup the tx queues the hal is called, so detach
627 * Other than that, it's straightforward...
629 ieee80211_ifdetach(&sc->sc_ic);
630 ath_rate_detach(sc->sc_rc);
633 ath_hal_detach(sc->sc_ah);
639 ath_suspend(struct ath_softc *sc)
641 struct ifnet *ifp = sc->sc_ifp;
643 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
644 __func__, ifp->if_flags);
650 ath_resume(struct ath_softc *sc)
652 struct ifnet *ifp = sc->sc_ifp;
654 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
655 __func__, ifp->if_flags);
657 if (ifp->if_flags & IFF_UP) {
659 if (ifp->if_flags & IFF_RUNNING)
662 if (sc->sc_softled) {
663 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
664 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
669 ath_shutdown(struct ath_softc *sc)
671 struct ifnet *ifp = sc->sc_ifp;
673 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
674 __func__, ifp->if_flags);
680 * Interrupt handler. Most of the actual processing is deferred.
685 struct ath_softc *sc = arg;
686 struct ifnet *ifp = sc->sc_ifp;
687 struct ath_hal *ah = sc->sc_ah;
690 if (sc->sc_invalid) {
692 * The hardware is not ready/present, don't touch anything.
693 * Note this can happen early on if the IRQ is shared.
695 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
698 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */
700 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) {
701 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
702 __func__, ifp->if_flags);
703 ath_hal_getisr(ah, &status); /* clear ISR */
704 ath_hal_intrset(ah, 0); /* disable further intr's */
708 * Figure out the reason(s) for the interrupt. Note
709 * that the hal returns a pseudo-ISR that may include
710 * bits we haven't explicitly enabled so we mask the
711 * value to insure we only process bits we requested.
713 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
714 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
715 status &= sc->sc_imask; /* discard unasked for bits */
716 if (status & HAL_INT_FATAL) {
718 * Fatal errors are unrecoverable. Typically
719 * these are caused by DMA errors. Unfortunately
720 * the exact reason is not (presently) returned
723 sc->sc_stats.ast_hardware++;
724 ath_hal_intrset(ah, 0); /* disable intr's until reset */
725 taskqueue_enqueue(taskqueue_swi, &sc->sc_fataltask);
726 } else if (status & HAL_INT_RXORN) {
727 sc->sc_stats.ast_rxorn++;
728 ath_hal_intrset(ah, 0); /* disable intr's until reset */
729 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxorntask);
731 if (status & HAL_INT_SWBA) {
733 * Software beacon alert--time to send a beacon.
734 * Handle beacon transmission directly; deferring
735 * this is too slow to meet timing constraints
738 ath_beacon_proc(sc, 0);
740 if (status & HAL_INT_RXEOL) {
742 * NB: the hardware should re-read the link when
743 * RXE bit is written, but it doesn't work at
744 * least on older hardware revs.
746 sc->sc_stats.ast_rxeol++;
747 sc->sc_rxlink = NULL;
749 if (status & HAL_INT_TXURN) {
750 sc->sc_stats.ast_txurn++;
751 /* bump tx trigger level */
752 ath_hal_updatetxtriglevel(ah, AH_TRUE);
754 if (status & HAL_INT_RX)
755 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxtask);
756 if (status & HAL_INT_TX)
757 taskqueue_enqueue(taskqueue_swi, &sc->sc_txtask);
758 if (status & HAL_INT_BMISS) {
759 sc->sc_stats.ast_bmiss++;
760 taskqueue_enqueue(taskqueue_swi, &sc->sc_bmisstask);
762 if (status & HAL_INT_MIB) {
763 sc->sc_stats.ast_mib++;
765 * Disable interrupts until we service the MIB
766 * interrupt; otherwise it will continue to fire.
768 ath_hal_intrset(ah, 0);
770 * Let the hal handle the event. We assume it will
771 * clear whatever condition caused the interrupt.
774 &ATH_NODE(sc->sc_ic.ic_bss)->an_halstats);
775 ath_hal_intrset(ah, sc->sc_imask);
781 ath_fatal_proc(void *arg, int pending)
783 struct ath_softc *sc = arg;
784 struct ifnet *ifp = sc->sc_ifp;
786 if_printf(ifp, "hardware error; resetting\n");
791 ath_rxorn_proc(void *arg, int pending)
793 struct ath_softc *sc = arg;
794 struct ifnet *ifp = sc->sc_ifp;
796 if_printf(ifp, "rx FIFO overrun; resetting\n");
801 ath_bmiss_proc(void *arg, int pending)
803 struct ath_softc *sc = arg;
804 struct ieee80211com *ic = &sc->sc_ic;
806 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
807 KASSERT(ic->ic_opmode == IEEE80211_M_STA,
808 ("unexpect operating mode %u", ic->ic_opmode));
809 if (ic->ic_state == IEEE80211_S_RUN) {
811 * Rather than go directly to scan state, try to
812 * reassociate first. If that fails then the state
813 * machine will drop us into scanning after timing
814 * out waiting for a probe response.
817 ieee80211_new_state(ic, IEEE80211_S_ASSOC, -1);
823 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan)
825 #define N(a) (sizeof(a) / sizeof(a[0]))
826 static const u_int modeflags[] = {
827 0, /* IEEE80211_MODE_AUTO */
828 CHANNEL_A, /* IEEE80211_MODE_11A */
829 CHANNEL_B, /* IEEE80211_MODE_11B */
830 CHANNEL_PUREG, /* IEEE80211_MODE_11G */
831 0, /* IEEE80211_MODE_FH */
832 CHANNEL_T, /* IEEE80211_MODE_TURBO_A */
833 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */
835 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan);
837 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode));
838 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode));
839 return modeflags[mode];
846 struct ath_softc *sc = (struct ath_softc *) arg;
847 struct ieee80211com *ic = &sc->sc_ic;
848 struct ifnet *ifp = sc->sc_ifp;
849 struct ieee80211_node *ni;
850 struct ath_hal *ah = sc->sc_ah;
853 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
854 __func__, ifp->if_flags);
858 * Stop anything previously setup. This is safe
859 * whether this is the first time through or not.
861 ath_stop_locked(ifp);
864 * The basic interface to setting the hardware in a good
865 * state is ``reset''. On return the hardware is known to
866 * be powered up and with interrupts disabled. This must
867 * be followed by initialization of the appropriate bits
868 * and then setup of the interrupt mask.
870 sc->sc_curchan.channel = ic->ic_ibss_chan->ic_freq;
871 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_ibss_chan);
872 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) {
873 if_printf(ifp, "unable to reset hardware; hal status %u\n",
879 * This is needed only to setup initial state
880 * but it's best done after a reset.
882 ath_update_txpow(sc);
885 * Setup the hardware after reset: the key cache
886 * is filled as needed and the receive engine is
887 * set going. Frame transmit is handled entirely
888 * in the frame output path; there's nothing to do
889 * here except setup the interrupt mask.
891 if (ath_startrecv(sc) != 0) {
892 if_printf(ifp, "unable to start recv logic\n");
899 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
900 | HAL_INT_RXEOL | HAL_INT_RXORN
901 | HAL_INT_FATAL | HAL_INT_GLOBAL;
903 * Enable MIB interrupts when there are hardware phy counters.
904 * Note we only do this (at the moment) for station mode.
906 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
907 sc->sc_imask |= HAL_INT_MIB;
908 ath_hal_intrset(ah, sc->sc_imask);
910 ifp->if_flags |= IFF_RUNNING;
911 ic->ic_state = IEEE80211_S_INIT;
914 * The hardware should be ready to go now so it's safe
915 * to kick the 802.11 state machine as it's likely to
916 * immediately call back to us to send mgmt frames.
919 ni->ni_chan = ic->ic_ibss_chan;
920 ath_chan_change(sc, ni->ni_chan);
921 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
922 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
923 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
925 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
931 ath_stop_locked(struct ifnet *ifp)
933 struct ath_softc *sc = ifp->if_softc;
934 struct ieee80211com *ic = &sc->sc_ic;
935 struct ath_hal *ah = sc->sc_ah;
937 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
938 __func__, sc->sc_invalid, ifp->if_flags);
941 if (ifp->if_flags & IFF_RUNNING) {
943 * Shutdown the hardware and driver:
944 * reset 802.11 state machine
948 * clear transmit machinery
949 * clear receive machinery
950 * drain and release tx queues
951 * reclaim beacon resources
952 * power down hardware
954 * Note that some of this work is not possible if the
955 * hardware is gone (invalid).
957 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
958 ifp->if_flags &= ~IFF_RUNNING;
960 if (!sc->sc_invalid) {
961 if (sc->sc_softled) {
962 callout_stop(&sc->sc_ledtimer);
963 ath_hal_gpioset(ah, sc->sc_ledpin,
967 ath_hal_intrset(ah, 0);
970 if (!sc->sc_invalid) {
972 ath_hal_phydisable(ah);
974 sc->sc_rxlink = NULL;
975 IFQ_DRV_PURGE(&ifp->if_snd);
981 ath_stop(struct ifnet *ifp)
983 struct ath_softc *sc = ifp->if_softc;
986 ath_stop_locked(ifp);
987 if (!sc->sc_invalid) {
989 * Set the chip in full sleep mode. Note that we are
990 * careful to do this only when bringing the interface
991 * completely to a stop. When the chip is in this state
992 * it must be carefully woken up or references to
993 * registers in the PCI clock domain may freeze the bus
994 * (and system). This varies by chip and is mostly an
995 * issue with newer parts that go to sleep more quickly.
997 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP, 0);
1003 * Reset the hardware w/o losing operational state. This is
1004 * basically a more efficient way of doing ath_stop, ath_init,
1005 * followed by state transitions to the current 802.11
1006 * operational state. Used to recover from various errors and
1007 * to reset or reload hardware state.
1010 ath_reset(struct ifnet *ifp)
1012 struct ath_softc *sc = ifp->if_softc;
1013 struct ieee80211com *ic = &sc->sc_ic;
1014 struct ath_hal *ah = sc->sc_ah;
1015 struct ieee80211_channel *c;
1019 * Convert to a HAL channel description with the flags
1020 * constrained to reflect the current operating mode.
1022 c = ic->ic_ibss_chan;
1023 sc->sc_curchan.channel = c->ic_freq;
1024 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c);
1026 ath_hal_intrset(ah, 0); /* disable interrupts */
1027 ath_draintxq(sc); /* stop xmit side */
1028 ath_stoprecv(sc); /* stop recv side */
1029 /* NB: indicate channel change so we do a full reset */
1030 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status))
1031 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
1033 ath_update_txpow(sc); /* update tx power state */
1034 if (ath_startrecv(sc) != 0) /* restart recv */
1035 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
1037 * We may be doing a reset in response to an ioctl
1038 * that changes the channel so update any state that
1039 * might change as a result.
1041 ath_chan_change(sc, c);
1042 if (ic->ic_state == IEEE80211_S_RUN)
1043 ath_beacon_config(sc); /* restart beacons */
1044 ath_hal_intrset(ah, sc->sc_imask);
1046 ath_start(ifp); /* restart xmit */
1051 ath_start(struct ifnet *ifp)
1053 struct ath_softc *sc = ifp->if_softc;
1054 struct ath_hal *ah = sc->sc_ah;
1055 struct ieee80211com *ic = &sc->sc_ic;
1056 struct ieee80211_node *ni;
1059 struct ieee80211_frame *wh;
1060 struct ether_header *eh;
1062 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid)
1066 * Grab a TX buffer and associated resources.
1069 bf = STAILQ_FIRST(&sc->sc_txbuf);
1071 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
1072 ATH_TXBUF_UNLOCK(sc);
1074 DPRINTF(sc, ATH_DEBUG_ANY, "%s: out of xmit buffers\n",
1076 sc->sc_stats.ast_tx_qstop++;
1077 ifp->if_flags |= IFF_OACTIVE;
1081 * Poll the management queue for frames; they
1082 * have priority over normal data frames.
1084 IF_DEQUEUE(&ic->ic_mgtq, m);
1087 * No data frames go out unless we're associated.
1089 if (ic->ic_state != IEEE80211_S_RUN) {
1090 DPRINTF(sc, ATH_DEBUG_ANY,
1091 "%s: ignore data packet, state %u\n",
1092 __func__, ic->ic_state);
1093 sc->sc_stats.ast_tx_discard++;
1095 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1096 ATH_TXBUF_UNLOCK(sc);
1099 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */
1102 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1103 ATH_TXBUF_UNLOCK(sc);
1107 * Find the node for the destination so we can do
1108 * things like power save and fast frames aggregation.
1110 if (m->m_len < sizeof(struct ether_header) &&
1111 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) {
1112 ic->ic_stats.is_tx_nobuf++; /* XXX */
1116 eh = mtod(m, struct ether_header *);
1117 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1119 /* NB: ieee80211_find_txnode does stat+msg */
1123 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) &&
1124 (m->m_flags & M_PWR_SAV) == 0) {
1126 * Station in power save mode; pass the frame
1127 * to the 802.11 layer and continue. We'll get
1128 * the frame back when the time is right.
1130 ieee80211_pwrsave(ic, ni, m);
1133 /* calculate priority so we can find the tx queue */
1134 if (ieee80211_classify(ic, m, ni)) {
1135 DPRINTF(sc, ATH_DEBUG_XMIT,
1136 "%s: discard, classification failure\n",
1144 * Encapsulate the packet in prep for transmission.
1146 m = ieee80211_encap(ic, m, ni);
1148 DPRINTF(sc, ATH_DEBUG_ANY,
1149 "%s: encapsulation failure\n",
1151 sc->sc_stats.ast_tx_encap++;
1156 * Hack! The referenced node pointer is in the
1157 * rcvif field of the packet header. This is
1158 * placed there by ieee80211_mgmt_output because
1159 * we need to hold the reference with the frame
1160 * and there's no other way (other than packet
1161 * tags which we consider too expensive to use)
1164 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1165 m->m_pkthdr.rcvif = NULL;
1167 wh = mtod(m, struct ieee80211_frame *);
1168 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1169 IEEE80211_FC0_SUBTYPE_PROBE_RESP) {
1170 /* fill time stamp */
1174 tsf = ath_hal_gettsf64(ah);
1175 /* XXX: adjust 100us delay to xmit */
1177 tstamp = (u_int32_t *)&wh[1];
1178 tstamp[0] = htole32(tsf & 0xffffffff);
1179 tstamp[1] = htole32(tsf >> 32);
1181 sc->sc_stats.ast_tx_mgmt++;
1184 if (ath_tx_start(sc, ni, bf, m)) {
1189 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1190 ATH_TXBUF_UNLOCK(sc);
1192 ieee80211_free_node(ni);
1196 sc->sc_tx_timer = 5;
1202 ath_media_change(struct ifnet *ifp)
1204 #define IS_UP(ifp) \
1205 ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP))
1208 error = ieee80211_media_change(ifp);
1209 if (error == ENETRESET) {
1211 ath_init(ifp->if_softc); /* XXX lose error */
1220 ath_keyprint(const char *tag, u_int ix,
1221 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1223 static const char *ciphers[] = {
1233 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]);
1234 for (i = 0, n = hk->kv_len; i < n; i++)
1235 printf("%02x", hk->kv_val[i]);
1236 printf(" mac %s", ether_sprintf(mac));
1237 if (hk->kv_type == HAL_CIPHER_TKIP) {
1239 for (i = 0; i < sizeof(hk->kv_mic); i++)
1240 printf("%02x", hk->kv_mic[i]);
1247 * Set a TKIP key into the hardware. This handles the
1248 * potential distribution of key state to multiple key
1249 * cache slots for TKIP.
1252 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k,
1253 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1255 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV)
1256 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN];
1257 struct ath_hal *ah = sc->sc_ah;
1259 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP,
1260 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher));
1261 KASSERT(sc->sc_splitmic, ("key cache !split"));
1262 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) {
1264 * TX key goes at first index, RX key at +32.
1265 * The hal handles the MIC keys at index+64.
1267 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic));
1268 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid);
1269 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid))
1272 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1273 KEYPRINTF(sc, k->wk_keyix+32, hk, mac);
1274 /* XXX delete tx key on failure? */
1275 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac);
1276 } else if (k->wk_flags & IEEE80211_KEY_XR) {
1278 * TX/RX key goes at first index.
1279 * The hal handles the MIC keys are index+64.
1281 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ?
1282 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic));
1283 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1284 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1287 #undef IEEE80211_KEY_XR
1291 * Set a net80211 key into the hardware. This handles the
1292 * potential distribution of key state to multiple key
1293 * cache slots for TKIP with hardware MIC support.
1296 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k,
1297 const u_int8_t mac0[IEEE80211_ADDR_LEN],
1298 struct ieee80211_node *bss)
1300 #define N(a) (sizeof(a)/sizeof(a[0]))
1301 static const u_int8_t ciphermap[] = {
1302 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */
1303 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */
1304 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */
1305 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */
1306 (u_int8_t) -1, /* 4 is not allocated */
1307 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */
1308 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */
1310 struct ath_hal *ah = sc->sc_ah;
1311 const struct ieee80211_cipher *cip = k->wk_cipher;
1312 u_int8_t gmac[IEEE80211_ADDR_LEN];
1313 const u_int8_t *mac;
1316 memset(&hk, 0, sizeof(hk));
1318 * Software crypto uses a "clear key" so non-crypto
1319 * state kept in the key cache are maintained and
1320 * so that rx frames have an entry to match.
1322 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) {
1323 KASSERT(cip->ic_cipher < N(ciphermap),
1324 ("invalid cipher type %u", cip->ic_cipher));
1325 hk.kv_type = ciphermap[cip->ic_cipher];
1326 hk.kv_len = k->wk_keylen;
1327 memcpy(hk.kv_val, k->wk_key, k->wk_keylen);
1329 hk.kv_type = HAL_CIPHER_CLR;
1331 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) {
1333 * Group keys on hardware that supports multicast frame
1334 * key search use a mac that is the sender's address with
1335 * the high bit set instead of the app-specified address.
1337 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr);
1343 if (hk.kv_type == HAL_CIPHER_TKIP &&
1344 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 &&
1346 return ath_keyset_tkip(sc, k, &hk, mac);
1348 KEYPRINTF(sc, k->wk_keyix, &hk, mac);
1349 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac);
1355 * Allocate tx/rx key slots for TKIP. We allocate two slots for
1356 * each key, one for decrypt/encrypt and the other for the MIC.
1359 key_alloc_2pair(struct ath_softc *sc)
1361 #define N(a) (sizeof(a)/sizeof(a[0]))
1364 KASSERT(sc->sc_splitmic, ("key cache !split"));
1365 /* XXX could optimize */
1366 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
1367 u_int8_t b = sc->sc_keymap[i];
1370 * One or more slots in this byte are free.
1378 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */
1379 if (isset(sc->sc_keymap, keyix+32) ||
1380 isset(sc->sc_keymap, keyix+64) ||
1381 isset(sc->sc_keymap, keyix+32+64)) {
1382 /* full pair unavailable */
1384 if (keyix == (i+1)*NBBY) {
1385 /* no slots were appropriate, advance */
1390 setbit(sc->sc_keymap, keyix);
1391 setbit(sc->sc_keymap, keyix+64);
1392 setbit(sc->sc_keymap, keyix+32);
1393 setbit(sc->sc_keymap, keyix+32+64);
1394 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1395 "%s: key pair %u,%u %u,%u\n",
1396 __func__, keyix, keyix+64,
1397 keyix+32, keyix+32+64);
1401 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
1402 return IEEE80211_KEYIX_NONE;
1407 * Allocate a single key cache slot.
1410 key_alloc_single(struct ath_softc *sc)
1412 #define N(a) (sizeof(a)/sizeof(a[0]))
1415 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */
1416 for (i = 0; i < N(sc->sc_keymap); i++) {
1417 u_int8_t b = sc->sc_keymap[i];
1420 * One or more slots are free.
1425 setbit(sc->sc_keymap, keyix);
1426 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n",
1431 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__);
1432 return IEEE80211_KEYIX_NONE;
1437 * Allocate one or more key cache slots for a uniacst key. The
1438 * key itself is needed only to identify the cipher. For hardware
1439 * TKIP with split cipher+MIC keys we allocate two key cache slot
1440 * pairs so that we can setup separate TX and RX MIC keys. Note
1441 * that the MIC key for a TKIP key at slot i is assumed by the
1442 * hardware to be at slot i+64. This limits TKIP keys to the first
1446 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k)
1448 struct ath_softc *sc = ic->ic_ifp->if_softc;
1451 * Group key allocation must be handled specially for
1452 * parts that do not support multicast key cache search
1453 * functionality. For those parts the key id must match
1454 * the h/w key index so lookups find the right key. On
1455 * parts w/ the key search facility we install the sender's
1456 * mac address (with the high bit set) and let the hardware
1457 * find the key w/o using the key id. This is preferred as
1458 * it permits us to support multiple users for adhoc and/or
1459 * multi-station operation.
1461 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) {
1464 if (!(&ic->ic_nw_keys[0] <= k &&
1465 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) {
1466 /* should not happen */
1467 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1468 "%s: bogus group key\n", __func__);
1469 return IEEE80211_KEYIX_NONE;
1471 keyix = k - ic->ic_nw_keys;
1473 * XXX we pre-allocate the global keys so
1474 * have no way to check if they've already been allocated.
1480 * We allocate two pair for TKIP when using the h/w to do
1481 * the MIC. For everything else, including software crypto,
1482 * we allocate a single entry. Note that s/w crypto requires
1483 * a pass-through slot on the 5211 and 5212. The 5210 does
1484 * not support pass-through cache entries and we map all
1485 * those requests to slot 0.
1487 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
1488 return key_alloc_single(sc);
1489 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP &&
1490 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) {
1491 return key_alloc_2pair(sc);
1493 return key_alloc_single(sc);
1498 * Delete an entry in the key cache allocated by ath_key_alloc.
1501 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
1503 struct ath_softc *sc = ic->ic_ifp->if_softc;
1504 struct ath_hal *ah = sc->sc_ah;
1505 const struct ieee80211_cipher *cip = k->wk_cipher;
1506 struct ieee80211_node *ni;
1507 u_int keyix = k->wk_keyix;
1509 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix);
1511 ath_hal_keyreset(ah, keyix);
1513 * Check the key->node map and flush any ref.
1515 ni = sc->sc_keyixmap[keyix];
1517 ieee80211_free_node(ni);
1518 sc->sc_keyixmap[keyix] = NULL;
1521 * Handle split tx/rx keying required for TKIP with h/w MIC.
1523 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1524 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) {
1525 ath_hal_keyreset(ah, keyix+32); /* RX key */
1526 ni = sc->sc_keyixmap[keyix+32];
1527 if (ni != NULL) { /* as above... */
1528 ieee80211_free_node(ni);
1529 sc->sc_keyixmap[keyix+32] = NULL;
1532 if (keyix >= IEEE80211_WEP_NKID) {
1534 * Don't touch keymap entries for global keys so
1535 * they are never considered for dynamic allocation.
1537 clrbit(sc->sc_keymap, keyix);
1538 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1539 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 &&
1541 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */
1542 clrbit(sc->sc_keymap, keyix+32); /* RX key */
1543 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */
1550 * Set the key cache contents for the specified key. Key cache
1551 * slot(s) must already have been allocated by ath_key_alloc.
1554 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
1555 const u_int8_t mac[IEEE80211_ADDR_LEN])
1557 struct ath_softc *sc = ic->ic_ifp->if_softc;
1559 return ath_keyset(sc, k, mac, ic->ic_bss);
1563 * Block/unblock tx+rx processing while a key change is done.
1564 * We assume the caller serializes key management operations
1565 * so we only need to worry about synchronization with other
1566 * uses that originate in the driver.
1569 ath_key_update_begin(struct ieee80211com *ic)
1571 struct ifnet *ifp = ic->ic_ifp;
1572 struct ath_softc *sc = ifp->if_softc;
1574 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1576 tasklet_disable(&sc->sc_rxtq);
1578 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
1582 ath_key_update_end(struct ieee80211com *ic)
1584 struct ifnet *ifp = ic->ic_ifp;
1585 struct ath_softc *sc = ifp->if_softc;
1587 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1588 IF_UNLOCK(&ifp->if_snd);
1590 tasklet_enable(&sc->sc_rxtq);
1595 * Calculate the receive filter according to the
1596 * operating mode and state:
1598 * o always accept unicast, broadcast, and multicast traffic
1599 * o maintain current state of phy error reception (the hal
1600 * may enable phy error frames for noise immunity work)
1601 * o probe request frames are accepted only when operating in
1602 * hostap, adhoc, or monitor modes
1603 * o enable promiscuous mode according to the interface state
1605 * - when operating in adhoc mode so the 802.11 layer creates
1606 * node table entries for peers,
1607 * - when operating in station mode for collecting rssi data when
1608 * the station is otherwise quiet, or
1612 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state)
1614 struct ieee80211com *ic = &sc->sc_ic;
1615 struct ath_hal *ah = sc->sc_ah;
1616 struct ifnet *ifp = sc->sc_ifp;
1619 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR)
1620 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
1621 if (ic->ic_opmode != IEEE80211_M_STA)
1622 rfilt |= HAL_RX_FILTER_PROBEREQ;
1623 if (ic->ic_opmode != IEEE80211_M_HOSTAP &&
1624 (ifp->if_flags & IFF_PROMISC))
1625 rfilt |= HAL_RX_FILTER_PROM;
1626 if (ic->ic_opmode == IEEE80211_M_STA ||
1627 ic->ic_opmode == IEEE80211_M_IBSS ||
1628 state == IEEE80211_S_SCAN)
1629 rfilt |= HAL_RX_FILTER_BEACON;
1634 ath_mode_init(struct ath_softc *sc)
1636 struct ieee80211com *ic = &sc->sc_ic;
1637 struct ath_hal *ah = sc->sc_ah;
1638 struct ifnet *ifp = sc->sc_ifp;
1639 u_int32_t rfilt, mfilt[2], val;
1641 struct ifmultiaddr *ifma;
1643 /* configure rx filter */
1644 rfilt = ath_calcrxfilter(sc, ic->ic_state);
1645 ath_hal_setrxfilter(ah, rfilt);
1647 /* configure operational mode */
1648 ath_hal_setopmode(ah);
1651 * Handle any link-level address change. Note that we only
1652 * need to force ic_myaddr; any other addresses are handled
1653 * as a byproduct of the ifnet code marking the interface
1656 * XXX should get from lladdr instead of arpcom but that's more work
1658 IEEE80211_ADDR_COPY(ic->ic_myaddr, IFP2ENADDR(ifp));
1659 ath_hal_setmac(ah, ic->ic_myaddr);
1661 /* calculate and install multicast filter */
1662 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
1663 mfilt[0] = mfilt[1] = 0;
1664 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1667 /* calculate XOR of eight 6bit values */
1668 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
1669 val = LE_READ_4(dl + 0);
1670 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1671 val = LE_READ_4(dl + 3);
1672 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1674 mfilt[pos / 32] |= (1 << (pos % 32));
1677 mfilt[0] = mfilt[1] = ~0;
1679 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]);
1680 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n",
1681 __func__, rfilt, mfilt[0], mfilt[1]);
1685 * Set the slot time based on the current setting.
1688 ath_setslottime(struct ath_softc *sc)
1690 struct ieee80211com *ic = &sc->sc_ic;
1691 struct ath_hal *ah = sc->sc_ah;
1693 if (ic->ic_flags & IEEE80211_F_SHSLOT)
1694 ath_hal_setslottime(ah, HAL_SLOT_TIME_9);
1696 ath_hal_setslottime(ah, HAL_SLOT_TIME_20);
1697 sc->sc_updateslot = OK;
1701 * Callback from the 802.11 layer to update the
1702 * slot time based on the current setting.
1705 ath_updateslot(struct ifnet *ifp)
1707 struct ath_softc *sc = ifp->if_softc;
1708 struct ieee80211com *ic = &sc->sc_ic;
1711 * When not coordinating the BSS, change the hardware
1712 * immediately. For other operation we defer the change
1713 * until beacon updates have propagated to the stations.
1715 if (ic->ic_opmode == IEEE80211_M_HOSTAP)
1716 sc->sc_updateslot = UPDATE;
1718 ath_setslottime(sc);
1722 * Setup a h/w transmit queue for beacons.
1725 ath_beaconq_setup(struct ath_hal *ah)
1729 memset(&qi, 0, sizeof(qi));
1730 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
1731 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
1732 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
1733 /* NB: for dynamic turbo, don't enable any other interrupts */
1734 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1735 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
1739 * Setup the transmit queue parameters for the beacon queue.
1742 ath_beaconq_config(struct ath_softc *sc)
1744 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
1745 struct ieee80211com *ic = &sc->sc_ic;
1746 struct ath_hal *ah = sc->sc_ah;
1749 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
1750 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1752 * Always burst out beacon and CAB traffic.
1754 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
1755 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
1756 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
1758 struct wmeParams *wmep =
1759 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
1761 * Adhoc mode; important thing is to use 2x cwmin.
1763 qi.tqi_aifs = wmep->wmep_aifsn;
1764 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
1765 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
1768 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
1769 device_printf(sc->sc_dev, "unable to update parameters for "
1770 "beacon hardware queue!\n");
1773 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
1776 #undef ATH_EXPONENT_TO_VALUE
1780 * Allocate and setup an initial beacon frame.
1783 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
1785 struct ieee80211com *ic = ni->ni_ic;
1790 bf = STAILQ_FIRST(&sc->sc_bbuf);
1792 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__);
1793 sc->sc_stats.ast_be_nombuf++; /* XXX */
1794 return ENOMEM; /* XXX */
1797 * NB: the beacon data buffer must be 32-bit aligned;
1798 * we assume the mbuf routines will return us something
1799 * with this alignment (perhaps should assert).
1801 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff);
1803 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n",
1805 sc->sc_stats.ast_be_nombuf++;
1808 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
1809 bf->bf_segs, &bf->bf_nseg,
1813 bf->bf_node = ieee80211_ref_node(ni);
1821 * Setup the beacon frame for transmit.
1824 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
1826 #define USE_SHPREAMBLE(_ic) \
1827 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
1828 == IEEE80211_F_SHPREAMBLE)
1829 struct ieee80211_node *ni = bf->bf_node;
1830 struct ieee80211com *ic = ni->ni_ic;
1831 struct mbuf *m = bf->bf_m;
1832 struct ath_hal *ah = sc->sc_ah;
1833 struct ath_node *an = ATH_NODE(ni);
1834 struct ath_desc *ds;
1838 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n",
1839 __func__, m, m->m_len);
1841 /* setup descriptors */
1844 flags = HAL_TXDESC_NOACK;
1845 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
1846 ds->ds_link = bf->bf_daddr; /* self-linked */
1847 flags |= HAL_TXDESC_VEOL;
1849 * Let hardware handle antenna switching.
1855 * Switch antenna every 4 beacons.
1856 * XXX assumes two antenna
1858 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
1861 KASSERT(bf->bf_nseg == 1,
1862 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
1863 ds->ds_data = bf->bf_segs[0].ds_addr;
1865 * Calculate rate code.
1866 * XXX everything at min xmit rate
1868 if (USE_SHPREAMBLE(ic))
1869 rate = an->an_tx_mgtratesp;
1871 rate = an->an_tx_mgtrate;
1872 ath_hal_setuptxdesc(ah, ds
1873 , m->m_len + IEEE80211_CRC_LEN /* frame length */
1874 , sizeof(struct ieee80211_frame)/* header length */
1875 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
1876 , ni->ni_txpower /* txpower XXX */
1877 , rate, 1 /* series 0 rate/tries */
1878 , HAL_TXKEYIX_INVALID /* no encryption */
1879 , antenna /* antenna mode */
1880 , flags /* no ack, veol for beacons */
1881 , 0 /* rts/cts rate */
1882 , 0 /* rts/cts duration */
1884 /* NB: beacon's BufLen must be a multiple of 4 bytes */
1885 ath_hal_filltxdesc(ah, ds
1886 , roundup(m->m_len, 4) /* buffer length */
1887 , AH_TRUE /* first segment */
1888 , AH_TRUE /* last segment */
1889 , ds /* first descriptor */
1891 #undef USE_SHPREAMBLE
1895 * Transmit a beacon frame at SWBA. Dynamic updates to the
1896 * frame contents are done as needed and the slot time is
1897 * also adjusted based on current state.
1900 ath_beacon_proc(void *arg, int pending)
1902 struct ath_softc *sc = arg;
1903 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
1904 struct ieee80211_node *ni = bf->bf_node;
1905 struct ieee80211com *ic = ni->ni_ic;
1906 struct ath_hal *ah = sc->sc_ah;
1908 int ncabq, error, otherant;
1910 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n",
1913 if (ic->ic_opmode == IEEE80211_M_STA ||
1914 ic->ic_opmode == IEEE80211_M_MONITOR ||
1915 bf == NULL || bf->bf_m == NULL) {
1916 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n",
1917 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL);
1921 * Check if the previous beacon has gone out. If
1922 * not don't don't try to post another, skip this
1923 * period and wait for the next. Missed beacons
1924 * indicate a problem and should not occur. If we
1925 * miss too many consecutive beacons reset the device.
1927 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
1928 sc->sc_bmisscount++;
1929 DPRINTF(sc, ATH_DEBUG_BEACON_PROC,
1930 "%s: missed %u consecutive beacons\n",
1931 __func__, sc->sc_bmisscount);
1932 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */
1933 taskqueue_enqueue(taskqueue_swi, &sc->sc_bstucktask);
1936 if (sc->sc_bmisscount != 0) {
1937 DPRINTF(sc, ATH_DEBUG_BEACON,
1938 "%s: resume beacon xmit after %u misses\n",
1939 __func__, sc->sc_bmisscount);
1940 sc->sc_bmisscount = 0;
1944 * Update dynamic beacon contents. If this returns
1945 * non-zero then we need to remap the memory because
1946 * the beacon frame changed size (probably because
1947 * of the TIM bitmap).
1950 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum);
1951 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) {
1952 /* XXX too conservative? */
1953 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
1954 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
1955 bf->bf_segs, &bf->bf_nseg,
1958 if_printf(ic->ic_ifp,
1959 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
1966 * Handle slot time change when a non-ERP station joins/leaves
1967 * an 11g network. The 802.11 layer notifies us via callback,
1968 * we mark updateslot, then wait one beacon before effecting
1969 * the change. This gives associated stations at least one
1970 * beacon interval to note the state change.
1973 if (sc->sc_updateslot == UPDATE)
1974 sc->sc_updateslot = COMMIT; /* commit next beacon */
1975 else if (sc->sc_updateslot == COMMIT)
1976 ath_setslottime(sc); /* commit change to h/w */
1979 * Check recent per-antenna transmit statistics and flip
1980 * the default antenna if noticeably more frames went out
1981 * on the non-default antenna.
1982 * XXX assumes 2 anntenae
1984 otherant = sc->sc_defant & 1 ? 2 : 1;
1985 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
1986 ath_setdefantenna(sc, otherant);
1987 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
1990 * Construct tx descriptor.
1992 ath_beacon_setup(sc, bf);
1995 * Stop any current dma and put the new frame on the queue.
1996 * This should never fail since we check above that no frames
1997 * are still pending on the queue.
1999 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
2000 DPRINTF(sc, ATH_DEBUG_ANY,
2001 "%s: beacon queue %u did not stop?\n",
2002 __func__, sc->sc_bhalq);
2004 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
2007 * Enable the CAB queue before the beacon queue to
2008 * insure cab frames are triggered by this beacon.
2010 if (sc->sc_boff.bo_tim[4] & 1) /* NB: only at DTIM */
2011 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum);
2012 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
2013 ath_hal_txstart(ah, sc->sc_bhalq);
2014 DPRINTF(sc, ATH_DEBUG_BEACON_PROC,
2015 "%s: TXDP[%u] = %p (%p)\n", __func__,
2016 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc);
2018 sc->sc_stats.ast_be_xmit++;
2022 * Reset the hardware after detecting beacons have stopped.
2025 ath_bstuck_proc(void *arg, int pending)
2027 struct ath_softc *sc = arg;
2028 struct ifnet *ifp = sc->sc_ifp;
2030 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
2036 * Reclaim beacon resources.
2039 ath_beacon_free(struct ath_softc *sc)
2043 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
2044 if (bf->bf_m != NULL) {
2045 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2049 if (bf->bf_node != NULL) {
2050 ieee80211_free_node(bf->bf_node);
2057 * Configure the beacon and sleep timers.
2059 * When operating as an AP this resets the TSF and sets
2060 * up the hardware to notify us when we need to issue beacons.
2062 * When operating in station mode this sets up the beacon
2063 * timers according to the timestamp of the last received
2064 * beacon and the current TSF, configures PCF and DTIM
2065 * handling, programs the sleep registers so the hardware
2066 * will wakeup in time to receive beacons, and configures
2067 * the beacon miss handling so we'll receive a BMISS
2068 * interrupt when we stop seeing beacons from the AP
2069 * we've associated with.
2072 ath_beacon_config(struct ath_softc *sc)
2074 #define TSF_TO_TU(_h,_l) (((_h) << 22) | ((_l) >> 10))
2075 struct ath_hal *ah = sc->sc_ah;
2076 struct ieee80211com *ic = &sc->sc_ic;
2077 struct ieee80211_node *ni = ic->ic_bss;
2078 u_int32_t nexttbtt, intval;
2080 /* extract tstamp from last beacon and convert to TU */
2081 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4),
2082 LE_READ_4(ni->ni_tstamp.data));
2083 /* NB: the beacon interval is kept internally in TU's */
2084 intval = ni->ni_intval & HAL_BEACON_PERIOD;
2085 if (nexttbtt == 0) /* e.g. for ap mode */
2087 else if (intval) /* NB: can be 0 for monitor mode */
2088 nexttbtt = roundup(nexttbtt, intval);
2089 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
2090 __func__, nexttbtt, intval, ni->ni_intval);
2091 if (ic->ic_opmode == IEEE80211_M_STA) {
2092 HAL_BEACON_STATE bs;
2095 int dtimperiod, dtimcount;
2096 int cfpperiod, cfpcount;
2099 * Setup dtim and cfp parameters according to
2100 * last beacon we received (which may be none).
2102 dtimperiod = ni->ni_dtim_period;
2103 if (dtimperiod <= 0) /* NB: 0 if not known */
2105 dtimcount = ni->ni_dtim_count;
2106 if (dtimcount >= dtimperiod) /* NB: sanity check */
2107 dtimcount = 0; /* XXX? */
2108 cfpperiod = 1; /* NB: no PCF support yet */
2112 * Pull nexttbtt forward to reflect the current
2113 * TSF and calculate dtim+cfp state for the result.
2115 tsf = ath_hal_gettsf64(ah);
2116 tsftu = TSF_TO_TU((u_int32_t)(tsf>>32), (u_int32_t)tsf) + FUDGE;
2119 if (--dtimcount < 0) {
2120 dtimcount = dtimperiod - 1;
2122 cfpcount = cfpperiod - 1;
2124 } while (nexttbtt < tsftu);
2126 memset(&bs, 0, sizeof(bs));
2127 bs.bs_intval = intval;
2128 bs.bs_nexttbtt = nexttbtt;
2129 bs.bs_dtimperiod = dtimperiod*intval;
2130 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
2131 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
2132 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
2133 bs.bs_cfpmaxduration = 0;
2136 * The 802.11 layer records the offset to the DTIM
2137 * bitmap while receiving beacons; use it here to
2138 * enable h/w detection of our AID being marked in
2139 * the bitmap vector (to indicate frames for us are
2140 * pending at the AP).
2141 * XXX do DTIM handling in s/w to WAR old h/w bugs
2142 * XXX enable based on h/w rev for newer chips
2144 bs.bs_timoffset = ni->ni_timoff;
2147 * Calculate the number of consecutive beacons to miss
2148 * before taking a BMISS interrupt. The configuration
2149 * is specified in ms, so we need to convert that to
2150 * TU's and then calculate based on the beacon interval.
2151 * Note that we clamp the result to at most 10 beacons.
2153 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval);
2154 if (bs.bs_bmissthreshold > 10)
2155 bs.bs_bmissthreshold = 10;
2156 else if (bs.bs_bmissthreshold <= 0)
2157 bs.bs_bmissthreshold = 1;
2160 * Calculate sleep duration. The configuration is
2161 * given in ms. We insure a multiple of the beacon
2162 * period is used. Also, if the sleep duration is
2163 * greater than the DTIM period then it makes senses
2164 * to make it a multiple of that.
2166 * XXX fixed at 100ms
2168 bs.bs_sleepduration =
2169 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
2170 if (bs.bs_sleepduration > bs.bs_dtimperiod)
2171 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
2173 DPRINTF(sc, ATH_DEBUG_BEACON,
2174 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n"
2181 , bs.bs_bmissthreshold
2182 , bs.bs_sleepduration
2184 , bs.bs_cfpmaxduration
2188 ath_hal_intrset(ah, 0);
2189 ath_hal_beacontimers(ah, &bs);
2190 sc->sc_imask |= HAL_INT_BMISS;
2191 ath_hal_intrset(ah, sc->sc_imask);
2193 ath_hal_intrset(ah, 0);
2194 if (nexttbtt == intval)
2195 intval |= HAL_BEACON_RESET_TSF;
2196 if (ic->ic_opmode == IEEE80211_M_IBSS) {
2198 * In IBSS mode enable the beacon timers but only
2199 * enable SWBA interrupts if we need to manually
2200 * prepare beacon frames. Otherwise we use a
2201 * self-linked tx descriptor and let the hardware
2204 intval |= HAL_BEACON_ENA;
2205 if (!sc->sc_hasveol)
2206 sc->sc_imask |= HAL_INT_SWBA;
2207 ath_beaconq_config(sc);
2208 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
2210 * In AP mode we enable the beacon timers and
2211 * SWBA interrupts to prepare beacon frames.
2213 intval |= HAL_BEACON_ENA;
2214 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
2215 ath_beaconq_config(sc);
2217 ath_hal_beaconinit(ah, nexttbtt, intval);
2218 sc->sc_bmisscount = 0;
2219 ath_hal_intrset(ah, sc->sc_imask);
2221 * When using a self-linked beacon descriptor in
2222 * ibss mode load it once here.
2224 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
2225 ath_beacon_proc(sc, 0);
2231 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2233 bus_addr_t *paddr = (bus_addr_t*) arg;
2234 KASSERT(error == 0, ("error %u on bus_dma callback", error));
2235 *paddr = segs->ds_addr;
2239 ath_descdma_setup(struct ath_softc *sc,
2240 struct ath_descdma *dd, ath_bufhead *head,
2241 const char *name, int nbuf, int ndesc)
2243 #define DS2PHYS(_dd, _ds) \
2244 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2245 struct ifnet *ifp = sc->sc_ifp;
2246 struct ath_desc *ds;
2248 int i, bsize, error;
2250 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n",
2251 __func__, name, nbuf, ndesc);
2254 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2257 * Setup DMA descriptor area.
2259 error = bus_dma_tag_create(NULL, /* parent */
2260 PAGE_SIZE, 0, /* alignment, bounds */
2261 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2262 BUS_SPACE_MAXADDR, /* highaddr */
2263 NULL, NULL, /* filter, filterarg */
2264 dd->dd_desc_len, /* maxsize */
2266 BUS_SPACE_MAXADDR, /* maxsegsize */
2267 BUS_DMA_ALLOCNOW, /* flags */
2268 NULL, /* lockfunc */
2272 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
2276 /* allocate descriptors */
2277 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap);
2279 if_printf(ifp, "unable to create dmamap for %s descriptors, "
2280 "error %u\n", dd->dd_name, error);
2284 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
2285 BUS_DMA_NOWAIT, &dd->dd_dmamap);
2287 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
2288 "error %u\n", nbuf * ndesc, dd->dd_name, error);
2292 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
2293 dd->dd_desc, dd->dd_desc_len,
2294 ath_load_cb, &dd->dd_desc_paddr,
2297 if_printf(ifp, "unable to map %s descriptors, error %u\n",
2298 dd->dd_name, error);
2303 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
2304 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len,
2305 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len);
2307 /* allocate rx buffers */
2308 bsize = sizeof(struct ath_buf) * nbuf;
2309 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
2311 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
2312 dd->dd_name, bsize);
2318 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2320 bf->bf_daddr = DS2PHYS(dd, ds);
2321 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
2324 if_printf(ifp, "unable to create dmamap for %s "
2325 "buffer %u, error %u\n", dd->dd_name, i, error);
2326 ath_descdma_cleanup(sc, dd, head);
2329 STAILQ_INSERT_TAIL(head, bf, bf_list);
2333 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2335 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2337 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2339 bus_dma_tag_destroy(dd->dd_dmat);
2340 memset(dd, 0, sizeof(*dd));
2346 ath_descdma_cleanup(struct ath_softc *sc,
2347 struct ath_descdma *dd, ath_bufhead *head)
2350 struct ieee80211_node *ni;
2352 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2353 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2354 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2355 bus_dma_tag_destroy(dd->dd_dmat);
2357 STAILQ_FOREACH(bf, head, bf_list) {
2362 if (bf->bf_dmamap != NULL) {
2363 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
2364 bf->bf_dmamap = NULL;
2370 * Reclaim node reference.
2372 ieee80211_free_node(ni);
2377 free(dd->dd_bufptr, M_ATHDEV);
2378 memset(dd, 0, sizeof(*dd));
2382 ath_desc_alloc(struct ath_softc *sc)
2386 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
2387 "rx", ATH_RXBUF, 1);
2391 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
2392 "tx", ATH_TXBUF, ATH_TXDESC);
2394 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2398 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
2401 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2402 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2409 ath_desc_free(struct ath_softc *sc)
2412 if (sc->sc_bdma.dd_desc_len != 0)
2413 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
2414 if (sc->sc_txdma.dd_desc_len != 0)
2415 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2416 if (sc->sc_rxdma.dd_desc_len != 0)
2417 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2420 static struct ieee80211_node *
2421 ath_node_alloc(struct ieee80211_node_table *nt)
2423 struct ieee80211com *ic = nt->nt_ic;
2424 struct ath_softc *sc = ic->ic_ifp->if_softc;
2425 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
2426 struct ath_node *an;
2428 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
2433 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER;
2434 an->an_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
2435 an->an_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
2436 an->an_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
2437 ath_rate_node_init(sc, an);
2439 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an);
2440 return &an->an_node;
2444 ath_node_free(struct ieee80211_node *ni)
2446 struct ieee80211com *ic = ni->ni_ic;
2447 struct ath_softc *sc = ic->ic_ifp->if_softc;
2449 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni);
2451 ath_rate_node_cleanup(sc, ATH_NODE(ni));
2452 sc->sc_node_free(ni);
2456 ath_node_getrssi(const struct ieee80211_node *ni)
2458 #define HAL_EP_RND(x, mul) \
2459 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
2460 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi;
2464 * When only one frame is received there will be no state in
2465 * avgrssi so fallback on the value recorded by the 802.11 layer.
2467 if (avgrssi != ATH_RSSI_DUMMY_MARKER)
2468 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER);
2471 /* NB: theoretically we shouldn't need this, but be paranoid */
2472 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi;
2477 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
2479 struct ath_hal *ah = sc->sc_ah;
2482 struct ath_desc *ds;
2487 * NB: by assigning a page to the rx dma buffer we
2488 * implicitly satisfy the Atheros requirement that
2489 * this buffer be cache-line-aligned and sized to be
2490 * multiple of the cache line size. Not doing this
2491 * causes weird stuff to happen (for the 5210 at least).
2493 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2495 DPRINTF(sc, ATH_DEBUG_ANY,
2496 "%s: no mbuf/cluster\n", __func__);
2497 sc->sc_stats.ast_rx_nombuf++;
2501 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
2503 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
2505 bf->bf_segs, &bf->bf_nseg,
2508 DPRINTF(sc, ATH_DEBUG_ANY,
2509 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
2511 sc->sc_stats.ast_rx_busdma++;
2514 KASSERT(bf->bf_nseg == 1,
2515 ("multi-segment packet; nseg %u", bf->bf_nseg));
2517 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
2520 * Setup descriptors. For receive we always terminate
2521 * the descriptor list with a self-linked entry so we'll
2522 * not get overrun under high load (as can happen with a
2523 * 5212 when ANI processing enables PHY error frames).
2525 * To insure the last descriptor is self-linked we create
2526 * each descriptor as self-linked and add it to the end. As
2527 * each additional descriptor is added the previous self-linked
2528 * entry is ``fixed'' naturally. This should be safe even
2529 * if DMA is happening. When processing RX interrupts we
2530 * never remove/process the last, self-linked, entry on the
2531 * descriptor list. This insures the hardware always has
2532 * someplace to write a new frame.
2535 ds->ds_link = bf->bf_daddr; /* link to self */
2536 ds->ds_data = bf->bf_segs[0].ds_addr;
2537 ath_hal_setuprxdesc(ah, ds
2538 , m->m_len /* buffer size */
2542 if (sc->sc_rxlink != NULL)
2543 *sc->sc_rxlink = bf->bf_daddr;
2544 sc->sc_rxlink = &ds->ds_link;
2549 * Extend 15-bit time stamp from rx descriptor to
2550 * a full 64-bit TSF using the current h/w TSF.
2552 static __inline u_int64_t
2553 ath_extend_tsf(struct ath_hal *ah, u_int32_t rstamp)
2557 tsf = ath_hal_gettsf64(ah);
2558 if ((tsf & 0x7fff) < rstamp)
2560 return ((tsf &~ 0x7fff) | rstamp);
2564 * Intercept management frames to collect beacon rssi data
2565 * and to do ibss merges.
2568 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
2569 struct ieee80211_node *ni,
2570 int subtype, int rssi, u_int32_t rstamp)
2572 struct ath_softc *sc = ic->ic_ifp->if_softc;
2575 * Call up first so subsequent work can use information
2576 * potentially stored in the node (e.g. for ibss merge).
2578 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp);
2580 case IEEE80211_FC0_SUBTYPE_BEACON:
2581 /* update rssi statistics for use by the hal */
2582 ATH_RSSI_LPF(ATH_NODE(ni)->an_halstats.ns_avgbrssi, rssi);
2584 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
2585 if (ic->ic_opmode == IEEE80211_M_IBSS &&
2586 ic->ic_state == IEEE80211_S_RUN) {
2587 u_int64_t tsf = ath_extend_tsf(sc->sc_ah, rstamp);
2589 * Handle ibss merge as needed; check the tsf on the
2590 * frame before attempting the merge. The 802.11 spec
2591 * says the station should change it's bssid to match
2592 * the oldest station with the same ssid, where oldest
2593 * is determined by the tsf. Note that hardware
2594 * reconfiguration happens through callback to
2595 * ath_newstate as the state machine will go from
2596 * RUN -> RUN when this happens.
2598 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
2599 DPRINTF(sc, ATH_DEBUG_STATE,
2600 "ibss merge, rstamp %u tsf %ju "
2601 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
2602 (uintmax_t)ni->ni_tstamp.tsf);
2603 (void) ieee80211_ibss_merge(ni);
2611 * Set the default antenna.
2614 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
2616 struct ath_hal *ah = sc->sc_ah;
2618 /* XXX block beacon interrupts */
2619 ath_hal_setdefantenna(ah, antenna);
2620 if (sc->sc_defant != antenna)
2621 sc->sc_stats.ast_ant_defswitch++;
2622 sc->sc_defant = antenna;
2623 sc->sc_rxotherant = 0;
2627 ath_rx_proc(void *arg, int npending)
2629 #define PA2DESC(_sc, _pa) \
2630 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
2631 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
2632 struct ath_softc *sc = arg;
2634 struct ieee80211com *ic = &sc->sc_ic;
2635 struct ifnet *ifp = sc->sc_ifp;
2636 struct ath_hal *ah = sc->sc_ah;
2637 struct ath_desc *ds;
2639 struct ieee80211_node *ni;
2640 struct ath_node *an;
2645 NET_LOCK_GIANT(); /* XXX */
2647 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
2649 bf = STAILQ_FIRST(&sc->sc_rxbuf);
2650 if (bf == NULL) { /* NB: shouldn't happen */
2651 if_printf(ifp, "%s: no buffer!\n", __func__);
2655 if (ds->ds_link == bf->bf_daddr) {
2656 /* NB: never process the self-linked entry at the end */
2660 if (m == NULL) { /* NB: shouldn't happen */
2661 if_printf(ifp, "%s: no mbuf!\n", __func__);
2664 /* XXX sync descriptor memory */
2666 * Must provide the virtual address of the current
2667 * descriptor, the physical address, and the virtual
2668 * address of the next descriptor in the h/w chain.
2669 * This allows the HAL to look ahead to see if the
2670 * hardware is done with a descriptor by checking the
2671 * done bit in the following descriptor and the address
2672 * of the current descriptor the DMA engine is working
2673 * on. All this is necessary because of our use of
2674 * a self-linked list to avoid rx overruns.
2676 status = ath_hal_rxprocdesc(ah, ds,
2677 bf->bf_daddr, PA2DESC(sc, ds->ds_link));
2679 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
2680 ath_printrxbuf(bf, status == HAL_OK);
2682 if (status == HAL_EINPROGRESS)
2684 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
2685 if (ds->ds_rxstat.rs_more) {
2687 * Frame spans multiple descriptors; this
2688 * cannot happen yet as we don't support
2689 * jumbograms. If not in monitor mode,
2690 * discard the frame.
2692 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2693 sc->sc_stats.ast_rx_toobig++;
2696 /* fall thru for monitor mode handling... */
2697 } else if (ds->ds_rxstat.rs_status != 0) {
2698 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC)
2699 sc->sc_stats.ast_rx_crcerr++;
2700 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO)
2701 sc->sc_stats.ast_rx_fifoerr++;
2702 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) {
2703 sc->sc_stats.ast_rx_phyerr++;
2704 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f;
2705 sc->sc_stats.ast_rx_phy[phyerr]++;
2708 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) {
2710 * Decrypt error. If the error occurred
2711 * because there was no hardware key, then
2712 * let the frame through so the upper layers
2713 * can process it. This is necessary for 5210
2714 * parts which have no way to setup a ``clear''
2717 * XXX do key cache faulting
2719 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID)
2721 sc->sc_stats.ast_rx_badcrypt++;
2723 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) {
2724 sc->sc_stats.ast_rx_badmic++;
2726 * Do minimal work required to hand off
2727 * the 802.11 header for notifcation.
2729 /* XXX frag's and qos frames */
2730 len = ds->ds_rxstat.rs_datalen;
2731 if (len >= sizeof (struct ieee80211_frame)) {
2732 bus_dmamap_sync(sc->sc_dmat,
2734 BUS_DMASYNC_POSTREAD);
2735 ieee80211_notify_michael_failure(ic,
2736 mtod(m, struct ieee80211_frame *),
2738 ds->ds_rxstat.rs_keyix-32 :
2739 ds->ds_rxstat.rs_keyix
2745 * Reject error frames, we normally don't want
2746 * to see them in monitor mode (in monitor mode
2747 * allow through packets that have crypto problems).
2749 if ((ds->ds_rxstat.rs_status &~
2750 (HAL_RXERR_DECRYPT|HAL_RXERR_MIC)) ||
2751 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR)
2756 * Sync and unmap the frame. At this point we're
2757 * committed to passing the mbuf somewhere so clear
2758 * bf_m; this means a new sk_buff must be allocated
2759 * when the rx descriptor is setup again to receive
2762 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2763 BUS_DMASYNC_POSTREAD);
2764 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2767 m->m_pkthdr.rcvif = ifp;
2768 len = ds->ds_rxstat.rs_datalen;
2769 m->m_pkthdr.len = m->m_len = len;
2771 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++;
2773 if (sc->sc_drvbpf) {
2777 * Discard anything shorter than an ack or cts.
2779 if (len < IEEE80211_ACK_LEN) {
2780 DPRINTF(sc, ATH_DEBUG_RECV,
2781 "%s: runt packet %d\n",
2783 sc->sc_stats.ast_rx_tooshort++;
2787 rix = ds->ds_rxstat.rs_rate;
2788 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
2789 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
2790 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi;
2791 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna;
2794 bpf_mtap2(sc->sc_drvbpf,
2795 &sc->sc_rx_th, sc->sc_rx_th_len, m);
2799 * From this point on we assume the frame is at least
2800 * as large as ieee80211_frame_min; verify that.
2802 if (len < IEEE80211_MIN_LEN) {
2803 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n",
2805 sc->sc_stats.ast_rx_tooshort++;
2810 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
2811 ieee80211_dump_pkt(mtod(m, caddr_t), len,
2812 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate,
2813 ds->ds_rxstat.rs_rssi);
2816 m_adj(m, -IEEE80211_CRC_LEN);
2819 * Locate the node for sender, track state, and then
2820 * pass the (referenced) node up to the 802.11 layer
2821 * for its use. If the sender is unknown spam the
2822 * frame; it'll be dropped where it's not wanted.
2824 if (ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID &&
2825 (ni = sc->sc_keyixmap[ds->ds_rxstat.rs_keyix]) != NULL) {
2827 * Fast path: node is present in the key map;
2828 * grab a reference for processing the frame.
2830 an = ATH_NODE(ieee80211_ref_node(ni));
2831 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi);
2832 type = ieee80211_input(ic, m, ni,
2833 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp);
2836 * Locate the node for sender, track state, and then
2837 * pass the (referenced) node up to the 802.11 layer
2840 ni = ieee80211_find_rxnode(ic,
2841 mtod(m, const struct ieee80211_frame_min *));
2843 * Track rx rssi and do any rx antenna management.
2846 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi);
2848 * Send frame up for processing.
2850 type = ieee80211_input(ic, m, ni,
2851 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp);
2852 if (ni != ic->ic_bss) {
2855 * If the station has a key cache slot assigned
2856 * update the key->node mapping table.
2858 keyix = ni->ni_ucastkey.wk_keyix;
2859 if (keyix != IEEE80211_KEYIX_NONE &&
2860 sc->sc_keyixmap[keyix] == NULL)
2861 sc->sc_keyixmap[keyix] =
2862 ieee80211_ref_node(ni);
2865 ieee80211_free_node(ni);
2866 if (sc->sc_diversity) {
2868 * When using fast diversity, change the default rx
2869 * antenna if diversity chooses the other antenna 3
2872 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) {
2873 if (++sc->sc_rxotherant >= 3)
2874 ath_setdefantenna(sc,
2875 ds->ds_rxstat.rs_antenna);
2877 sc->sc_rxotherant = 0;
2879 if (sc->sc_softled) {
2881 * Blink for any data frame. Otherwise do a
2882 * heartbeat-style blink when idle. The latter
2883 * is mainly for station mode where we depend on
2884 * periodic beacon frames to trigger the poll event.
2886 if (type == IEEE80211_FC0_TYPE_DATA) {
2887 sc->sc_rxrate = ds->ds_rxstat.rs_rate;
2888 ath_led_event(sc, ATH_LED_RX);
2889 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
2890 ath_led_event(sc, ATH_LED_POLL);
2893 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
2894 } while (ath_rxbuf_init(sc, bf) == 0);
2896 /* rx signal state monitoring */
2897 ath_hal_rxmonitor(ah, &ATH_NODE(ic->ic_bss)->an_halstats);
2899 NET_UNLOCK_GIANT(); /* XXX */
2904 * Setup a h/w transmit queue.
2906 static struct ath_txq *
2907 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
2909 #define N(a) (sizeof(a)/sizeof(a[0]))
2910 struct ath_hal *ah = sc->sc_ah;
2914 memset(&qi, 0, sizeof(qi));
2915 qi.tqi_subtype = subtype;
2916 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
2917 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
2918 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
2920 * Enable interrupts only for EOL and DESC conditions.
2921 * We mark tx descriptors to receive a DESC interrupt
2922 * when a tx queue gets deep; otherwise waiting for the
2923 * EOL to reap descriptors. Note that this is done to
2924 * reduce interrupt load and this only defers reaping
2925 * descriptors, never transmitting frames. Aside from
2926 * reducing interrupts this also permits more concurrency.
2927 * The only potential downside is if the tx queue backs
2928 * up in which case the top half of the kernel may backup
2929 * due to a lack of tx descriptors.
2931 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | TXQ_FLAG_TXDESCINT_ENABLE;
2932 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
2935 * NB: don't print a message, this happens
2936 * normally on parts with too few tx queues
2940 if (qnum >= N(sc->sc_txq)) {
2941 device_printf(sc->sc_dev,
2942 "hal qnum %u out of range, max %zu!\n",
2943 qnum, N(sc->sc_txq));
2944 ath_hal_releasetxqueue(ah, qnum);
2947 if (!ATH_TXQ_SETUP(sc, qnum)) {
2948 struct ath_txq *txq = &sc->sc_txq[qnum];
2950 txq->axq_qnum = qnum;
2952 txq->axq_intrcnt = 0;
2953 txq->axq_link = NULL;
2954 STAILQ_INIT(&txq->axq_q);
2955 ATH_TXQ_LOCK_INIT(sc, txq);
2956 sc->sc_txqsetup |= 1<<qnum;
2958 return &sc->sc_txq[qnum];
2963 * Setup a hardware data transmit queue for the specified
2964 * access control. The hal may not support all requested
2965 * queues in which case it will return a reference to a
2966 * previously setup queue. We record the mapping from ac's
2967 * to h/w queues for use by ath_tx_start and also track
2968 * the set of h/w queues being used to optimize work in the
2969 * transmit interrupt handler and related routines.
2972 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
2974 #define N(a) (sizeof(a)/sizeof(a[0]))
2975 struct ath_txq *txq;
2977 if (ac >= N(sc->sc_ac2q)) {
2978 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
2979 ac, N(sc->sc_ac2q));
2982 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
2984 sc->sc_ac2q[ac] = txq;
2992 * Update WME parameters for a transmit queue.
2995 ath_txq_update(struct ath_softc *sc, int ac)
2997 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
2998 #define ATH_TXOP_TO_US(v) (v<<5)
2999 struct ieee80211com *ic = &sc->sc_ic;
3000 struct ath_txq *txq = sc->sc_ac2q[ac];
3001 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
3002 struct ath_hal *ah = sc->sc_ah;
3005 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
3006 qi.tqi_aifs = wmep->wmep_aifsn;
3007 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
3008 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
3009 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
3011 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
3012 device_printf(sc->sc_dev, "unable to update hardware queue "
3013 "parameters for %s traffic!\n",
3014 ieee80211_wme_acnames[ac]);
3017 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
3020 #undef ATH_TXOP_TO_US
3021 #undef ATH_EXPONENT_TO_VALUE
3025 * Callback from the 802.11 layer to update WME parameters.
3028 ath_wme_update(struct ieee80211com *ic)
3030 struct ath_softc *sc = ic->ic_ifp->if_softc;
3032 return !ath_txq_update(sc, WME_AC_BE) ||
3033 !ath_txq_update(sc, WME_AC_BK) ||
3034 !ath_txq_update(sc, WME_AC_VI) ||
3035 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
3039 * Reclaim resources for a setup queue.
3042 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
3045 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
3046 ATH_TXQ_LOCK_DESTROY(txq);
3047 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
3051 * Reclaim all tx queue resources.
3054 ath_tx_cleanup(struct ath_softc *sc)
3058 ATH_TXBUF_LOCK_DESTROY(sc);
3059 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3060 if (ATH_TXQ_SETUP(sc, i))
3061 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
3065 * Defragment an mbuf chain, returning at most maxfrags separate
3066 * mbufs+clusters. If this is not possible NULL is returned and
3067 * the original mbuf chain is left in it's present (potentially
3068 * modified) state. We use two techniques: collapsing consecutive
3069 * mbufs and replacing consecutive mbufs by a cluster.
3071 static struct mbuf *
3072 ath_defrag(struct mbuf *m0, int how, int maxfrags)
3074 struct mbuf *m, *n, *n2, **prev;
3078 * Calculate the current number of frags.
3081 for (m = m0; m != NULL; m = m->m_next)
3084 * First, try to collapse mbufs. Note that we always collapse
3085 * towards the front so we don't need to deal with moving the
3086 * pkthdr. This may be suboptimal if the first mbuf has much
3087 * less data than the following.
3095 if ((m->m_flags & M_RDONLY) == 0 &&
3096 n->m_len < M_TRAILINGSPACE(m)) {
3097 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len,
3099 m->m_len += n->m_len;
3100 m->m_next = n->m_next;
3102 if (--curfrags <= maxfrags)
3107 KASSERT(maxfrags > 1,
3108 ("maxfrags %u, but normal collapse failed", maxfrags));
3110 * Collapse consecutive mbufs to a cluster.
3112 prev = &m0->m_next; /* NB: not the first mbuf */
3113 while ((n = *prev) != NULL) {
3114 if ((n2 = n->m_next) != NULL &&
3115 n->m_len + n2->m_len < MCLBYTES) {
3116 m = m_getcl(how, MT_DATA, 0);
3119 bcopy(mtod(n, void *), mtod(m, void *), n->m_len);
3120 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len,
3122 m->m_len = n->m_len + n2->m_len;
3123 m->m_next = n2->m_next;
3127 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */
3130 * Still not there, try the normal collapse
3131 * again before we allocate another cluster.
3138 * No place where we can collapse to a cluster; punt.
3139 * This can occur if, for example, you request 2 frags
3140 * but the packet requires that both be clusters (we
3141 * never reallocate the first mbuf to avoid moving the
3149 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf,
3152 #define CTS_DURATION \
3153 ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, AH_TRUE)
3154 #define updateCTSForBursting(_ah, _ds, _txq) \
3155 ath_hal_updateCTSForBursting(_ah, _ds, \
3156 _txq->axq_linkbuf != NULL ? _txq->axq_linkbuf->bf_desc : NULL, \
3157 _txq->axq_lastdsWithCTS, _txq->axq_gatingds, \
3158 txopLimit, CTS_DURATION)
3159 struct ieee80211com *ic = &sc->sc_ic;
3160 struct ath_hal *ah = sc->sc_ah;
3161 struct ifnet *ifp = sc->sc_ifp;
3162 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
3163 int i, error, iswep, ismcast, keyix, hdrlen, pktlen, try0;
3164 u_int8_t rix, txrate, ctsrate;
3165 u_int8_t cix = 0xff; /* NB: silence compiler */
3166 struct ath_desc *ds, *ds0;
3167 struct ath_txq *txq;
3168 struct ieee80211_frame *wh;
3169 u_int subtype, flags, ctsduration;
3171 const HAL_RATE_TABLE *rt;
3172 HAL_BOOL shortPreamble;
3173 struct ath_node *an;
3177 wh = mtod(m0, struct ieee80211_frame *);
3178 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
3179 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3180 hdrlen = ieee80211_anyhdrsize(wh);
3182 * Packet length must not include any
3183 * pad bytes; deduct them here.
3185 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
3188 const struct ieee80211_cipher *cip;
3189 struct ieee80211_key *k;
3192 * Construct the 802.11 header+trailer for an encrypted
3193 * frame. The only reason this can fail is because of an
3194 * unknown or unsupported cipher/key type.
3196 k = ieee80211_crypto_encap(ic, ni, m0);
3199 * This can happen when the key is yanked after the
3200 * frame was queued. Just discard the frame; the
3201 * 802.11 layer counts failures and provides
3202 * debugging/diagnostics.
3208 * Adjust the packet + header lengths for the crypto
3209 * additions and calculate the h/w key index. When
3210 * a s/w mic is done the frame will have had any mic
3211 * added to it prior to entry so skb->len above will
3212 * account for it. Otherwise we need to add it to the
3216 hdrlen += cip->ic_header;
3217 pktlen += cip->ic_header + cip->ic_trailer;
3218 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0)
3219 pktlen += cip->ic_miclen;
3220 keyix = k->wk_keyix;
3222 /* packet header may have moved, reset our local pointer */
3223 wh = mtod(m0, struct ieee80211_frame *);
3224 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
3226 * Use station key cache slot, if assigned.
3228 keyix = ni->ni_ucastkey.wk_keyix;
3229 if (keyix == IEEE80211_KEYIX_NONE)
3230 keyix = HAL_TXKEYIX_INVALID;
3232 keyix = HAL_TXKEYIX_INVALID;
3234 pktlen += IEEE80211_CRC_LEN;
3237 * Load the DMA map so any coalescing is done. This
3238 * also calculates the number of descriptors we need.
3240 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
3241 bf->bf_segs, &bf->bf_nseg,
3243 if (error == EFBIG) {
3244 /* XXX packet requires too many descriptors */
3245 bf->bf_nseg = ATH_TXDESC+1;
3246 } else if (error != 0) {
3247 sc->sc_stats.ast_tx_busdma++;
3252 * Discard null packets and check for packets that
3253 * require too many TX descriptors. We try to convert
3254 * the latter to a cluster.
3256 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */
3257 sc->sc_stats.ast_tx_linear++;
3258 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC);
3261 sc->sc_stats.ast_tx_nombuf++;
3265 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
3266 bf->bf_segs, &bf->bf_nseg,
3269 sc->sc_stats.ast_tx_busdma++;
3273 KASSERT(bf->bf_nseg <= ATH_TXDESC,
3274 ("too many segments after defrag; nseg %u", bf->bf_nseg));
3275 } else if (bf->bf_nseg == 0) { /* null packet, discard */
3276 sc->sc_stats.ast_tx_nodata++;
3280 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen);
3281 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
3283 bf->bf_node = ni; /* NB: held reference */
3285 /* setup descriptors */
3287 rt = sc->sc_currates;
3288 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
3291 * NB: the 802.11 layer marks whether or not we should
3292 * use short preamble based on the current mode and
3293 * negotiated parameters.
3295 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3296 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
3297 shortPreamble = AH_TRUE;
3298 sc->sc_stats.ast_tx_shortpre++;
3300 shortPreamble = AH_FALSE;
3304 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
3306 * Calculate Atheros packet type from IEEE80211 packet header,
3307 * setup for rate calculations, and select h/w transmit queue.
3309 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
3310 case IEEE80211_FC0_TYPE_MGT:
3311 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3312 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
3313 atype = HAL_PKT_TYPE_BEACON;
3314 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3315 atype = HAL_PKT_TYPE_PROBE_RESP;
3316 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
3317 atype = HAL_PKT_TYPE_ATIM;
3319 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
3320 rix = 0; /* XXX lowest rate */
3321 try0 = ATH_TXMAXTRY;
3323 txrate = an->an_tx_mgtratesp;
3325 txrate = an->an_tx_mgtrate;
3326 /* NB: force all management frames to highest queue */
3327 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3328 /* NB: force all management frames to highest queue */
3332 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3334 case IEEE80211_FC0_TYPE_CTL:
3335 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
3336 rix = 0; /* XXX lowest rate */
3337 try0 = ATH_TXMAXTRY;
3339 txrate = an->an_tx_mgtratesp;
3341 txrate = an->an_tx_mgtrate;
3342 /* NB: force all ctl frames to highest queue */
3343 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3344 /* NB: force all ctl frames to highest queue */
3348 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3350 case IEEE80211_FC0_TYPE_DATA:
3351 atype = HAL_PKT_TYPE_NORMAL; /* default */
3353 * Data frames; consult the rate control module.
3355 ath_rate_findrate(sc, an, shortPreamble, pktlen,
3356 &rix, &try0, &txrate);
3357 sc->sc_txrate = txrate; /* for LED blinking */
3359 * Default all non-QoS traffic to the background queue.
3361 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) {
3362 pri = M_WME_GETAC(m0);
3363 if (cap->cap_wmeParams[pri].wmep_noackPolicy) {
3364 flags |= HAL_TXDESC_NOACK;
3365 sc->sc_stats.ast_tx_noack++;
3371 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
3372 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
3377 txq = sc->sc_ac2q[pri];
3380 * When servicing one or more stations in power-save mode
3381 * multicast frames must be buffered until after the beacon.
3382 * We use the CAB queue for that.
3384 if (ismcast && ic->ic_ps_sta) {
3386 /* XXX? more bit in 802.11 frame header */
3390 * Calculate miscellaneous flags.
3393 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
3394 sc->sc_stats.ast_tx_noack++;
3395 } else if (pktlen > ic->ic_rtsthreshold) {
3396 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
3397 cix = rt->info[rix].controlRate;
3398 sc->sc_stats.ast_tx_rts++;
3402 * If 802.11g protection is enabled, determine whether
3403 * to use RTS/CTS or just CTS. Note that this is only
3404 * done for OFDM unicast frames.
3406 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
3407 rt->info[rix].phy == IEEE80211_T_OFDM &&
3408 (flags & HAL_TXDESC_NOACK) == 0) {
3409 /* XXX fragments must use CCK rates w/ protection */
3410 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3411 flags |= HAL_TXDESC_RTSENA;
3412 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3413 flags |= HAL_TXDESC_CTSENA;
3414 cix = rt->info[sc->sc_protrix].controlRate;
3415 sc->sc_stats.ast_tx_protect++;
3419 * Calculate duration. This logically belongs in the 802.11
3420 * layer but it lacks sufficient information to calculate it.
3422 if ((flags & HAL_TXDESC_NOACK) == 0 &&
3423 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
3426 * XXX not right with fragmentation.
3429 dur = rt->info[rix].spAckDuration;
3431 dur = rt->info[rix].lpAckDuration;
3432 *(u_int16_t *)wh->i_dur = htole16(dur);
3436 * Calculate RTS/CTS rate and duration if needed.
3439 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
3441 * CTS transmit rate is derived from the transmit rate
3442 * by looking in the h/w rate table. We must also factor
3443 * in whether or not a short preamble is to be used.
3445 /* NB: cix is set above where RTS/CTS is enabled */
3446 KASSERT(cix != 0xff, ("cix not setup"));
3447 ctsrate = rt->info[cix].rateCode;
3449 * Compute the transmit duration based on the frame
3450 * size and the size of an ACK frame. We call into the
3451 * HAL to do the computation since it depends on the
3452 * characteristics of the actual PHY being used.
3454 * NB: CTS is assumed the same size as an ACK so we can
3455 * use the precalculated ACK durations.
3457 if (shortPreamble) {
3458 ctsrate |= rt->info[cix].shortPreamble;
3459 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3460 ctsduration += rt->info[cix].spAckDuration;
3461 ctsduration += ath_hal_computetxtime(ah,
3462 rt, pktlen, rix, AH_TRUE);
3463 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3464 ctsduration += rt->info[cix].spAckDuration;
3466 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3467 ctsduration += rt->info[cix].lpAckDuration;
3468 ctsduration += ath_hal_computetxtime(ah,
3469 rt, pktlen, rix, AH_FALSE);
3470 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3471 ctsduration += rt->info[cix].lpAckDuration;
3474 * Must disable multi-rate retry when using RTS/CTS.
3476 try0 = ATH_TXMAXTRY;
3480 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
3481 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len,
3482 sc->sc_hwmap[txrate].ieeerate, -1);
3485 bpf_mtap(ic->ic_rawbpf, m0);
3486 if (sc->sc_drvbpf) {
3487 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags;
3489 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3490 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate;
3491 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
3492 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
3494 bpf_mtap2(sc->sc_drvbpf,
3495 &sc->sc_tx_th, sc->sc_tx_th_len, m0);
3499 * Determine if a tx interrupt should be generated for
3500 * this descriptor. We take a tx interrupt to reap
3501 * descriptors when the h/w hits an EOL condition or
3502 * when the descriptor is specifically marked to generate
3503 * an interrupt. We periodically mark descriptors in this
3504 * way to insure timely replenishing of the supply needed
3505 * for sending frames. Defering interrupts reduces system
3506 * load and potentially allows more concurrent work to be
3507 * done but if done to aggressively can cause senders to
3510 * NB: use >= to deal with sc_txintrperiod changing
3511 * dynamically through sysctl.
3513 if (flags & HAL_TXDESC_INTREQ) {
3514 txq->axq_intrcnt = 0;
3515 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
3516 flags |= HAL_TXDESC_INTREQ;
3517 txq->axq_intrcnt = 0;
3521 * Formulate first tx descriptor with tx controls.
3523 /* XXX check return value? */
3524 ath_hal_setuptxdesc(ah, ds
3525 , pktlen /* packet length */
3526 , hdrlen /* header length */
3527 , atype /* Atheros packet type */
3528 , ni->ni_txpower /* txpower */
3529 , txrate, try0 /* series 0 rate/tries */
3530 , keyix /* key cache index */
3531 , sc->sc_txantenna /* antenna mode */
3533 , ctsrate /* rts/cts rate */
3534 , ctsduration /* rts/cts duration */
3536 bf->bf_flags = flags;
3538 * Setup the multi-rate retry state only when we're
3539 * going to use it. This assumes ath_hal_setuptxdesc
3540 * initializes the descriptors (so we don't have to)
3541 * when the hardware supports multi-rate retry and
3544 if (try0 != ATH_TXMAXTRY)
3545 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix);
3548 * Fillin the remainder of the descriptor info.
3551 for (i = 0; i < bf->bf_nseg; i++, ds++) {
3552 ds->ds_data = bf->bf_segs[i].ds_addr;
3553 if (i == bf->bf_nseg - 1)
3556 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
3557 ath_hal_filltxdesc(ah, ds
3558 , bf->bf_segs[i].ds_len /* segment length */
3559 , i == 0 /* first segment */
3560 , i == bf->bf_nseg - 1 /* last segment */
3561 , ds0 /* first descriptor */
3563 DPRINTF(sc, ATH_DEBUG_XMIT,
3564 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
3565 __func__, i, ds->ds_link, ds->ds_data,
3566 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
3569 * Insert the frame on the outbound list and
3570 * pass it on to the hardware.
3573 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
3574 u_int32_t txopLimit = IEEE80211_TXOP_TO_US(
3575 cap->cap_wmeParams[pri].wmep_txopLimit);
3577 * When bursting, potentially extend the CTS duration
3578 * of a previously queued frame to cover this frame
3579 * and not exceed the txopLimit. If that can be done
3580 * then disable RTS/CTS on this frame since it's now
3581 * covered (burst extension). Otherwise we must terminate
3582 * the burst before this frame goes out so as not to
3583 * violate the WME parameters. All this is complicated
3584 * as we need to update the state of packets on the
3585 * (live) hardware queue. The logic is buried in the hal
3586 * because it's highly chip-specific.
3588 if (txopLimit != 0) {
3589 sc->sc_stats.ast_tx_ctsburst++;
3590 if (updateCTSForBursting(ah, ds0, txq) == 0) {
3592 * This frame was not covered by RTS/CTS from
3593 * the previous frame in the burst; update the
3594 * descriptor pointers so this frame is now
3595 * treated as the last frame for extending a
3598 txq->axq_lastdsWithCTS = ds0;
3599 /* set gating Desc to final desc */
3601 (struct ath_desc *)txq->axq_link;
3603 sc->sc_stats.ast_tx_ctsext++;
3606 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
3607 if (txq->axq_link == NULL) {
3608 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
3609 DPRINTF(sc, ATH_DEBUG_XMIT,
3610 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__,
3611 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc,
3614 *txq->axq_link = bf->bf_daddr;
3615 DPRINTF(sc, ATH_DEBUG_XMIT,
3616 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
3617 txq->axq_qnum, txq->axq_link,
3618 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth);
3620 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
3622 * The CAB queue is started from the SWBA handler since
3623 * frames only go out on DTIM and to avoid possible races.
3625 if (txq != sc->sc_cabq)
3626 ath_hal_txstart(ah, txq->axq_qnum);
3627 ATH_TXQ_UNLOCK(txq);
3630 #undef updateCTSForBursting
3635 * Process completed xmit descriptors from the specified queue.
3638 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
3640 struct ath_hal *ah = sc->sc_ah;
3641 struct ieee80211com *ic = &sc->sc_ic;
3643 struct ath_desc *ds, *ds0;
3644 struct ieee80211_node *ni;
3645 struct ath_node *an;
3649 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
3650 __func__, txq->axq_qnum,
3651 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
3655 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
3656 bf = STAILQ_FIRST(&txq->axq_q);
3658 txq->axq_link = NULL;
3659 ATH_TXQ_UNLOCK(txq);
3662 ds0 = &bf->bf_desc[0];
3663 ds = &bf->bf_desc[bf->bf_nseg - 1];
3664 status = ath_hal_txprocdesc(ah, ds);
3666 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
3667 ath_printtxbuf(bf, status == HAL_OK);
3669 if (status == HAL_EINPROGRESS) {
3670 ATH_TXQ_UNLOCK(txq);
3673 if (ds0 == txq->axq_lastdsWithCTS)
3674 txq->axq_lastdsWithCTS = NULL;
3675 if (ds == txq->axq_gatingds)
3676 txq->axq_gatingds = NULL;
3677 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3678 ATH_TXQ_UNLOCK(txq);
3683 if (ds->ds_txstat.ts_status == 0) {
3684 u_int8_t txant = ds->ds_txstat.ts_antenna;
3685 sc->sc_stats.ast_ant_tx[txant]++;
3686 sc->sc_ant_tx[txant]++;
3687 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
3688 sc->sc_stats.ast_tx_altrate++;
3689 sc->sc_stats.ast_tx_rssi =
3690 ds->ds_txstat.ts_rssi;
3691 ATH_RSSI_LPF(an->an_halstats.ns_avgtxrssi,
3692 ds->ds_txstat.ts_rssi);
3693 pri = M_WME_GETAC(bf->bf_m);
3694 if (pri >= WME_AC_VO)
3695 ic->ic_wme.wme_hipri_traffic++;
3696 ni->ni_inact = ni->ni_inact_reload;
3698 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
3699 sc->sc_stats.ast_tx_xretries++;
3700 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
3701 sc->sc_stats.ast_tx_fifoerr++;
3702 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
3703 sc->sc_stats.ast_tx_filtered++;
3705 sr = ds->ds_txstat.ts_shortretry;
3706 lr = ds->ds_txstat.ts_longretry;
3707 sc->sc_stats.ast_tx_shortretry += sr;
3708 sc->sc_stats.ast_tx_longretry += lr;
3710 * Hand the descriptor to the rate control algorithm.
3712 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 &&
3713 (bf->bf_flags & HAL_TXDESC_NOACK) == 0)
3714 ath_rate_tx_complete(sc, an, ds, ds0);
3716 * Reclaim reference to node.
3718 * NB: the node may be reclaimed here if, for example
3719 * this is a DEAUTH message that was sent and the
3720 * node was timed out due to inactivity.
3722 ieee80211_free_node(ni);
3724 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3725 BUS_DMASYNC_POSTWRITE);
3726 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3732 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
3733 ATH_TXBUF_UNLOCK(sc);
3738 * Deferred processing of transmit interrupt; special-cased
3739 * for a single hardware transmit queue (e.g. 5210 and 5211).
3742 ath_tx_proc_q0(void *arg, int npending)
3744 struct ath_softc *sc = arg;
3745 struct ifnet *ifp = sc->sc_ifp;
3747 ath_tx_processq(sc, &sc->sc_txq[0]);
3748 ath_tx_processq(sc, sc->sc_cabq);
3749 ifp->if_flags &= ~IFF_OACTIVE;
3750 sc->sc_tx_timer = 0;
3753 ath_led_event(sc, ATH_LED_TX);
3759 * Deferred processing of transmit interrupt; special-cased
3760 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
3763 ath_tx_proc_q0123(void *arg, int npending)
3765 struct ath_softc *sc = arg;
3766 struct ifnet *ifp = sc->sc_ifp;
3769 * Process each active queue.
3771 ath_tx_processq(sc, &sc->sc_txq[0]);
3772 ath_tx_processq(sc, &sc->sc_txq[1]);
3773 ath_tx_processq(sc, &sc->sc_txq[2]);
3774 ath_tx_processq(sc, &sc->sc_txq[3]);
3775 ath_tx_processq(sc, sc->sc_cabq);
3777 ifp->if_flags &= ~IFF_OACTIVE;
3778 sc->sc_tx_timer = 0;
3781 ath_led_event(sc, ATH_LED_TX);
3787 * Deferred processing of transmit interrupt.
3790 ath_tx_proc(void *arg, int npending)
3792 struct ath_softc *sc = arg;
3793 struct ifnet *ifp = sc->sc_ifp;
3797 * Process each active queue.
3799 /* XXX faster to read ISR_S0_S and ISR_S1_S to determine q's? */
3800 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3801 if (ATH_TXQ_SETUP(sc, i))
3802 ath_tx_processq(sc, &sc->sc_txq[i]);
3804 ifp->if_flags &= ~IFF_OACTIVE;
3805 sc->sc_tx_timer = 0;
3808 ath_led_event(sc, ATH_LED_TX);
3814 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
3816 struct ath_hal *ah = sc->sc_ah;
3817 struct ieee80211_node *ni;
3821 * NB: this assumes output has been stopped and
3822 * we do not need to block ath_tx_tasklet
3826 bf = STAILQ_FIRST(&txq->axq_q);
3828 txq->axq_link = NULL;
3829 ATH_TXQ_UNLOCK(txq);
3832 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3833 ATH_TXQ_UNLOCK(txq);
3835 if (sc->sc_debug & ATH_DEBUG_RESET)
3837 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK);
3838 #endif /* AR_DEBUG */
3839 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3846 * Reclaim node reference.
3848 ieee80211_free_node(ni);
3851 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
3852 ATH_TXBUF_UNLOCK(sc);
3857 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
3859 struct ath_hal *ah = sc->sc_ah;
3861 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
3862 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
3863 __func__, txq->axq_qnum,
3864 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
3869 * Drain the transmit queues and reclaim resources.
3872 ath_draintxq(struct ath_softc *sc)
3874 struct ath_hal *ah = sc->sc_ah;
3875 struct ifnet *ifp = sc->sc_ifp;
3878 /* XXX return value */
3879 if (!sc->sc_invalid) {
3880 /* don't touch the hardware if marked invalid */
3881 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
3882 DPRINTF(sc, ATH_DEBUG_RESET,
3883 "%s: beacon queue %p\n", __func__,
3884 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq));
3885 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3886 if (ATH_TXQ_SETUP(sc, i))
3887 ath_tx_stopdma(sc, &sc->sc_txq[i]);
3889 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3890 if (ATH_TXQ_SETUP(sc, i))
3891 ath_tx_draintxq(sc, &sc->sc_txq[i]);
3892 ifp->if_flags &= ~IFF_OACTIVE;
3893 sc->sc_tx_timer = 0;
3897 * Disable the receive h/w in preparation for a reset.
3900 ath_stoprecv(struct ath_softc *sc)
3902 #define PA2DESC(_sc, _pa) \
3903 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
3904 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
3905 struct ath_hal *ah = sc->sc_ah;
3907 ath_hal_stoppcurecv(ah); /* disable PCU */
3908 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
3909 ath_hal_stopdmarecv(ah); /* disable DMA engine */
3910 DELAY(3000); /* 3ms is long enough for 1 frame */
3912 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
3915 printf("%s: rx queue %p, link %p\n", __func__,
3916 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink);
3917 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
3918 struct ath_desc *ds = bf->bf_desc;
3919 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
3920 bf->bf_daddr, PA2DESC(sc, ds->ds_link));
3921 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
3922 ath_printrxbuf(bf, status == HAL_OK);
3926 sc->sc_rxlink = NULL; /* just in case */
3931 * Enable the receive h/w following a reset.
3934 ath_startrecv(struct ath_softc *sc)
3936 struct ath_hal *ah = sc->sc_ah;
3939 sc->sc_rxlink = NULL;
3940 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
3941 int error = ath_rxbuf_init(sc, bf);
3943 DPRINTF(sc, ATH_DEBUG_RECV,
3944 "%s: ath_rxbuf_init failed %d\n",
3950 bf = STAILQ_FIRST(&sc->sc_rxbuf);
3951 ath_hal_putrxbuf(ah, bf->bf_daddr);
3952 ath_hal_rxena(ah); /* enable recv descriptors */
3953 ath_mode_init(sc); /* set filters, etc. */
3954 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
3959 * Update internal state after a channel change.
3962 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
3964 struct ieee80211com *ic = &sc->sc_ic;
3965 enum ieee80211_phymode mode;
3969 * Change channels and update the h/w rate map
3970 * if we're switching; e.g. 11a to 11b/g.
3972 mode = ieee80211_chan2mode(ic, chan);
3973 if (mode != sc->sc_curmode)
3974 ath_setcurmode(sc, mode);
3976 * Update BPF state. NB: ethereal et. al. don't handle
3977 * merged flags well so pick a unique mode for their use.
3979 if (IEEE80211_IS_CHAN_A(chan))
3980 flags = IEEE80211_CHAN_A;
3981 /* XXX 11g schizophrenia */
3982 else if (IEEE80211_IS_CHAN_G(chan) ||
3983 IEEE80211_IS_CHAN_PUREG(chan))
3984 flags = IEEE80211_CHAN_G;
3986 flags = IEEE80211_CHAN_B;
3987 if (IEEE80211_IS_CHAN_T(chan))
3988 flags |= IEEE80211_CHAN_TURBO;
3989 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
3990 htole16(chan->ic_freq);
3991 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
3996 * Set/change channels. If the channel is really being changed,
3997 * it's done by reseting the chip. To accomplish this we must
3998 * first cleanup any pending DMA, then restart stuff after a la
4002 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
4004 struct ath_hal *ah = sc->sc_ah;
4005 struct ieee80211com *ic = &sc->sc_ic;
4009 * Convert to a HAL channel description with
4010 * the flags constrained to reflect the current
4013 hchan.channel = chan->ic_freq;
4014 hchan.channelFlags = ath_chan2flags(ic, chan);
4016 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n",
4018 ath_hal_mhz2ieee(sc->sc_curchan.channel,
4019 sc->sc_curchan.channelFlags),
4020 sc->sc_curchan.channel,
4021 ath_hal_mhz2ieee(hchan.channel, hchan.channelFlags), hchan.channel);
4022 if (hchan.channel != sc->sc_curchan.channel ||
4023 hchan.channelFlags != sc->sc_curchan.channelFlags) {
4027 * To switch channels clear any pending DMA operations;
4028 * wait long enough for the RX fifo to drain, reset the
4029 * hardware at the new frequency, and then re-enable
4030 * the relevant bits of the h/w.
4032 ath_hal_intrset(ah, 0); /* disable interrupts */
4033 ath_draintxq(sc); /* clear pending tx frames */
4034 ath_stoprecv(sc); /* turn off frame recv */
4035 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) {
4036 if_printf(ic->ic_ifp, "ath_chan_set: unable to reset "
4037 "channel %u (%u Mhz)\n",
4038 ieee80211_chan2ieee(ic, chan), chan->ic_freq);
4041 sc->sc_curchan = hchan;
4042 ath_update_txpow(sc); /* update tx power state */
4045 * Re-enable rx framework.
4047 if (ath_startrecv(sc) != 0) {
4048 if_printf(ic->ic_ifp,
4049 "ath_chan_set: unable to restart recv logic\n");
4054 * Change channels and update the h/w rate map
4055 * if we're switching; e.g. 11a to 11b/g.
4057 ic->ic_ibss_chan = chan;
4058 ath_chan_change(sc, chan);
4061 * Re-enable interrupts.
4063 ath_hal_intrset(ah, sc->sc_imask);
4069 ath_next_scan(void *arg)
4071 struct ath_softc *sc = arg;
4072 struct ieee80211com *ic = &sc->sc_ic;
4074 if (ic->ic_state == IEEE80211_S_SCAN)
4075 ieee80211_next_scan(ic);
4079 * Periodically recalibrate the PHY to account
4080 * for temperature/environment changes.
4083 ath_calibrate(void *arg)
4085 struct ath_softc *sc = arg;
4086 struct ath_hal *ah = sc->sc_ah;
4088 sc->sc_stats.ast_per_cal++;
4090 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: channel %u/%x\n",
4091 __func__, sc->sc_curchan.channel, sc->sc_curchan.channelFlags);
4093 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
4095 * Rfgain is out of bounds, reset the chip
4096 * to load new gain values.
4098 sc->sc_stats.ast_per_rfgain++;
4099 ath_reset(sc->sc_ifp);
4101 if (!ath_hal_calibrate(ah, &sc->sc_curchan)) {
4102 DPRINTF(sc, ATH_DEBUG_ANY,
4103 "%s: calibration of channel %u failed\n",
4104 __func__, sc->sc_curchan.channel);
4105 sc->sc_stats.ast_per_calfail++;
4107 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, ath_calibrate, sc);
4111 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
4113 struct ifnet *ifp = ic->ic_ifp;
4114 struct ath_softc *sc = ifp->if_softc;
4115 struct ath_hal *ah = sc->sc_ah;
4116 struct ieee80211_node *ni;
4118 const u_int8_t *bssid;
4120 static const HAL_LED_STATE leds[] = {
4121 HAL_LED_INIT, /* IEEE80211_S_INIT */
4122 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
4123 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
4124 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
4125 HAL_LED_RUN, /* IEEE80211_S_RUN */
4128 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
4129 ieee80211_state_name[ic->ic_state],
4130 ieee80211_state_name[nstate]);
4132 callout_stop(&sc->sc_scan_ch);
4133 callout_stop(&sc->sc_cal_ch);
4134 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
4136 if (nstate == IEEE80211_S_INIT) {
4137 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4139 * NB: disable interrupts so we don't rx frames.
4141 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
4143 * Notify the rate control algorithm.
4145 ath_rate_newstate(sc, nstate);
4149 error = ath_chan_set(sc, ni->ni_chan);
4152 rfilt = ath_calcrxfilter(sc, nstate);
4153 if (nstate == IEEE80211_S_SCAN)
4154 bssid = ifp->if_broadcastaddr;
4156 bssid = ni->ni_bssid;
4157 ath_hal_setrxfilter(ah, rfilt);
4158 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n",
4159 __func__, rfilt, ether_sprintf(bssid));
4161 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA)
4162 ath_hal_setassocid(ah, bssid, ni->ni_associd);
4164 ath_hal_setassocid(ah, bssid, 0);
4165 if (ic->ic_flags & IEEE80211_F_PRIVACY) {
4166 for (i = 0; i < IEEE80211_WEP_NKID; i++)
4167 if (ath_hal_keyisvalid(ah, i))
4168 ath_hal_keysetmac(ah, i, bssid);
4172 * Notify the rate control algorithm so rates
4173 * are setup should ath_beacon_alloc be called.
4175 ath_rate_newstate(sc, nstate);
4177 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
4178 /* nothing to do */;
4179 } else if (nstate == IEEE80211_S_RUN) {
4180 DPRINTF(sc, ATH_DEBUG_STATE,
4181 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s "
4182 "capinfo=0x%04x chan=%d\n"
4186 , ether_sprintf(ni->ni_bssid)
4188 , ieee80211_chan2ieee(ic, ni->ni_chan));
4190 switch (ic->ic_opmode) {
4191 case IEEE80211_M_HOSTAP:
4192 case IEEE80211_M_IBSS:
4194 * Allocate and setup the beacon frame.
4196 * Stop any previous beacon DMA. This may be
4197 * necessary, for example, when an ibss merge
4198 * causes reconfiguration; there will be a state
4199 * transition from RUN->RUN that means we may
4200 * be called with beacon transmission active.
4202 ath_hal_stoptxdma(ah, sc->sc_bhalq);
4203 ath_beacon_free(sc);
4204 error = ath_beacon_alloc(sc, ni);
4208 case IEEE80211_M_STA:
4210 * Allocate a key cache slot to the station.
4212 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 &&
4214 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
4215 ath_setup_stationkey(ni);
4222 * Configure the beacon and sleep timers.
4224 ath_beacon_config(sc);
4227 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
4228 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4232 * Invoke the parent method to complete the work.
4234 error = sc->sc_newstate(ic, nstate, arg);
4236 * Finally, start any timers.
4238 if (nstate == IEEE80211_S_RUN) {
4239 /* start periodic recalibration timer */
4240 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz,
4242 } else if (nstate == IEEE80211_S_SCAN) {
4243 /* start ap/neighbor scan timer */
4244 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000,
4252 * Allocate a key cache slot to the station so we can
4253 * setup a mapping from key index to node. The key cache
4254 * slot is needed for managing antenna state and for
4255 * compression when stations do not use crypto. We do
4256 * it uniliaterally here; if crypto is employed this slot
4257 * will be reassigned.
4260 ath_setup_stationkey(struct ieee80211_node *ni)
4262 struct ieee80211com *ic = ni->ni_ic;
4263 struct ath_softc *sc = ic->ic_ifp->if_softc;
4266 keyix = ath_key_alloc(ic, &ni->ni_ucastkey);
4267 if (keyix == IEEE80211_KEYIX_NONE) {
4269 * Key cache is full; we'll fall back to doing
4270 * the more expensive lookup in software. Note
4271 * this also means no h/w compression.
4273 /* XXX msg+statistic */
4275 ni->ni_ucastkey.wk_keyix = keyix;
4276 /* NB: this will create a pass-thru key entry */
4277 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss);
4282 * Setup driver-specific state for a newly associated node.
4283 * Note that we're called also on a re-associate, the isnew
4284 * param tells us if this is the first time or not.
4287 ath_newassoc(struct ieee80211_node *ni, int isnew)
4289 struct ieee80211com *ic = ni->ni_ic;
4290 struct ath_softc *sc = ic->ic_ifp->if_softc;
4292 ath_rate_newassoc(sc, ATH_NODE(ni), isnew);
4294 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) {
4295 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE,
4296 ("new assoc with a unicast key already setup (keyix %u)",
4297 ni->ni_ucastkey.wk_keyix));
4298 ath_setup_stationkey(ni);
4303 ath_getchannels(struct ath_softc *sc, u_int cc,
4304 HAL_BOOL outdoor, HAL_BOOL xchanmode)
4306 struct ieee80211com *ic = &sc->sc_ic;
4307 struct ifnet *ifp = sc->sc_ifp;
4308 struct ath_hal *ah = sc->sc_ah;
4312 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL),
4314 if (chans == NULL) {
4315 if_printf(ifp, "unable to allocate channel table\n");
4318 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan,
4319 cc, HAL_MODE_ALL, outdoor, xchanmode)) {
4322 ath_hal_getregdomain(ah, &rd);
4323 if_printf(ifp, "unable to collect channel list from hal; "
4324 "regdomain likely %u country code %u\n", rd, cc);
4325 free(chans, M_TEMP);
4330 * Convert HAL channels to ieee80211 ones and insert
4331 * them in the table according to their channel number.
4333 for (i = 0; i < nchan; i++) {
4334 HAL_CHANNEL *c = &chans[i];
4335 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags);
4336 if (ix > IEEE80211_CHAN_MAX) {
4337 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n",
4338 ix, c->channel, c->channelFlags);
4341 /* NB: flags are known to be compatible */
4342 if (ic->ic_channels[ix].ic_freq == 0) {
4343 ic->ic_channels[ix].ic_freq = c->channel;
4344 ic->ic_channels[ix].ic_flags = c->channelFlags;
4346 /* channels overlap; e.g. 11g and 11b */
4347 ic->ic_channels[ix].ic_flags |= c->channelFlags;
4350 free(chans, M_TEMP);
4355 ath_led_done(void *arg)
4357 struct ath_softc *sc = arg;
4359 sc->sc_blinking = 0;
4363 * Turn the LED off: flip the pin and then set a timer so no
4364 * update will happen for the specified duration.
4367 ath_led_off(void *arg)
4369 struct ath_softc *sc = arg;
4371 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
4372 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc);
4376 * Blink the LED according to the specified on/off times.
4379 ath_led_blink(struct ath_softc *sc, int on, int off)
4381 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off);
4382 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon);
4383 sc->sc_blinking = 1;
4384 sc->sc_ledoff = off;
4385 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc);
4389 ath_led_event(struct ath_softc *sc, int event)
4392 sc->sc_ledevent = ticks; /* time of last event */
4393 if (sc->sc_blinking) /* don't interrupt active blink */
4397 ath_led_blink(sc, sc->sc_hwmap[0].ledon,
4398 sc->sc_hwmap[0].ledoff);
4401 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon,
4402 sc->sc_hwmap[sc->sc_txrate].ledoff);
4405 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon,
4406 sc->sc_hwmap[sc->sc_rxrate].ledoff);
4412 ath_update_txpow(struct ath_softc *sc)
4414 struct ieee80211com *ic = &sc->sc_ic;
4415 struct ath_hal *ah = sc->sc_ah;
4418 if (sc->sc_curtxpow != ic->ic_txpowlimit) {
4419 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
4420 /* read back in case value is clamped */
4421 ath_hal_gettxpowlimit(ah, &txpow);
4422 ic->ic_txpowlimit = sc->sc_curtxpow = txpow;
4425 * Fetch max tx power level for status requests.
4427 ath_hal_getmaxtxpow(sc->sc_ah, &txpow);
4428 ic->ic_bss->ni_txpower = txpow;
4432 ath_rate_setup(struct ath_softc *sc, u_int mode)
4434 struct ath_hal *ah = sc->sc_ah;
4435 struct ieee80211com *ic = &sc->sc_ic;
4436 const HAL_RATE_TABLE *rt;
4437 struct ieee80211_rateset *rs;
4441 case IEEE80211_MODE_11A:
4442 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A);
4444 case IEEE80211_MODE_11B:
4445 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B);
4447 case IEEE80211_MODE_11G:
4448 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G);
4450 case IEEE80211_MODE_TURBO_A:
4451 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO);
4453 case IEEE80211_MODE_TURBO_G:
4454 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_108G);
4457 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
4461 rt = sc->sc_rates[mode];
4464 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) {
4465 DPRINTF(sc, ATH_DEBUG_ANY,
4466 "%s: rate table too small (%u > %u)\n",
4467 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE);
4468 maxrates = IEEE80211_RATE_MAXSIZE;
4470 maxrates = rt->rateCount;
4471 rs = &ic->ic_sup_rates[mode];
4472 for (i = 0; i < maxrates; i++)
4473 rs->rs_rates[i] = rt->info[i].dot11Rate;
4474 rs->rs_nrates = maxrates;
4479 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
4481 #define N(a) (sizeof(a)/sizeof(a[0]))
4482 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
4483 static const struct {
4484 u_int rate; /* tx/rx 802.11 rate */
4485 u_int16_t timeOn; /* LED on time (ms) */
4486 u_int16_t timeOff; /* LED off time (ms) */
4503 const HAL_RATE_TABLE *rt;
4506 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
4507 rt = sc->sc_rates[mode];
4508 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
4509 for (i = 0; i < rt->rateCount; i++)
4510 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i;
4511 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
4512 for (i = 0; i < 32; i++) {
4513 u_int8_t ix = rt->rateCodeToIndex[i];
4515 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
4516 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
4519 sc->sc_hwmap[i].ieeerate =
4520 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL;
4521 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
4522 if (rt->info[ix].shortPreamble ||
4523 rt->info[ix].phy == IEEE80211_T_OFDM)
4524 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
4525 /* NB: receive frames include FCS */
4526 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags |
4527 IEEE80211_RADIOTAP_F_FCS;
4528 /* setup blink rate table to avoid per-packet lookup */
4529 for (j = 0; j < N(blinkrates)-1; j++)
4530 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
4532 /* NB: this uses the last entry if the rate isn't found */
4533 /* XXX beware of overlow */
4534 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
4535 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
4537 sc->sc_currates = rt;
4538 sc->sc_curmode = mode;
4540 * All protection frames are transmited at 2Mb/s for
4541 * 11g, otherwise at 1Mb/s.
4542 * XXX select protection rate index from rate table.
4544 sc->sc_protrix = (mode == IEEE80211_MODE_11G ? 1 : 0);
4545 /* NB: caller is responsible for reseting rate control state */
4551 ath_printrxbuf(struct ath_buf *bf, int done)
4553 struct ath_desc *ds;
4556 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
4557 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n",
4558 i, ds, (struct ath_desc *)bf->bf_daddr + i,
4559 ds->ds_link, ds->ds_data,
4560 ds->ds_ctl0, ds->ds_ctl1,
4561 ds->ds_hw[0], ds->ds_hw[1],
4562 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!');
4567 ath_printtxbuf(struct ath_buf *bf, int done)
4569 struct ath_desc *ds;
4572 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
4573 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n",
4574 i, ds, (struct ath_desc *)bf->bf_daddr + i,
4575 ds->ds_link, ds->ds_data,
4576 ds->ds_ctl0, ds->ds_ctl1,
4577 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3],
4578 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!');
4581 #endif /* AR_DEBUG */
4584 ath_watchdog(struct ifnet *ifp)
4586 struct ath_softc *sc = ifp->if_softc;
4587 struct ieee80211com *ic = &sc->sc_ic;
4590 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid)
4592 if (sc->sc_tx_timer) {
4593 if (--sc->sc_tx_timer == 0) {
4594 if_printf(ifp, "device timeout\n");
4597 sc->sc_stats.ast_watchdog++;
4601 ieee80211_watchdog(ic);
4605 * Diagnostic interface to the HAL. This is used by various
4606 * tools to do things like retrieve register contents for
4607 * debugging. The mechanism is intentionally opaque so that
4608 * it can change frequently w/o concern for compatiblity.
4611 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
4613 struct ath_hal *ah = sc->sc_ah;
4614 u_int id = ad->ad_id & ATH_DIAG_ID;
4615 void *indata = NULL;
4616 void *outdata = NULL;
4617 u_int32_t insize = ad->ad_in_size;
4618 u_int32_t outsize = ad->ad_out_size;
4621 if (ad->ad_id & ATH_DIAG_IN) {
4625 indata = malloc(insize, M_TEMP, M_NOWAIT);
4626 if (indata == NULL) {
4630 error = copyin(ad->ad_in_data, indata, insize);
4634 if (ad->ad_id & ATH_DIAG_DYN) {
4636 * Allocate a buffer for the results (otherwise the HAL
4637 * returns a pointer to a buffer where we can read the
4638 * results). Note that we depend on the HAL leaving this
4639 * pointer for us to use below in reclaiming the buffer;
4640 * may want to be more defensive.
4642 outdata = malloc(outsize, M_TEMP, M_NOWAIT);
4643 if (outdata == NULL) {
4648 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
4649 if (outsize < ad->ad_out_size)
4650 ad->ad_out_size = outsize;
4651 if (outdata != NULL)
4652 error = copyout(outdata, ad->ad_out_data,
4658 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
4659 free(indata, M_TEMP);
4660 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
4661 free(outdata, M_TEMP);
4666 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
4668 #define IS_RUNNING(ifp) \
4669 ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP))
4670 struct ath_softc *sc = ifp->if_softc;
4671 struct ieee80211com *ic = &sc->sc_ic;
4672 struct ifreq *ifr = (struct ifreq *)data;
4678 if (IS_RUNNING(ifp)) {
4680 * To avoid rescanning another access point,
4681 * do not call ath_init() here. Instead,
4682 * only reflect promisc mode settings.
4685 } else if (ifp->if_flags & IFF_UP) {
4687 * Beware of being called during attach/detach
4688 * to reset promiscuous mode. In that case we
4689 * will still be marked UP but not RUNNING.
4690 * However trying to re-init the interface
4691 * is the wrong thing to do as we've already
4692 * torn down much of our state. There's
4693 * probably a better way to deal with this.
4695 if (!sc->sc_invalid && ic->ic_bss != NULL)
4696 ath_init(sc); /* XXX lose error */
4698 ath_stop_locked(ifp);
4703 * The upper layer has already installed/removed
4704 * the multicast address(es), just recalculate the
4705 * multicast filter for the card.
4707 if (ifp->if_flags & IFF_RUNNING)
4711 /* NB: embed these numbers to get a consistent view */
4712 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
4713 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
4714 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic);
4717 * NB: Drop the softc lock in case of a page fault;
4718 * we'll accept any potential inconsisentcy in the
4719 * statistics. The alternative is to copy the data
4720 * to a local structure.
4722 return copyout(&sc->sc_stats,
4723 ifr->ifr_data, sizeof (sc->sc_stats));
4725 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
4728 error = ieee80211_ioctl(ic, cmd, data);
4729 if (error == ENETRESET) {
4730 if (IS_RUNNING(ifp) &&
4731 ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
4732 ath_init(sc); /* XXX lose error */
4735 if (error == ERESTART)
4736 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0;
4745 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS)
4747 struct ath_softc *sc = arg1;
4748 u_int slottime = ath_hal_getslottime(sc->sc_ah);
4751 error = sysctl_handle_int(oidp, &slottime, 0, req);
4752 if (error || !req->newptr)
4754 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0;
4758 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS)
4760 struct ath_softc *sc = arg1;
4761 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah);
4764 error = sysctl_handle_int(oidp, &acktimeout, 0, req);
4765 if (error || !req->newptr)
4767 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0;
4771 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS)
4773 struct ath_softc *sc = arg1;
4774 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah);
4777 error = sysctl_handle_int(oidp, &ctstimeout, 0, req);
4778 if (error || !req->newptr)
4780 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0;
4784 ath_sysctl_softled(SYSCTL_HANDLER_ARGS)
4786 struct ath_softc *sc = arg1;
4787 int softled = sc->sc_softled;
4790 error = sysctl_handle_int(oidp, &softled, 0, req);
4791 if (error || !req->newptr)
4793 softled = (softled != 0);
4794 if (softled != sc->sc_softled) {
4796 /* NB: handle any sc_ledpin change */
4797 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
4798 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
4801 sc->sc_softled = softled;
4807 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS)
4809 struct ath_softc *sc = arg1;
4810 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah);
4813 error = sysctl_handle_int(oidp, &defantenna, 0, req);
4814 if (!error && req->newptr)
4815 ath_hal_setdefantenna(sc->sc_ah, defantenna);
4820 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS)
4822 struct ath_softc *sc = arg1;
4823 u_int diversity = sc->sc_diversity;
4826 error = sysctl_handle_int(oidp, &diversity, 0, req);
4827 if (error || !req->newptr)
4829 sc->sc_diversity = diversity;
4830 return !ath_hal_setdiversity(sc->sc_ah, diversity) ? EINVAL : 0;
4834 ath_sysctl_diag(SYSCTL_HANDLER_ARGS)
4836 struct ath_softc *sc = arg1;
4840 if (!ath_hal_getdiag(sc->sc_ah, &diag))
4842 error = sysctl_handle_int(oidp, &diag, 0, req);
4843 if (error || !req->newptr)
4845 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0;
4849 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS)
4851 struct ath_softc *sc = arg1;
4852 struct ifnet *ifp = sc->sc_ifp;
4856 ath_hal_gettpscale(sc->sc_ah, &scale);
4857 error = sysctl_handle_int(oidp, &scale, 0, req);
4858 if (error || !req->newptr)
4860 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : ath_reset(ifp);
4864 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS)
4866 struct ath_softc *sc = arg1;
4867 u_int tpc = ath_hal_gettpc(sc->sc_ah);
4870 error = sysctl_handle_int(oidp, &tpc, 0, req);
4871 if (error || !req->newptr)
4873 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0;
4877 ath_sysctlattach(struct ath_softc *sc)
4879 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
4880 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
4882 ath_hal_getcountrycode(sc->sc_ah, &sc->sc_countrycode);
4883 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4884 "countrycode", CTLFLAG_RD, &sc->sc_countrycode, 0,
4885 "EEPROM country code");
4886 ath_hal_getregdomain(sc->sc_ah, &sc->sc_regdomain);
4887 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4888 "regdomain", CTLFLAG_RD, &sc->sc_regdomain, 0,
4889 "EEPROM regdomain code");
4890 sc->sc_debug = ath_debug;
4891 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4892 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
4893 "control debugging printfs");
4895 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4896 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4897 ath_sysctl_slottime, "I", "802.11 slot time (us)");
4898 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4899 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4900 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)");
4901 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4902 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4903 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)");
4904 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4905 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4906 ath_sysctl_softled, "I", "enable/disable software LED support");
4907 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4908 "ledpin", CTLFLAG_RW, &sc->sc_ledpin, 0,
4909 "GPIO pin connected to LED");
4910 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4911 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0,
4912 "setting to turn LED on");
4913 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4914 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0,
4915 "idle time for inactivity LED (ticks)");
4916 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4917 "txantenna", CTLFLAG_RW, &sc->sc_txantenna, 0,
4918 "tx antenna (0=auto)");
4919 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4920 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4921 ath_sysctl_rxantenna, "I", "default/rx antenna");
4922 if (sc->sc_hasdiversity)
4923 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4924 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4925 ath_sysctl_diversity, "I", "antenna diversity");
4926 sc->sc_txintrperiod = ATH_TXINTR_PERIOD;
4927 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4928 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0,
4929 "tx descriptor batching");
4930 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4931 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4932 ath_sysctl_diag, "I", "h/w diagnostic control");
4933 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4934 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4935 ath_sysctl_tpscale, "I", "tx power scaling");
4937 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4938 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4939 ath_sysctl_tpc, "I", "enable/disable per-packet TPC");
4943 ath_bpfattach(struct ath_softc *sc)
4945 struct ifnet *ifp = sc->sc_ifp;
4947 bpfattach2(ifp, DLT_IEEE802_11_RADIO,
4948 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
4951 * Initialize constant fields.
4952 * XXX make header lengths a multiple of 32-bits so subsequent
4953 * headers are properly aligned; this is a kludge to keep
4954 * certain applications happy.
4956 * NB: the channel is setup each time we transition to the
4957 * RUN state to avoid filling it in for each frame.
4959 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t));
4960 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
4961 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT);
4963 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t));
4964 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
4965 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT);
4969 * Announce various information on device/driver attach.
4972 ath_announce(struct ath_softc *sc)
4974 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B)
4975 struct ifnet *ifp = sc->sc_ifp;
4976 struct ath_hal *ah = sc->sc_ah;
4979 if_printf(ifp, "mac %d.%d phy %d.%d",
4980 ah->ah_macVersion, ah->ah_macRev,
4981 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
4983 * Print radio revision(s). We check the wireless modes
4984 * to avoid falsely printing revs for inoperable parts.
4985 * Dual-band radio revs are returned in the 5Ghz rev number.
4987 ath_hal_getcountrycode(ah, &cc);
4988 modes = ath_hal_getwirelessmodes(ah, cc);
4989 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) {
4990 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev)
4991 printf(" 5ghz radio %d.%d 2ghz radio %d.%d",
4992 ah->ah_analog5GhzRev >> 4,
4993 ah->ah_analog5GhzRev & 0xf,
4994 ah->ah_analog2GhzRev >> 4,
4995 ah->ah_analog2GhzRev & 0xf);
4997 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
4998 ah->ah_analog5GhzRev & 0xf);
5000 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
5001 ah->ah_analog5GhzRev & 0xf);
5005 for (i = 0; i <= WME_AC_VO; i++) {
5006 struct ath_txq *txq = sc->sc_ac2q[i];
5007 if_printf(ifp, "Use hw queue %u for %s traffic\n",
5008 txq->axq_qnum, ieee80211_wme_acnames[i]);
5010 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
5011 sc->sc_cabq->axq_qnum);
5012 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
5014 #undef HAL_MODE_DUALBAND
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