2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for the Atheros Wireless LAN controller.
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/sysctl.h>
47 #include <sys/malloc.h>
49 #include <sys/mutex.h>
50 #include <sys/kernel.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/errno.h>
54 #include <sys/callout.h>
56 #include <sys/endian.h>
57 #include <sys/kthread.h>
58 #include <sys/taskqueue.h>
60 #include <machine/bus.h>
63 #include <net/if_dl.h>
64 #include <net/if_media.h>
65 #include <net/if_types.h>
66 #include <net/if_arp.h>
67 #include <net/ethernet.h>
68 #include <net/if_llc.h>
70 #include <net80211/ieee80211_var.h>
75 #include <netinet/in.h>
76 #include <netinet/if_ether.h>
79 #include <dev/ath/if_athvar.h>
80 #include <contrib/dev/ath/ah_desc.h>
81 #include <contrib/dev/ath/ah_devid.h> /* XXX for softled */
84 #include <dev/ath/ath_tx99/ath_tx99.h>
88 * ATH_BCBUF determines the number of vap's that can transmit
89 * beacons and also (currently) the number of vap's that can
90 * have unique mac addresses/bssid. When staggering beacons
91 * 4 is probably a good max as otherwise the beacons become
92 * very closely spaced and there is limited time for cab q traffic
93 * to go out. You can burst beacons instead but that is not good
94 * for stations in power save and at some point you really want
95 * another radio (and channel).
97 * The limit on the number of mac addresses is tied to our use of
98 * the U/L bit and tracking addresses in a byte; it would be
99 * worthwhile to allow more for applications like proxy sta.
101 CTASSERT(ATH_BCBUF <= 8);
103 /* unaligned little endian access */
104 #define LE_READ_2(p) \
106 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8)))
107 #define LE_READ_4(p) \
109 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \
110 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24)))
118 static struct ieee80211vap *ath_vap_create(struct ieee80211com *,
119 const char name[IFNAMSIZ], int unit, int opmode,
120 int flags, const uint8_t bssid[IEEE80211_ADDR_LEN],
121 const uint8_t mac[IEEE80211_ADDR_LEN]);
122 static void ath_vap_delete(struct ieee80211vap *);
123 static void ath_init(void *);
124 static void ath_stop_locked(struct ifnet *);
125 static void ath_stop(struct ifnet *);
126 static void ath_start(struct ifnet *);
127 static int ath_reset(struct ifnet *);
128 static int ath_reset_vap(struct ieee80211vap *, u_long);
129 static int ath_media_change(struct ifnet *);
130 static void ath_watchdog(struct ifnet *);
131 static int ath_ioctl(struct ifnet *, u_long, caddr_t);
132 static void ath_fatal_proc(void *, int);
133 static void ath_rxorn_proc(void *, int);
134 static void ath_bmiss_vap(struct ieee80211vap *);
135 static void ath_bmiss_proc(void *, int);
136 static int ath_key_alloc(struct ieee80211vap *,
137 const struct ieee80211_key *,
138 ieee80211_keyix *, ieee80211_keyix *);
139 static int ath_key_delete(struct ieee80211vap *,
140 const struct ieee80211_key *);
141 static int ath_key_set(struct ieee80211vap *, const struct ieee80211_key *,
142 const u_int8_t mac[IEEE80211_ADDR_LEN]);
143 static void ath_key_update_begin(struct ieee80211vap *);
144 static void ath_key_update_end(struct ieee80211vap *);
145 static void ath_update_mcast(struct ifnet *);
146 static void ath_update_promisc(struct ifnet *);
147 static void ath_mode_init(struct ath_softc *);
148 static void ath_setslottime(struct ath_softc *);
149 static void ath_updateslot(struct ifnet *);
150 static int ath_beaconq_setup(struct ath_hal *);
151 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *);
152 static void ath_beacon_update(struct ieee80211vap *, int item);
153 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *);
154 static void ath_beacon_proc(void *, int);
155 static struct ath_buf *ath_beacon_generate(struct ath_softc *,
156 struct ieee80211vap *);
157 static void ath_bstuck_proc(void *, int);
158 static void ath_beacon_return(struct ath_softc *, struct ath_buf *);
159 static void ath_beacon_free(struct ath_softc *);
160 static void ath_beacon_config(struct ath_softc *, struct ieee80211vap *);
161 static void ath_descdma_cleanup(struct ath_softc *sc,
162 struct ath_descdma *, ath_bufhead *);
163 static int ath_desc_alloc(struct ath_softc *);
164 static void ath_desc_free(struct ath_softc *);
165 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *);
166 static void ath_node_free(struct ieee80211_node *);
167 static void ath_node_getsignal(const struct ieee80211_node *,
169 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *);
170 static void ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
171 int subtype, int rssi, int noise, u_int32_t rstamp);
172 static void ath_setdefantenna(struct ath_softc *, u_int);
173 static void ath_rx_proc(void *, int);
174 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int);
175 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
176 static int ath_tx_setup(struct ath_softc *, int, int);
177 static int ath_wme_update(struct ieee80211com *);
178 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
179 static void ath_tx_cleanup(struct ath_softc *);
180 static void ath_freetx(struct mbuf *);
181 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *,
182 struct ath_buf *, struct mbuf *);
183 static void ath_tx_proc_q0(void *, int);
184 static void ath_tx_proc_q0123(void *, int);
185 static void ath_tx_proc(void *, int);
186 static void ath_tx_draintxq(struct ath_softc *, struct ath_txq *);
187 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
188 static void ath_draintxq(struct ath_softc *);
189 static void ath_stoprecv(struct ath_softc *);
190 static int ath_startrecv(struct ath_softc *);
191 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
192 static void ath_scan_start(struct ieee80211com *);
193 static void ath_scan_end(struct ieee80211com *);
194 static void ath_set_channel(struct ieee80211com *);
195 static void ath_calibrate(void *);
196 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int);
197 static void ath_setup_stationkey(struct ieee80211_node *);
198 static void ath_newassoc(struct ieee80211_node *, int);
199 static int ath_setregdomain(struct ieee80211com *,
200 struct ieee80211_regdomain *, int,
201 struct ieee80211_channel []);
202 static void ath_getradiocaps(struct ieee80211com *, int *,
203 struct ieee80211_channel []);
204 static int ath_getchannels(struct ath_softc *);
205 static void ath_led_event(struct ath_softc *, int);
207 static int ath_rate_setup(struct ath_softc *, u_int mode);
208 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
210 static void ath_sysctlattach(struct ath_softc *);
211 static int ath_raw_xmit(struct ieee80211_node *,
212 struct mbuf *, const struct ieee80211_bpf_params *);
213 static void ath_bpfattach(struct ath_softc *);
214 static void ath_announce(struct ath_softc *);
216 SYSCTL_DECL(_hw_ath);
218 /* XXX validate sysctl values */
219 static int ath_calinterval = 30; /* calibrate every 30 secs */
220 SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval,
221 0, "chip calibration interval (secs)");
223 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
224 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RW, &ath_rxbuf,
225 0, "rx buffers allocated");
226 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf);
227 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
228 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RW, &ath_txbuf,
229 0, "tx buffers allocated");
230 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf);
233 static int ath_debug = 0;
234 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug,
235 0, "control debugging printfs");
236 TUNABLE_INT("hw.ath.debug", &ath_debug);
238 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
239 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */
240 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */
241 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */
242 ATH_DEBUG_RATE = 0x00000010, /* rate control */
243 ATH_DEBUG_RESET = 0x00000020, /* reset processing */
244 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */
245 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */
246 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */
247 ATH_DEBUG_INTR = 0x00001000, /* ISR */
248 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */
249 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */
250 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */
251 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */
252 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */
253 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */
254 ATH_DEBUG_NODE = 0x00080000, /* node management */
255 ATH_DEBUG_LED = 0x00100000, /* led management */
256 ATH_DEBUG_FF = 0x00200000, /* fast frames */
257 ATH_DEBUG_DFS = 0x00400000, /* DFS processing */
258 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */
259 ATH_DEBUG_ANY = 0xffffffff
261 #define IFF_DUMPPKTS(sc, m) \
262 ((sc->sc_debug & (m)) || \
263 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
264 #define DPRINTF(sc, m, fmt, ...) do { \
265 if (sc->sc_debug & (m)) \
266 printf(fmt, __VA_ARGS__); \
268 #define KEYPRINTF(sc, ix, hk, mac) do { \
269 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \
270 ath_keyprint(sc, __func__, ix, hk, mac); \
272 static void ath_printrxbuf(const struct ath_buf *bf, u_int ix, int);
273 static void ath_printtxbuf(const struct ath_buf *bf, u_int qnum, u_int ix, int done);
275 #define IFF_DUMPPKTS(sc, m) \
276 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
277 #define DPRINTF(sc, m, fmt, ...) do { \
280 #define KEYPRINTF(sc, k, ix, mac) do { \
285 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
288 ath_attach(u_int16_t devid, struct ath_softc *sc)
291 struct ieee80211com *ic;
292 struct ath_hal *ah = NULL;
296 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
298 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
300 device_printf(sc->sc_dev, "can not if_alloc()\n");
306 /* set these up early for if_printf use */
307 if_initname(ifp, device_get_name(sc->sc_dev),
308 device_get_unit(sc->sc_dev));
310 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status);
312 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
317 if (ah->ah_abi != HAL_ABI_VERSION) {
318 if_printf(ifp, "HAL ABI mismatch detected "
319 "(HAL:0x%x != driver:0x%x)\n",
320 ah->ah_abi, HAL_ABI_VERSION);
325 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
328 * Check if the MAC has multi-rate retry support.
329 * We do this by trying to setup a fake extended
330 * descriptor. MAC's that don't have support will
331 * return false w/o doing anything. MAC's that do
332 * support it will return true w/o doing anything.
334 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
337 * Check if the device has hardware counters for PHY
338 * errors. If so we need to enable the MIB interrupt
339 * so we can act on stat triggers.
341 if (ath_hal_hwphycounters(ah))
345 * Get the hardware key cache size.
347 sc->sc_keymax = ath_hal_keycachesize(ah);
348 if (sc->sc_keymax > ATH_KEYMAX) {
349 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
350 ATH_KEYMAX, sc->sc_keymax);
351 sc->sc_keymax = ATH_KEYMAX;
354 * Reset the key cache since some parts do not
355 * reset the contents on initial power up.
357 for (i = 0; i < sc->sc_keymax; i++)
358 ath_hal_keyreset(ah, i);
361 * Collect the default channel list.
363 error = ath_getchannels(sc);
368 * Setup rate tables for all potential media types.
370 ath_rate_setup(sc, IEEE80211_MODE_11A);
371 ath_rate_setup(sc, IEEE80211_MODE_11B);
372 ath_rate_setup(sc, IEEE80211_MODE_11G);
373 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
374 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
375 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A);
376 ath_rate_setup(sc, IEEE80211_MODE_11NA);
377 ath_rate_setup(sc, IEEE80211_MODE_11NG);
378 ath_rate_setup(sc, IEEE80211_MODE_HALF);
379 ath_rate_setup(sc, IEEE80211_MODE_QUARTER);
381 /* NB: setup here so ath_rate_update is happy */
382 ath_setcurmode(sc, IEEE80211_MODE_11A);
385 * Allocate tx+rx descriptors and populate the lists.
387 error = ath_desc_alloc(sc);
389 if_printf(ifp, "failed to allocate descriptors: %d\n", error);
392 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE);
394 ATH_TXBUF_LOCK_INIT(sc);
396 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT,
397 taskqueue_thread_enqueue, &sc->sc_tq);
398 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET,
399 "%s taskq", ifp->if_xname);
401 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc);
402 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc);
403 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
404 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc);
407 * Allocate hardware transmit queues: one queue for
408 * beacon frames and one data queue for each QoS
409 * priority. Note that the hal handles reseting
410 * these queues at the needed time.
414 sc->sc_bhalq = ath_beaconq_setup(ah);
415 if (sc->sc_bhalq == (u_int) -1) {
416 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
420 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
421 if (sc->sc_cabq == NULL) {
422 if_printf(ifp, "unable to setup CAB xmit queue!\n");
426 /* NB: insure BK queue is the lowest priority h/w queue */
427 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
428 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
429 ieee80211_wme_acnames[WME_AC_BK]);
433 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
434 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
435 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
437 * Not enough hardware tx queues to properly do WME;
438 * just punt and assign them all to the same h/w queue.
439 * We could do a better job of this if, for example,
440 * we allocate queues when we switch from station to
443 if (sc->sc_ac2q[WME_AC_VI] != NULL)
444 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
445 if (sc->sc_ac2q[WME_AC_BE] != NULL)
446 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
447 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
448 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
449 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
453 * Special case certain configurations. Note the
454 * CAB queue is handled by these specially so don't
455 * include them when checking the txq setup mask.
457 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
459 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
462 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
465 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
470 * Setup rate control. Some rate control modules
471 * call back to change the anntena state so expose
472 * the necessary entry points.
473 * XXX maybe belongs in struct ath_ratectrl?
475 sc->sc_setdefantenna = ath_setdefantenna;
476 sc->sc_rc = ath_rate_attach(sc);
477 if (sc->sc_rc == NULL) {
484 sc->sc_ledon = 0; /* low true */
485 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
486 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE);
488 * Auto-enable soft led processing for IBM cards and for
489 * 5211 minipci cards. Users can also manually enable/disable
490 * support with a sysctl.
492 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
493 if (sc->sc_softled) {
494 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin);
495 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
499 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
500 ifp->if_start = ath_start;
501 ifp->if_watchdog = ath_watchdog;
502 ifp->if_ioctl = ath_ioctl;
503 ifp->if_init = ath_init;
504 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
505 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
506 IFQ_SET_READY(&ifp->if_snd);
509 /* XXX not right but it's not used anywhere important */
510 ic->ic_phytype = IEEE80211_T_OFDM;
511 ic->ic_opmode = IEEE80211_M_STA;
513 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
514 | IEEE80211_C_HOSTAP /* hostap mode */
515 | IEEE80211_C_MONITOR /* monitor mode */
516 | IEEE80211_C_AHDEMO /* adhoc demo mode */
517 | IEEE80211_C_WDS /* 4-address traffic works */
518 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
519 | IEEE80211_C_SHSLOT /* short slot time supported */
520 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
521 | IEEE80211_C_BGSCAN /* capable of bg scanning */
522 | IEEE80211_C_TXFRAG /* handle tx frags */
525 * Query the hal to figure out h/w crypto support.
527 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
528 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP;
529 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
530 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB;
531 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
532 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM;
533 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
534 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP;
535 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
536 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP;
538 * Check if h/w does the MIC and/or whether the
539 * separate key cache entries are required to
540 * handle both tx+rx MIC keys.
542 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
543 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
545 * If the h/w supports storing tx+rx MIC keys
546 * in one cache slot automatically enable use.
548 if (ath_hal_hastkipsplit(ah) ||
549 !ath_hal_settkipsplit(ah, AH_FALSE))
552 * If the h/w can do TKIP MIC together with WME then
553 * we use it; otherwise we force the MIC to be done
554 * in software by the net80211 layer.
556 if (ath_hal_haswmetkipmic(ah))
557 sc->sc_wmetkipmic = 1;
559 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
560 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
562 * Mark key cache slots associated with global keys
563 * as in use. If we knew TKIP was not to be used we
564 * could leave the +32, +64, and +32+64 slots free.
566 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
567 setbit(sc->sc_keymap, i);
568 setbit(sc->sc_keymap, i+64);
569 if (sc->sc_splitmic) {
570 setbit(sc->sc_keymap, i+32);
571 setbit(sc->sc_keymap, i+32+64);
575 * TPC support can be done either with a global cap or
576 * per-packet support. The latter is not available on
577 * all parts. We're a bit pedantic here as all parts
578 * support a global cap.
580 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
581 ic->ic_caps |= IEEE80211_C_TXPMGT;
584 * Mark WME capability only if we have sufficient
585 * hardware queues to do proper priority scheduling.
587 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
588 ic->ic_caps |= IEEE80211_C_WME;
590 * Check for misc other capabilities.
592 if (ath_hal_hasbursting(ah))
593 ic->ic_caps |= IEEE80211_C_BURST;
594 sc->sc_hasbmask = ath_hal_hasbssidmask(ah);
595 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah);
596 if (ath_hal_hasfastframes(ah))
597 ic->ic_caps |= IEEE80211_C_FF;
598 if (ath_hal_getwirelessmodes(ah, ic->ic_regdomain.country) & (HAL_MODE_108G|HAL_MODE_TURBO))
599 ic->ic_caps |= IEEE80211_C_TURBOP;
602 * Indicate we need the 802.11 header padded to a
603 * 32-bit boundary for 4-address and QoS frames.
605 ic->ic_flags |= IEEE80211_F_DATAPAD;
608 * Query the hal about antenna support.
610 sc->sc_defant = ath_hal_getdefantenna(ah);
613 * Not all chips have the VEOL support we want to
614 * use with IBSS beacons; check here for it.
616 sc->sc_hasveol = ath_hal_hasveol(ah);
618 /* get mac address from hardware */
619 ath_hal_getmac(ah, ic->ic_myaddr);
621 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask);
623 /* NB: used to size node table key mapping array */
624 ic->ic_max_keyix = sc->sc_keymax;
625 /* call MI attach routine. */
626 ieee80211_ifattach(ic);
627 ic->ic_setregdomain = ath_setregdomain;
628 ic->ic_getradiocaps = ath_getradiocaps;
629 sc->sc_opmode = HAL_M_STA;
631 /* override default methods */
632 ic->ic_newassoc = ath_newassoc;
633 ic->ic_updateslot = ath_updateslot;
634 ic->ic_wme.wme_update = ath_wme_update;
635 ic->ic_vap_create = ath_vap_create;
636 ic->ic_vap_delete = ath_vap_delete;
637 ic->ic_raw_xmit = ath_raw_xmit;
638 ic->ic_update_mcast = ath_update_mcast;
639 ic->ic_update_promisc = ath_update_promisc;
640 ic->ic_node_alloc = ath_node_alloc;
641 sc->sc_node_free = ic->ic_node_free;
642 ic->ic_node_free = ath_node_free;
643 ic->ic_node_getsignal = ath_node_getsignal;
644 ic->ic_scan_start = ath_scan_start;
645 ic->ic_scan_end = ath_scan_end;
646 ic->ic_set_channel = ath_set_channel;
650 * Setup dynamic sysctl's now that country code and
651 * regdomain are available from the hal.
653 ath_sysctlattach(sc);
656 ieee80211_announce(ic);
672 ath_detach(struct ath_softc *sc)
674 struct ifnet *ifp = sc->sc_ifp;
676 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
677 __func__, ifp->if_flags);
682 * NB: the order of these is important:
683 * o call the 802.11 layer before detaching the hal to
684 * insure callbacks into the driver to delete global
685 * key cache entries can be handled
686 * o reclaim the tx queue data structures after calling
687 * the 802.11 layer as we'll get called back to reclaim
688 * node state and potentially want to use them
689 * o to cleanup the tx queues the hal is called, so detach
691 * Other than that, it's straightforward...
693 ieee80211_ifdetach(ifp->if_l2com);
695 if (sc->sc_tx99 != NULL)
696 sc->sc_tx99->detach(sc->sc_tx99);
698 taskqueue_free(sc->sc_tq);
699 ath_rate_detach(sc->sc_rc);
702 ath_hal_detach(sc->sc_ah);
709 * MAC address handling for multiple BSS on the same radio.
710 * The first vap uses the MAC address from the EEPROM. For
711 * subsequent vap's we set the U/L bit (bit 1) in the MAC
712 * address and use the next six bits as an index.
715 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone)
719 if (clone && sc->sc_hasbmask) {
720 /* NB: we only do this if h/w supports multiple bssid */
721 for (i = 0; i < 8; i++)
722 if ((sc->sc_bssidmask & (1<<i)) == 0)
725 mac[0] |= (i << 2)|0x2;
728 sc->sc_bssidmask |= 1<<i;
729 sc->sc_hwbssidmask[0] &= ~mac[0];
735 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN])
740 if (i != 0 || --sc->sc_nbssid0 == 0) {
741 sc->sc_bssidmask &= ~(1<<i);
742 /* recalculate bssid mask from remaining addresses */
744 for (i = 1; i < 8; i++)
745 if (sc->sc_bssidmask & (1<<i))
746 mask &= ~((i<<2)|0x2);
747 sc->sc_hwbssidmask[0] |= mask;
752 * Assign a beacon xmit slot. We try to space out
753 * assignments so when beacons are staggered the
754 * traffic coming out of the cab q has maximal time
755 * to go out before the next beacon is scheduled.
758 assign_bslot(struct ath_softc *sc)
763 for (slot = 0; slot < ATH_BCBUF; slot++)
764 if (sc->sc_bslot[slot] == NULL) {
765 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL &&
766 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL)
769 /* NB: keep looking for a double slot */
774 static struct ieee80211vap *
775 ath_vap_create(struct ieee80211com *ic,
776 const char name[IFNAMSIZ], int unit, int opmode, int flags,
777 const uint8_t bssid[IEEE80211_ADDR_LEN],
778 const uint8_t mac0[IEEE80211_ADDR_LEN])
780 struct ath_softc *sc = ic->ic_ifp->if_softc;
782 struct ieee80211vap *vap;
783 uint8_t mac[IEEE80211_ADDR_LEN];
784 int ic_opmode, needbeacon, error;
786 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap),
787 M_80211_VAP, M_WAITOK | M_ZERO);
789 IEEE80211_ADDR_COPY(mac, mac0);
793 case IEEE80211_M_STA:
794 if (sc->sc_nstavaps != 0) { /* XXX only 1 sta for now */
795 device_printf(sc->sc_dev, "only 1 sta vap supported\n");
800 * When there are multiple vaps we must fall
801 * back to s/w beacon miss handling.
803 flags |= IEEE80211_CLONE_NOBEACONS;
805 if (flags & IEEE80211_CLONE_NOBEACONS) {
807 ic_opmode = IEEE80211_M_HOSTAP;
811 case IEEE80211_M_IBSS:
812 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */
813 device_printf(sc->sc_dev,
814 "only 1 ibss vap supported\n");
820 case IEEE80211_M_AHDEMO:
822 case IEEE80211_M_MONITOR:
823 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) {
824 /* XXX not right for monitor mode */
825 ic_opmode = ic->ic_opmode;
829 case IEEE80211_M_HOSTAP:
832 case IEEE80211_M_WDS:
833 if (sc->sc_nvaps && ic->ic_opmode == IEEE80211_M_STA) {
834 device_printf(sc->sc_dev,
835 "wds not supported in sta mode\n");
838 if (opmode == IEEE80211_M_WDS) {
840 * Silently remove any request for a unique
841 * bssid; WDS vap's always share the local
844 flags &= ~IEEE80211_CLONE_BSSID;
846 ic_opmode = IEEE80211_M_HOSTAP;
849 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
853 * Check that a beacon buffer is available; the code below assumes it.
855 if (needbeacon & STAILQ_EMPTY(&sc->sc_bbuf)) {
856 device_printf(sc->sc_dev, "no beacon buffer available\n");
861 if (opmode == IEEE80211_M_HOSTAP) {
862 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID);
863 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
867 /* XXX can't hold mutex across if_alloc */
869 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags,
873 device_printf(sc->sc_dev, "%s: error %d creating vap\n",
878 /* h/w crypto support */
879 vap->iv_key_alloc = ath_key_alloc;
880 vap->iv_key_delete = ath_key_delete;
881 vap->iv_key_set = ath_key_set;
882 vap->iv_key_update_begin = ath_key_update_begin;
883 vap->iv_key_update_end = ath_key_update_end;
885 /* override various methods */
886 avp->av_recv_mgmt = vap->iv_recv_mgmt;
887 vap->iv_recv_mgmt = ath_recv_mgmt;
888 vap->iv_reset = ath_reset_vap;
889 vap->iv_update_beacon = ath_beacon_update;
890 avp->av_newstate = vap->iv_newstate;
891 vap->iv_newstate = ath_newstate;
892 avp->av_bmiss = vap->iv_bmiss;
893 vap->iv_bmiss = ath_bmiss_vap;
898 * Allocate beacon state and setup the q for buffered
899 * multicast frames. We know a beacon buffer is
900 * available because we checked above.
902 avp->av_bcbuf = STAILQ_FIRST(&sc->sc_bbuf);
903 STAILQ_REMOVE_HEAD(&sc->sc_bbuf, bf_list);
904 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) {
906 * Assign the vap to a beacon xmit slot. As above
907 * this cannot fail to find a free one.
909 avp->av_bslot = assign_bslot(sc);
910 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL,
911 ("beacon slot %u not empty", avp->av_bslot));
912 sc->sc_bslot[avp->av_bslot] = vap;
915 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) {
917 * Multple vaps are to transmit beacons and we
918 * have h/w support for TSF adjusting; enable
919 * use of staggered beacons.
921 sc->sc_stagbeacons = 1;
923 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ);
926 ic->ic_opmode = ic_opmode;
927 if (opmode != IEEE80211_M_WDS) {
929 if (opmode == IEEE80211_M_STA)
933 case IEEE80211_M_IBSS:
934 sc->sc_opmode = HAL_M_IBSS;
936 case IEEE80211_M_STA:
937 sc->sc_opmode = HAL_M_STA;
939 case IEEE80211_M_AHDEMO:
940 case IEEE80211_M_HOSTAP:
941 sc->sc_opmode = HAL_M_HOSTAP;
943 case IEEE80211_M_MONITOR:
944 sc->sc_opmode = HAL_M_MONITOR;
947 /* XXX should not happen */
950 if (sc->sc_hastsfadd) {
952 * Configure whether or not TSF adjust should be done.
954 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons);
959 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status);
962 reclaim_address(sc, mac);
963 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
965 free(avp, M_80211_VAP);
971 ath_vap_delete(struct ieee80211vap *vap)
973 struct ieee80211com *ic = vap->iv_ic;
974 struct ifnet *ifp = ic->ic_ifp;
975 struct ath_softc *sc = ifp->if_softc;
976 struct ath_hal *ah = sc->sc_ah;
977 struct ath_vap *avp = ATH_VAP(vap);
979 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
981 * Quiesce the hardware while we remove the vap. In
982 * particular we need to reclaim all references to
983 * the vap state by any frames pending on the tx queues.
985 ath_hal_intrset(ah, 0); /* disable interrupts */
986 ath_draintxq(sc); /* stop xmit side */
987 ath_stoprecv(sc); /* stop recv side */
990 ieee80211_vap_detach(vap);
993 * Reclaim beacon state. Note this must be done before
994 * the vap instance is reclaimed as we may have a reference
995 * to it in the buffer for the beacon frame.
997 if (avp->av_bcbuf != NULL) {
998 if (avp->av_bslot != -1) {
999 sc->sc_bslot[avp->av_bslot] = NULL;
1002 ath_beacon_return(sc, avp->av_bcbuf);
1003 avp->av_bcbuf = NULL;
1004 if (sc->sc_nbcnvaps == 0) {
1005 sc->sc_stagbeacons = 0;
1006 if (sc->sc_hastsfadd)
1007 ath_hal_settsfadjust(sc->sc_ah, 0);
1010 * Reclaim any pending mcast frames for the vap.
1012 ath_tx_draintxq(sc, &avp->av_mcastq);
1013 ATH_TXQ_LOCK_DESTROY(&avp->av_mcastq);
1016 * Update bookkeeping.
1018 if (vap->iv_opmode == IEEE80211_M_STA) {
1020 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss)
1022 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP) {
1023 reclaim_address(sc, vap->iv_myaddr);
1024 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask);
1026 if (vap->iv_opmode != IEEE80211_M_WDS)
1029 free(avp, M_80211_VAP);
1031 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1033 * Restart rx+tx machines if still running (RUNNING will
1034 * be reset if we just destroyed the last vap).
1036 if (ath_startrecv(sc) != 0)
1037 if_printf(ifp, "%s: unable to restart recv logic\n",
1040 ath_beacon_config(sc, NULL);
1041 ath_hal_intrset(ah, sc->sc_imask);
1046 ath_suspend(struct ath_softc *sc)
1048 struct ifnet *ifp = sc->sc_ifp;
1050 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1051 __func__, ifp->if_flags);
1057 ath_resume(struct ath_softc *sc)
1059 struct ifnet *ifp = sc->sc_ifp;
1061 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1062 __func__, ifp->if_flags);
1064 if (ifp->if_flags & IFF_UP) {
1066 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1069 if (sc->sc_softled) {
1070 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
1071 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
1076 ath_shutdown(struct ath_softc *sc)
1078 struct ifnet *ifp = sc->sc_ifp;
1080 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1081 __func__, ifp->if_flags);
1087 * Interrupt handler. Most of the actual processing is deferred.
1092 struct ath_softc *sc = arg;
1093 struct ifnet *ifp = sc->sc_ifp;
1094 struct ath_hal *ah = sc->sc_ah;
1097 if (sc->sc_invalid) {
1099 * The hardware is not ready/present, don't touch anything.
1100 * Note this can happen early on if the IRQ is shared.
1102 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
1105 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */
1107 if ((ifp->if_flags & IFF_UP) == 0 ||
1108 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1111 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
1112 __func__, ifp->if_flags);
1113 ath_hal_getisr(ah, &status); /* clear ISR */
1114 ath_hal_intrset(ah, 0); /* disable further intr's */
1118 * Figure out the reason(s) for the interrupt. Note
1119 * that the hal returns a pseudo-ISR that may include
1120 * bits we haven't explicitly enabled so we mask the
1121 * value to insure we only process bits we requested.
1123 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
1124 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
1125 status &= sc->sc_imask; /* discard unasked for bits */
1126 if (status & HAL_INT_FATAL) {
1127 sc->sc_stats.ast_hardware++;
1128 ath_hal_intrset(ah, 0); /* disable intr's until reset */
1129 ath_fatal_proc(sc, 0);
1130 } else if (status & HAL_INT_RXORN) {
1131 sc->sc_stats.ast_rxorn++;
1132 ath_hal_intrset(ah, 0); /* disable intr's until reset */
1133 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxorntask);
1135 if (status & HAL_INT_SWBA) {
1137 * Software beacon alert--time to send a beacon.
1138 * Handle beacon transmission directly; deferring
1139 * this is too slow to meet timing constraints
1142 ath_beacon_proc(sc, 0);
1144 if (status & HAL_INT_RXEOL) {
1146 * NB: the hardware should re-read the link when
1147 * RXE bit is written, but it doesn't work at
1148 * least on older hardware revs.
1150 sc->sc_stats.ast_rxeol++;
1151 sc->sc_rxlink = NULL;
1153 if (status & HAL_INT_TXURN) {
1154 sc->sc_stats.ast_txurn++;
1155 /* bump tx trigger level */
1156 ath_hal_updatetxtriglevel(ah, AH_TRUE);
1158 if (status & HAL_INT_RX)
1159 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1160 if (status & HAL_INT_TX)
1161 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
1162 if (status & HAL_INT_BMISS) {
1163 sc->sc_stats.ast_bmiss++;
1164 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
1166 if (status & HAL_INT_MIB) {
1167 sc->sc_stats.ast_mib++;
1169 * Disable interrupts until we service the MIB
1170 * interrupt; otherwise it will continue to fire.
1172 ath_hal_intrset(ah, 0);
1174 * Let the hal handle the event. We assume it will
1175 * clear whatever condition caused the interrupt.
1177 ath_hal_mibevent(ah, &sc->sc_halstats);
1178 ath_hal_intrset(ah, sc->sc_imask);
1184 ath_fatal_proc(void *arg, int pending)
1186 struct ath_softc *sc = arg;
1187 struct ifnet *ifp = sc->sc_ifp;
1192 if_printf(ifp, "hardware error; resetting\n");
1194 * Fatal errors are unrecoverable. Typically these
1195 * are caused by DMA errors. Collect h/w state from
1196 * the hal so we can diagnose what's going on.
1198 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) {
1199 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len));
1201 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n",
1202 state[0], state[1] , state[2], state[3],
1203 state[4], state[5]);
1209 ath_rxorn_proc(void *arg, int pending)
1211 struct ath_softc *sc = arg;
1212 struct ifnet *ifp = sc->sc_ifp;
1214 if_printf(ifp, "rx FIFO overrun; resetting\n");
1219 ath_bmiss_vap(struct ieee80211vap *vap)
1221 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
1222 u_int64_t lastrx = sc->sc_lastrx;
1223 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
1224 u_int bmisstimeout =
1225 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024;
1227 DPRINTF(sc, ATH_DEBUG_BEACON,
1228 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
1229 __func__, (unsigned long long) tsf,
1230 (unsigned long long)(tsf - lastrx),
1231 (unsigned long long) lastrx, bmisstimeout);
1233 * Workaround phantom bmiss interrupts by sanity-checking
1234 * the time of our last rx'd frame. If it is within the
1235 * beacon miss interval then ignore the interrupt. If it's
1236 * truly a bmiss we'll get another interrupt soon and that'll
1237 * be dispatched up for processing.
1239 if (tsf - lastrx > bmisstimeout)
1240 ATH_VAP(vap)->av_bmiss(vap);
1242 sc->sc_stats.ast_bmiss_phantom++;
1246 ath_bmiss_proc(void *arg, int pending)
1248 struct ath_softc *sc = arg;
1249 struct ifnet *ifp = sc->sc_ifp;
1251 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
1252 ieee80211_beacon_miss(ifp->if_l2com);
1256 * Convert net80211 channel to a HAL channel with the flags
1257 * constrained to reflect the current operating mode and
1258 * the frequency possibly mapped for GSM channels.
1261 ath_mapchan(HAL_CHANNEL *hc, const struct ieee80211_channel *chan)
1263 #define N(a) (sizeof(a) / sizeof(a[0]))
1264 static const u_int modeflags[IEEE80211_MODE_MAX] = {
1265 0, /* IEEE80211_MODE_AUTO */
1266 CHANNEL_A, /* IEEE80211_MODE_11A */
1267 CHANNEL_B, /* IEEE80211_MODE_11B */
1268 CHANNEL_PUREG, /* IEEE80211_MODE_11G */
1269 0, /* IEEE80211_MODE_FH */
1270 CHANNEL_108A, /* IEEE80211_MODE_TURBO_A */
1271 CHANNEL_108G, /* IEEE80211_MODE_TURBO_G */
1272 CHANNEL_ST, /* IEEE80211_MODE_STURBO_A */
1273 CHANNEL_A, /* IEEE80211_MODE_11NA */
1274 CHANNEL_PUREG, /* IEEE80211_MODE_11NG */
1276 enum ieee80211_phymode mode = ieee80211_chan2mode(chan);
1278 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode));
1279 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode));
1280 hc->channelFlags = modeflags[mode];
1281 if (IEEE80211_IS_CHAN_HALF(chan))
1282 hc->channelFlags |= CHANNEL_HALF;
1283 if (IEEE80211_IS_CHAN_QUARTER(chan))
1284 hc->channelFlags |= CHANNEL_QUARTER;
1285 if (IEEE80211_IS_CHAN_HT20(chan))
1286 hc->channelFlags |= CHANNEL_HT20;
1287 if (IEEE80211_IS_CHAN_HT40D(chan))
1288 hc->channelFlags |= CHANNEL_HT40MINUS;
1289 if (IEEE80211_IS_CHAN_HT40U(chan))
1290 hc->channelFlags |= CHANNEL_HT40PLUS;
1292 hc->channel = IEEE80211_IS_CHAN_GSM(chan) ?
1293 2422 + (922 - chan->ic_freq) : chan->ic_freq;
1298 * Handle TKIP MIC setup to deal hardware that doesn't do MIC
1299 * calcs together with WME. If necessary disable the crypto
1300 * hardware and mark the 802.11 state so keys will be setup
1301 * with the MIC work done in software.
1304 ath_settkipmic(struct ath_softc *sc)
1306 struct ifnet *ifp = sc->sc_ifp;
1307 struct ieee80211com *ic = ifp->if_l2com;
1309 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) {
1310 if (ic->ic_flags & IEEE80211_F_WME) {
1311 ath_hal_settkipmic(sc->sc_ah, AH_FALSE);
1312 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC;
1314 ath_hal_settkipmic(sc->sc_ah, AH_TRUE);
1315 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
1323 struct ath_softc *sc = (struct ath_softc *) arg;
1324 struct ifnet *ifp = sc->sc_ifp;
1325 struct ieee80211com *ic = ifp->if_l2com;
1326 struct ath_hal *ah = sc->sc_ah;
1329 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
1330 __func__, ifp->if_flags);
1334 * Stop anything previously setup. This is safe
1335 * whether this is the first time through or not.
1337 ath_stop_locked(ifp);
1340 * The basic interface to setting the hardware in a good
1341 * state is ``reset''. On return the hardware is known to
1342 * be powered up and with interrupts disabled. This must
1343 * be followed by initialization of the appropriate bits
1344 * and then setup of the interrupt mask.
1346 ath_mapchan(&sc->sc_curchan, ic->ic_curchan);
1348 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_FALSE, &status)) {
1349 if_printf(ifp, "unable to reset hardware; hal status %u\n",
1354 ath_chan_change(sc, ic->ic_curchan);
1357 * Likewise this is set during reset so update
1358 * state cached in the driver.
1360 sc->sc_diversity = ath_hal_getdiversity(ah);
1361 sc->sc_calinterval = 1;
1362 sc->sc_caltries = 0;
1365 * Setup the hardware after reset: the key cache
1366 * is filled as needed and the receive engine is
1367 * set going. Frame transmit is handled entirely
1368 * in the frame output path; there's nothing to do
1369 * here except setup the interrupt mask.
1371 if (ath_startrecv(sc) != 0) {
1372 if_printf(ifp, "unable to start recv logic\n");
1378 * Enable interrupts.
1380 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1381 | HAL_INT_RXEOL | HAL_INT_RXORN
1382 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1384 * Enable MIB interrupts when there are hardware phy counters.
1385 * Note we only do this (at the moment) for station mode.
1387 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
1388 sc->sc_imask |= HAL_INT_MIB;
1390 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1391 ath_hal_intrset(ah, sc->sc_imask);
1395 #ifdef ATH_TX99_DIAG
1396 if (sc->sc_tx99 != NULL)
1397 sc->sc_tx99->start(sc->sc_tx99);
1400 ieee80211_start_all(ic); /* start all vap's */
1404 ath_stop_locked(struct ifnet *ifp)
1406 struct ath_softc *sc = ifp->if_softc;
1407 struct ath_hal *ah = sc->sc_ah;
1409 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
1410 __func__, sc->sc_invalid, ifp->if_flags);
1412 ATH_LOCK_ASSERT(sc);
1413 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1415 * Shutdown the hardware and driver:
1416 * reset 802.11 state machine
1418 * disable interrupts
1419 * turn off the radio
1420 * clear transmit machinery
1421 * clear receive machinery
1422 * drain and release tx queues
1423 * reclaim beacon resources
1424 * power down hardware
1426 * Note that some of this work is not possible if the
1427 * hardware is gone (invalid).
1429 #ifdef ATH_TX99_DIAG
1430 if (sc->sc_tx99 != NULL)
1431 sc->sc_tx99->stop(sc->sc_tx99);
1433 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1435 if (!sc->sc_invalid) {
1436 if (sc->sc_softled) {
1437 callout_stop(&sc->sc_ledtimer);
1438 ath_hal_gpioset(ah, sc->sc_ledpin,
1440 sc->sc_blinking = 0;
1442 ath_hal_intrset(ah, 0);
1445 if (!sc->sc_invalid) {
1447 ath_hal_phydisable(ah);
1449 sc->sc_rxlink = NULL;
1450 ath_beacon_free(sc); /* XXX not needed */
1455 ath_stop(struct ifnet *ifp)
1457 struct ath_softc *sc = ifp->if_softc;
1460 ath_stop_locked(ifp);
1461 if (!sc->sc_invalid) {
1463 * Set the chip in full sleep mode. Note that we are
1464 * careful to do this only when bringing the interface
1465 * completely to a stop. When the chip is in this state
1466 * it must be carefully woken up or references to
1467 * registers in the PCI clock domain may freeze the bus
1468 * (and system). This varies by chip and is mostly an
1469 * issue with newer parts that go to sleep more quickly.
1471 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP);
1477 * Reset the hardware w/o losing operational state. This is
1478 * basically a more efficient way of doing ath_stop, ath_init,
1479 * followed by state transitions to the current 802.11
1480 * operational state. Used to recover from various errors and
1481 * to reset or reload hardware state.
1484 ath_reset(struct ifnet *ifp)
1486 struct ath_softc *sc = ifp->if_softc;
1487 struct ieee80211com *ic = ifp->if_l2com;
1488 struct ath_hal *ah = sc->sc_ah;
1492 * Convert to a HAL channel description with the flags
1493 * constrained to reflect the current operating mode.
1495 ath_mapchan(&sc->sc_curchan, ic->ic_curchan);
1497 ath_hal_intrset(ah, 0); /* disable interrupts */
1498 ath_draintxq(sc); /* stop xmit side */
1499 ath_stoprecv(sc); /* stop recv side */
1500 ath_settkipmic(sc); /* configure TKIP MIC handling */
1501 /* NB: indicate channel change so we do a full reset */
1502 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_TRUE, &status))
1503 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
1505 sc->sc_diversity = ath_hal_getdiversity(ah);
1506 sc->sc_calinterval = 1;
1507 sc->sc_caltries = 0;
1508 if (ath_startrecv(sc) != 0) /* restart recv */
1509 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
1511 * We may be doing a reset in response to an ioctl
1512 * that changes the channel so update any state that
1513 * might change as a result.
1515 ath_chan_change(sc, ic->ic_curchan);
1517 ath_beacon_config(sc, NULL); /* restart beacons */
1518 ath_hal_intrset(ah, sc->sc_imask);
1520 ath_start(ifp); /* restart xmit */
1525 ath_reset_vap(struct ieee80211vap *vap, u_long cmd)
1527 return ath_reset(vap->iv_ic->ic_ifp);
1531 ath_ff_always(struct ath_txq *txq, struct ath_buf *bf)
1538 ath_ff_ageflushtestdone(struct ath_txq *txq, struct ath_buf *bf)
1540 return (txq->axq_curage - bf->bf_age) < ATH_FF_STAGEMAX;
1545 * Flush FF staging queue.
1548 ath_ff_stageq_flush(struct ath_softc *sc, struct ath_txq *txq,
1549 int (*ath_ff_flushdonetest)(struct ath_txq *txq, struct ath_buf *bf))
1552 struct ieee80211_node *ni;
1558 * Go from the back (oldest) to front so we can
1559 * stop early based on the age of the entry.
1561 bf = TAILQ_LAST(&txq->axq_stageq, axq_headtype);
1562 if (bf == NULL || ath_ff_flushdonetest(txq, bf)) {
1563 ATH_TXQ_UNLOCK(txq);
1568 pri = M_WME_GETAC(bf->bf_m);
1569 KASSERT(ATH_NODE(ni)->an_ff_buf[pri],
1570 ("no bf on staging queue %p", bf));
1571 ATH_NODE(ni)->an_ff_buf[pri] = NULL;
1572 TAILQ_REMOVE(&txq->axq_stageq, bf, bf_stagelist);
1574 ATH_TXQ_UNLOCK(txq);
1576 DPRINTF(sc, ATH_DEBUG_FF, "%s: flush frame, age %u\n",
1577 __func__, bf->bf_age);
1579 sc->sc_stats.ast_ff_flush++;
1581 /* encap and xmit */
1582 bf->bf_m = ieee80211_encap(ni, bf->bf_m);
1583 if (bf->bf_m == NULL) {
1584 DPRINTF(sc, ATH_DEBUG_XMIT | ATH_DEBUG_FF,
1585 "%s: discard, encapsulation failure\n",
1587 sc->sc_stats.ast_tx_encap++;
1590 pktlen = bf->bf_m->m_pkthdr.len; /* NB: don't reference below */
1591 if (ath_tx_start(sc, ni, bf, bf->bf_m) == 0) {
1599 ieee80211_free_node(ni);
1601 if (bf->bf_m != NULL) {
1607 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1608 ATH_TXBUF_UNLOCK(sc);
1612 static __inline u_int32_t
1613 ath_ff_approx_txtime(struct ath_softc *sc, struct ath_node *an, struct mbuf *m)
1615 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
1620 * Approximate the frame length to be transmitted. A swag to add
1621 * the following maximal values to the skb payload:
1622 * - 32: 802.11 encap + CRC
1623 * - 24: encryption overhead (if wep bit)
1624 * - 4 + 6: fast-frame header and padding
1625 * - 16: 2 LLC FF tunnel headers
1626 * - 14: 1 802.3 FF tunnel header (skb already accounts for 2nd)
1628 framelen = m->m_pkthdr.len + 32 + 4 + 6 + 16 + 14;
1629 if (ic->ic_flags & IEEE80211_F_PRIVACY)
1631 bf = an->an_ff_buf[M_WME_GETAC(m)];
1633 framelen += bf->bf_m->m_pkthdr.len;
1634 return ath_hal_computetxtime(sc->sc_ah, sc->sc_currates, framelen,
1635 sc->sc_lastdatarix, AH_FALSE);
1639 * Determine if a data frame may be aggregated via ff tunnelling.
1640 * Note the caller is responsible for checking if the destination
1641 * supports fast frames.
1643 * NB: allowing EAPOL frames to be aggregated with other unicast traffic.
1644 * Do 802.1x EAPOL frames proceed in the clear? Then they couldn't
1645 * be aggregated with other types of frames when encryption is on?
1647 * NB: assumes lock on an_ff_buf effectively held by txq lock mechanism.
1650 ath_ff_can_aggregate(struct ath_softc *sc,
1651 struct ath_node *an, struct mbuf *m, int *flushq)
1653 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
1654 struct ath_txq *txq;
1655 u_int32_t txoplimit;
1661 * If there is no frame to combine with and the txq has
1662 * fewer frames than the minimum required; then do not
1663 * attempt to aggregate this frame.
1665 pri = M_WME_GETAC(m);
1666 txq = sc->sc_ac2q[pri];
1667 if (an->an_ff_buf[pri] == NULL && txq->axq_depth < sc->sc_fftxqmin)
1670 * When not in station mode never aggregate a multicast
1671 * frame; this insures, for example, that a combined frame
1672 * does not require multiple encryption keys when using
1675 if (ic->ic_opmode != IEEE80211_M_STA &&
1676 ETHER_IS_MULTICAST(mtod(m, struct ether_header *)->ether_dhost))
1679 * Consult the max bursting interval to insure a combined
1680 * frame fits within the TxOp window.
1682 txoplimit = IEEE80211_TXOP_TO_US(
1683 ic->ic_wme.wme_chanParams.cap_wmeParams[pri].wmep_txopLimit);
1684 if (txoplimit != 0 && ath_ff_approx_txtime(sc, an, m) > txoplimit) {
1685 DPRINTF(sc, ATH_DEBUG_XMIT | ATH_DEBUG_FF,
1686 "%s: FF TxOp violation\n", __func__);
1687 if (an->an_ff_buf[pri] != NULL)
1691 return 1; /* try to aggregate */
1695 * Check if the supplied frame can be partnered with an existing
1696 * or pending frame. Return a reference to any frame that should be
1697 * sent on return; otherwise return NULL.
1699 static struct mbuf *
1700 ath_ff_check(struct ath_softc *sc, struct ath_txq *txq,
1701 struct ath_buf *bf, struct mbuf *m, struct ieee80211_node *ni)
1703 struct ath_node *an = ATH_NODE(ni);
1704 struct ath_buf *bfstaged;
1708 * Check if the supplied frame can be aggregated.
1710 * NB: we use the txq lock to protect references to
1711 * an->an_ff_txbuf in ath_ff_can_aggregate().
1714 pri = M_WME_GETAC(m);
1715 if (ath_ff_can_aggregate(sc, an, m, &ff_flush)) {
1716 struct ath_buf *bfstaged = an->an_ff_buf[pri];
1717 if (bfstaged != NULL) {
1719 * A frame is available for partnering; remove
1720 * it, chain it to this one, and encapsulate.
1722 an->an_ff_buf[pri] = NULL;
1723 TAILQ_REMOVE(&txq->axq_stageq, bfstaged, bf_stagelist);
1724 ATH_TXQ_UNLOCK(txq);
1727 * Chain mbufs and add FF magic.
1729 DPRINTF(sc, ATH_DEBUG_FF,
1730 "[%s] aggregate fast-frame, age %u\n",
1731 ether_sprintf(ni->ni_macaddr), txq->axq_curage);
1732 m->m_nextpkt = NULL;
1733 bfstaged->bf_m->m_nextpkt = m;
1735 bfstaged->bf_m = NULL;
1738 * Release the node reference held while
1739 * the packet sat on an_ff_buf[]
1741 bfstaged->bf_node = NULL;
1742 ieee80211_free_node(ni);
1745 * Return bfstaged to the free list.
1748 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bfstaged, bf_list);
1749 ATH_TXBUF_UNLOCK(sc);
1751 return m; /* ready to go */
1754 * No frame available, queue this frame to wait
1755 * for a partner. Note that we hold the buffer
1756 * and a reference to the node; we need the
1757 * buffer in particular so we're certain we
1758 * can flush the frame at a later time.
1760 DPRINTF(sc, ATH_DEBUG_FF,
1761 "[%s] stage fast-frame, age %u\n",
1762 ether_sprintf(ni->ni_macaddr), txq->axq_curage);
1765 bf->bf_node = ni; /* NB: held reference */
1766 bf->bf_age = txq->axq_curage;
1767 an->an_ff_buf[pri] = bf;
1768 TAILQ_INSERT_HEAD(&txq->axq_stageq, bf, bf_stagelist);
1769 ATH_TXQ_UNLOCK(txq);
1771 return NULL; /* consumed */
1775 * Frame could not be aggregated, it needs to be returned
1776 * to the caller for immediate transmission. In addition
1777 * we check if we should first flush a frame from the
1778 * staging queue before sending this one.
1780 * NB: ath_ff_can_aggregate only marks ff_flush if a frame
1781 * is present to flush.
1786 bfstaged = an->an_ff_buf[pri];
1787 an->an_ff_buf[pri] = NULL;
1788 TAILQ_REMOVE(&txq->axq_stageq, bfstaged, bf_stagelist);
1789 ATH_TXQ_UNLOCK(txq);
1791 DPRINTF(sc, ATH_DEBUG_FF, "[%s] flush staged frame\n",
1792 ether_sprintf(an->an_node.ni_macaddr));
1794 /* encap and xmit */
1795 bfstaged->bf_m = ieee80211_encap(ni, bfstaged->bf_m);
1796 if (bfstaged->bf_m == NULL) {
1797 DPRINTF(sc, ATH_DEBUG_XMIT | ATH_DEBUG_FF,
1798 "%s: discard, encap failure\n", __func__);
1799 sc->sc_stats.ast_tx_encap++;
1802 pktlen = bfstaged->bf_m->m_pkthdr.len;
1803 if (ath_tx_start(sc, ni, bfstaged, bfstaged->bf_m)) {
1804 DPRINTF(sc, ATH_DEBUG_XMIT,
1805 "%s: discard, xmit failure\n", __func__);
1808 * Unable to transmit frame that was on the staging
1809 * queue. Reclaim the node reference and other
1813 ieee80211_free_node(ni);
1814 bfstaged->bf_node = NULL;
1815 if (bfstaged->bf_m != NULL) {
1816 m_freem(bfstaged->bf_m);
1817 bfstaged->bf_m = NULL;
1821 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bfstaged, bf_list);
1822 ATH_TXBUF_UNLOCK(sc);
1829 if (an->an_ff_buf[pri] != NULL) {
1831 * XXX: out-of-order condition only occurs for AP
1832 * mode and multicast. There may be no valid way
1833 * to get this condition.
1835 DPRINTF(sc, ATH_DEBUG_FF, "[%s] out-of-order frame\n",
1836 ether_sprintf(an->an_node.ni_macaddr));
1839 ATH_TXQ_UNLOCK(txq);
1845 * Cleanup driver resources when we run out of buffers
1846 * while processing fragments; return the tx buffers
1847 * allocated and drop node references.
1850 ath_txfrag_cleanup(struct ath_softc *sc,
1851 ath_bufhead *frags, struct ieee80211_node *ni)
1853 struct ath_buf *bf, *next;
1855 ATH_TXBUF_LOCK_ASSERT(sc);
1857 STAILQ_FOREACH_SAFE(bf, frags, bf_list, next) {
1858 /* NB: bf assumed clean */
1859 STAILQ_REMOVE_HEAD(frags, bf_list);
1860 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1861 ieee80211_node_decref(ni);
1866 * Setup xmit of a fragmented frame. Allocate a buffer
1867 * for each frag and bump the node reference count to
1868 * reflect the held reference to be setup by ath_tx_start.
1871 ath_txfrag_setup(struct ath_softc *sc, ath_bufhead *frags,
1872 struct mbuf *m0, struct ieee80211_node *ni)
1878 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) {
1879 bf = STAILQ_FIRST(&sc->sc_txbuf);
1880 if (bf == NULL) { /* out of buffers, cleanup */
1881 ath_txfrag_cleanup(sc, frags, ni);
1884 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
1885 ieee80211_node_incref(ni);
1886 STAILQ_INSERT_TAIL(frags, bf, bf_list);
1888 ATH_TXBUF_UNLOCK(sc);
1890 return !STAILQ_EMPTY(frags);
1894 ath_start(struct ifnet *ifp)
1896 struct ath_softc *sc = ifp->if_softc;
1897 struct ieee80211com *ic = ifp->if_l2com;
1898 struct ieee80211_node *ni;
1900 struct mbuf *m, *next;
1901 struct ath_txq *txq;
1905 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
1909 * Grab a TX buffer and associated resources.
1912 bf = STAILQ_FIRST(&sc->sc_txbuf);
1914 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
1915 ATH_TXBUF_UNLOCK(sc);
1917 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n",
1919 sc->sc_stats.ast_tx_qstop++;
1920 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1924 IFQ_DEQUEUE(&ifp->if_snd, m);
1927 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1928 ATH_TXBUF_UNLOCK(sc);
1931 STAILQ_INIT(&frags);
1932 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1933 pri = M_WME_GETAC(m);
1934 txq = sc->sc_ac2q[pri];
1935 if (ni->ni_ath_flags & IEEE80211_NODE_FF) {
1937 * Check queue length; if too deep drop this
1938 * frame (tail drop considered good).
1940 if (txq->axq_depth >= sc->sc_fftxqmax) {
1941 DPRINTF(sc, ATH_DEBUG_FF,
1942 "[%s] tail drop on q %u depth %u\n",
1943 ether_sprintf(ni->ni_macaddr),
1944 txq->axq_qnum, txq->axq_depth);
1945 sc->sc_stats.ast_tx_qfull++;
1949 m = ath_ff_check(sc, txq, bf, m, ni);
1951 /* NB: ni ref & bf held on stageq */
1957 * Encapsulate the packet in prep for transmission.
1959 m = ieee80211_encap(ni, m);
1961 DPRINTF(sc, ATH_DEBUG_XMIT,
1962 "%s: encapsulation failure\n", __func__);
1963 sc->sc_stats.ast_tx_encap++;
1967 * Check for fragmentation. If this frame
1968 * has been broken up verify we have enough
1969 * buffers to send all the fragments so all
1972 if ((m->m_flags & M_FRAG) &&
1973 !ath_txfrag_setup(sc, &frags, m, ni)) {
1974 DPRINTF(sc, ATH_DEBUG_XMIT,
1975 "%s: out of txfrag buffers\n", __func__);
1976 ic->ic_stats.is_tx_nobuf++; /* XXX */
1982 * Pass the frame to the h/w for transmission.
1983 * Fragmented frames have each frag chained together
1984 * with m_nextpkt. We know there are sufficient ath_buf's
1985 * to send all the frags because of work done by
1986 * ath_txfrag_setup. We leave m_nextpkt set while
1987 * calling ath_tx_start so it can use it to extend the
1988 * the tx duration to cover the subsequent frag and
1989 * so it can reclaim all the mbufs in case of an error;
1990 * ath_tx_start clears m_nextpkt once it commits to
1991 * handing the frame to the hardware.
1993 next = m->m_nextpkt;
1994 if (ath_tx_start(sc, ni, bf, m)) {
2001 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
2002 ath_txfrag_cleanup(sc, &frags, ni);
2003 ATH_TXBUF_UNLOCK(sc);
2005 ieee80211_free_node(ni);
2010 * Beware of state changing between frags.
2011 * XXX check sta power-save state?
2013 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) {
2014 DPRINTF(sc, ATH_DEBUG_XMIT,
2015 "%s: flush fragmented packet, state %s\n",
2017 ieee80211_state_name[ni->ni_vap->iv_state]);
2022 bf = STAILQ_FIRST(&frags);
2023 KASSERT(bf != NULL, ("no buf for txfrag"));
2024 STAILQ_REMOVE_HEAD(&frags, bf_list);
2031 * Flush stale frames from the fast-frame staging queue.
2033 if (ic->ic_opmode != IEEE80211_M_STA)
2034 ath_ff_stageq_flush(sc, txq, ath_ff_ageflushtestdone);
2040 ath_media_change(struct ifnet *ifp)
2042 int error = ieee80211_media_change(ifp);
2043 /* NB: only the fixed rate can change and that doesn't need a reset */
2044 return (error == ENETRESET ? 0 : error);
2049 ath_keyprint(struct ath_softc *sc, const char *tag, u_int ix,
2050 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
2052 static const char *ciphers[] = {
2062 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]);
2063 for (i = 0, n = hk->kv_len; i < n; i++)
2064 printf("%02x", hk->kv_val[i]);
2065 printf(" mac %s", ether_sprintf(mac));
2066 if (hk->kv_type == HAL_CIPHER_TKIP) {
2067 printf(" %s ", sc->sc_splitmic ? "mic" : "rxmic");
2068 for (i = 0; i < sizeof(hk->kv_mic); i++)
2069 printf("%02x", hk->kv_mic[i]);
2070 #if HAL_ABI_VERSION > 0x06052200
2071 if (!sc->sc_splitmic) {
2073 for (i = 0; i < sizeof(hk->kv_txmic); i++)
2074 printf("%02x", hk->kv_txmic[i]);
2083 * Set a TKIP key into the hardware. This handles the
2084 * potential distribution of key state to multiple key
2085 * cache slots for TKIP.
2088 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k,
2089 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
2091 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV)
2092 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN];
2093 struct ath_hal *ah = sc->sc_ah;
2095 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP,
2096 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher));
2097 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) {
2098 if (sc->sc_splitmic) {
2100 * TX key goes at first index, RX key at the rx index.
2101 * The hal handles the MIC keys at index+64.
2103 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic));
2104 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid);
2105 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid))
2108 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
2109 KEYPRINTF(sc, k->wk_keyix+32, hk, mac);
2110 /* XXX delete tx key on failure? */
2111 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac);
2114 * Room for both TX+RX MIC keys in one key cache
2115 * slot, just set key at the first index; the hal
2116 * will handle the rest.
2118 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
2119 #if HAL_ABI_VERSION > 0x06052200
2120 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic));
2122 KEYPRINTF(sc, k->wk_keyix, hk, mac);
2123 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
2125 } else if (k->wk_flags & IEEE80211_KEY_XMIT) {
2126 #if HAL_ABI_VERSION > 0x06052200
2127 memcpy(hk->kv_txmic, k->wk_txmic, sizeof(hk->kv_txmic));
2129 memcpy(hk->kv_mic, k->wk_mic, sizeof(hk->kv_mic));
2131 KEYPRINTF(sc, k->wk_keyix, hk, mac);
2132 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
2133 } else if (k->wk_flags & IEEE80211_KEY_RECV) {
2134 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
2135 KEYPRINTF(sc, k->wk_keyix, hk, mac);
2136 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
2139 #undef IEEE80211_KEY_XR
2143 * Set a net80211 key into the hardware. This handles the
2144 * potential distribution of key state to multiple key
2145 * cache slots for TKIP with hardware MIC support.
2148 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k,
2149 const u_int8_t mac0[IEEE80211_ADDR_LEN],
2150 struct ieee80211_node *bss)
2152 #define N(a) (sizeof(a)/sizeof(a[0]))
2153 static const u_int8_t ciphermap[] = {
2154 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */
2155 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */
2156 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */
2157 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */
2158 (u_int8_t) -1, /* 4 is not allocated */
2159 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */
2160 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */
2162 struct ath_hal *ah = sc->sc_ah;
2163 const struct ieee80211_cipher *cip = k->wk_cipher;
2164 u_int8_t gmac[IEEE80211_ADDR_LEN];
2165 const u_int8_t *mac;
2168 memset(&hk, 0, sizeof(hk));
2170 * Software crypto uses a "clear key" so non-crypto
2171 * state kept in the key cache are maintained and
2172 * so that rx frames have an entry to match.
2174 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) {
2175 KASSERT(cip->ic_cipher < N(ciphermap),
2176 ("invalid cipher type %u", cip->ic_cipher));
2177 hk.kv_type = ciphermap[cip->ic_cipher];
2178 hk.kv_len = k->wk_keylen;
2179 memcpy(hk.kv_val, k->wk_key, k->wk_keylen);
2181 hk.kv_type = HAL_CIPHER_CLR;
2183 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) {
2185 * Group keys on hardware that supports multicast frame
2186 * key search use a mac that is the sender's address with
2187 * the high bit set instead of the app-specified address.
2189 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr);
2195 if (hk.kv_type == HAL_CIPHER_TKIP &&
2196 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
2197 return ath_keyset_tkip(sc, k, &hk, mac);
2199 KEYPRINTF(sc, k->wk_keyix, &hk, mac);
2200 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac);
2206 * Allocate tx/rx key slots for TKIP. We allocate two slots for
2207 * each key, one for decrypt/encrypt and the other for the MIC.
2210 key_alloc_2pair(struct ath_softc *sc,
2211 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
2213 #define N(a) (sizeof(a)/sizeof(a[0]))
2216 KASSERT(sc->sc_splitmic, ("key cache !split"));
2217 /* XXX could optimize */
2218 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
2219 u_int8_t b = sc->sc_keymap[i];
2222 * One or more slots in this byte are free.
2230 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */
2231 if (isset(sc->sc_keymap, keyix+32) ||
2232 isset(sc->sc_keymap, keyix+64) ||
2233 isset(sc->sc_keymap, keyix+32+64)) {
2234 /* full pair unavailable */
2236 if (keyix == (i+1)*NBBY) {
2237 /* no slots were appropriate, advance */
2242 setbit(sc->sc_keymap, keyix);
2243 setbit(sc->sc_keymap, keyix+64);
2244 setbit(sc->sc_keymap, keyix+32);
2245 setbit(sc->sc_keymap, keyix+32+64);
2246 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
2247 "%s: key pair %u,%u %u,%u\n",
2248 __func__, keyix, keyix+64,
2249 keyix+32, keyix+32+64);
2251 *rxkeyix = keyix+32;
2255 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
2261 * Allocate tx/rx key slots for TKIP. We allocate two slots for
2262 * each key, one for decrypt/encrypt and the other for the MIC.
2265 key_alloc_pair(struct ath_softc *sc,
2266 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
2268 #define N(a) (sizeof(a)/sizeof(a[0]))
2271 KASSERT(!sc->sc_splitmic, ("key cache split"));
2272 /* XXX could optimize */
2273 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
2274 u_int8_t b = sc->sc_keymap[i];
2277 * One or more slots in this byte are free.
2285 if (isset(sc->sc_keymap, keyix+64)) {
2286 /* full pair unavailable */
2288 if (keyix == (i+1)*NBBY) {
2289 /* no slots were appropriate, advance */
2294 setbit(sc->sc_keymap, keyix);
2295 setbit(sc->sc_keymap, keyix+64);
2296 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
2297 "%s: key pair %u,%u\n",
2298 __func__, keyix, keyix+64);
2299 *txkeyix = *rxkeyix = keyix;
2303 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
2309 * Allocate a single key cache slot.
2312 key_alloc_single(struct ath_softc *sc,
2313 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
2315 #define N(a) (sizeof(a)/sizeof(a[0]))
2318 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */
2319 for (i = 0; i < N(sc->sc_keymap); i++) {
2320 u_int8_t b = sc->sc_keymap[i];
2323 * One or more slots are free.
2328 setbit(sc->sc_keymap, keyix);
2329 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n",
2331 *txkeyix = *rxkeyix = keyix;
2335 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__);
2341 * Allocate one or more key cache slots for a uniacst key. The
2342 * key itself is needed only to identify the cipher. For hardware
2343 * TKIP with split cipher+MIC keys we allocate two key cache slot
2344 * pairs so that we can setup separate TX and RX MIC keys. Note
2345 * that the MIC key for a TKIP key at slot i is assumed by the
2346 * hardware to be at slot i+64. This limits TKIP keys to the first
2350 ath_key_alloc(struct ieee80211vap *vap, const struct ieee80211_key *k,
2351 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix)
2353 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
2356 * Group key allocation must be handled specially for
2357 * parts that do not support multicast key cache search
2358 * functionality. For those parts the key id must match
2359 * the h/w key index so lookups find the right key. On
2360 * parts w/ the key search facility we install the sender's
2361 * mac address (with the high bit set) and let the hardware
2362 * find the key w/o using the key id. This is preferred as
2363 * it permits us to support multiple users for adhoc and/or
2364 * multi-station operation.
2366 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) {
2367 if (!(&vap->iv_nw_keys[0] <= k &&
2368 k < &vap->iv_nw_keys[IEEE80211_WEP_NKID])) {
2369 /* should not happen */
2370 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
2371 "%s: bogus group key\n", __func__);
2375 * XXX we pre-allocate the global keys so
2376 * have no way to check if they've already been allocated.
2378 *keyix = *rxkeyix = k - vap->iv_nw_keys;
2383 * We allocate two pair for TKIP when using the h/w to do
2384 * the MIC. For everything else, including software crypto,
2385 * we allocate a single entry. Note that s/w crypto requires
2386 * a pass-through slot on the 5211 and 5212. The 5210 does
2387 * not support pass-through cache entries and we map all
2388 * those requests to slot 0.
2390 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
2391 return key_alloc_single(sc, keyix, rxkeyix);
2392 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP &&
2393 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
2394 if (sc->sc_splitmic)
2395 return key_alloc_2pair(sc, keyix, rxkeyix);
2397 return key_alloc_pair(sc, keyix, rxkeyix);
2399 return key_alloc_single(sc, keyix, rxkeyix);
2404 * Delete an entry in the key cache allocated by ath_key_alloc.
2407 ath_key_delete(struct ieee80211vap *vap, const struct ieee80211_key *k)
2409 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
2410 struct ath_hal *ah = sc->sc_ah;
2411 const struct ieee80211_cipher *cip = k->wk_cipher;
2412 u_int keyix = k->wk_keyix;
2414 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix);
2416 ath_hal_keyreset(ah, keyix);
2418 * Handle split tx/rx keying required for TKIP with h/w MIC.
2420 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
2421 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic)
2422 ath_hal_keyreset(ah, keyix+32); /* RX key */
2423 if (keyix >= IEEE80211_WEP_NKID) {
2425 * Don't touch keymap entries for global keys so
2426 * they are never considered for dynamic allocation.
2428 clrbit(sc->sc_keymap, keyix);
2429 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
2430 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0) {
2431 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */
2432 if (sc->sc_splitmic) {
2433 /* +32 for RX key, +32+64 for RX key MIC */
2434 clrbit(sc->sc_keymap, keyix+32);
2435 clrbit(sc->sc_keymap, keyix+32+64);
2443 * Set the key cache contents for the specified key. Key cache
2444 * slot(s) must already have been allocated by ath_key_alloc.
2447 ath_key_set(struct ieee80211vap *vap, const struct ieee80211_key *k,
2448 const u_int8_t mac[IEEE80211_ADDR_LEN])
2450 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
2452 return ath_keyset(sc, k, mac, vap->iv_bss);
2456 * Block/unblock tx+rx processing while a key change is done.
2457 * We assume the caller serializes key management operations
2458 * so we only need to worry about synchronization with other
2459 * uses that originate in the driver.
2462 ath_key_update_begin(struct ieee80211vap *vap)
2464 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2465 struct ath_softc *sc = ifp->if_softc;
2467 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2468 taskqueue_block(sc->sc_tq);
2469 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
2473 ath_key_update_end(struct ieee80211vap *vap)
2475 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2476 struct ath_softc *sc = ifp->if_softc;
2478 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
2479 IF_UNLOCK(&ifp->if_snd);
2480 taskqueue_unblock(sc->sc_tq);
2484 * Calculate the receive filter according to the
2485 * operating mode and state:
2487 * o always accept unicast, broadcast, and multicast traffic
2488 * o accept PHY error frames when hardware doesn't have MIB support
2489 * to count and we need them for ANI (sta mode only at the moment)
2490 * and we are not scanning (ANI is disabled)
2491 * NB: only with recent hal's; older hal's add rx filter bits out
2492 * of sight and we need to blindly preserve them
2493 * o probe request frames are accepted only when operating in
2494 * hostap, adhoc, or monitor modes
2495 * o enable promiscuous mode
2496 * - when in monitor mode
2497 * - if interface marked PROMISC (assumes bridge setting is filtered)
2499 * - when operating in station mode for collecting rssi data when
2500 * the station is otherwise quiet, or
2501 * - when operating in adhoc mode so the 802.11 layer creates
2502 * node table entries for peers,
2504 * - when doing s/w beacon miss (e.g. for ap+sta)
2505 * - when operating in ap mode in 11g to detect overlapping bss that
2506 * require protection
2507 * o accept control frames:
2508 * - when in monitor mode
2509 * XXX BAR frames for 11n
2510 * XXX HT protection for 11n
2513 ath_calcrxfilter(struct ath_softc *sc)
2515 struct ifnet *ifp = sc->sc_ifp;
2516 struct ieee80211com *ic = ifp->if_l2com;
2519 #if HAL_ABI_VERSION < 0x08011600
2520 rfilt = (ath_hal_getrxfilter(sc->sc_ah) &
2521 (HAL_RX_FILTER_PHYRADAR | HAL_RX_FILTER_PHYERR))
2522 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
2524 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
2525 if (ic->ic_opmode == IEEE80211_M_STA &&
2526 !sc->sc_needmib && !sc->sc_scanning)
2527 rfilt |= HAL_RX_FILTER_PHYERR;
2529 if (ic->ic_opmode != IEEE80211_M_STA)
2530 rfilt |= HAL_RX_FILTER_PROBEREQ;
2531 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC))
2532 rfilt |= HAL_RX_FILTER_PROM;
2533 if (ic->ic_opmode == IEEE80211_M_STA ||
2534 sc->sc_opmode == HAL_M_IBSS ||
2535 sc->sc_swbmiss || sc->sc_scanning)
2536 rfilt |= HAL_RX_FILTER_BEACON;
2538 * NB: We don't recalculate the rx filter when
2539 * ic_protmode changes; otherwise we could do
2540 * this only when ic_protmode != NONE.
2542 if (ic->ic_opmode == IEEE80211_M_HOSTAP &&
2543 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
2544 rfilt |= HAL_RX_FILTER_BEACON;
2545 if (ic->ic_opmode == IEEE80211_M_MONITOR)
2546 rfilt |= HAL_RX_FILTER_CONTROL;
2547 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n",
2548 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags);
2553 ath_update_promisc(struct ifnet *ifp)
2555 struct ath_softc *sc = ifp->if_softc;
2558 /* configure rx filter */
2559 rfilt = ath_calcrxfilter(sc);
2560 ath_hal_setrxfilter(sc->sc_ah, rfilt);
2562 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt);
2566 ath_update_mcast(struct ifnet *ifp)
2568 struct ath_softc *sc = ifp->if_softc;
2571 /* calculate and install multicast filter */
2572 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
2573 struct ifmultiaddr *ifma;
2575 * Merge multicast addresses to form the hardware filter.
2577 mfilt[0] = mfilt[1] = 0;
2578 IF_ADDR_LOCK(ifp); /* XXX need some fiddling to remove? */
2579 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2584 /* calculate XOR of eight 6bit values */
2585 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
2586 val = LE_READ_4(dl + 0);
2587 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2588 val = LE_READ_4(dl + 3);
2589 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2591 mfilt[pos / 32] |= (1 << (pos % 32));
2593 IF_ADDR_UNLOCK(ifp);
2595 mfilt[0] = mfilt[1] = ~0;
2596 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]);
2597 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n",
2598 __func__, mfilt[0], mfilt[1]);
2602 ath_mode_init(struct ath_softc *sc)
2604 struct ifnet *ifp = sc->sc_ifp;
2605 struct ieee80211com *ic = ifp->if_l2com;
2606 struct ath_hal *ah = sc->sc_ah;
2609 /* configure rx filter */
2610 rfilt = ath_calcrxfilter(sc);
2611 ath_hal_setrxfilter(ah, rfilt);
2613 /* configure operational mode */
2614 ath_hal_setopmode(ah);
2617 * Handle any link-level address change. Note that we only
2618 * need to force ic_myaddr; any other addresses are handled
2619 * as a byproduct of the ifnet code marking the interface
2622 * XXX should get from lladdr instead of arpcom but that's more work
2624 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp));
2625 ath_hal_setmac(ah, ic->ic_myaddr);
2627 /* calculate and install multicast filter */
2628 ath_update_mcast(ifp);
2632 * Set the slot time based on the current setting.
2635 ath_setslottime(struct ath_softc *sc)
2637 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2638 struct ath_hal *ah = sc->sc_ah;
2641 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan))
2643 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan))
2645 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
2646 /* honor short/long slot time only in 11g */
2647 /* XXX shouldn't honor on pure g or turbo g channel */
2648 if (ic->ic_flags & IEEE80211_F_SHSLOT)
2649 usec = HAL_SLOT_TIME_9;
2651 usec = HAL_SLOT_TIME_20;
2653 usec = HAL_SLOT_TIME_9;
2655 DPRINTF(sc, ATH_DEBUG_RESET,
2656 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n",
2657 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags,
2658 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec);
2660 ath_hal_setslottime(ah, usec);
2661 sc->sc_updateslot = OK;
2665 * Callback from the 802.11 layer to update the
2666 * slot time based on the current setting.
2669 ath_updateslot(struct ifnet *ifp)
2671 struct ath_softc *sc = ifp->if_softc;
2672 struct ieee80211com *ic = ifp->if_l2com;
2675 * When not coordinating the BSS, change the hardware
2676 * immediately. For other operation we defer the change
2677 * until beacon updates have propagated to the stations.
2679 if (ic->ic_opmode == IEEE80211_M_HOSTAP)
2680 sc->sc_updateslot = UPDATE;
2682 ath_setslottime(sc);
2686 * Setup a h/w transmit queue for beacons.
2689 ath_beaconq_setup(struct ath_hal *ah)
2693 memset(&qi, 0, sizeof(qi));
2694 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
2695 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
2696 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
2697 /* NB: for dynamic turbo, don't enable any other interrupts */
2698 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE;
2699 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
2703 * Setup the transmit queue parameters for the beacon queue.
2706 ath_beaconq_config(struct ath_softc *sc)
2708 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
2709 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2710 struct ath_hal *ah = sc->sc_ah;
2713 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
2714 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
2716 * Always burst out beacon and CAB traffic.
2718 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
2719 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
2720 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
2722 struct wmeParams *wmep =
2723 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
2725 * Adhoc mode; important thing is to use 2x cwmin.
2727 qi.tqi_aifs = wmep->wmep_aifsn;
2728 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
2729 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
2732 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
2733 device_printf(sc->sc_dev, "unable to update parameters for "
2734 "beacon hardware queue!\n");
2737 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
2740 #undef ATH_EXPONENT_TO_VALUE
2744 * Allocate and setup an initial beacon frame.
2747 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
2749 struct ieee80211vap *vap = ni->ni_vap;
2750 struct ath_vap *avp = ATH_VAP(vap);
2756 if (bf->bf_m != NULL) {
2757 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2761 if (bf->bf_node != NULL) {
2762 ieee80211_free_node(bf->bf_node);
2767 * NB: the beacon data buffer must be 32-bit aligned;
2768 * we assume the mbuf routines will return us something
2769 * with this alignment (perhaps should assert).
2771 m = ieee80211_beacon_alloc(ni, &avp->av_boff);
2773 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__);
2774 sc->sc_stats.ast_be_nombuf++;
2777 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
2778 bf->bf_segs, &bf->bf_nseg,
2781 device_printf(sc->sc_dev,
2782 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n",
2789 * Calculate a TSF adjustment factor required for staggered
2790 * beacons. Note that we assume the format of the beacon
2791 * frame leaves the tstamp field immediately following the
2794 if (sc->sc_stagbeacons && avp->av_bslot > 0) {
2796 struct ieee80211_frame *wh;
2799 * The beacon interval is in TU's; the TSF is in usecs.
2800 * We figure out how many TU's to add to align the timestamp
2801 * then convert to TSF units and handle byte swapping before
2802 * inserting it in the frame. The hardware will then add this
2803 * each time a beacon frame is sent. Note that we align vap's
2804 * 1..N and leave vap 0 untouched. This means vap 0 has a
2805 * timestamp in one beacon interval while the others get a
2806 * timstamp aligned to the next interval.
2808 tsfadjust = ni->ni_intval *
2809 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF;
2810 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */
2812 DPRINTF(sc, ATH_DEBUG_BEACON,
2813 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n",
2814 __func__, sc->sc_stagbeacons ? "stagger" : "burst",
2815 avp->av_bslot, ni->ni_intval, le64toh(tsfadjust));
2817 wh = mtod(m, struct ieee80211_frame *);
2818 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust));
2821 bf->bf_node = ieee80211_ref_node(ni);
2827 * Setup the beacon frame for transmit.
2830 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
2832 #define USE_SHPREAMBLE(_ic) \
2833 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
2834 == IEEE80211_F_SHPREAMBLE)
2835 struct ieee80211_node *ni = bf->bf_node;
2836 struct ieee80211com *ic = ni->ni_ic;
2837 struct mbuf *m = bf->bf_m;
2838 struct ath_hal *ah = sc->sc_ah;
2839 struct ath_desc *ds;
2841 const HAL_RATE_TABLE *rt;
2844 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n",
2845 __func__, m, m->m_len);
2847 /* setup descriptors */
2850 flags = HAL_TXDESC_NOACK;
2851 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
2852 ds->ds_link = bf->bf_daddr; /* self-linked */
2853 flags |= HAL_TXDESC_VEOL;
2855 * Let hardware handle antenna switching.
2857 antenna = sc->sc_txantenna;
2861 * Switch antenna every 4 beacons.
2862 * XXX assumes two antenna
2864 if (sc->sc_txantenna != 0)
2865 antenna = sc->sc_txantenna;
2866 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0)
2867 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1);
2869 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
2872 KASSERT(bf->bf_nseg == 1,
2873 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
2874 ds->ds_data = bf->bf_segs[0].ds_addr;
2876 * Calculate rate code.
2877 * XXX everything at min xmit rate
2880 rt = sc->sc_currates;
2881 rate = rt->info[rix].rateCode;
2882 if (USE_SHPREAMBLE(ic))
2883 rate |= rt->info[rix].shortPreamble;
2884 ath_hal_setuptxdesc(ah, ds
2885 , m->m_len + IEEE80211_CRC_LEN /* frame length */
2886 , sizeof(struct ieee80211_frame)/* header length */
2887 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
2888 , ni->ni_txpower /* txpower XXX */
2889 , rate, 1 /* series 0 rate/tries */
2890 , HAL_TXKEYIX_INVALID /* no encryption */
2891 , antenna /* antenna mode */
2892 , flags /* no ack, veol for beacons */
2893 , 0 /* rts/cts rate */
2894 , 0 /* rts/cts duration */
2896 /* NB: beacon's BufLen must be a multiple of 4 bytes */
2897 ath_hal_filltxdesc(ah, ds
2898 , roundup(m->m_len, 4) /* buffer length */
2899 , AH_TRUE /* first segment */
2900 , AH_TRUE /* last segment */
2901 , ds /* first descriptor */
2906 #undef USE_SHPREAMBLE
2910 ath_beacon_update(struct ieee80211vap *vap, int item)
2912 struct ieee80211_beacon_offsets *bo = &ATH_VAP(vap)->av_boff;
2914 setbit(bo->bo_flags, item);
2918 * Append the contents of src to dst; both queues
2919 * are assumed to be locked.
2922 ath_txqmove(struct ath_txq *dst, struct ath_txq *src)
2924 STAILQ_CONCAT(&dst->axq_q, &src->axq_q);
2925 dst->axq_link = src->axq_link;
2926 src->axq_link = NULL;
2927 dst->axq_depth += src->axq_depth;
2932 * Transmit a beacon frame at SWBA. Dynamic updates to the
2933 * frame contents are done as needed and the slot time is
2934 * also adjusted based on current state.
2937 ath_beacon_proc(void *arg, int pending)
2939 struct ath_softc *sc = arg;
2940 struct ath_hal *ah = sc->sc_ah;
2941 struct ieee80211vap *vap;
2946 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n",
2949 * Check if the previous beacon has gone out. If
2950 * not don't try to post another, skip this period
2951 * and wait for the next. Missed beacons indicate
2952 * a problem and should not occur. If we miss too
2953 * many consecutive beacons reset the device.
2955 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
2956 sc->sc_bmisscount++;
2957 DPRINTF(sc, ATH_DEBUG_BEACON,
2958 "%s: missed %u consecutive beacons\n",
2959 __func__, sc->sc_bmisscount);
2960 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */
2961 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
2964 if (sc->sc_bmisscount != 0) {
2965 DPRINTF(sc, ATH_DEBUG_BEACON,
2966 "%s: resume beacon xmit after %u misses\n",
2967 __func__, sc->sc_bmisscount);
2968 sc->sc_bmisscount = 0;
2971 if (sc->sc_stagbeacons) { /* staggered beacons */
2972 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
2975 tsftu = ath_hal_gettsf32(ah) >> 10;
2977 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval;
2978 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF];
2980 if (vap != NULL && vap->iv_state == IEEE80211_S_RUN) {
2981 bf = ath_beacon_generate(sc, vap);
2983 bfaddr = bf->bf_daddr;
2985 } else { /* burst'd beacons */
2986 uint32_t *bflink = &bfaddr;
2988 for (slot = 0; slot < ATH_BCBUF; slot++) {
2989 vap = sc->sc_bslot[slot];
2990 if (vap != NULL && vap->iv_state == IEEE80211_S_RUN) {
2991 bf = ath_beacon_generate(sc, vap);
2993 *bflink = bf->bf_daddr;
2994 bflink = &bf->bf_desc->ds_link;
2998 *bflink = 0; /* terminate list */
3002 * Handle slot time change when a non-ERP station joins/leaves
3003 * an 11g network. The 802.11 layer notifies us via callback,
3004 * we mark updateslot, then wait one beacon before effecting
3005 * the change. This gives associated stations at least one
3006 * beacon interval to note the state change.
3009 if (sc->sc_updateslot == UPDATE) {
3010 sc->sc_updateslot = COMMIT; /* commit next beacon */
3011 sc->sc_slotupdate = slot;
3012 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot)
3013 ath_setslottime(sc); /* commit change to h/w */
3016 * Check recent per-antenna transmit statistics and flip
3017 * the default antenna if noticeably more frames went out
3018 * on the non-default antenna.
3019 * XXX assumes 2 anntenae
3021 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) {
3022 otherant = sc->sc_defant & 1 ? 2 : 1;
3023 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
3024 ath_setdefantenna(sc, otherant);
3025 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
3030 * Stop any current dma and put the new frame on the queue.
3031 * This should never fail since we check above that no frames
3032 * are still pending on the queue.
3034 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
3035 DPRINTF(sc, ATH_DEBUG_ANY,
3036 "%s: beacon queue %u did not stop?\n",
3037 __func__, sc->sc_bhalq);
3039 /* NB: cabq traffic should already be queued and primed */
3040 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr);
3041 ath_hal_txstart(ah, sc->sc_bhalq);
3043 sc->sc_stats.ast_be_xmit++;
3047 static struct ath_buf *
3048 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap)
3050 struct ath_vap *avp = ATH_VAP(vap);
3051 struct ath_txq *cabq = sc->sc_cabq;
3056 KASSERT(vap->iv_state == IEEE80211_S_RUN,
3057 ("not running, state %d", vap->iv_state));
3058 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
3061 * Update dynamic beacon contents. If this returns
3062 * non-zero then we need to remap the memory because
3063 * the beacon frame changed size (probably because
3064 * of the TIM bitmap).
3068 nmcastq = avp->av_mcastq.axq_depth;
3069 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, nmcastq)) {
3070 /* XXX too conservative? */
3071 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3072 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
3073 bf->bf_segs, &bf->bf_nseg,
3076 if_printf(vap->iv_ifp,
3077 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
3082 if ((avp->av_boff.bo_tim[4] & 1) && cabq->axq_depth) {
3083 DPRINTF(sc, ATH_DEBUG_BEACON,
3084 "%s: cabq did not drain, mcastq %u cabq %u\n",
3085 __func__, nmcastq, cabq->axq_depth);
3086 sc->sc_stats.ast_cabq_busy++;
3087 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) {
3089 * CABQ traffic from a previous vap is still pending.
3090 * We must drain the q before this beacon frame goes
3091 * out as otherwise this vap's stations will get cab
3092 * frames from a different vap.
3093 * XXX could be slow causing us to miss DBA
3095 ath_tx_draintxq(sc, cabq);
3098 ath_beacon_setup(sc, bf);
3099 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
3102 * Enable the CAB queue before the beacon queue to
3103 * insure cab frames are triggered by this beacon.
3105 if (avp->av_boff.bo_tim[4] & 1) {
3106 struct ath_hal *ah = sc->sc_ah;
3108 /* NB: only at DTIM */
3110 ATH_TXQ_LOCK(&avp->av_mcastq);
3112 struct ath_buf *bfm;
3115 * Move frames from the s/w mcast q to the h/w cab q.
3118 bfm = STAILQ_FIRST(&avp->av_mcastq.axq_q);
3119 if (cabq->axq_link != NULL) {
3120 *cabq->axq_link = bfm->bf_daddr;
3122 ath_hal_puttxbuf(ah, cabq->axq_qnum,
3124 ath_txqmove(cabq, &avp->av_mcastq);
3126 sc->sc_stats.ast_cabq_xmit += nmcastq;
3128 /* NB: gated by beacon so safe to start here */
3129 ath_hal_txstart(ah, cabq->axq_qnum);
3130 ATH_TXQ_UNLOCK(cabq);
3131 ATH_TXQ_UNLOCK(&avp->av_mcastq);
3137 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap)
3139 struct ath_vap *avp = ATH_VAP(vap);
3140 struct ath_hal *ah = sc->sc_ah;
3145 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
3148 * Update dynamic beacon contents. If this returns
3149 * non-zero then we need to remap the memory because
3150 * the beacon frame changed size (probably because
3151 * of the TIM bitmap).
3155 if (ieee80211_beacon_update(bf->bf_node, &avp->av_boff, m, 0)) {
3156 /* XXX too conservative? */
3157 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3158 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
3159 bf->bf_segs, &bf->bf_nseg,
3162 if_printf(vap->iv_ifp,
3163 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
3168 ath_beacon_setup(sc, bf);
3169 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
3171 /* NB: caller is known to have already stopped tx dma */
3172 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
3173 ath_hal_txstart(ah, sc->sc_bhalq);
3177 * Reset the hardware after detecting beacons have stopped.
3180 ath_bstuck_proc(void *arg, int pending)
3182 struct ath_softc *sc = arg;
3183 struct ifnet *ifp = sc->sc_ifp;
3185 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
3191 * Reclaim beacon resources and return buffer to the pool.
3194 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf)
3197 if (bf->bf_m != NULL) {
3198 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3202 if (bf->bf_node != NULL) {
3203 ieee80211_free_node(bf->bf_node);
3206 STAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list);
3210 * Reclaim beacon resources.
3213 ath_beacon_free(struct ath_softc *sc)
3217 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
3218 if (bf->bf_m != NULL) {
3219 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3223 if (bf->bf_node != NULL) {
3224 ieee80211_free_node(bf->bf_node);
3231 * Configure the beacon and sleep timers.
3233 * When operating as an AP this resets the TSF and sets
3234 * up the hardware to notify us when we need to issue beacons.
3236 * When operating in station mode this sets up the beacon
3237 * timers according to the timestamp of the last received
3238 * beacon and the current TSF, configures PCF and DTIM
3239 * handling, programs the sleep registers so the hardware
3240 * will wakeup in time to receive beacons, and configures
3241 * the beacon miss handling so we'll receive a BMISS
3242 * interrupt when we stop seeing beacons from the AP
3243 * we've associated with.
3246 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap)
3248 #define TSF_TO_TU(_h,_l) \
3249 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
3251 struct ath_hal *ah = sc->sc_ah;
3252 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3253 struct ieee80211_node *ni;
3254 u_int32_t nexttbtt, intval, tsftu;
3258 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */
3261 /* extract tstamp from last beacon and convert to TU */
3262 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4),
3263 LE_READ_4(ni->ni_tstamp.data));
3264 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
3266 * For multi-bss ap support beacons are either staggered
3267 * evenly over N slots or burst together. For the former
3268 * arrange for the SWBA to be delivered for each slot.
3269 * Slots that are not occupied will generate nothing.
3271 /* NB: the beacon interval is kept internally in TU's */
3272 intval = ni->ni_intval & HAL_BEACON_PERIOD;
3273 if (sc->sc_stagbeacons)
3274 intval /= ATH_BCBUF;
3276 /* NB: the beacon interval is kept internally in TU's */
3277 intval = ni->ni_intval & HAL_BEACON_PERIOD;
3279 if (nexttbtt == 0) /* e.g. for ap mode */
3281 else if (intval) /* NB: can be 0 for monitor mode */
3282 nexttbtt = roundup(nexttbtt, intval);
3283 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
3284 __func__, nexttbtt, intval, ni->ni_intval);
3285 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) {
3286 HAL_BEACON_STATE bs;
3287 int dtimperiod, dtimcount;
3288 int cfpperiod, cfpcount;
3291 * Setup dtim and cfp parameters according to
3292 * last beacon we received (which may be none).
3294 dtimperiod = ni->ni_dtim_period;
3295 if (dtimperiod <= 0) /* NB: 0 if not known */
3297 dtimcount = ni->ni_dtim_count;
3298 if (dtimcount >= dtimperiod) /* NB: sanity check */
3299 dtimcount = 0; /* XXX? */
3300 cfpperiod = 1; /* NB: no PCF support yet */
3303 * Pull nexttbtt forward to reflect the current
3304 * TSF and calculate dtim+cfp state for the result.
3306 tsf = ath_hal_gettsf64(ah);
3307 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
3310 if (--dtimcount < 0) {
3311 dtimcount = dtimperiod - 1;
3313 cfpcount = cfpperiod - 1;
3315 } while (nexttbtt < tsftu);
3316 memset(&bs, 0, sizeof(bs));
3317 bs.bs_intval = intval;
3318 bs.bs_nexttbtt = nexttbtt;
3319 bs.bs_dtimperiod = dtimperiod*intval;
3320 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
3321 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
3322 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
3323 bs.bs_cfpmaxduration = 0;
3326 * The 802.11 layer records the offset to the DTIM
3327 * bitmap while receiving beacons; use it here to
3328 * enable h/w detection of our AID being marked in
3329 * the bitmap vector (to indicate frames for us are
3330 * pending at the AP).
3331 * XXX do DTIM handling in s/w to WAR old h/w bugs
3332 * XXX enable based on h/w rev for newer chips
3334 bs.bs_timoffset = ni->ni_timoff;
3337 * Calculate the number of consecutive beacons to miss
3338 * before taking a BMISS interrupt.
3339 * Note that we clamp the result to at most 10 beacons.
3341 bs.bs_bmissthreshold = vap->iv_bmissthreshold;
3342 if (bs.bs_bmissthreshold > 10)
3343 bs.bs_bmissthreshold = 10;
3344 else if (bs.bs_bmissthreshold <= 0)
3345 bs.bs_bmissthreshold = 1;
3348 * Calculate sleep duration. The configuration is
3349 * given in ms. We insure a multiple of the beacon
3350 * period is used. Also, if the sleep duration is
3351 * greater than the DTIM period then it makes senses
3352 * to make it a multiple of that.
3354 * XXX fixed at 100ms
3356 bs.bs_sleepduration =
3357 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
3358 if (bs.bs_sleepduration > bs.bs_dtimperiod)
3359 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
3361 DPRINTF(sc, ATH_DEBUG_BEACON,
3362 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n"
3369 , bs.bs_bmissthreshold
3370 , bs.bs_sleepduration
3372 , bs.bs_cfpmaxduration
3376 ath_hal_intrset(ah, 0);
3377 ath_hal_beacontimers(ah, &bs);
3378 sc->sc_imask |= HAL_INT_BMISS;
3379 ath_hal_intrset(ah, sc->sc_imask);
3381 ath_hal_intrset(ah, 0);
3382 if (nexttbtt == intval)
3383 intval |= HAL_BEACON_RESET_TSF;
3384 if (ic->ic_opmode == IEEE80211_M_IBSS) {
3386 * In IBSS mode enable the beacon timers but only
3387 * enable SWBA interrupts if we need to manually
3388 * prepare beacon frames. Otherwise we use a
3389 * self-linked tx descriptor and let the hardware
3392 intval |= HAL_BEACON_ENA;
3393 if (!sc->sc_hasveol)
3394 sc->sc_imask |= HAL_INT_SWBA;
3395 if ((intval & HAL_BEACON_RESET_TSF) == 0) {
3397 * Pull nexttbtt forward to reflect
3400 tsf = ath_hal_gettsf64(ah);
3401 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
3404 } while (nexttbtt < tsftu);
3406 ath_beaconq_config(sc);
3407 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
3409 * In AP mode we enable the beacon timers and
3410 * SWBA interrupts to prepare beacon frames.
3412 intval |= HAL_BEACON_ENA;
3413 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
3414 ath_beaconq_config(sc);
3416 ath_hal_beaconinit(ah, nexttbtt, intval);
3417 sc->sc_bmisscount = 0;
3418 ath_hal_intrset(ah, sc->sc_imask);
3420 * When using a self-linked beacon descriptor in
3421 * ibss mode load it once here.
3423 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
3424 ath_beacon_start_adhoc(sc, vap);
3426 sc->sc_syncbeacon = 0;
3432 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3434 bus_addr_t *paddr = (bus_addr_t*) arg;
3435 KASSERT(error == 0, ("error %u on bus_dma callback", error));
3436 *paddr = segs->ds_addr;
3440 ath_descdma_setup(struct ath_softc *sc,
3441 struct ath_descdma *dd, ath_bufhead *head,
3442 const char *name, int nbuf, int ndesc)
3444 #define DS2PHYS(_dd, _ds) \
3445 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
3446 struct ifnet *ifp = sc->sc_ifp;
3447 struct ath_desc *ds;
3449 int i, bsize, error;
3451 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n",
3452 __func__, name, nbuf, ndesc);
3455 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
3458 * Setup DMA descriptor area.
3460 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
3461 PAGE_SIZE, 0, /* alignment, bounds */
3462 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3463 BUS_SPACE_MAXADDR, /* highaddr */
3464 NULL, NULL, /* filter, filterarg */
3465 dd->dd_desc_len, /* maxsize */
3467 dd->dd_desc_len, /* maxsegsize */
3468 BUS_DMA_ALLOCNOW, /* flags */
3469 NULL, /* lockfunc */
3473 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
3477 /* allocate descriptors */
3478 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap);
3480 if_printf(ifp, "unable to create dmamap for %s descriptors, "
3481 "error %u\n", dd->dd_name, error);
3485 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
3486 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
3489 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
3490 "error %u\n", nbuf * ndesc, dd->dd_name, error);
3494 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
3495 dd->dd_desc, dd->dd_desc_len,
3496 ath_load_cb, &dd->dd_desc_paddr,
3499 if_printf(ifp, "unable to map %s descriptors, error %u\n",
3500 dd->dd_name, error);
3505 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
3506 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len,
3507 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len);
3509 /* allocate rx buffers */
3510 bsize = sizeof(struct ath_buf) * nbuf;
3511 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
3513 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
3514 dd->dd_name, bsize);
3520 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
3522 bf->bf_daddr = DS2PHYS(dd, ds);
3523 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
3526 if_printf(ifp, "unable to create dmamap for %s "
3527 "buffer %u, error %u\n", dd->dd_name, i, error);
3528 ath_descdma_cleanup(sc, dd, head);
3531 STAILQ_INSERT_TAIL(head, bf, bf_list);
3535 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3537 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3539 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
3541 bus_dma_tag_destroy(dd->dd_dmat);
3542 memset(dd, 0, sizeof(*dd));
3548 ath_descdma_cleanup(struct ath_softc *sc,
3549 struct ath_descdma *dd, ath_bufhead *head)
3552 struct ieee80211_node *ni;
3554 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3555 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3556 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
3557 bus_dma_tag_destroy(dd->dd_dmat);
3559 STAILQ_FOREACH(bf, head, bf_list) {
3564 if (bf->bf_dmamap != NULL) {
3565 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
3566 bf->bf_dmamap = NULL;
3572 * Reclaim node reference.
3574 ieee80211_free_node(ni);
3579 free(dd->dd_bufptr, M_ATHDEV);
3580 memset(dd, 0, sizeof(*dd));
3584 ath_desc_alloc(struct ath_softc *sc)
3588 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
3589 "rx", ath_rxbuf, 1);
3593 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
3594 "tx", ath_txbuf, ATH_TXDESC);
3596 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
3600 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
3601 "beacon", ATH_BCBUF, 1);
3603 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3604 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
3611 ath_desc_free(struct ath_softc *sc)
3614 if (sc->sc_bdma.dd_desc_len != 0)
3615 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
3616 if (sc->sc_txdma.dd_desc_len != 0)
3617 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
3618 if (sc->sc_rxdma.dd_desc_len != 0)
3619 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
3622 static struct ieee80211_node *
3623 ath_node_alloc(struct ieee80211_node_table *nt)
3625 struct ieee80211com *ic = nt->nt_ic;
3626 struct ath_softc *sc = ic->ic_ifp->if_softc;
3627 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
3628 struct ath_node *an;
3630 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
3635 ath_rate_node_init(sc, an);
3637 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an);
3638 return &an->an_node;
3642 ath_node_free(struct ieee80211_node *ni)
3644 struct ieee80211com *ic = ni->ni_ic;
3645 struct ath_softc *sc = ic->ic_ifp->if_softc;
3647 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni);
3649 ath_rate_node_cleanup(sc, ATH_NODE(ni));
3650 sc->sc_node_free(ni);
3654 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise)
3656 struct ieee80211com *ic = ni->ni_ic;
3657 struct ath_softc *sc = ic->ic_ifp->if_softc;
3658 struct ath_hal *ah = sc->sc_ah;
3661 *rssi = ic->ic_node_getrssi(ni);
3662 if (ni->ni_chan != IEEE80211_CHAN_ANYC) {
3663 ath_mapchan(&hchan, ni->ni_chan);
3664 *noise = ath_hal_getchannoise(ah, &hchan);
3666 *noise = -95; /* nominally correct */
3670 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
3672 struct ath_hal *ah = sc->sc_ah;
3675 struct ath_desc *ds;
3680 * NB: by assigning a page to the rx dma buffer we
3681 * implicitly satisfy the Atheros requirement that
3682 * this buffer be cache-line-aligned and sized to be
3683 * multiple of the cache line size. Not doing this
3684 * causes weird stuff to happen (for the 5210 at least).
3686 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3688 DPRINTF(sc, ATH_DEBUG_ANY,
3689 "%s: no mbuf/cluster\n", __func__);
3690 sc->sc_stats.ast_rx_nombuf++;
3693 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
3695 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
3697 bf->bf_segs, &bf->bf_nseg,
3700 DPRINTF(sc, ATH_DEBUG_ANY,
3701 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
3703 sc->sc_stats.ast_rx_busdma++;
3707 KASSERT(bf->bf_nseg == 1,
3708 ("multi-segment packet; nseg %u", bf->bf_nseg));
3711 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
3714 * Setup descriptors. For receive we always terminate
3715 * the descriptor list with a self-linked entry so we'll
3716 * not get overrun under high load (as can happen with a
3717 * 5212 when ANI processing enables PHY error frames).
3719 * To insure the last descriptor is self-linked we create
3720 * each descriptor as self-linked and add it to the end. As
3721 * each additional descriptor is added the previous self-linked
3722 * entry is ``fixed'' naturally. This should be safe even
3723 * if DMA is happening. When processing RX interrupts we
3724 * never remove/process the last, self-linked, entry on the
3725 * descriptor list. This insures the hardware always has
3726 * someplace to write a new frame.
3729 ds->ds_link = bf->bf_daddr; /* link to self */
3730 ds->ds_data = bf->bf_segs[0].ds_addr;
3731 ath_hal_setuprxdesc(ah, ds
3732 , m->m_len /* buffer size */
3736 if (sc->sc_rxlink != NULL)
3737 *sc->sc_rxlink = bf->bf_daddr;
3738 sc->sc_rxlink = &ds->ds_link;
3743 * Extend 15-bit time stamp from rx descriptor to
3744 * a full 64-bit TSF using the specified TSF.
3746 static __inline u_int64_t
3747 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf)
3749 if ((tsf & 0x7fff) < rstamp)
3751 return ((tsf &~ 0x7fff) | rstamp);
3755 * Intercept management frames to collect beacon rssi data
3756 * and to do ibss merges.
3759 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
3760 int subtype, int rssi, int noise, u_int32_t rstamp)
3762 struct ieee80211vap *vap = ni->ni_vap;
3763 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
3766 * Call up first so subsequent work can use information
3767 * potentially stored in the node (e.g. for ibss merge).
3769 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, noise, rstamp);
3771 case IEEE80211_FC0_SUBTYPE_BEACON:
3772 /* update rssi statistics for use by the hal */
3773 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
3774 if (sc->sc_syncbeacon &&
3775 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) {
3777 * Resync beacon timers using the tsf of the beacon
3778 * frame we just received.
3780 ath_beacon_config(sc, vap);
3783 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
3784 if (vap->iv_opmode == IEEE80211_M_IBSS &&
3785 vap->iv_state == IEEE80211_S_RUN) {
3786 u_int64_t tsf = ath_extend_tsf(rstamp,
3787 ath_hal_gettsf64(sc->sc_ah));
3789 * Handle ibss merge as needed; check the tsf on the
3790 * frame before attempting the merge. The 802.11 spec
3791 * says the station should change it's bssid to match
3792 * the oldest station with the same ssid, where oldest
3793 * is determined by the tsf. Note that hardware
3794 * reconfiguration happens through callback to
3795 * ath_newstate as the state machine will go from
3796 * RUN -> RUN when this happens.
3798 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
3799 DPRINTF(sc, ATH_DEBUG_STATE,
3800 "ibss merge, rstamp %u tsf %ju "
3801 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
3802 (uintmax_t)ni->ni_tstamp.tsf);
3803 (void) ieee80211_ibss_merge(ni);
3811 * Set the default antenna.
3814 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
3816 struct ath_hal *ah = sc->sc_ah;
3818 /* XXX block beacon interrupts */
3819 ath_hal_setdefantenna(ah, antenna);
3820 if (sc->sc_defant != antenna)
3821 sc->sc_stats.ast_ant_defswitch++;
3822 sc->sc_defant = antenna;
3823 sc->sc_rxotherant = 0;
3827 ath_rx_tap(struct ifnet *ifp, struct mbuf *m,
3828 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
3830 #define CHANNEL_HT (CHANNEL_HT20|CHANNEL_HT40PLUS|CHANNEL_HT40MINUS)
3831 struct ath_softc *sc = ifp->if_softc;
3835 * Discard anything shorter than an ack or cts.
3837 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) {
3838 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n",
3839 __func__, m->m_pkthdr.len);
3840 sc->sc_stats.ast_rx_tooshort++;
3844 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
3845 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
3846 #if HAL_ABI_VERSION >= 0x07050400
3847 if (sc->sc_curchan.channelFlags & CHANNEL_HT) {
3849 * For HT operation we must specify the channel
3850 * attributes for each packet since they vary.
3851 * We deduce this by from HT40 bit in the rx
3852 * status and the MCS/legacy rate bit.
3854 sc->sc_rx_th.wr_chan_flags &= ~IEEE80211_CHAN_HT;
3855 if (sc->sc_rx_th.wr_rate & 0x80) { /* HT rate */
3857 sc->sc_rx_th.wr_chan_flags |=
3858 (rs->rs_flags & HAL_RX_2040) ?
3859 IEEE80211_CHAN_HT40U : IEEE80211_CHAN_HT20;
3860 if ((rs->rs_flags & HAL_RX_GI) == 0)
3861 sc->sc_rx_th.wr_flags |=
3862 IEEE80211_RADIOTAP_F_SHORTGI;
3866 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(rs->rs_tstamp, tsf));
3867 if (rs->rs_status & HAL_RXERR_CRC)
3868 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
3869 /* XXX propagate other error flags from descriptor */
3870 sc->sc_rx_th.wr_antsignal = rs->rs_rssi + nf;
3871 sc->sc_rx_th.wr_antnoise = nf;
3872 sc->sc_rx_th.wr_antenna = rs->rs_antenna;
3874 bpf_mtap2(ifp->if_bpf, &sc->sc_rx_th, sc->sc_rx_th_len, m);
3881 ath_handle_micerror(struct ieee80211com *ic,
3882 struct ieee80211_frame *wh, int keyix)
3884 struct ieee80211_node *ni;
3886 /* XXX recheck MIC to deal w/ chips that lie */
3887 /* XXX discard MIC errors on !data frames */
3888 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh);
3890 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix);
3891 ieee80211_free_node(ni);
3896 ath_rx_proc(void *arg, int npending)
3898 #define PA2DESC(_sc, _pa) \
3899 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
3900 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
3901 struct ath_softc *sc = arg;
3903 struct ifnet *ifp = sc->sc_ifp;
3904 struct ieee80211com *ic = ifp->if_l2com;
3905 struct ath_hal *ah = sc->sc_ah;
3906 struct ath_desc *ds;
3907 struct ath_rx_status *rs;
3909 struct ieee80211_node *ni;
3910 int len, type, ngood;
3916 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
3918 nf = ath_hal_getchannoise(ah, &sc->sc_curchan);
3919 tsf = ath_hal_gettsf64(ah);
3921 bf = STAILQ_FIRST(&sc->sc_rxbuf);
3922 if (bf == NULL) { /* NB: shouldn't happen */
3923 if_printf(ifp, "%s: no buffer!\n", __func__);
3927 if (m == NULL) { /* NB: shouldn't happen */
3929 * If mbuf allocation failed previously there
3930 * will be no mbuf; try again to re-populate it.
3932 /* XXX make debug msg */
3933 if_printf(ifp, "%s: no mbuf!\n", __func__);
3934 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
3938 if (ds->ds_link == bf->bf_daddr) {
3939 /* NB: never process the self-linked entry at the end */
3942 /* XXX sync descriptor memory */
3944 * Must provide the virtual address of the current
3945 * descriptor, the physical address, and the virtual
3946 * address of the next descriptor in the h/w chain.
3947 * This allows the HAL to look ahead to see if the
3948 * hardware is done with a descriptor by checking the
3949 * done bit in the following descriptor and the address
3950 * of the current descriptor the DMA engine is working
3951 * on. All this is necessary because of our use of
3952 * a self-linked list to avoid rx overruns.
3954 rs = &bf->bf_status.ds_rxstat;
3955 status = ath_hal_rxprocdesc(ah, ds,
3956 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
3958 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
3959 ath_printrxbuf(bf, 0, status == HAL_OK);
3961 if (status == HAL_EINPROGRESS)
3963 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
3964 if (rs->rs_status != 0) {
3965 if (rs->rs_status & HAL_RXERR_CRC)
3966 sc->sc_stats.ast_rx_crcerr++;
3967 if (rs->rs_status & HAL_RXERR_FIFO)
3968 sc->sc_stats.ast_rx_fifoerr++;
3969 if (rs->rs_status & HAL_RXERR_PHY) {
3970 sc->sc_stats.ast_rx_phyerr++;
3971 phyerr = rs->rs_phyerr & 0x1f;
3972 sc->sc_stats.ast_rx_phy[phyerr]++;
3973 goto rx_error; /* NB: don't count in ierrors */
3975 if (rs->rs_status & HAL_RXERR_DECRYPT) {
3977 * Decrypt error. If the error occurred
3978 * because there was no hardware key, then
3979 * let the frame through so the upper layers
3980 * can process it. This is necessary for 5210
3981 * parts which have no way to setup a ``clear''
3984 * XXX do key cache faulting
3986 if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
3988 sc->sc_stats.ast_rx_badcrypt++;
3990 if (rs->rs_status & HAL_RXERR_MIC) {
3991 sc->sc_stats.ast_rx_badmic++;
3993 * Do minimal work required to hand off
3994 * the 802.11 header for notifcation.
3996 /* XXX frag's and qos frames */
3997 len = rs->rs_datalen;
3998 if (len >= sizeof (struct ieee80211_frame)) {
3999 bus_dmamap_sync(sc->sc_dmat,
4001 BUS_DMASYNC_POSTREAD);
4002 ath_handle_micerror(ic,
4003 mtod(m, struct ieee80211_frame *),
4005 rs->rs_keyix-32 : rs->rs_keyix);
4011 * Cleanup any pending partial frame.
4013 if (sc->sc_rxpending != NULL) {
4014 m_freem(sc->sc_rxpending);
4015 sc->sc_rxpending = NULL;
4018 * When a tap is present pass error frames
4019 * that have been requested. By default we
4020 * pass decrypt+mic errors but others may be
4021 * interesting (e.g. crc).
4023 if (bpf_peers_present(ifp->if_bpf) &&
4024 (rs->rs_status & sc->sc_monpass)) {
4025 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
4026 BUS_DMASYNC_POSTREAD);
4027 /* NB: bpf needs the mbuf length setup */
4028 len = rs->rs_datalen;
4029 m->m_pkthdr.len = m->m_len = len;
4030 (void) ath_rx_tap(ifp, m, rs, tsf, nf);
4032 /* XXX pass MIC errors up for s/w reclaculation */
4037 * Sync and unmap the frame. At this point we're
4038 * committed to passing the mbuf somewhere so clear
4039 * bf_m; this means a new mbuf must be allocated
4040 * when the rx descriptor is setup again to receive
4043 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
4044 BUS_DMASYNC_POSTREAD);
4045 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4048 len = rs->rs_datalen;
4053 * Frame spans multiple descriptors; save
4054 * it for the next completed descriptor, it
4055 * will be used to construct a jumbogram.
4057 if (sc->sc_rxpending != NULL) {
4058 /* NB: max frame size is currently 2 clusters */
4059 sc->sc_stats.ast_rx_toobig++;
4060 m_freem(sc->sc_rxpending);
4062 m->m_pkthdr.rcvif = ifp;
4063 m->m_pkthdr.len = len;
4064 sc->sc_rxpending = m;
4066 } else if (sc->sc_rxpending != NULL) {
4068 * This is the second part of a jumbogram,
4069 * chain it to the first mbuf, adjust the
4070 * frame length, and clear the rxpending state.
4072 sc->sc_rxpending->m_next = m;
4073 sc->sc_rxpending->m_pkthdr.len += len;
4074 m = sc->sc_rxpending;
4075 sc->sc_rxpending = NULL;
4078 * Normal single-descriptor receive; setup
4079 * the rcvif and packet length.
4081 m->m_pkthdr.rcvif = ifp;
4082 m->m_pkthdr.len = len;
4086 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
4088 if (bpf_peers_present(ifp->if_bpf) &&
4089 !ath_rx_tap(ifp, m, rs, tsf, nf)) {
4090 m_freem(m); /* XXX reclaim */
4095 * From this point on we assume the frame is at least
4096 * as large as ieee80211_frame_min; verify that.
4098 if (len < IEEE80211_MIN_LEN) {
4099 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n",
4101 sc->sc_stats.ast_rx_tooshort++;
4106 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
4107 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len,
4108 sc->sc_hwmap[rs->rs_rate].ieeerate,
4112 m_adj(m, -IEEE80211_CRC_LEN);
4115 * Locate the node for sender, track state, and then
4116 * pass the (referenced) node up to the 802.11 layer
4119 ni = ieee80211_find_rxnode_withkey(ic,
4120 mtod(m, const struct ieee80211_frame_min *),
4121 rs->rs_keyix == HAL_RXKEYIX_INVALID ?
4122 IEEE80211_KEYIX_NONE : rs->rs_keyix);
4125 * Sending station is known, dispatch directly.
4127 type = ieee80211_input(ni, m,
4128 rs->rs_rssi, nf, rs->rs_tstamp);
4129 ieee80211_free_node(ni);
4131 * Arrange to update the last rx timestamp only for
4132 * frames from our ap when operating in station mode.
4133 * This assumes the rx key is always setup when
4136 if (ic->ic_opmode == IEEE80211_M_STA &&
4137 rs->rs_keyix != HAL_RXKEYIX_INVALID)
4140 type = ieee80211_input_all(ic, m,
4141 rs->rs_rssi, nf, rs->rs_tstamp);
4144 * Track rx rssi and do any rx antenna management.
4146 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
4147 if (sc->sc_diversity) {
4149 * When using fast diversity, change the default rx
4150 * antenna if diversity chooses the other antenna 3
4153 if (sc->sc_defant != rs->rs_antenna) {
4154 if (++sc->sc_rxotherant >= 3)
4155 ath_setdefantenna(sc, rs->rs_antenna);
4157 sc->sc_rxotherant = 0;
4159 if (sc->sc_softled) {
4161 * Blink for any data frame. Otherwise do a
4162 * heartbeat-style blink when idle. The latter
4163 * is mainly for station mode where we depend on
4164 * periodic beacon frames to trigger the poll event.
4166 if (type == IEEE80211_FC0_TYPE_DATA) {
4167 sc->sc_rxrate = rs->rs_rate;
4168 ath_led_event(sc, ATH_LED_RX);
4169 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
4170 ath_led_event(sc, ATH_LED_POLL);
4173 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
4174 } while (ath_rxbuf_init(sc, bf) == 0);
4176 /* rx signal state monitoring */
4177 ath_hal_rxmonitor(ah, &sc->sc_halstats, &sc->sc_curchan);
4179 sc->sc_lastrx = tsf;
4181 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0 &&
4182 !IFQ_IS_EMPTY(&ifp->if_snd))
4189 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
4191 txq->axq_qnum = qnum;
4193 txq->axq_intrcnt = 0;
4194 txq->axq_link = NULL;
4195 STAILQ_INIT(&txq->axq_q);
4196 ATH_TXQ_LOCK_INIT(sc, txq);
4197 TAILQ_INIT(&txq->axq_stageq);
4198 txq->axq_curage = 0;
4202 * Setup a h/w transmit queue.
4204 static struct ath_txq *
4205 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
4207 #define N(a) (sizeof(a)/sizeof(a[0]))
4208 struct ath_hal *ah = sc->sc_ah;
4212 memset(&qi, 0, sizeof(qi));
4213 qi.tqi_subtype = subtype;
4214 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
4215 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
4216 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
4218 * Enable interrupts only for EOL and DESC conditions.
4219 * We mark tx descriptors to receive a DESC interrupt
4220 * when a tx queue gets deep; otherwise waiting for the
4221 * EOL to reap descriptors. Note that this is done to
4222 * reduce interrupt load and this only defers reaping
4223 * descriptors, never transmitting frames. Aside from
4224 * reducing interrupts this also permits more concurrency.
4225 * The only potential downside is if the tx queue backs
4226 * up in which case the top half of the kernel may backup
4227 * due to a lack of tx descriptors.
4229 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE | HAL_TXQ_TXDESCINT_ENABLE;
4230 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
4233 * NB: don't print a message, this happens
4234 * normally on parts with too few tx queues
4238 if (qnum >= N(sc->sc_txq)) {
4239 device_printf(sc->sc_dev,
4240 "hal qnum %u out of range, max %zu!\n",
4241 qnum, N(sc->sc_txq));
4242 ath_hal_releasetxqueue(ah, qnum);
4245 if (!ATH_TXQ_SETUP(sc, qnum)) {
4246 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
4247 sc->sc_txqsetup |= 1<<qnum;
4249 return &sc->sc_txq[qnum];
4254 * Setup a hardware data transmit queue for the specified
4255 * access control. The hal may not support all requested
4256 * queues in which case it will return a reference to a
4257 * previously setup queue. We record the mapping from ac's
4258 * to h/w queues for use by ath_tx_start and also track
4259 * the set of h/w queues being used to optimize work in the
4260 * transmit interrupt handler and related routines.
4263 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
4265 #define N(a) (sizeof(a)/sizeof(a[0]))
4266 struct ath_txq *txq;
4268 if (ac >= N(sc->sc_ac2q)) {
4269 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
4270 ac, N(sc->sc_ac2q));
4273 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
4275 sc->sc_ac2q[ac] = txq;
4283 * Update WME parameters for a transmit queue.
4286 ath_txq_update(struct ath_softc *sc, int ac)
4288 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
4289 #define ATH_TXOP_TO_US(v) (v<<5)
4290 struct ifnet *ifp = sc->sc_ifp;
4291 struct ieee80211com *ic = ifp->if_l2com;
4292 struct ath_txq *txq = sc->sc_ac2q[ac];
4293 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
4294 struct ath_hal *ah = sc->sc_ah;
4297 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
4298 qi.tqi_aifs = wmep->wmep_aifsn;
4299 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
4300 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
4301 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
4303 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
4304 if_printf(ifp, "unable to update hardware queue "
4305 "parameters for %s traffic!\n",
4306 ieee80211_wme_acnames[ac]);
4309 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
4312 #undef ATH_TXOP_TO_US
4313 #undef ATH_EXPONENT_TO_VALUE
4317 * Callback from the 802.11 layer to update WME parameters.
4320 ath_wme_update(struct ieee80211com *ic)
4322 struct ath_softc *sc = ic->ic_ifp->if_softc;
4324 return !ath_txq_update(sc, WME_AC_BE) ||
4325 !ath_txq_update(sc, WME_AC_BK) ||
4326 !ath_txq_update(sc, WME_AC_VI) ||
4327 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
4331 * Reclaim resources for a setup queue.
4334 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
4337 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
4338 ATH_TXQ_LOCK_DESTROY(txq);
4339 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
4343 * Reclaim all tx queue resources.
4346 ath_tx_cleanup(struct ath_softc *sc)
4350 ATH_TXBUF_LOCK_DESTROY(sc);
4351 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4352 if (ATH_TXQ_SETUP(sc, i))
4353 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
4357 * Return h/w rate index for an IEEE rate (w/o basic rate bit).
4360 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate)
4364 for (i = 0; i < rt->rateCount; i++)
4365 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate)
4367 return 0; /* NB: lowest rate */
4371 * Reclaim mbuf resources. For fragmented frames we
4372 * need to claim each frag chained with m_nextpkt.
4375 ath_freetx(struct mbuf *m)
4380 next = m->m_nextpkt;
4381 m->m_nextpkt = NULL;
4383 } while ((m = next) != NULL);
4387 ath_tx_dmasetup(struct ath_softc *sc, struct ath_buf *bf, struct mbuf *m0)
4393 * Load the DMA map so any coalescing is done. This
4394 * also calculates the number of descriptors we need.
4396 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
4397 bf->bf_segs, &bf->bf_nseg,
4399 if (error == EFBIG) {
4400 /* XXX packet requires too many descriptors */
4401 bf->bf_nseg = ATH_TXDESC+1;
4402 } else if (error != 0) {
4403 sc->sc_stats.ast_tx_busdma++;
4408 * Discard null packets and check for packets that
4409 * require too many TX descriptors. We try to convert
4410 * the latter to a cluster.
4412 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */
4413 sc->sc_stats.ast_tx_linear++;
4414 m = m_collapse(m0, M_DONTWAIT, ATH_TXDESC);
4417 sc->sc_stats.ast_tx_nombuf++;
4421 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
4422 bf->bf_segs, &bf->bf_nseg,
4425 sc->sc_stats.ast_tx_busdma++;
4429 KASSERT(bf->bf_nseg <= ATH_TXDESC,
4430 ("too many segments after defrag; nseg %u", bf->bf_nseg));
4431 } else if (bf->bf_nseg == 0) { /* null packet, discard */
4432 sc->sc_stats.ast_tx_nodata++;
4436 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n",
4437 __func__, m0, m0->m_pkthdr.len);
4438 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
4445 ath_tx_handoff(struct ath_softc *sc, struct ath_txq *txq, struct ath_buf *bf)
4447 struct ath_hal *ah = sc->sc_ah;
4448 struct ath_desc *ds, *ds0;
4452 * Fillin the remainder of the descriptor info.
4454 ds0 = ds = bf->bf_desc;
4455 for (i = 0; i < bf->bf_nseg; i++, ds++) {
4456 ds->ds_data = bf->bf_segs[i].ds_addr;
4457 if (i == bf->bf_nseg - 1)
4460 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
4461 ath_hal_filltxdesc(ah, ds
4462 , bf->bf_segs[i].ds_len /* segment length */
4463 , i == 0 /* first segment */
4464 , i == bf->bf_nseg - 1 /* last segment */
4465 , ds0 /* first descriptor */
4467 DPRINTF(sc, ATH_DEBUG_XMIT,
4468 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
4469 __func__, i, ds->ds_link, ds->ds_data,
4470 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
4473 * Insert the frame on the outbound list and pass it on
4474 * to the hardware. Multicast frames buffered for power
4475 * save stations and transmit from the CAB queue are stored
4476 * on a s/w only queue and loaded on to the CAB queue in
4477 * the SWBA handler since frames only go out on DTIM and
4478 * to avoid possible races.
4481 if (txq->axq_qnum != ATH_TXQ_SWQ) {
4482 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
4483 if (txq->axq_link == NULL) {
4484 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
4485 DPRINTF(sc, ATH_DEBUG_XMIT,
4486 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__,
4487 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc,
4490 *txq->axq_link = bf->bf_daddr;
4491 DPRINTF(sc, ATH_DEBUG_XMIT,
4492 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
4493 txq->axq_qnum, txq->axq_link,
4494 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth);
4496 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
4497 ath_hal_txstart(ah, txq->axq_qnum);
4499 if (txq->axq_link != NULL) {
4500 struct ath_buf *last = ATH_TXQ_LAST(txq);
4501 struct ieee80211_frame *wh;
4503 /* mark previous frame */
4504 wh = mtod(last->bf_m, struct ieee80211_frame *);
4505 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
4506 bus_dmamap_sync(sc->sc_dmat, last->bf_dmamap,
4507 BUS_DMASYNC_PREWRITE);
4509 /* link descriptor */
4510 *txq->axq_link = bf->bf_daddr;
4512 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
4513 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
4515 ATH_TXQ_UNLOCK(txq);
4519 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf,
4522 struct ieee80211vap *vap = ni->ni_vap;
4523 struct ath_vap *avp = ATH_VAP(vap);
4524 struct ath_hal *ah = sc->sc_ah;
4525 struct ifnet *ifp = sc->sc_ifp;
4526 struct ieee80211com *ic = ifp->if_l2com;
4527 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
4528 int error, iswep, ismcast, isfrag, ismrr;
4529 int keyix, hdrlen, pktlen, try0;
4530 u_int8_t rix, txrate, ctsrate;
4531 u_int8_t cix = 0xff; /* NB: silence compiler */
4532 struct ath_desc *ds;
4533 struct ath_txq *txq;
4534 struct ieee80211_frame *wh;
4535 u_int subtype, flags, ctsduration;
4537 const HAL_RATE_TABLE *rt;
4538 HAL_BOOL shortPreamble;
4539 struct ath_node *an;
4542 wh = mtod(m0, struct ieee80211_frame *);
4543 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
4544 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
4545 isfrag = m0->m_flags & M_FRAG;
4546 hdrlen = ieee80211_anyhdrsize(wh);
4548 * Packet length must not include any
4549 * pad bytes; deduct them here.
4551 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
4554 const struct ieee80211_cipher *cip;
4555 struct ieee80211_key *k;
4558 * Construct the 802.11 header+trailer for an encrypted
4559 * frame. The only reason this can fail is because of an
4560 * unknown or unsupported cipher/key type.
4562 k = ieee80211_crypto_encap(ni, m0);
4565 * This can happen when the key is yanked after the
4566 * frame was queued. Just discard the frame; the
4567 * 802.11 layer counts failures and provides
4568 * debugging/diagnostics.
4574 * Adjust the packet + header lengths for the crypto
4575 * additions and calculate the h/w key index. When
4576 * a s/w mic is done the frame will have had any mic
4577 * added to it prior to entry so m0->m_pkthdr.len will
4578 * account for it. Otherwise we need to add it to the
4582 hdrlen += cip->ic_header;
4583 pktlen += cip->ic_header + cip->ic_trailer;
4584 /* NB: frags always have any TKIP MIC done in s/w */
4585 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && !isfrag)
4586 pktlen += cip->ic_miclen;
4587 keyix = k->wk_keyix;
4589 /* packet header may have moved, reset our local pointer */
4590 wh = mtod(m0, struct ieee80211_frame *);
4591 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
4593 * Use station key cache slot, if assigned.
4595 keyix = ni->ni_ucastkey.wk_keyix;
4596 if (keyix == IEEE80211_KEYIX_NONE)
4597 keyix = HAL_TXKEYIX_INVALID;
4599 keyix = HAL_TXKEYIX_INVALID;
4601 pktlen += IEEE80211_CRC_LEN;
4604 * Load the DMA map so any coalescing is done. This
4605 * also calculates the number of descriptors we need.
4607 error = ath_tx_dmasetup(sc, bf, m0);
4610 bf->bf_node = ni; /* NB: held reference */
4611 m0 = bf->bf_m; /* NB: may have changed */
4612 wh = mtod(m0, struct ieee80211_frame *);
4614 /* setup descriptors */
4616 rt = sc->sc_currates;
4617 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
4620 * NB: the 802.11 layer marks whether or not we should
4621 * use short preamble based on the current mode and
4622 * negotiated parameters.
4624 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
4625 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
4626 shortPreamble = AH_TRUE;
4627 sc->sc_stats.ast_tx_shortpre++;
4629 shortPreamble = AH_FALSE;
4633 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
4634 ismrr = 0; /* default no multi-rate retry*/
4635 pri = M_WME_GETAC(m0); /* honor classification */
4637 * Calculate Atheros packet type from IEEE80211 packet header,
4638 * setup for rate calculations, and select h/w transmit queue.
4640 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
4641 case IEEE80211_FC0_TYPE_MGT:
4642 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
4643 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
4644 atype = HAL_PKT_TYPE_BEACON;
4645 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
4646 atype = HAL_PKT_TYPE_PROBE_RESP;
4647 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
4648 atype = HAL_PKT_TYPE_ATIM;
4650 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
4651 rix = an->an_mgmtrix;
4652 txrate = rt->info[rix].rateCode;
4654 txrate |= rt->info[rix].shortPreamble;
4655 try0 = ATH_TXMGTTRY;
4656 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
4658 case IEEE80211_FC0_TYPE_CTL:
4659 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
4660 rix = an->an_mgmtrix;
4661 txrate = rt->info[rix].rateCode;
4663 txrate |= rt->info[rix].shortPreamble;
4664 try0 = ATH_TXMGTTRY;
4665 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
4667 case IEEE80211_FC0_TYPE_DATA:
4668 atype = HAL_PKT_TYPE_NORMAL; /* default */
4670 * Data frames: multicast frames go out at a fixed rate,
4671 * otherwise consult the rate control module for the
4675 rix = an->an_mcastrix;
4676 txrate = rt->info[rix].rateCode;
4678 txrate |= rt->info[rix].shortPreamble;
4681 ath_rate_findrate(sc, an, shortPreamble, pktlen,
4682 &rix, &try0, &txrate);
4683 sc->sc_txrate = txrate; /* for LED blinking */
4684 sc->sc_lastdatarix = rix; /* for fast frames */
4685 if (try0 != ATH_TXMAXTRY)
4688 if (cap->cap_wmeParams[pri].wmep_noackPolicy)
4689 flags |= HAL_TXDESC_NOACK;
4692 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
4693 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
4698 txq = sc->sc_ac2q[pri];
4701 * When servicing one or more stations in power-save mode
4702 * (or) if there is some mcast data waiting on the mcast
4703 * queue (to prevent out of order delivery) multicast
4704 * frames must be buffered until after the beacon.
4706 if (ismcast && (vap->iv_ps_sta || avp->av_mcastq.axq_depth))
4707 txq = &avp->av_mcastq;
4710 * Calculate miscellaneous flags.
4713 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
4714 } else if (pktlen > vap->iv_rtsthreshold &&
4715 (ni->ni_ath_flags & IEEE80211_NODE_FF) == 0) {
4716 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
4717 cix = rt->info[rix].controlRate;
4718 sc->sc_stats.ast_tx_rts++;
4720 if (flags & HAL_TXDESC_NOACK) /* NB: avoid double counting */
4721 sc->sc_stats.ast_tx_noack++;
4724 * If 802.11g protection is enabled, determine whether
4725 * to use RTS/CTS or just CTS. Note that this is only
4726 * done for OFDM unicast frames.
4728 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
4729 rt->info[rix].phy == IEEE80211_T_OFDM &&
4730 (flags & HAL_TXDESC_NOACK) == 0) {
4731 /* XXX fragments must use CCK rates w/ protection */
4732 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
4733 flags |= HAL_TXDESC_RTSENA;
4734 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
4735 flags |= HAL_TXDESC_CTSENA;
4738 * For frags it would be desirable to use the
4739 * highest CCK rate for RTS/CTS. But stations
4740 * farther away may detect it at a lower CCK rate
4741 * so use the configured protection rate instead
4744 cix = rt->info[sc->sc_protrix].controlRate;
4746 cix = rt->info[sc->sc_protrix].controlRate;
4747 sc->sc_stats.ast_tx_protect++;
4751 * Calculate duration. This logically belongs in the 802.11
4752 * layer but it lacks sufficient information to calculate it.
4754 if ((flags & HAL_TXDESC_NOACK) == 0 &&
4755 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
4758 dur = rt->info[rix].spAckDuration;
4760 dur = rt->info[rix].lpAckDuration;
4761 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG) {
4762 dur += dur; /* additional SIFS+ACK */
4763 KASSERT(m0->m_nextpkt != NULL, ("no fragment"));
4765 * Include the size of next fragment so NAV is
4766 * updated properly. The last fragment uses only
4769 dur += ath_hal_computetxtime(ah, rt,
4770 m0->m_nextpkt->m_pkthdr.len,
4771 rix, shortPreamble);
4775 * Force hardware to use computed duration for next
4776 * fragment by disabling multi-rate retry which updates
4777 * duration based on the multi-rate duration table.
4780 try0 = ATH_TXMGTTRY; /* XXX? */
4782 *(u_int16_t *)wh->i_dur = htole16(dur);
4786 * Calculate RTS/CTS rate and duration if needed.
4789 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
4791 * CTS transmit rate is derived from the transmit rate
4792 * by looking in the h/w rate table. We must also factor
4793 * in whether or not a short preamble is to be used.
4795 /* NB: cix is set above where RTS/CTS is enabled */
4796 KASSERT(cix != 0xff, ("cix not setup"));
4797 ctsrate = rt->info[cix].rateCode;
4799 * Compute the transmit duration based on the frame
4800 * size and the size of an ACK frame. We call into the
4801 * HAL to do the computation since it depends on the
4802 * characteristics of the actual PHY being used.
4804 * NB: CTS is assumed the same size as an ACK so we can
4805 * use the precalculated ACK durations.
4807 if (shortPreamble) {
4808 ctsrate |= rt->info[cix].shortPreamble;
4809 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
4810 ctsduration += rt->info[cix].spAckDuration;
4811 ctsduration += ath_hal_computetxtime(ah,
4812 rt, pktlen, rix, AH_TRUE);
4813 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
4814 ctsduration += rt->info[rix].spAckDuration;
4816 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
4817 ctsduration += rt->info[cix].lpAckDuration;
4818 ctsduration += ath_hal_computetxtime(ah,
4819 rt, pktlen, rix, AH_FALSE);
4820 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
4821 ctsduration += rt->info[rix].lpAckDuration;
4824 * Must disable multi-rate retry when using RTS/CTS.
4827 try0 = ATH_TXMGTTRY; /* XXX */
4832 * At this point we are committed to sending the frame
4833 * and we don't need to look at m_nextpkt; clear it in
4834 * case this frame is part of frag chain.
4836 m0->m_nextpkt = NULL;
4838 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
4839 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len,
4840 sc->sc_hwmap[txrate].ieeerate, -1);
4842 if (bpf_peers_present(ifp->if_bpf)) {
4843 u_int64_t tsf = ath_hal_gettsf64(ah);
4845 sc->sc_tx_th.wt_tsf = htole64(tsf);
4846 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags;
4848 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
4850 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_FRAG;
4851 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate;
4852 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
4853 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
4855 bpf_mtap2(ifp->if_bpf, &sc->sc_tx_th, sc->sc_tx_th_len, m0);
4859 * Determine if a tx interrupt should be generated for
4860 * this descriptor. We take a tx interrupt to reap
4861 * descriptors when the h/w hits an EOL condition or
4862 * when the descriptor is specifically marked to generate
4863 * an interrupt. We periodically mark descriptors in this
4864 * way to insure timely replenishing of the supply needed
4865 * for sending frames. Defering interrupts reduces system
4866 * load and potentially allows more concurrent work to be
4867 * done but if done to aggressively can cause senders to
4870 * NB: use >= to deal with sc_txintrperiod changing
4871 * dynamically through sysctl.
4873 if (flags & HAL_TXDESC_INTREQ) {
4874 txq->axq_intrcnt = 0;
4875 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
4876 flags |= HAL_TXDESC_INTREQ;
4877 txq->axq_intrcnt = 0;
4881 * Formulate first tx descriptor with tx controls.
4883 /* XXX check return value? */
4884 ath_hal_setuptxdesc(ah, ds
4885 , pktlen /* packet length */
4886 , hdrlen /* header length */
4887 , atype /* Atheros packet type */
4888 , ni->ni_txpower /* txpower */
4889 , txrate, try0 /* series 0 rate/tries */
4890 , keyix /* key cache index */
4891 , sc->sc_txantenna /* antenna mode */
4893 , ctsrate /* rts/cts rate */
4894 , ctsduration /* rts/cts duration */
4896 bf->bf_flags = flags;
4898 * Setup the multi-rate retry state only when we're
4899 * going to use it. This assumes ath_hal_setuptxdesc
4900 * initializes the descriptors (so we don't have to)
4901 * when the hardware supports multi-rate retry and
4905 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix);
4907 ath_tx_handoff(sc, txq, bf);
4912 * Process completed xmit descriptors from the specified queue.
4915 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
4917 struct ath_hal *ah = sc->sc_ah;
4918 struct ifnet *ifp = sc->sc_ifp;
4919 struct ieee80211com *ic = ifp->if_l2com;
4921 struct ath_desc *ds, *ds0;
4922 struct ath_tx_status *ts;
4923 struct ieee80211_node *ni;
4924 struct ath_node *an;
4925 int sr, lr, pri, nacked;
4928 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
4929 __func__, txq->axq_qnum,
4930 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4935 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
4936 bf = STAILQ_FIRST(&txq->axq_q);
4938 ATH_TXQ_UNLOCK(txq);
4941 ds0 = &bf->bf_desc[0];
4942 ds = &bf->bf_desc[bf->bf_nseg - 1];
4943 ts = &bf->bf_status.ds_txstat;
4944 status = ath_hal_txprocdesc(ah, ds, ts);
4946 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
4947 ath_printtxbuf(bf, txq->axq_qnum, 0, status == HAL_OK);
4949 if (status == HAL_EINPROGRESS) {
4950 ATH_TXQ_UNLOCK(txq);
4953 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
4954 if (txq->axq_depth == 0)
4955 txq->axq_link = NULL;
4956 ATH_TXQ_UNLOCK(txq);
4961 if (ts->ts_status == 0) {
4962 u_int8_t txant = ts->ts_antenna;
4963 sc->sc_stats.ast_ant_tx[txant]++;
4964 sc->sc_ant_tx[txant]++;
4965 if (ts->ts_rate & HAL_TXSTAT_ALTRATE)
4966 sc->sc_stats.ast_tx_altrate++;
4967 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
4968 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
4970 pri = M_WME_GETAC(bf->bf_m);
4971 if (pri >= WME_AC_VO)
4972 ic->ic_wme.wme_hipri_traffic++;
4973 ni->ni_inact = ni->ni_inact_reload;
4975 if (ts->ts_status & HAL_TXERR_XRETRY)
4976 sc->sc_stats.ast_tx_xretries++;
4977 if (ts->ts_status & HAL_TXERR_FIFO)
4978 sc->sc_stats.ast_tx_fifoerr++;
4979 if (ts->ts_status & HAL_TXERR_FILT)
4980 sc->sc_stats.ast_tx_filtered++;
4981 if (bf->bf_m->m_flags & M_FF)
4982 sc->sc_stats.ast_ff_txerr++;
4984 sr = ts->ts_shortretry;
4985 lr = ts->ts_longretry;
4986 sc->sc_stats.ast_tx_shortretry += sr;
4987 sc->sc_stats.ast_tx_longretry += lr;
4989 * Hand the descriptor to the rate control algorithm.
4991 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
4992 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
4994 * If frame was ack'd update the last rx time
4995 * used to workaround phantom bmiss interrupts.
4997 if (ts->ts_status == 0)
4999 ath_rate_tx_complete(sc, an, bf);
5002 * Do any tx complete callback. Note this must
5003 * be done before releasing the node reference.
5005 if (bf->bf_m->m_flags & M_TXCB)
5006 ieee80211_process_callback(ni, bf->bf_m,
5009 * Reclaim reference to node.
5011 * NB: the node may be reclaimed here if, for example
5012 * this is a DEAUTH message that was sent and the
5013 * node was timed out due to inactivity.
5015 ieee80211_free_node(ni);
5017 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
5018 BUS_DMASYNC_POSTWRITE);
5019 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
5026 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
5027 ATH_TXBUF_UNLOCK(sc);
5030 * Flush fast-frame staging queue when traffic slows.
5032 if (txq->axq_depth <= 1)
5033 ath_ff_stageq_flush(sc, txq, ath_ff_always);
5038 txqactive(struct ath_hal *ah, int qnum)
5040 u_int32_t txqs = 1<<qnum;
5041 ath_hal_gettxintrtxqs(ah, &txqs);
5042 return (txqs & (1<<qnum));
5046 * Deferred processing of transmit interrupt; special-cased
5047 * for a single hardware transmit queue (e.g. 5210 and 5211).
5050 ath_tx_proc_q0(void *arg, int npending)
5052 struct ath_softc *sc = arg;
5053 struct ifnet *ifp = sc->sc_ifp;
5055 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]))
5056 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5057 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
5058 ath_tx_processq(sc, sc->sc_cabq);
5059 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5063 ath_led_event(sc, ATH_LED_TX);
5069 * Deferred processing of transmit interrupt; special-cased
5070 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
5073 ath_tx_proc_q0123(void *arg, int npending)
5075 struct ath_softc *sc = arg;
5076 struct ifnet *ifp = sc->sc_ifp;
5080 * Process each active queue.
5083 if (txqactive(sc->sc_ah, 0))
5084 nacked += ath_tx_processq(sc, &sc->sc_txq[0]);
5085 if (txqactive(sc->sc_ah, 1))
5086 nacked += ath_tx_processq(sc, &sc->sc_txq[1]);
5087 if (txqactive(sc->sc_ah, 2))
5088 nacked += ath_tx_processq(sc, &sc->sc_txq[2]);
5089 if (txqactive(sc->sc_ah, 3))
5090 nacked += ath_tx_processq(sc, &sc->sc_txq[3]);
5091 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
5092 ath_tx_processq(sc, sc->sc_cabq);
5094 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5096 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5100 ath_led_event(sc, ATH_LED_TX);
5106 * Deferred processing of transmit interrupt.
5109 ath_tx_proc(void *arg, int npending)
5111 struct ath_softc *sc = arg;
5112 struct ifnet *ifp = sc->sc_ifp;
5116 * Process each active queue.
5119 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
5120 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i))
5121 nacked += ath_tx_processq(sc, &sc->sc_txq[i]);
5123 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
5125 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5129 ath_led_event(sc, ATH_LED_TX);
5135 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
5138 struct ath_hal *ah = sc->sc_ah;
5140 struct ieee80211_node *ni;
5145 * NB: this assumes output has been stopped and
5146 * we do not need to block ath_tx_tasklet
5148 for (ix = 0;; ix++) {
5150 bf = STAILQ_FIRST(&txq->axq_q);
5152 txq->axq_link = NULL;
5153 ATH_TXQ_UNLOCK(txq);
5156 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
5157 ATH_TXQ_UNLOCK(txq);
5159 if (sc->sc_debug & ATH_DEBUG_RESET) {
5160 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
5162 ath_printtxbuf(bf, txq->axq_qnum, ix,
5163 ath_hal_txprocdesc(ah, bf->bf_desc,
5164 &bf->bf_status.ds_txstat) == HAL_OK);
5165 ieee80211_dump_pkt(ic, mtod(bf->bf_m, caddr_t),
5166 bf->bf_m->m_len, 0, -1);
5168 #endif /* ATH_DEBUG */
5169 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
5174 * Do any callback and reclaim the node reference.
5176 if (bf->bf_m->m_flags & M_TXCB)
5177 ieee80211_process_callback(ni, bf->bf_m, -1);
5178 ieee80211_free_node(ni);
5184 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
5185 ATH_TXBUF_UNLOCK(sc);
5190 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
5192 struct ath_hal *ah = sc->sc_ah;
5194 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
5195 __func__, txq->axq_qnum,
5196 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
5198 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
5202 * Drain the transmit queues and reclaim resources.
5205 ath_draintxq(struct ath_softc *sc)
5207 struct ath_hal *ah = sc->sc_ah;
5208 struct ifnet *ifp = sc->sc_ifp;
5211 /* XXX return value */
5212 if (!sc->sc_invalid) {
5213 /* don't touch the hardware if marked invalid */
5214 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
5215 __func__, sc->sc_bhalq,
5216 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq),
5218 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
5219 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
5220 if (ATH_TXQ_SETUP(sc, i))
5221 ath_tx_stopdma(sc, &sc->sc_txq[i]);
5223 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
5224 if (ATH_TXQ_SETUP(sc, i))
5225 ath_tx_draintxq(sc, &sc->sc_txq[i]);
5227 if (sc->sc_debug & ATH_DEBUG_RESET) {
5228 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
5229 if (bf != NULL && bf->bf_m != NULL) {
5230 ath_printtxbuf(bf, sc->sc_bhalq, 0,
5231 ath_hal_txprocdesc(ah, bf->bf_desc,
5232 &bf->bf_status.ds_txstat) == HAL_OK);
5233 ieee80211_dump_pkt(ifp->if_l2com, mtod(bf->bf_m, caddr_t),
5234 bf->bf_m->m_len, 0, -1);
5237 #endif /* ATH_DEBUG */
5238 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5243 * Disable the receive h/w in preparation for a reset.
5246 ath_stoprecv(struct ath_softc *sc)
5248 #define PA2DESC(_sc, _pa) \
5249 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
5250 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
5251 struct ath_hal *ah = sc->sc_ah;
5253 ath_hal_stoppcurecv(ah); /* disable PCU */
5254 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
5255 ath_hal_stopdmarecv(ah); /* disable DMA engine */
5256 DELAY(3000); /* 3ms is long enough for 1 frame */
5258 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
5262 printf("%s: rx queue %p, link %p\n", __func__,
5263 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink);
5265 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
5266 struct ath_desc *ds = bf->bf_desc;
5267 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
5268 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
5269 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
5270 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
5271 ath_printrxbuf(bf, ix, status == HAL_OK);
5276 if (sc->sc_rxpending != NULL) {
5277 m_freem(sc->sc_rxpending);
5278 sc->sc_rxpending = NULL;
5280 sc->sc_rxlink = NULL; /* just in case */
5285 * Enable the receive h/w following a reset.
5288 ath_startrecv(struct ath_softc *sc)
5290 struct ath_hal *ah = sc->sc_ah;
5293 sc->sc_rxlink = NULL;
5294 sc->sc_rxpending = NULL;
5295 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
5296 int error = ath_rxbuf_init(sc, bf);
5298 DPRINTF(sc, ATH_DEBUG_RECV,
5299 "%s: ath_rxbuf_init failed %d\n",
5305 bf = STAILQ_FIRST(&sc->sc_rxbuf);
5306 ath_hal_putrxbuf(ah, bf->bf_daddr);
5307 ath_hal_rxena(ah); /* enable recv descriptors */
5308 ath_mode_init(sc); /* set filters, etc. */
5309 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
5314 * Update internal state after a channel change.
5317 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
5319 enum ieee80211_phymode mode;
5322 * Change channels and update the h/w rate map
5323 * if we're switching; e.g. 11a to 11b/g.
5325 if (IEEE80211_IS_CHAN_HALF(chan))
5326 mode = IEEE80211_MODE_HALF;
5327 else if (IEEE80211_IS_CHAN_QUARTER(chan))
5328 mode = IEEE80211_MODE_QUARTER;
5330 mode = ieee80211_chan2mode(chan);
5331 if (mode != sc->sc_curmode)
5332 ath_setcurmode(sc, mode);
5334 sc->sc_rx_th.wr_chan_flags = htole32(chan->ic_flags);
5335 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags;
5336 sc->sc_rx_th.wr_chan_freq = htole16(chan->ic_freq);
5337 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq;
5338 sc->sc_rx_th.wr_chan_ieee = chan->ic_ieee;
5339 sc->sc_tx_th.wt_chan_ieee = sc->sc_rx_th.wr_chan_ieee;
5340 sc->sc_rx_th.wr_chan_maxpow = chan->ic_maxregpower;
5341 sc->sc_tx_th.wt_chan_maxpow = sc->sc_rx_th.wr_chan_maxpow;
5345 * Set/change channels. If the channel is really being changed,
5346 * it's done by reseting the chip. To accomplish this we must
5347 * first cleanup any pending DMA, then restart stuff after a la
5351 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
5353 struct ifnet *ifp = sc->sc_ifp;
5354 struct ieee80211com *ic = ifp->if_l2com;
5355 struct ath_hal *ah = sc->sc_ah;
5359 * Convert to a HAL channel description with
5360 * the flags constrained to reflect the current
5363 ath_mapchan(&hchan, chan);
5365 DPRINTF(sc, ATH_DEBUG_RESET,
5366 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n",
5368 ath_hal_mhz2ieee(ah, sc->sc_curchan.channel,
5369 sc->sc_curchan.channelFlags),
5370 sc->sc_curchan.channel, sc->sc_curchan.channelFlags,
5371 ath_hal_mhz2ieee(ah, hchan.channel, hchan.channelFlags),
5372 hchan.channel, hchan.channelFlags);
5373 if (hchan.channel != sc->sc_curchan.channel ||
5374 hchan.channelFlags != sc->sc_curchan.channelFlags) {
5378 * To switch channels clear any pending DMA operations;
5379 * wait long enough for the RX fifo to drain, reset the
5380 * hardware at the new frequency, and then re-enable
5381 * the relevant bits of the h/w.
5383 ath_hal_intrset(ah, 0); /* disable interrupts */
5384 ath_draintxq(sc); /* clear pending tx frames */
5385 ath_stoprecv(sc); /* turn off frame recv */
5386 if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, AH_TRUE, &status)) {
5387 if_printf(ifp, "%s: unable to reset "
5388 "channel %u (%u Mhz, flags 0x%x hal flags 0x%x), "
5389 "hal status %u\n", __func__,
5390 ieee80211_chan2ieee(ic, chan), chan->ic_freq,
5391 chan->ic_flags, hchan.channelFlags, status);
5394 sc->sc_curchan = hchan;
5395 sc->sc_diversity = ath_hal_getdiversity(ah);
5396 sc->sc_calinterval = 1;
5397 sc->sc_caltries = 0;
5400 * Re-enable rx framework.
5402 if (ath_startrecv(sc) != 0) {
5403 if_printf(ifp, "%s: unable to restart recv logic\n",
5409 * Change channels and update the h/w rate map
5410 * if we're switching; e.g. 11a to 11b/g.
5412 ath_chan_change(sc, chan);
5415 * Re-enable interrupts.
5417 ath_hal_intrset(ah, sc->sc_imask);
5423 * Periodically recalibrate the PHY to account
5424 * for temperature/environment changes.
5427 ath_calibrate(void *arg)
5429 struct ath_softc *sc = arg;
5430 struct ath_hal *ah = sc->sc_ah;
5433 sc->sc_stats.ast_per_cal++;
5435 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
5437 * Rfgain is out of bounds, reset the chip
5438 * to load new gain values.
5440 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5441 "%s: rfgain change\n", __func__);
5442 sc->sc_stats.ast_per_rfgain++;
5443 ath_reset(sc->sc_ifp);
5445 if (!ath_hal_calibrate(ah, &sc->sc_curchan, &iqCalDone)) {
5446 DPRINTF(sc, ATH_DEBUG_ANY,
5447 "%s: calibration of channel %u failed\n",
5448 __func__, sc->sc_curchan.channel);
5449 sc->sc_stats.ast_per_calfail++;
5452 * Calibrate noise floor data again in case of change.
5454 ath_hal_process_noisefloor(ah);
5456 * Poll more frequently when the IQ calibration is in
5457 * progress to speedup loading the final settings.
5458 * We temper this aggressive polling with an exponential
5459 * back off after 4 tries up to ath_calinterval.
5461 if (iqCalDone || sc->sc_calinterval >= ath_calinterval) {
5462 sc->sc_caltries = 0;
5463 sc->sc_calinterval = ath_calinterval;
5464 } else if (sc->sc_caltries > 4) {
5465 sc->sc_caltries = 0;
5466 sc->sc_calinterval <<= 1;
5467 if (sc->sc_calinterval > ath_calinterval)
5468 sc->sc_calinterval = ath_calinterval;
5470 KASSERT(0 < sc->sc_calinterval && sc->sc_calinterval <= ath_calinterval,
5471 ("bad calibration interval %u", sc->sc_calinterval));
5473 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5474 "%s: next +%u (%siqCalDone tries %u)\n", __func__,
5475 sc->sc_calinterval, iqCalDone ? "" : "!", sc->sc_caltries);
5477 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz,
5482 ath_scan_start(struct ieee80211com *ic)
5484 struct ifnet *ifp = ic->ic_ifp;
5485 struct ath_softc *sc = ifp->if_softc;
5486 struct ath_hal *ah = sc->sc_ah;
5489 /* XXX calibration timer? */
5491 sc->sc_scanning = 1;
5492 sc->sc_syncbeacon = 0;
5493 rfilt = ath_calcrxfilter(sc);
5494 ath_hal_setrxfilter(ah, rfilt);
5495 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0);
5497 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n",
5498 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr));
5502 ath_scan_end(struct ieee80211com *ic)
5504 struct ifnet *ifp = ic->ic_ifp;
5505 struct ath_softc *sc = ifp->if_softc;
5506 struct ath_hal *ah = sc->sc_ah;
5509 sc->sc_scanning = 0;
5510 rfilt = ath_calcrxfilter(sc);
5511 ath_hal_setrxfilter(ah, rfilt);
5512 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5514 ath_hal_process_noisefloor(ah);
5516 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5517 __func__, rfilt, ether_sprintf(sc->sc_curbssid),
5522 ath_set_channel(struct ieee80211com *ic)
5524 struct ifnet *ifp = ic->ic_ifp;
5525 struct ath_softc *sc = ifp->if_softc;
5527 (void) ath_chan_set(sc, ic->ic_curchan);
5529 * If we are returning to our bss channel then mark state
5530 * so the next recv'd beacon's tsf will be used to sync the
5531 * beacon timers. Note that since we only hear beacons in
5532 * sta/ibss mode this has no effect in other operating modes.
5534 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan)
5535 sc->sc_syncbeacon = 1;
5539 * Walk the vap list and check if there any vap's in RUN state.
5542 ath_isanyrunningvaps(struct ieee80211vap *this)
5544 struct ieee80211com *ic = this->iv_ic;
5545 struct ieee80211vap *vap;
5547 IEEE80211_LOCK_ASSERT(ic);
5549 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
5550 if (vap != this && vap->iv_state == IEEE80211_S_RUN)
5557 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
5559 struct ieee80211com *ic = vap->iv_ic;
5560 struct ath_softc *sc = ic->ic_ifp->if_softc;
5561 struct ath_vap *avp = ATH_VAP(vap);
5562 struct ath_hal *ah = sc->sc_ah;
5563 struct ieee80211_node *ni = NULL;
5564 int i, error, stamode;
5566 static const HAL_LED_STATE leds[] = {
5567 HAL_LED_INIT, /* IEEE80211_S_INIT */
5568 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
5569 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
5570 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
5571 HAL_LED_RUN, /* IEEE80211_S_CAC */
5572 HAL_LED_RUN, /* IEEE80211_S_RUN */
5573 HAL_LED_RUN, /* IEEE80211_S_CSA */
5574 HAL_LED_RUN, /* IEEE80211_S_SLEEP */
5577 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
5578 ieee80211_state_name[vap->iv_state],
5579 ieee80211_state_name[nstate]);
5581 callout_stop(&sc->sc_cal_ch);
5582 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
5584 if (nstate == IEEE80211_S_SCAN) {
5586 * Scanning: turn off beacon miss and don't beacon.
5587 * Mark beacon state so when we reach RUN state we'll
5588 * [re]setup beacons. Unblock the task q thread so
5589 * deferred interrupt processing is done.
5592 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
5593 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5595 taskqueue_unblock(sc->sc_tq);
5599 rfilt = ath_calcrxfilter(sc);
5600 stamode = (vap->iv_opmode == IEEE80211_M_STA ||
5601 vap->iv_opmode == IEEE80211_M_IBSS);
5602 if (stamode && nstate == IEEE80211_S_RUN) {
5603 sc->sc_curaid = ni->ni_associd;
5604 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid);
5605 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5607 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5608 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid);
5609 ath_hal_setrxfilter(ah, rfilt);
5611 /* XXX is this to restore keycache on resume? */
5612 if (vap->iv_opmode != IEEE80211_M_STA &&
5613 (vap->iv_flags & IEEE80211_F_PRIVACY)) {
5614 for (i = 0; i < IEEE80211_WEP_NKID; i++)
5615 if (ath_hal_keyisvalid(ah, i))
5616 ath_hal_keysetmac(ah, i, ni->ni_bssid);
5619 * Notify the rate control algorithm so rates
5620 * are setup should ath_beacon_alloc be called.
5622 ath_rate_newstate(vap, nstate);
5625 * Invoke the parent method to do net80211 work.
5627 error = avp->av_newstate(vap, nstate, arg);
5631 if (nstate == IEEE80211_S_RUN) {
5632 /* NB: collect bss node again, it may have changed */
5635 DPRINTF(sc, ATH_DEBUG_STATE,
5636 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s "
5637 "capinfo 0x%04x chan %d\n", __func__,
5638 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid),
5639 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan));
5641 switch (vap->iv_opmode) {
5642 case IEEE80211_M_HOSTAP:
5643 case IEEE80211_M_IBSS:
5645 * Allocate and setup the beacon frame.
5647 * Stop any previous beacon DMA. This may be
5648 * necessary, for example, when an ibss merge
5649 * causes reconfiguration; there will be a state
5650 * transition from RUN->RUN that means we may
5651 * be called with beacon transmission active.
5653 ath_hal_stoptxdma(ah, sc->sc_bhalq);
5655 error = ath_beacon_alloc(sc, ni);
5659 * If joining an adhoc network defer beacon timer
5660 * configuration to the next beacon frame so we
5661 * have a current TSF to use. Otherwise we're
5662 * starting an ibss/bss so there's no need to delay;
5663 * if this is the first vap moving to RUN state, then
5664 * beacon state needs to be [re]configured.
5666 if (vap->iv_opmode == IEEE80211_M_IBSS &&
5667 ni->ni_tstamp.tsf != 0) {
5668 sc->sc_syncbeacon = 1;
5669 } else if (!sc->sc_beacons) {
5670 ath_beacon_config(sc, vap);
5674 case IEEE80211_M_STA:
5676 * Fakeup since we're not called by net80211.
5678 ath_newassoc(ni, 1);
5680 * Defer beacon timer configuration to the next
5681 * beacon frame so we have a current TSF to use
5682 * (any TSF collected when scanning is likely old).
5684 sc->sc_syncbeacon = 1;
5686 case IEEE80211_M_MONITOR:
5688 * Monitor mode vaps have only INIT->RUN and RUN->RUN
5689 * transitions so we must re-enable interrupts here to
5690 * handle the case of a single monitor mode vap.
5692 ath_hal_intrset(ah, sc->sc_imask);
5694 case IEEE80211_M_WDS:
5700 * Let the hal process statistics collected during a
5701 * scan so it can provide calibrated noise floor data.
5703 ath_hal_process_noisefloor(ah);
5705 * Reset rssi stats; maybe not the best place...
5707 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
5708 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
5709 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
5711 * Finally, start any timers and the task q thread
5712 * (in case we didn't go through SCAN state).
5714 if (sc->sc_calinterval != 0) {
5715 /* start periodic recalibration timer */
5716 callout_reset(&sc->sc_cal_ch, sc->sc_calinterval * hz,
5719 taskqueue_unblock(sc->sc_tq);
5720 } else if (nstate == IEEE80211_S_INIT) {
5722 * If there are no vaps left in RUN state then
5723 * shutdown host/driver operation:
5724 * o disable interrupts
5725 * o disable the task queue thread
5726 * o mark beacon processing as stopped
5728 if (!ath_isanyrunningvaps(vap)) {
5729 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5730 /* disable interrupts */
5731 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
5732 taskqueue_block(sc->sc_tq);
5741 * Allocate a key cache slot to the station so we can
5742 * setup a mapping from key index to node. The key cache
5743 * slot is needed for managing antenna state and for
5744 * compression when stations do not use crypto. We do
5745 * it uniliaterally here; if crypto is employed this slot
5746 * will be reassigned.
5749 ath_setup_stationkey(struct ieee80211_node *ni)
5751 struct ieee80211vap *vap = ni->ni_vap;
5752 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
5753 ieee80211_keyix keyix, rxkeyix;
5755 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
5757 * Key cache is full; we'll fall back to doing
5758 * the more expensive lookup in software. Note
5759 * this also means no h/w compression.
5761 /* XXX msg+statistic */
5764 ni->ni_ucastkey.wk_keyix = keyix;
5765 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
5766 /* NB: this will create a pass-thru key entry */
5767 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, vap->iv_bss);
5772 * Setup driver-specific state for a newly associated node.
5773 * Note that we're called also on a re-associate, the isnew
5774 * param tells us if this is the first time or not.
5777 ath_newassoc(struct ieee80211_node *ni, int isnew)
5779 struct ath_node *an = ATH_NODE(ni);
5780 struct ieee80211vap *vap = ni->ni_vap;
5781 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
5782 const struct ieee80211_txparam *tp;
5783 enum ieee80211_phymode mode;
5786 * Deduce netband of station to simplify setting up xmit
5787 * parameters. Note this allows us to assign different
5788 * parameters to each station in a mixed bss (b/g, n/[abg]).
5790 if (ni->ni_flags & IEEE80211_NODE_HT) {
5791 if (IEEE80211_IS_CHAN_5GHZ(ni->ni_chan))
5792 mode = IEEE80211_MODE_11NA;
5794 mode = IEEE80211_MODE_11NG;
5795 } else if (IEEE80211_IS_CHAN_A(ni->ni_chan))
5796 mode = IEEE80211_MODE_11A;
5797 else if (ni->ni_flags & IEEE80211_NODE_ERP)
5798 mode = IEEE80211_MODE_11G;
5800 mode = IEEE80211_MODE_11B;
5801 tp = &vap->iv_txparms[mode];
5803 an->an_mcastrix = ath_tx_findrix(sc->sc_rates[mode], tp->mcastrate);
5804 an->an_mgmtrix = ath_tx_findrix(sc->sc_rates[mode], tp->mgmtrate);
5806 ath_rate_newassoc(sc, an, isnew);
5808 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey &&
5809 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
5810 ath_setup_stationkey(ni);
5814 getchannels(struct ath_softc *sc, int *nchans, struct ieee80211_channel chans[],
5815 int cc, int ecm, int outdoor)
5817 struct ath_hal *ah = sc->sc_ah;
5818 HAL_CHANNEL *halchans;
5819 int i, nhalchans, error;
5821 halchans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL),
5822 M_TEMP, M_NOWAIT | M_ZERO);
5823 if (halchans == NULL) {
5824 device_printf(sc->sc_dev,
5825 "%s: unable to allocate channel table\n", __func__);
5829 if (!ath_hal_init_channels(ah, halchans, IEEE80211_CHAN_MAX, &nhalchans,
5830 NULL, 0, NULL, CTRY_DEFAULT, HAL_MODE_ALL, AH_FALSE, AH_TRUE)) {
5834 if (nchans == NULL) /* no table requested */
5838 * Convert HAL channels to ieee80211 ones.
5840 for (i = 0; i < nhalchans; i++) {
5841 HAL_CHANNEL *c = &halchans[i];
5842 struct ieee80211_channel *ichan = &chans[i];
5844 ichan->ic_ieee = ath_hal_mhz2ieee(ah, c->channel,
5847 device_printf(sc->sc_dev, "hal channel %u/%x -> %u "
5848 "maxpow %d minpow %d maxreg %d\n",
5849 c->channel, c->channelFlags, ichan->ic_ieee,
5850 c->maxTxPower, c->minTxPower, c->maxRegTxPower);
5851 ichan->ic_freq = c->channel;
5853 if ((c->channelFlags & CHANNEL_PUREG) == CHANNEL_PUREG) {
5855 * Except for AR5211, HAL's PUREG means mixed
5858 ichan->ic_flags = c->channelFlags &~ CHANNEL_PUREG;
5859 ichan->ic_flags |= IEEE80211_CHAN_G;
5861 ichan->ic_flags = c->channelFlags;
5864 if (ath_hal_isgsmsku(ah)) {
5865 /* remap to true frequencies */
5866 ichan->ic_freq = 922 + (2422 - ichan->ic_freq);
5867 ichan->ic_flags |= IEEE80211_CHAN_GSM;
5868 ichan->ic_ieee = ieee80211_mhz2ieee(ichan->ic_freq,
5871 ichan->ic_maxregpower = c->maxRegTxPower; /* dBm */
5872 /* XXX: old hal's don't provide maxTxPower for some parts */
5873 ichan->ic_maxpower = (c->maxTxPower != 0) ?
5874 c->maxTxPower : 2*c->maxRegTxPower; /* 1/2 dBm */
5875 ichan->ic_minpower = c->minTxPower; /* 1/2 dBm */
5877 *nchans = nhalchans;
5879 free(halchans, M_TEMP);
5884 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *rd,
5885 int nchans, struct ieee80211_channel chans[])
5887 struct ath_softc *sc = ic->ic_ifp->if_softc;
5888 struct ath_hal *ah = sc->sc_ah;
5892 (void) ath_hal_getregdomain(ah, &ord);
5893 /* XXX map sku->rd */
5894 ath_hal_setregdomain(ah, rd->regdomain);
5895 error = getchannels(sc, &nchans, chans, rd->country,
5896 rd->ecm ? AH_TRUE : AH_FALSE,
5897 rd->location == 'O' ? AH_TRUE : AH_FALSE);
5900 * Restore previous state.
5902 ath_hal_setregdomain(ah, ord);
5903 (void) getchannels(sc, NULL, NULL, ic->ic_regdomain.country,
5904 ic->ic_regdomain.ecm ? AH_TRUE : AH_FALSE,
5905 ic->ic_regdomain.location == 'O' ? AH_TRUE : AH_FALSE);
5912 ath_getradiocaps(struct ieee80211com *ic,
5913 int *nchans, struct ieee80211_channel chans[])
5915 struct ath_softc *sc = ic->ic_ifp->if_softc;
5916 struct ath_hal *ah = sc->sc_ah;
5919 (void) ath_hal_getregdomain(ah, &ord);
5920 ath_hal_setregdomain(ah, 0);
5921 /* XXX not quite right but close enough for now */
5922 getchannels(sc, nchans, chans, CTRY_DEBUG, AH_TRUE, AH_FALSE);
5923 ath_hal_setregdomain(ah, ord);
5927 ath_mapregdomain(struct ath_softc *sc, u_int32_t rd)
5929 /* map Atheros rd's to SKU's */
5934 ath_getchannels(struct ath_softc *sc)
5936 struct ifnet *ifp = sc->sc_ifp;
5937 struct ieee80211com *ic = ifp->if_l2com;
5938 struct ath_hal *ah = sc->sc_ah;
5943 * Convert HAL channels to ieee80211 ones.
5945 error = getchannels(sc, &ic->ic_nchans, ic->ic_channels,
5946 CTRY_DEFAULT, AH_TRUE, AH_FALSE);
5947 (void) ath_hal_getregdomain(ah, &rd);
5948 ath_hal_getcountrycode(ah, &cc); /* NB: cannot fail */
5950 if_printf(ifp, "%s: unable to collect channel list from hal, "
5951 "error %d\n", __func__, error);
5952 if (error == EINVAL) {
5953 if_printf(ifp, "%s: regdomain likely %u country code %u\n",
5958 ic->ic_regdomain.regdomain = ath_mapregdomain(sc, rd);
5959 ic->ic_regdomain.country = cc;
5960 ic->ic_regdomain.ecm = 1;
5961 ic->ic_regdomain.location = 'I';
5962 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */
5963 ic->ic_regdomain.isocc[1] = ' ';
5968 ath_led_done(void *arg)
5970 struct ath_softc *sc = arg;
5972 sc->sc_blinking = 0;
5976 * Turn the LED off: flip the pin and then set a timer so no
5977 * update will happen for the specified duration.
5980 ath_led_off(void *arg)
5982 struct ath_softc *sc = arg;
5984 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
5985 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc);
5989 * Blink the LED according to the specified on/off times.
5992 ath_led_blink(struct ath_softc *sc, int on, int off)
5994 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off);
5995 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon);
5996 sc->sc_blinking = 1;
5997 sc->sc_ledoff = off;
5998 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc);
6002 ath_led_event(struct ath_softc *sc, int event)
6005 sc->sc_ledevent = ticks; /* time of last event */
6006 if (sc->sc_blinking) /* don't interrupt active blink */
6010 ath_led_blink(sc, sc->sc_hwmap[0].ledon,
6011 sc->sc_hwmap[0].ledoff);
6014 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon,
6015 sc->sc_hwmap[sc->sc_txrate].ledoff);
6018 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon,
6019 sc->sc_hwmap[sc->sc_rxrate].ledoff);
6025 ath_rate_setup(struct ath_softc *sc, u_int mode)
6027 struct ath_hal *ah = sc->sc_ah;
6028 const HAL_RATE_TABLE *rt;
6031 case IEEE80211_MODE_11A:
6032 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
6034 case IEEE80211_MODE_HALF:
6035 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE);
6037 case IEEE80211_MODE_QUARTER:
6038 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE);
6040 case IEEE80211_MODE_11B:
6041 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
6043 case IEEE80211_MODE_11G:
6044 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
6046 case IEEE80211_MODE_TURBO_A:
6047 rt = ath_hal_getratetable(ah, HAL_MODE_108A);
6048 #if HAL_ABI_VERSION < 0x07013100
6049 if (rt == NULL) /* XXX bandaid for old hal's */
6050 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
6053 case IEEE80211_MODE_TURBO_G:
6054 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
6056 case IEEE80211_MODE_STURBO_A:
6057 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
6059 case IEEE80211_MODE_11NA:
6060 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20);
6062 case IEEE80211_MODE_11NG:
6063 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20);
6066 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
6070 sc->sc_rates[mode] = rt;
6071 return (rt != NULL);
6075 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
6077 #define N(a) (sizeof(a)/sizeof(a[0]))
6078 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
6079 static const struct {
6080 u_int rate; /* tx/rx 802.11 rate */
6081 u_int16_t timeOn; /* LED on time (ms) */
6082 u_int16_t timeOff; /* LED off time (ms) */
6098 /* XXX half/quarter rates */
6100 const HAL_RATE_TABLE *rt;
6103 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
6104 rt = sc->sc_rates[mode];
6105 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
6106 for (i = 0; i < rt->rateCount; i++)
6107 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i;
6108 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
6109 for (i = 0; i < 32; i++) {
6110 u_int8_t ix = rt->rateCodeToIndex[i];
6112 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
6113 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
6116 sc->sc_hwmap[i].ieeerate =
6117 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL;
6118 if (rt->info[ix].phy == IEEE80211_T_HT)
6119 sc->sc_hwmap[i].ieeerate |= 0x80; /* MCS */
6120 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
6121 if (rt->info[ix].shortPreamble ||
6122 rt->info[ix].phy == IEEE80211_T_OFDM)
6123 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6124 /* NB: receive frames include FCS */
6125 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags |
6126 IEEE80211_RADIOTAP_F_FCS;
6127 /* setup blink rate table to avoid per-packet lookup */
6128 for (j = 0; j < N(blinkrates)-1; j++)
6129 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
6131 /* NB: this uses the last entry if the rate isn't found */
6132 /* XXX beware of overlow */
6133 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
6134 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
6136 sc->sc_currates = rt;
6137 sc->sc_curmode = mode;
6139 * All protection frames are transmited at 2Mb/s for
6140 * 11g, otherwise at 1Mb/s.
6142 if (mode == IEEE80211_MODE_11G)
6143 sc->sc_protrix = ath_tx_findrix(rt, 2*2);
6145 sc->sc_protrix = ath_tx_findrix(rt, 2*1);
6146 /* NB: caller is responsible for reseting rate control state */
6152 ath_printrxbuf(const struct ath_buf *bf, u_int ix, int done)
6154 const struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
6155 const struct ath_desc *ds;
6158 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
6159 printf("R[%2u] (DS.V:%p DS.P:%p) L:%08x D:%08x%s\n"
6160 " %08x %08x %08x %08x\n",
6161 ix, ds, (const struct ath_desc *)bf->bf_daddr + i,
6162 ds->ds_link, ds->ds_data,
6163 !done ? "" : (rs->rs_status == 0) ? " *" : " !",
6164 ds->ds_ctl0, ds->ds_ctl1,
6165 ds->ds_hw[0], ds->ds_hw[1]);
6170 ath_printtxbuf(const struct ath_buf *bf, u_int qnum, u_int ix, int done)
6172 const struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
6173 const struct ath_desc *ds;
6176 printf("Q%u[%3u]", qnum, ix);
6177 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
6178 printf(" (DS.V:%p DS.P:%p) L:%08x D:%08x F:04%x%s\n"
6179 " %08x %08x %08x %08x %08x %08x\n",
6180 ds, (const struct ath_desc *)bf->bf_daddr + i,
6181 ds->ds_link, ds->ds_data, bf->bf_flags,
6182 !done ? "" : (ts->ts_status == 0) ? " *" : " !",
6183 ds->ds_ctl0, ds->ds_ctl1,
6184 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3]);
6187 #endif /* ATH_DEBUG */
6190 ath_watchdog(struct ifnet *ifp)
6192 struct ath_softc *sc = ifp->if_softc;
6194 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && !sc->sc_invalid) {
6195 if_printf(ifp, "device timeout\n");
6198 sc->sc_stats.ast_watchdog++;
6204 * Diagnostic interface to the HAL. This is used by various
6205 * tools to do things like retrieve register contents for
6206 * debugging. The mechanism is intentionally opaque so that
6207 * it can change frequently w/o concern for compatiblity.
6210 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
6212 struct ath_hal *ah = sc->sc_ah;
6213 u_int id = ad->ad_id & ATH_DIAG_ID;
6214 void *indata = NULL;
6215 void *outdata = NULL;
6216 u_int32_t insize = ad->ad_in_size;
6217 u_int32_t outsize = ad->ad_out_size;
6220 if (ad->ad_id & ATH_DIAG_IN) {
6224 indata = malloc(insize, M_TEMP, M_NOWAIT);
6225 if (indata == NULL) {
6229 error = copyin(ad->ad_in_data, indata, insize);
6233 if (ad->ad_id & ATH_DIAG_DYN) {
6235 * Allocate a buffer for the results (otherwise the HAL
6236 * returns a pointer to a buffer where we can read the
6237 * results). Note that we depend on the HAL leaving this
6238 * pointer for us to use below in reclaiming the buffer;
6239 * may want to be more defensive.
6241 outdata = malloc(outsize, M_TEMP, M_NOWAIT);
6242 if (outdata == NULL) {
6247 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
6248 if (outsize < ad->ad_out_size)
6249 ad->ad_out_size = outsize;
6250 if (outdata != NULL)
6251 error = copyout(outdata, ad->ad_out_data,
6257 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
6258 free(indata, M_TEMP);
6259 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
6260 free(outdata, M_TEMP);
6263 #endif /* ATH_DIAGAPI */
6266 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
6268 #define IS_RUNNING(ifp) \
6269 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
6270 struct ath_softc *sc = ifp->if_softc;
6271 struct ieee80211com *ic = ifp->if_l2com;
6272 struct ifreq *ifr = (struct ifreq *)data;
6278 if (IS_RUNNING(ifp)) {
6280 * To avoid rescanning another access point,
6281 * do not call ath_init() here. Instead,
6282 * only reflect promisc mode settings.
6285 } else if (ifp->if_flags & IFF_UP) {
6287 * Beware of being called during attach/detach
6288 * to reset promiscuous mode. In that case we
6289 * will still be marked UP but not RUNNING.
6290 * However trying to re-init the interface
6291 * is the wrong thing to do as we've already
6292 * torn down much of our state. There's
6293 * probably a better way to deal with this.
6295 if (!sc->sc_invalid)
6296 ath_init(sc); /* XXX lose error */
6298 ath_stop_locked(ifp);
6303 * The upper layer has already installed/removed
6304 * the multicast address(es), just recalculate the
6305 * multicast filter for the card.
6307 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
6312 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
6315 /* NB: embed these numbers to get a consistent view */
6316 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
6317 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
6319 ieee80211_getsignal(ic, &sc->sc_stats.ast_rx_rssi,
6320 &sc->sc_stats.ast_rx_noise);
6322 sc->sc_stats.ast_tx_rate = sc->sc_hwmap[sc->sc_txrate].ieeerate;
6325 * NB: Drop the softc lock in case of a page fault;
6326 * we'll accept any potential inconsisentcy in the
6327 * statistics. The alternative is to copy the data
6328 * to a local structure.
6330 return copyout(&sc->sc_stats,
6331 ifr->ifr_data, sizeof (sc->sc_stats));
6335 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
6340 error = ether_ioctl(ifp, cmd, data);
6349 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS)
6351 struct ath_softc *sc = arg1;
6352 u_int slottime = ath_hal_getslottime(sc->sc_ah);
6355 error = sysctl_handle_int(oidp, &slottime, 0, req);
6356 if (error || !req->newptr)
6358 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0;
6362 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS)
6364 struct ath_softc *sc = arg1;
6365 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah);
6368 error = sysctl_handle_int(oidp, &acktimeout, 0, req);
6369 if (error || !req->newptr)
6371 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0;
6375 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS)
6377 struct ath_softc *sc = arg1;
6378 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah);
6381 error = sysctl_handle_int(oidp, &ctstimeout, 0, req);
6382 if (error || !req->newptr)
6384 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0;
6388 ath_sysctl_softled(SYSCTL_HANDLER_ARGS)
6390 struct ath_softc *sc = arg1;
6391 int softled = sc->sc_softled;
6394 error = sysctl_handle_int(oidp, &softled, 0, req);
6395 if (error || !req->newptr)
6397 softled = (softled != 0);
6398 if (softled != sc->sc_softled) {
6400 /* NB: handle any sc_ledpin change */
6401 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
6402 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
6405 sc->sc_softled = softled;
6411 ath_sysctl_ledpin(SYSCTL_HANDLER_ARGS)
6413 struct ath_softc *sc = arg1;
6414 int ledpin = sc->sc_ledpin;
6417 error = sysctl_handle_int(oidp, &ledpin, 0, req);
6418 if (error || !req->newptr)
6420 if (ledpin != sc->sc_ledpin) {
6421 sc->sc_ledpin = ledpin;
6422 if (sc->sc_softled) {
6423 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
6424 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
6432 ath_sysctl_txantenna(SYSCTL_HANDLER_ARGS)
6434 struct ath_softc *sc = arg1;
6435 u_int txantenna = ath_hal_getantennaswitch(sc->sc_ah);
6438 error = sysctl_handle_int(oidp, &txantenna, 0, req);
6439 if (!error && req->newptr) {
6440 /* XXX assumes 2 antenna ports */
6441 if (txantenna < HAL_ANT_VARIABLE || txantenna > HAL_ANT_FIXED_B)
6443 ath_hal_setantennaswitch(sc->sc_ah, txantenna);
6445 * NB: with the switch locked this isn't meaningful,
6446 * but set it anyway so things like radiotap get
6447 * consistent info in their data.
6449 sc->sc_txantenna = txantenna;
6455 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS)
6457 struct ath_softc *sc = arg1;
6458 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah);
6461 error = sysctl_handle_int(oidp, &defantenna, 0, req);
6462 if (!error && req->newptr)
6463 ath_hal_setdefantenna(sc->sc_ah, defantenna);
6468 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS)
6470 struct ath_softc *sc = arg1;
6471 u_int diversity = ath_hal_getdiversity(sc->sc_ah);
6474 error = sysctl_handle_int(oidp, &diversity, 0, req);
6475 if (error || !req->newptr)
6477 if (!ath_hal_setdiversity(sc->sc_ah, diversity))
6479 sc->sc_diversity = diversity;
6484 ath_sysctl_diag(SYSCTL_HANDLER_ARGS)
6486 struct ath_softc *sc = arg1;
6490 if (!ath_hal_getdiag(sc->sc_ah, &diag))
6492 error = sysctl_handle_int(oidp, &diag, 0, req);
6493 if (error || !req->newptr)
6495 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0;
6499 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS)
6501 struct ath_softc *sc = arg1;
6502 struct ifnet *ifp = sc->sc_ifp;
6506 (void) ath_hal_gettpscale(sc->sc_ah, &scale);
6507 error = sysctl_handle_int(oidp, &scale, 0, req);
6508 if (error || !req->newptr)
6510 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL :
6511 (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0;
6515 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS)
6517 struct ath_softc *sc = arg1;
6518 u_int tpc = ath_hal_gettpc(sc->sc_ah);
6521 error = sysctl_handle_int(oidp, &tpc, 0, req);
6522 if (error || !req->newptr)
6524 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0;
6528 ath_sysctl_rfkill(SYSCTL_HANDLER_ARGS)
6530 struct ath_softc *sc = arg1;
6531 struct ifnet *ifp = sc->sc_ifp;
6532 struct ath_hal *ah = sc->sc_ah;
6533 u_int rfkill = ath_hal_getrfkill(ah);
6536 error = sysctl_handle_int(oidp, &rfkill, 0, req);
6537 if (error || !req->newptr)
6539 if (rfkill == ath_hal_getrfkill(ah)) /* unchanged */
6541 if (!ath_hal_setrfkill(ah, rfkill))
6543 return (ifp->if_drv_flags & IFF_DRV_RUNNING) ? ath_reset(ifp) : 0;
6547 ath_sysctl_rfsilent(SYSCTL_HANDLER_ARGS)
6549 struct ath_softc *sc = arg1;
6553 (void) ath_hal_getrfsilent(sc->sc_ah, &rfsilent);
6554 error = sysctl_handle_int(oidp, &rfsilent, 0, req);
6555 if (error || !req->newptr)
6557 if (!ath_hal_setrfsilent(sc->sc_ah, rfsilent))
6559 sc->sc_rfsilentpin = rfsilent & 0x1c;
6560 sc->sc_rfsilentpol = (rfsilent & 0x2) != 0;
6565 ath_sysctl_tpack(SYSCTL_HANDLER_ARGS)
6567 struct ath_softc *sc = arg1;
6571 (void) ath_hal_gettpack(sc->sc_ah, &tpack);
6572 error = sysctl_handle_int(oidp, &tpack, 0, req);
6573 if (error || !req->newptr)
6575 return !ath_hal_settpack(sc->sc_ah, tpack) ? EINVAL : 0;
6579 ath_sysctl_tpcts(SYSCTL_HANDLER_ARGS)
6581 struct ath_softc *sc = arg1;
6585 (void) ath_hal_gettpcts(sc->sc_ah, &tpcts);
6586 error = sysctl_handle_int(oidp, &tpcts, 0, req);
6587 if (error || !req->newptr)
6589 return !ath_hal_settpcts(sc->sc_ah, tpcts) ? EINVAL : 0;
6593 ath_sysctlattach(struct ath_softc *sc)
6595 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
6596 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
6597 struct ath_hal *ah = sc->sc_ah;
6600 sc->sc_debug = ath_debug;
6601 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6602 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
6603 "control debugging printfs");
6605 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6606 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6607 ath_sysctl_slottime, "I", "802.11 slot time (us)");
6608 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6609 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6610 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)");
6611 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6612 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6613 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)");
6614 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6615 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6616 ath_sysctl_softled, "I", "enable/disable software LED support");
6617 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6618 "ledpin", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6619 ath_sysctl_ledpin, "I", "GPIO pin connected to LED");
6620 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6621 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0,
6622 "setting to turn LED on");
6623 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6624 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0,
6625 "idle time for inactivity LED (ticks)");
6626 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6627 "txantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6628 ath_sysctl_txantenna, "I", "antenna switch");
6629 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6630 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6631 ath_sysctl_rxantenna, "I", "default/rx antenna");
6632 if (ath_hal_hasdiversity(ah))
6633 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6634 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6635 ath_sysctl_diversity, "I", "antenna diversity");
6636 sc->sc_txintrperiod = ATH_TXINTR_PERIOD;
6637 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6638 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0,
6639 "tx descriptor batching");
6640 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6641 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6642 ath_sysctl_diag, "I", "h/w diagnostic control");
6643 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6644 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6645 ath_sysctl_tpscale, "I", "tx power scaling");
6646 if (ath_hal_hastpc(ah)) {
6647 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6648 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6649 ath_sysctl_tpc, "I", "enable/disable per-packet TPC");
6650 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6651 "tpack", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6652 ath_sysctl_tpack, "I", "tx power for ack frames");
6653 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6654 "tpcts", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6655 ath_sysctl_tpcts, "I", "tx power for cts frames");
6657 if (ath_hal_hasfastframes(sc->sc_ah)) {
6658 sc->sc_fftxqmin = ATH_FF_TXQMIN;
6659 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6660 "fftxqmin", CTLFLAG_RW, &sc->sc_fftxqmin, 0,
6661 "min frames before fast-frame staging");
6662 sc->sc_fftxqmax = ATH_FF_TXQMAX;
6663 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6664 "fftxqmax", CTLFLAG_RW, &sc->sc_fftxqmax, 0,
6665 "max queued frames before tail drop");
6667 if (ath_hal_hasrfsilent(ah)) {
6668 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6669 "rfsilent", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6670 ath_sysctl_rfsilent, "I", "h/w RF silent config");
6671 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6672 "rfkill", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
6673 ath_sysctl_rfkill, "I", "enable/disable RF kill switch");
6675 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC;
6676 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
6677 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0,
6678 "mask of error frames to pass when monitoring");
6682 ath_bpfattach(struct ath_softc *sc)
6684 struct ifnet *ifp = sc->sc_ifp;
6686 bpfattach(ifp, DLT_IEEE802_11_RADIO,
6687 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th));
6689 * Initialize constant fields.
6690 * XXX make header lengths a multiple of 32-bits so subsequent
6691 * headers are properly aligned; this is a kludge to keep
6692 * certain applications happy.
6694 * NB: the channel is setup each time we transition to the
6695 * RUN state to avoid filling it in for each frame.
6697 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t));
6698 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
6699 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT);
6701 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t));
6702 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
6703 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT);
6707 ath_tx_raw_start(struct ath_softc *sc, struct ieee80211_node *ni,
6708 struct ath_buf *bf, struct mbuf *m0,
6709 const struct ieee80211_bpf_params *params)
6711 struct ifnet *ifp = sc->sc_ifp;
6712 struct ieee80211com *ic = ifp->if_l2com;
6713 struct ath_hal *ah = sc->sc_ah;
6714 int error, ismcast, ismrr;
6715 int hdrlen, pktlen, try0, txantenna;
6716 u_int8_t rix, cix, txrate, ctsrate, rate1, rate2, rate3;
6717 struct ieee80211_frame *wh;
6718 u_int flags, ctsduration;
6720 const HAL_RATE_TABLE *rt;
6721 struct ath_desc *ds;
6724 wh = mtod(m0, struct ieee80211_frame *);
6725 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
6726 hdrlen = ieee80211_anyhdrsize(wh);
6728 * Packet length must not include any
6729 * pad bytes; deduct them here.
6731 /* XXX honor IEEE80211_BPF_DATAPAD */
6732 pktlen = m0->m_pkthdr.len - (hdrlen & 3) + IEEE80211_CRC_LEN;
6734 error = ath_tx_dmasetup(sc, bf, m0);
6737 m0 = bf->bf_m; /* NB: may have changed */
6738 wh = mtod(m0, struct ieee80211_frame *);
6739 bf->bf_node = ni; /* NB: held reference */
6741 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
6742 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
6743 if (params->ibp_flags & IEEE80211_BPF_RTS)
6744 flags |= HAL_TXDESC_RTSENA;
6745 else if (params->ibp_flags & IEEE80211_BPF_CTS)
6746 flags |= HAL_TXDESC_CTSENA;
6747 /* XXX leave ismcast to injector? */
6748 if ((params->ibp_flags & IEEE80211_BPF_NOACK) || ismcast)
6749 flags |= HAL_TXDESC_NOACK;
6751 rt = sc->sc_currates;
6752 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
6753 rix = ath_tx_findrix(rt, params->ibp_rate0);
6754 txrate = rt->info[rix].rateCode;
6755 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6756 txrate |= rt->info[rix].shortPreamble;
6757 sc->sc_txrate = txrate;
6758 try0 = params->ibp_try0;
6759 ismrr = (params->ibp_try1 != 0);
6760 txantenna = params->ibp_pri >> 2;
6761 if (txantenna == 0) /* XXX? */
6762 txantenna = sc->sc_txantenna;
6764 if (flags & (HAL_TXDESC_CTSENA | HAL_TXDESC_RTSENA)) {
6765 cix = ath_tx_findrix(rt, params->ibp_ctsrate);
6766 ctsrate = rt->info[cix].rateCode;
6767 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) {
6768 ctsrate |= rt->info[cix].shortPreamble;
6769 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
6770 ctsduration += rt->info[cix].spAckDuration;
6771 ctsduration += ath_hal_computetxtime(ah,
6772 rt, pktlen, rix, AH_TRUE);
6773 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
6774 ctsduration += rt->info[rix].spAckDuration;
6776 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
6777 ctsduration += rt->info[cix].lpAckDuration;
6778 ctsduration += ath_hal_computetxtime(ah,
6779 rt, pktlen, rix, AH_FALSE);
6780 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
6781 ctsduration += rt->info[rix].lpAckDuration;
6783 ismrr = 0; /* XXX */
6786 pri = params->ibp_pri & 3;
6788 * NB: we mark all packets as type PSPOLL so the h/w won't
6789 * set the sequence number, duration, etc.
6791 atype = HAL_PKT_TYPE_PSPOLL;
6793 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
6794 ieee80211_dump_pkt(ic, mtod(m0, caddr_t), m0->m_len,
6795 sc->sc_hwmap[txrate].ieeerate, -1);
6797 if (bpf_peers_present(ifp->if_bpf)) {
6798 u_int64_t tsf = ath_hal_gettsf64(ah);
6800 sc->sc_tx_th.wt_tsf = htole64(tsf);
6801 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags;
6802 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
6803 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
6804 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate;
6805 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
6806 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
6808 bpf_mtap2(ifp->if_bpf, &sc->sc_tx_th, sc->sc_tx_th_len, m0);
6812 * Formulate first tx descriptor with tx controls.
6815 /* XXX check return value? */
6816 ath_hal_setuptxdesc(ah, ds
6817 , pktlen /* packet length */
6818 , hdrlen /* header length */
6819 , atype /* Atheros packet type */
6820 , params->ibp_power /* txpower */
6821 , txrate, try0 /* series 0 rate/tries */
6822 , HAL_TXKEYIX_INVALID /* key cache index */
6823 , txantenna /* antenna mode */
6825 , ctsrate /* rts/cts rate */
6826 , ctsduration /* rts/cts duration */
6828 bf->bf_flags = flags;
6831 rix = ath_tx_findrix(rt, params->ibp_rate1);
6832 rate1 = rt->info[rix].rateCode;
6833 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6834 rate1 |= rt->info[rix].shortPreamble;
6835 if (params->ibp_try2) {
6836 rix = ath_tx_findrix(rt, params->ibp_rate2);
6837 rate2 = rt->info[rix].rateCode;
6838 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6839 rate2 |= rt->info[rix].shortPreamble;
6842 if (params->ibp_try3) {
6843 rix = ath_tx_findrix(rt, params->ibp_rate3);
6844 rate3 = rt->info[rix].rateCode;
6845 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
6846 rate3 |= rt->info[rix].shortPreamble;
6849 ath_hal_setupxtxdesc(ah, ds
6850 , rate1, params->ibp_try1 /* series 1 */
6851 , rate2, params->ibp_try2 /* series 2 */
6852 , rate3, params->ibp_try3 /* series 3 */
6856 /* NB: no buffered multicast in power save support */
6857 ath_tx_handoff(sc, sc->sc_ac2q[pri], bf);
6862 ath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
6863 const struct ieee80211_bpf_params *params)
6865 struct ieee80211com *ic = ni->ni_ic;
6866 struct ifnet *ifp = ic->ic_ifp;
6867 struct ath_softc *sc = ifp->if_softc;
6870 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) {
6871 ieee80211_free_node(ni);
6876 * Grab a TX buffer and associated resources.
6879 bf = STAILQ_FIRST(&sc->sc_txbuf);
6881 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
6882 ATH_TXBUF_UNLOCK(sc);
6884 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n",
6886 sc->sc_stats.ast_tx_qstop++;
6887 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
6888 ieee80211_free_node(ni);
6894 sc->sc_stats.ast_tx_raw++;
6896 if (params == NULL) {
6898 * Legacy path; interpret frame contents to decide
6899 * precisely how to send the frame.
6901 if (ath_tx_start(sc, ni, bf, m))
6905 * Caller supplied explicit parameters to use in
6906 * sending the frame.
6908 if (ath_tx_raw_start(sc, ni, bf, m, params))
6917 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
6918 ATH_TXBUF_UNLOCK(sc);
6919 ieee80211_free_node(ni);
6920 return EIO; /* XXX */
6924 * Announce various information on device/driver attach.
6927 ath_announce(struct ath_softc *sc)
6929 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B)
6930 struct ifnet *ifp = sc->sc_ifp;
6931 struct ath_hal *ah = sc->sc_ah;
6934 if_printf(ifp, "mac %d.%d phy %d.%d",
6935 ah->ah_macVersion, ah->ah_macRev,
6936 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
6938 * Print radio revision(s). We check the wireless modes
6939 * to avoid falsely printing revs for inoperable parts.
6940 * Dual-band radio revs are returned in the 5Ghz rev number.
6942 ath_hal_getcountrycode(ah, &cc);
6943 modes = ath_hal_getwirelessmodes(ah, cc);
6944 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) {
6945 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev)
6946 printf(" 5ghz radio %d.%d 2ghz radio %d.%d",
6947 ah->ah_analog5GhzRev >> 4,
6948 ah->ah_analog5GhzRev & 0xf,
6949 ah->ah_analog2GhzRev >> 4,
6950 ah->ah_analog2GhzRev & 0xf);
6952 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
6953 ah->ah_analog5GhzRev & 0xf);
6955 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
6956 ah->ah_analog5GhzRev & 0xf);
6960 for (i = 0; i <= WME_AC_VO; i++) {
6961 struct ath_txq *txq = sc->sc_ac2q[i];
6962 if_printf(ifp, "Use hw queue %u for %s traffic\n",
6963 txq->axq_qnum, ieee80211_wme_acnames[i]);
6965 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
6966 sc->sc_cabq->axq_qnum);
6967 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
6969 if (ath_rxbuf != ATH_RXBUF)
6970 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
6971 if (ath_txbuf != ATH_TXBUF)
6972 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
6973 #undef HAL_MODE_DUALBAND