2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for the Atheros Wireless LAN controller.
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
56 #include <sys/malloc.h>
58 #include <sys/mutex.h>
59 #include <sys/kernel.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/errno.h>
63 #include <sys/callout.h>
65 #include <sys/endian.h>
66 #include <sys/kthread.h>
67 #include <sys/taskqueue.h>
69 #include <sys/module.h>
71 #include <sys/smp.h> /* for mp_ncpus */
73 #include <machine/bus.h>
76 #include <net/if_var.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/if_types.h>
80 #include <net/if_arp.h>
81 #include <net/ethernet.h>
82 #include <net/if_llc.h>
84 #include <net80211/ieee80211_var.h>
85 #include <net80211/ieee80211_regdomain.h>
86 #ifdef IEEE80211_SUPPORT_SUPERG
87 #include <net80211/ieee80211_superg.h>
89 #ifdef IEEE80211_SUPPORT_TDMA
90 #include <net80211/ieee80211_tdma.h>
96 #include <netinet/in.h>
97 #include <netinet/if_ether.h>
100 #include <dev/ath/if_athvar.h>
101 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
102 #include <dev/ath/ath_hal/ah_diagcodes.h>
104 #include <dev/ath/if_ath_debug.h>
105 #include <dev/ath/if_ath_misc.h>
106 #include <dev/ath/if_ath_tsf.h>
107 #include <dev/ath/if_ath_tx.h>
108 #include <dev/ath/if_ath_sysctl.h>
109 #include <dev/ath/if_ath_led.h>
110 #include <dev/ath/if_ath_keycache.h>
111 #include <dev/ath/if_ath_rx.h>
112 #include <dev/ath/if_ath_rx_edma.h>
113 #include <dev/ath/if_ath_tx_edma.h>
114 #include <dev/ath/if_ath_beacon.h>
115 #include <dev/ath/if_ath_btcoex.h>
116 #include <dev/ath/if_ath_spectral.h>
117 #include <dev/ath/if_ath_lna_div.h>
118 #include <dev/ath/if_athdfs.h>
121 #include <dev/ath/ath_tx99/ath_tx99.h>
125 #include <dev/ath/if_ath_alq.h>
129 * Only enable this if you're working on PS-POLL support.
134 * ATH_BCBUF determines the number of vap's that can transmit
135 * beacons and also (currently) the number of vap's that can
136 * have unique mac addresses/bssid. When staggering beacons
137 * 4 is probably a good max as otherwise the beacons become
138 * very closely spaced and there is limited time for cab q traffic
139 * to go out. You can burst beacons instead but that is not good
140 * for stations in power save and at some point you really want
141 * another radio (and channel).
143 * The limit on the number of mac addresses is tied to our use of
144 * the U/L bit and tracking addresses in a byte; it would be
145 * worthwhile to allow more for applications like proxy sta.
147 CTASSERT(ATH_BCBUF <= 8);
149 static struct ieee80211vap *ath_vap_create(struct ieee80211com *,
150 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
151 const uint8_t [IEEE80211_ADDR_LEN],
152 const uint8_t [IEEE80211_ADDR_LEN]);
153 static void ath_vap_delete(struct ieee80211vap *);
154 static void ath_init(void *);
155 static void ath_stop_locked(struct ifnet *);
156 static void ath_stop(struct ifnet *);
157 static int ath_reset_vap(struct ieee80211vap *, u_long);
158 static int ath_transmit(struct ifnet *ifp, struct mbuf *m);
159 static void ath_qflush(struct ifnet *ifp);
160 static int ath_media_change(struct ifnet *);
161 static void ath_watchdog(void *);
162 static int ath_ioctl(struct ifnet *, u_long, caddr_t);
163 static void ath_fatal_proc(void *, int);
164 static void ath_bmiss_vap(struct ieee80211vap *);
165 static void ath_bmiss_proc(void *, int);
166 static void ath_key_update_begin(struct ieee80211vap *);
167 static void ath_key_update_end(struct ieee80211vap *);
168 static void ath_update_mcast_hw(struct ath_softc *);
169 static void ath_update_mcast(struct ifnet *);
170 static void ath_update_promisc(struct ifnet *);
171 static void ath_updateslot(struct ifnet *);
172 static void ath_bstuck_proc(void *, int);
173 static void ath_reset_proc(void *, int);
174 static int ath_desc_alloc(struct ath_softc *);
175 static void ath_desc_free(struct ath_softc *);
176 static struct ieee80211_node *ath_node_alloc(struct ieee80211vap *,
177 const uint8_t [IEEE80211_ADDR_LEN]);
178 static void ath_node_cleanup(struct ieee80211_node *);
179 static void ath_node_free(struct ieee80211_node *);
180 static void ath_node_getsignal(const struct ieee80211_node *,
182 static void ath_txq_init(struct ath_softc *sc, struct ath_txq *, int);
183 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
184 static int ath_tx_setup(struct ath_softc *, int, int);
185 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
186 static void ath_tx_cleanup(struct ath_softc *);
187 static int ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq,
189 static void ath_tx_proc_q0(void *, int);
190 static void ath_tx_proc_q0123(void *, int);
191 static void ath_tx_proc(void *, int);
192 static void ath_txq_sched_tasklet(void *, int);
193 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
194 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
195 static void ath_scan_start(struct ieee80211com *);
196 static void ath_scan_end(struct ieee80211com *);
197 static void ath_set_channel(struct ieee80211com *);
198 #ifdef ATH_ENABLE_11N
199 static void ath_update_chw(struct ieee80211com *);
200 #endif /* ATH_ENABLE_11N */
201 static void ath_calibrate(void *);
202 static int ath_newstate(struct ieee80211vap *, enum ieee80211_state, int);
203 static void ath_setup_stationkey(struct ieee80211_node *);
204 static void ath_newassoc(struct ieee80211_node *, int);
205 static int ath_setregdomain(struct ieee80211com *,
206 struct ieee80211_regdomain *, int,
207 struct ieee80211_channel []);
208 static void ath_getradiocaps(struct ieee80211com *, int, int *,
209 struct ieee80211_channel []);
210 static int ath_getchannels(struct ath_softc *);
212 static int ath_rate_setup(struct ath_softc *, u_int mode);
213 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
215 static void ath_announce(struct ath_softc *);
217 static void ath_dfs_tasklet(void *, int);
218 static void ath_node_powersave(struct ieee80211_node *, int);
219 static int ath_node_set_tim(struct ieee80211_node *, int);
220 static void ath_node_recv_pspoll(struct ieee80211_node *, struct mbuf *);
222 #ifdef IEEE80211_SUPPORT_TDMA
223 #include <dev/ath/if_ath_tdma.h>
226 SYSCTL_DECL(_hw_ath);
228 /* XXX validate sysctl values */
229 static int ath_longcalinterval = 30; /* long cals every 30 secs */
230 SYSCTL_INT(_hw_ath, OID_AUTO, longcal, CTLFLAG_RW, &ath_longcalinterval,
231 0, "long chip calibration interval (secs)");
232 static int ath_shortcalinterval = 100; /* short cals every 100 ms */
233 SYSCTL_INT(_hw_ath, OID_AUTO, shortcal, CTLFLAG_RW, &ath_shortcalinterval,
234 0, "short chip calibration interval (msecs)");
235 static int ath_resetcalinterval = 20*60; /* reset cal state 20 mins */
236 SYSCTL_INT(_hw_ath, OID_AUTO, resetcal, CTLFLAG_RW, &ath_resetcalinterval,
237 0, "reset chip calibration results (secs)");
238 static int ath_anicalinterval = 100; /* ANI calibration - 100 msec */
239 SYSCTL_INT(_hw_ath, OID_AUTO, anical, CTLFLAG_RW, &ath_anicalinterval,
240 0, "ANI calibration (msecs)");
242 int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
243 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RWTUN, &ath_rxbuf,
244 0, "rx buffers allocated");
245 int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
246 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RWTUN, &ath_txbuf,
247 0, "tx buffers allocated");
248 int ath_txbuf_mgmt = ATH_MGMT_TXBUF; /* # mgmt tx buffers to allocate */
249 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf_mgmt, CTLFLAG_RWTUN, &ath_txbuf_mgmt,
250 0, "tx (mgmt) buffers allocated");
252 int ath_bstuck_threshold = 4; /* max missed beacons */
253 SYSCTL_INT(_hw_ath, OID_AUTO, bstuck, CTLFLAG_RW, &ath_bstuck_threshold,
254 0, "max missed beacon xmits before chip reset");
256 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
259 ath_legacy_attach_comp_func(struct ath_softc *sc)
263 * Special case certain configurations. Note the
264 * CAB queue is handled by these specially so don't
265 * include them when checking the txq setup mask.
267 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
269 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
272 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
275 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
281 * Set the target power mode.
283 * If this is called during a point in time where
284 * the hardware is being programmed elsewhere, it will
285 * simply store it away and update it when all current
286 * uses of the hardware are completed.
289 _ath_power_setpower(struct ath_softc *sc, int power_state, const char *file, int line)
293 sc->sc_target_powerstate = power_state;
295 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n",
300 sc->sc_powersave_refcnt);
302 if (sc->sc_powersave_refcnt == 0 &&
303 power_state != sc->sc_cur_powerstate) {
304 sc->sc_cur_powerstate = power_state;
305 ath_hal_setpower(sc->sc_ah, power_state);
308 * If the NIC is force-awake, then set the
309 * self-gen frame state appropriately.
311 * If the nic is in network sleep or full-sleep,
312 * we let the above call leave the self-gen
315 if (sc->sc_cur_powerstate == HAL_PM_AWAKE &&
316 sc->sc_target_selfgen_state != HAL_PM_AWAKE) {
317 ath_hal_setselfgenpower(sc->sc_ah,
318 sc->sc_target_selfgen_state);
324 * Set the current self-generated frames state.
326 * This is separate from the target power mode. The chip may be
327 * awake but the desired state is "sleep", so frames sent to the
328 * destination has PWRMGT=1 in the 802.11 header. The NIC also
329 * needs to know to set PWRMGT=1 in self-generated frames.
332 _ath_power_set_selfgen(struct ath_softc *sc, int power_state, const char *file, int line)
337 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n",
342 sc->sc_target_selfgen_state);
344 sc->sc_target_selfgen_state = power_state;
347 * If the NIC is force-awake, then set the power state.
348 * Network-state and full-sleep will already transition it to
349 * mark self-gen frames as sleeping - and we can't
350 * guarantee the NIC is awake to program the self-gen frame
353 if (sc->sc_cur_powerstate == HAL_PM_AWAKE) {
354 ath_hal_setselfgenpower(sc->sc_ah, power_state);
359 * Set the hardware power mode and take a reference.
361 * This doesn't update the target power mode in the driver;
362 * it just updates the hardware power state.
364 * XXX it should only ever force the hardware awake; it should
365 * never be called to set it asleep.
368 _ath_power_set_power_state(struct ath_softc *sc, int power_state, const char *file, int line)
372 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) state=%d, refcnt=%d\n",
377 sc->sc_powersave_refcnt);
379 sc->sc_powersave_refcnt++;
381 if (power_state != sc->sc_cur_powerstate) {
382 ath_hal_setpower(sc->sc_ah, power_state);
383 sc->sc_cur_powerstate = power_state;
386 * Adjust the self-gen powerstate if appropriate.
388 if (sc->sc_cur_powerstate == HAL_PM_AWAKE &&
389 sc->sc_target_selfgen_state != HAL_PM_AWAKE) {
390 ath_hal_setselfgenpower(sc->sc_ah,
391 sc->sc_target_selfgen_state);
398 * Restore the power save mode to what it once was.
400 * This will decrement the reference counter and once it hits
401 * zero, it'll restore the powersave state.
404 _ath_power_restore_power_state(struct ath_softc *sc, const char *file, int line)
409 DPRINTF(sc, ATH_DEBUG_PWRSAVE, "%s: (%s:%d) refcnt=%d, target state=%d\n",
413 sc->sc_powersave_refcnt,
414 sc->sc_target_powerstate);
416 if (sc->sc_powersave_refcnt == 0)
417 device_printf(sc->sc_dev, "%s: refcnt=0?\n", __func__);
419 sc->sc_powersave_refcnt--;
421 if (sc->sc_powersave_refcnt == 0 &&
422 sc->sc_target_powerstate != sc->sc_cur_powerstate) {
423 sc->sc_cur_powerstate = sc->sc_target_powerstate;
424 ath_hal_setpower(sc->sc_ah, sc->sc_target_powerstate);
428 * Adjust the self-gen powerstate if appropriate.
430 if (sc->sc_cur_powerstate == HAL_PM_AWAKE &&
431 sc->sc_target_selfgen_state != HAL_PM_AWAKE) {
432 ath_hal_setselfgenpower(sc->sc_ah,
433 sc->sc_target_selfgen_state);
439 * Configure the initial HAL configuration values based on bus
440 * specific parameters.
442 * Some PCI IDs and other information may need tweaking.
444 * XXX TODO: ath9k and the Atheros HAL only program comm2g_switch_enable
445 * if BT antenna diversity isn't enabled.
447 * So, let's also figure out how to enable BT diversity for AR9485.
450 ath_setup_hal_config(struct ath_softc *sc, HAL_OPS_CONFIG *ah_config)
452 /* XXX TODO: only for PCI devices? */
454 if (sc->sc_pci_devinfo & (ATH_PCI_CUS198 | ATH_PCI_CUS230)) {
455 ah_config->ath_hal_ext_lna_ctl_gpio = 0x200; /* bit 9 */
456 ah_config->ath_hal_ext_atten_margin_cfg = AH_TRUE;
457 ah_config->ath_hal_min_gainidx = AH_TRUE;
458 ah_config->ath_hal_ant_ctrl_comm2g_switch_enable = 0x000bbb88;
459 /* XXX low_rssi_thresh */
460 /* XXX fast_div_bias */
461 device_printf(sc->sc_dev, "configuring for %s\n",
462 (sc->sc_pci_devinfo & ATH_PCI_CUS198) ?
463 "CUS198" : "CUS230");
466 if (sc->sc_pci_devinfo & ATH_PCI_CUS217)
467 device_printf(sc->sc_dev, "CUS217 card detected\n");
469 if (sc->sc_pci_devinfo & ATH_PCI_CUS252)
470 device_printf(sc->sc_dev, "CUS252 card detected\n");
472 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_1ANT)
473 device_printf(sc->sc_dev, "WB335 1-ANT card detected\n");
475 if (sc->sc_pci_devinfo & ATH_PCI_AR9565_2ANT)
476 device_printf(sc->sc_dev, "WB335 2-ANT card detected\n");
478 if (sc->sc_pci_devinfo & ATH_PCI_KILLER)
479 device_printf(sc->sc_dev, "Killer Wireless card detected\n");
483 * Some WB335 cards do not support antenna diversity. Since
484 * we use a hardcoded value for AR9565 instead of using the
485 * EEPROM/OTP data, remove the combining feature from
486 * the HW capabilities bitmap.
488 if (sc->sc_pci_devinfo & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
489 if (!(sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV))
490 pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
493 if (sc->sc_pci_devinfo & ATH9K_PCI_BT_ANT_DIV) {
494 pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
495 device_printf(sc->sc_dev, "Set BT/WLAN RX diversity capability\n");
499 if (sc->sc_pci_devinfo & ATH_PCI_D3_L1_WAR) {
500 ah_config->ath_hal_pcie_waen = 0x0040473b;
501 device_printf(sc->sc_dev, "Enable WAR for ASPM D3/L1\n");
505 if (sc->sc_pci_devinfo & ATH9K_PCI_NO_PLL_PWRSAVE) {
506 ah->config.no_pll_pwrsave = true;
507 device_printf(sc->sc_dev, "Disable PLL PowerSave\n");
513 #define HAL_MODE_HT20 (HAL_MODE_11NG_HT20 | HAL_MODE_11NA_HT20)
514 #define HAL_MODE_HT40 \
515 (HAL_MODE_11NG_HT40PLUS | HAL_MODE_11NG_HT40MINUS | \
516 HAL_MODE_11NA_HT40PLUS | HAL_MODE_11NA_HT40MINUS)
518 ath_attach(u_int16_t devid, struct ath_softc *sc)
521 struct ieee80211com *ic;
522 struct ath_hal *ah = NULL;
526 uint8_t macaddr[IEEE80211_ADDR_LEN];
527 int rx_chainmask, tx_chainmask;
528 HAL_OPS_CONFIG ah_config;
530 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
533 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
535 device_printf(sc->sc_dev, "can not if_alloc()\n");
542 /* set these up early for if_printf use */
543 if_initname(ifp, device_get_name(sc->sc_dev),
544 device_get_unit(sc->sc_dev));
548 * Configure the initial configuration data.
550 * This is stuff that may be needed early during attach
551 * rather than done via configuration calls later.
553 bzero(&ah_config, sizeof(ah_config));
554 ath_setup_hal_config(sc, &ah_config);
556 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh,
557 sc->sc_eepromdata, &ah_config, &status);
559 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
565 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
567 sc->sc_debug = ath_debug;
571 * Setup the DMA/EDMA functions based on the current
574 * This is required before the descriptors are allocated.
576 if (ath_hal_hasedma(sc->sc_ah)) {
578 ath_recv_setup_edma(sc);
579 ath_xmit_setup_edma(sc);
581 ath_recv_setup_legacy(sc);
582 ath_xmit_setup_legacy(sc);
585 if (ath_hal_hasmybeacon(sc->sc_ah)) {
586 sc->sc_do_mybeacon = 1;
590 * Check if the MAC has multi-rate retry support.
591 * We do this by trying to setup a fake extended
592 * descriptor. MAC's that don't have support will
593 * return false w/o doing anything. MAC's that do
594 * support it will return true w/o doing anything.
596 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
599 * Check if the device has hardware counters for PHY
600 * errors. If so we need to enable the MIB interrupt
601 * so we can act on stat triggers.
603 if (ath_hal_hwphycounters(ah))
607 * Get the hardware key cache size.
609 sc->sc_keymax = ath_hal_keycachesize(ah);
610 if (sc->sc_keymax > ATH_KEYMAX) {
611 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
612 ATH_KEYMAX, sc->sc_keymax);
613 sc->sc_keymax = ATH_KEYMAX;
616 * Reset the key cache since some parts do not
617 * reset the contents on initial power up.
619 for (i = 0; i < sc->sc_keymax; i++)
620 ath_hal_keyreset(ah, i);
623 * Collect the default channel list.
625 error = ath_getchannels(sc);
630 * Setup rate tables for all potential media types.
632 ath_rate_setup(sc, IEEE80211_MODE_11A);
633 ath_rate_setup(sc, IEEE80211_MODE_11B);
634 ath_rate_setup(sc, IEEE80211_MODE_11G);
635 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
636 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
637 ath_rate_setup(sc, IEEE80211_MODE_STURBO_A);
638 ath_rate_setup(sc, IEEE80211_MODE_11NA);
639 ath_rate_setup(sc, IEEE80211_MODE_11NG);
640 ath_rate_setup(sc, IEEE80211_MODE_HALF);
641 ath_rate_setup(sc, IEEE80211_MODE_QUARTER);
643 /* NB: setup here so ath_rate_update is happy */
644 ath_setcurmode(sc, IEEE80211_MODE_11A);
647 * Allocate TX descriptors and populate the lists.
649 error = ath_desc_alloc(sc);
651 if_printf(ifp, "failed to allocate TX descriptors: %d\n",
655 error = ath_txdma_setup(sc);
657 if_printf(ifp, "failed to allocate TX descriptors: %d\n",
663 * Allocate RX descriptors and populate the lists.
665 error = ath_rxdma_setup(sc);
667 if_printf(ifp, "failed to allocate RX descriptors: %d\n",
672 callout_init_mtx(&sc->sc_cal_ch, &sc->sc_mtx, 0);
673 callout_init_mtx(&sc->sc_wd_ch, &sc->sc_mtx, 0);
675 ATH_TXBUF_LOCK_INIT(sc);
677 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT,
678 taskqueue_thread_enqueue, &sc->sc_tq);
679 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET,
680 "%s taskq", ifp->if_xname);
682 TASK_INIT(&sc->sc_rxtask, 0, sc->sc_rx.recv_tasklet, sc);
683 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
684 TASK_INIT(&sc->sc_bstucktask,0, ath_bstuck_proc, sc);
685 TASK_INIT(&sc->sc_resettask,0, ath_reset_proc, sc);
686 TASK_INIT(&sc->sc_txqtask, 0, ath_txq_sched_tasklet, sc);
687 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc);
690 * Allocate hardware transmit queues: one queue for
691 * beacon frames and one data queue for each QoS
692 * priority. Note that the hal handles resetting
693 * these queues at the needed time.
697 sc->sc_bhalq = ath_beaconq_setup(sc);
698 if (sc->sc_bhalq == (u_int) -1) {
699 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
703 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
704 if (sc->sc_cabq == NULL) {
705 if_printf(ifp, "unable to setup CAB xmit queue!\n");
709 /* NB: insure BK queue is the lowest priority h/w queue */
710 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
711 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
712 ieee80211_wme_acnames[WME_AC_BK]);
716 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
717 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
718 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
720 * Not enough hardware tx queues to properly do WME;
721 * just punt and assign them all to the same h/w queue.
722 * We could do a better job of this if, for example,
723 * we allocate queues when we switch from station to
726 if (sc->sc_ac2q[WME_AC_VI] != NULL)
727 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
728 if (sc->sc_ac2q[WME_AC_BE] != NULL)
729 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
730 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
731 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
732 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
736 * Attach the TX completion function.
738 * The non-EDMA chips may have some special case optimisations;
739 * this method gives everyone a chance to attach cleanly.
741 sc->sc_tx.xmit_attach_comp_func(sc);
744 * Setup rate control. Some rate control modules
745 * call back to change the anntena state so expose
746 * the necessary entry points.
747 * XXX maybe belongs in struct ath_ratectrl?
749 sc->sc_setdefantenna = ath_setdefantenna;
750 sc->sc_rc = ath_rate_attach(sc);
751 if (sc->sc_rc == NULL) {
756 /* Attach DFS module */
757 if (! ath_dfs_attach(sc)) {
758 device_printf(sc->sc_dev,
759 "%s: unable to attach DFS\n", __func__);
764 /* Attach spectral module */
765 if (ath_spectral_attach(sc) < 0) {
766 device_printf(sc->sc_dev,
767 "%s: unable to attach spectral\n", __func__);
772 /* Attach bluetooth coexistence module */
773 if (ath_btcoex_attach(sc) < 0) {
774 device_printf(sc->sc_dev,
775 "%s: unable to attach bluetooth coexistence\n", __func__);
780 /* Attach LNA diversity module */
781 if (ath_lna_div_attach(sc) < 0) {
782 device_printf(sc->sc_dev,
783 "%s: unable to attach LNA diversity\n", __func__);
788 /* Start DFS processing tasklet */
789 TASK_INIT(&sc->sc_dfstask, 0, ath_dfs_tasklet, sc);
791 /* Configure LED state */
794 sc->sc_ledon = 0; /* low true */
795 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
796 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE);
799 * Don't setup hardware-based blinking.
801 * Although some NICs may have this configured in the
802 * default reset register values, the user may wish
803 * to alter which pins have which function.
805 * The reference driver attaches the MAC network LED to GPIO1 and
806 * the MAC power LED to GPIO2. However, the DWA-552 cardbus
807 * NIC has these reversed.
809 sc->sc_hardled = (1 == 0);
810 sc->sc_led_net_pin = -1;
811 sc->sc_led_pwr_pin = -1;
813 * Auto-enable soft led processing for IBM cards and for
814 * 5211 minipci cards. Users can also manually enable/disable
815 * support with a sysctl.
817 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
819 ath_hal_setledstate(ah, HAL_LED_INIT);
822 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
823 ifp->if_transmit = ath_transmit;
824 ifp->if_qflush = ath_qflush;
825 ifp->if_ioctl = ath_ioctl;
826 ifp->if_init = ath_init;
827 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
828 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
829 IFQ_SET_READY(&ifp->if_snd);
832 /* XXX not right but it's not used anywhere important */
833 ic->ic_phytype = IEEE80211_T_OFDM;
834 ic->ic_opmode = IEEE80211_M_STA;
836 IEEE80211_C_STA /* station mode */
837 | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
838 | IEEE80211_C_HOSTAP /* hostap mode */
839 | IEEE80211_C_MONITOR /* monitor mode */
840 | IEEE80211_C_AHDEMO /* adhoc demo mode */
841 | IEEE80211_C_WDS /* 4-address traffic works */
842 | IEEE80211_C_MBSS /* mesh point link mode */
843 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
844 | IEEE80211_C_SHSLOT /* short slot time supported */
845 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
846 #ifndef ATH_ENABLE_11N
847 | IEEE80211_C_BGSCAN /* capable of bg scanning */
849 | IEEE80211_C_TXFRAG /* handle tx frags */
850 #ifdef ATH_ENABLE_DFS
851 | IEEE80211_C_DFS /* Enable radar detection */
853 | IEEE80211_C_PMGT /* Station side power mgmt */
854 | IEEE80211_C_SWSLEEP
857 * Query the hal to figure out h/w crypto support.
859 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
860 ic->ic_cryptocaps |= IEEE80211_CRYPTO_WEP;
861 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
862 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_OCB;
863 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
864 ic->ic_cryptocaps |= IEEE80211_CRYPTO_AES_CCM;
865 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
866 ic->ic_cryptocaps |= IEEE80211_CRYPTO_CKIP;
867 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
868 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIP;
870 * Check if h/w does the MIC and/or whether the
871 * separate key cache entries are required to
872 * handle both tx+rx MIC keys.
874 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
875 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
877 * If the h/w supports storing tx+rx MIC keys
878 * in one cache slot automatically enable use.
880 if (ath_hal_hastkipsplit(ah) ||
881 !ath_hal_settkipsplit(ah, AH_FALSE))
884 * If the h/w can do TKIP MIC together with WME then
885 * we use it; otherwise we force the MIC to be done
886 * in software by the net80211 layer.
888 if (ath_hal_haswmetkipmic(ah))
889 sc->sc_wmetkipmic = 1;
891 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
893 * Check for multicast key search support.
895 if (ath_hal_hasmcastkeysearch(sc->sc_ah) &&
896 !ath_hal_getmcastkeysearch(sc->sc_ah)) {
897 ath_hal_setmcastkeysearch(sc->sc_ah, 1);
899 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
901 * Mark key cache slots associated with global keys
902 * as in use. If we knew TKIP was not to be used we
903 * could leave the +32, +64, and +32+64 slots free.
905 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
906 setbit(sc->sc_keymap, i);
907 setbit(sc->sc_keymap, i+64);
908 if (sc->sc_splitmic) {
909 setbit(sc->sc_keymap, i+32);
910 setbit(sc->sc_keymap, i+32+64);
914 * TPC support can be done either with a global cap or
915 * per-packet support. The latter is not available on
916 * all parts. We're a bit pedantic here as all parts
917 * support a global cap.
919 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
920 ic->ic_caps |= IEEE80211_C_TXPMGT;
923 * Mark WME capability only if we have sufficient
924 * hardware queues to do proper priority scheduling.
926 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
927 ic->ic_caps |= IEEE80211_C_WME;
929 * Check for misc other capabilities.
931 if (ath_hal_hasbursting(ah))
932 ic->ic_caps |= IEEE80211_C_BURST;
933 sc->sc_hasbmask = ath_hal_hasbssidmask(ah);
934 sc->sc_hasbmatch = ath_hal_hasbssidmatch(ah);
935 sc->sc_hastsfadd = ath_hal_hastsfadjust(ah);
936 sc->sc_rxslink = ath_hal_self_linked_final_rxdesc(ah);
937 sc->sc_rxtsf32 = ath_hal_has_long_rxdesc_tsf(ah);
938 sc->sc_hasenforcetxop = ath_hal_hasenforcetxop(ah);
939 sc->sc_rx_lnamixer = ath_hal_hasrxlnamixer(ah);
940 sc->sc_hasdivcomb = ath_hal_hasdivantcomb(ah);
942 if (ath_hal_hasfastframes(ah))
943 ic->ic_caps |= IEEE80211_C_FF;
944 wmodes = ath_hal_getwirelessmodes(ah);
945 if (wmodes & (HAL_MODE_108G|HAL_MODE_TURBO))
946 ic->ic_caps |= IEEE80211_C_TURBOP;
947 #ifdef IEEE80211_SUPPORT_TDMA
948 if (ath_hal_macversion(ah) > 0x78) {
949 ic->ic_caps |= IEEE80211_C_TDMA; /* capable of TDMA */
950 ic->ic_tdma_update = ath_tdma_update;
955 * TODO: enforce that at least this many frames are available
956 * in the txbuf list before allowing data frames (raw or
957 * otherwise) to be transmitted.
959 sc->sc_txq_data_minfree = 10;
961 * Leave this as default to maintain legacy behaviour.
962 * Shortening the cabq/mcastq may end up causing some
963 * undesirable behaviour.
965 sc->sc_txq_mcastq_maxdepth = ath_txbuf;
968 * How deep can the node software TX queue get whilst it's asleep.
970 sc->sc_txq_node_psq_maxdepth = 16;
973 * Default the maximum queue depth for a given node
974 * to 1/4'th the TX buffers, or 64, whichever
977 sc->sc_txq_node_maxdepth = MAX(64, ath_txbuf / 4);
979 /* Enable CABQ by default */
980 sc->sc_cabq_enable = 1;
983 * Allow the TX and RX chainmasks to be overridden by
984 * environment variables and/or device.hints.
986 * This must be done early - before the hardware is
987 * calibrated or before the 802.11n stream calculation
990 if (resource_int_value(device_get_name(sc->sc_dev),
991 device_get_unit(sc->sc_dev), "rx_chainmask",
992 &rx_chainmask) == 0) {
993 device_printf(sc->sc_dev, "Setting RX chainmask to 0x%x\n",
995 (void) ath_hal_setrxchainmask(sc->sc_ah, rx_chainmask);
997 if (resource_int_value(device_get_name(sc->sc_dev),
998 device_get_unit(sc->sc_dev), "tx_chainmask",
999 &tx_chainmask) == 0) {
1000 device_printf(sc->sc_dev, "Setting TX chainmask to 0x%x\n",
1002 (void) ath_hal_settxchainmask(sc->sc_ah, tx_chainmask);
1006 * Query the TX/RX chainmask configuration.
1008 * This is only relevant for 11n devices.
1010 ath_hal_getrxchainmask(ah, &sc->sc_rxchainmask);
1011 ath_hal_gettxchainmask(ah, &sc->sc_txchainmask);
1014 * Disable MRR with protected frames by default.
1015 * Only 802.11n series NICs can handle this.
1017 sc->sc_mrrprot = 0; /* XXX should be a capability */
1020 * Query the enterprise mode information the HAL.
1022 if (ath_hal_getcapability(ah, HAL_CAP_ENTERPRISE_MODE, 0,
1023 &sc->sc_ent_cfg) == HAL_OK)
1026 #ifdef ATH_ENABLE_11N
1028 * Query HT capabilities
1030 if (ath_hal_getcapability(ah, HAL_CAP_HT, 0, NULL) == HAL_OK &&
1031 (wmodes & (HAL_MODE_HT20 | HAL_MODE_HT40))) {
1034 device_printf(sc->sc_dev, "[HT] enabling HT modes\n");
1036 sc->sc_mrrprot = 1; /* XXX should be a capability */
1038 ic->ic_htcaps = IEEE80211_HTC_HT /* HT operation */
1039 | IEEE80211_HTC_AMPDU /* A-MPDU tx/rx */
1040 | IEEE80211_HTC_AMSDU /* A-MSDU tx/rx */
1041 | IEEE80211_HTCAP_MAXAMSDU_3839
1042 /* max A-MSDU length */
1043 | IEEE80211_HTCAP_SMPS_OFF; /* SM power save off */
1047 * Enable short-GI for HT20 only if the hardware
1048 * advertises support.
1049 * Notably, anything earlier than the AR9287 doesn't.
1051 if ((ath_hal_getcapability(ah,
1052 HAL_CAP_HT20_SGI, 0, NULL) == HAL_OK) &&
1053 (wmodes & HAL_MODE_HT20)) {
1054 device_printf(sc->sc_dev,
1055 "[HT] enabling short-GI in 20MHz mode\n");
1056 ic->ic_htcaps |= IEEE80211_HTCAP_SHORTGI20;
1059 if (wmodes & HAL_MODE_HT40)
1060 ic->ic_htcaps |= IEEE80211_HTCAP_CHWIDTH40
1061 | IEEE80211_HTCAP_SHORTGI40;
1064 * TX/RX streams need to be taken into account when
1065 * negotiating which MCS rates it'll receive and
1066 * what MCS rates are available for TX.
1068 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 0, &txs);
1069 (void) ath_hal_getcapability(ah, HAL_CAP_STREAMS, 1, &rxs);
1070 ic->ic_txstream = txs;
1071 ic->ic_rxstream = rxs;
1074 * Setup TX and RX STBC based on what the HAL allows and
1075 * the currently configured chainmask set.
1076 * Ie - don't enable STBC TX if only one chain is enabled.
1077 * STBC RX is fine on a single RX chain; it just won't
1078 * provide any real benefit.
1080 if (ath_hal_getcapability(ah, HAL_CAP_RX_STBC, 0,
1083 device_printf(sc->sc_dev,
1084 "[HT] 1 stream STBC receive enabled\n");
1085 ic->ic_htcaps |= IEEE80211_HTCAP_RXSTBC_1STREAM;
1087 if (txs > 1 && ath_hal_getcapability(ah, HAL_CAP_TX_STBC, 0,
1090 device_printf(sc->sc_dev,
1091 "[HT] 1 stream STBC transmit enabled\n");
1092 ic->ic_htcaps |= IEEE80211_HTCAP_TXSTBC;
1095 (void) ath_hal_getcapability(ah, HAL_CAP_RTS_AGGR_LIMIT, 1,
1096 &sc->sc_rts_aggr_limit);
1097 if (sc->sc_rts_aggr_limit != (64 * 1024))
1098 device_printf(sc->sc_dev,
1099 "[HT] RTS aggregates limited to %d KiB\n",
1100 sc->sc_rts_aggr_limit / 1024);
1102 device_printf(sc->sc_dev,
1103 "[HT] %d RX streams; %d TX streams\n", rxs, txs);
1108 * Initial aggregation settings.
1110 sc->sc_hwq_limit_aggr = ATH_AGGR_MIN_QDEPTH;
1111 sc->sc_hwq_limit_nonaggr = ATH_NONAGGR_MIN_QDEPTH;
1112 sc->sc_tid_hwq_lo = ATH_AGGR_SCHED_LOW;
1113 sc->sc_tid_hwq_hi = ATH_AGGR_SCHED_HIGH;
1114 sc->sc_aggr_limit = ATH_AGGR_MAXSIZE;
1115 sc->sc_delim_min_pad = 0;
1118 * Check if the hardware requires PCI register serialisation.
1119 * Some of the Owl based MACs require this.
1122 ath_hal_getcapability(ah, HAL_CAP_SERIALISE_WAR,
1123 0, NULL) == HAL_OK) {
1124 sc->sc_ah->ah_config.ah_serialise_reg_war = 1;
1125 device_printf(sc->sc_dev,
1126 "Enabling register serialisation\n");
1130 * Initialise the deferred completed RX buffer list.
1132 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP]);
1133 TAILQ_INIT(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP]);
1136 * Indicate we need the 802.11 header padded to a
1137 * 32-bit boundary for 4-address and QoS frames.
1139 ic->ic_flags |= IEEE80211_F_DATAPAD;
1142 * Query the hal about antenna support.
1144 sc->sc_defant = ath_hal_getdefantenna(ah);
1147 * Not all chips have the VEOL support we want to
1148 * use with IBSS beacons; check here for it.
1150 sc->sc_hasveol = ath_hal_hasveol(ah);
1152 /* get mac address from hardware */
1153 ath_hal_getmac(ah, macaddr);
1154 if (sc->sc_hasbmask)
1155 ath_hal_getbssidmask(ah, sc->sc_hwbssidmask);
1157 /* NB: used to size node table key mapping array */
1158 ic->ic_max_keyix = sc->sc_keymax;
1159 /* call MI attach routine. */
1160 ieee80211_ifattach(ic, macaddr);
1161 ic->ic_setregdomain = ath_setregdomain;
1162 ic->ic_getradiocaps = ath_getradiocaps;
1163 sc->sc_opmode = HAL_M_STA;
1165 /* override default methods */
1166 ic->ic_newassoc = ath_newassoc;
1167 ic->ic_updateslot = ath_updateslot;
1168 ic->ic_wme.wme_update = ath_wme_update;
1169 ic->ic_vap_create = ath_vap_create;
1170 ic->ic_vap_delete = ath_vap_delete;
1171 ic->ic_raw_xmit = ath_raw_xmit;
1172 ic->ic_update_mcast = ath_update_mcast;
1173 ic->ic_update_promisc = ath_update_promisc;
1174 ic->ic_node_alloc = ath_node_alloc;
1175 sc->sc_node_free = ic->ic_node_free;
1176 ic->ic_node_free = ath_node_free;
1177 sc->sc_node_cleanup = ic->ic_node_cleanup;
1178 ic->ic_node_cleanup = ath_node_cleanup;
1179 ic->ic_node_getsignal = ath_node_getsignal;
1180 ic->ic_scan_start = ath_scan_start;
1181 ic->ic_scan_end = ath_scan_end;
1182 ic->ic_set_channel = ath_set_channel;
1183 #ifdef ATH_ENABLE_11N
1184 /* 802.11n specific - but just override anyway */
1185 sc->sc_addba_request = ic->ic_addba_request;
1186 sc->sc_addba_response = ic->ic_addba_response;
1187 sc->sc_addba_stop = ic->ic_addba_stop;
1188 sc->sc_bar_response = ic->ic_bar_response;
1189 sc->sc_addba_response_timeout = ic->ic_addba_response_timeout;
1191 ic->ic_addba_request = ath_addba_request;
1192 ic->ic_addba_response = ath_addba_response;
1193 ic->ic_addba_response_timeout = ath_addba_response_timeout;
1194 ic->ic_addba_stop = ath_addba_stop;
1195 ic->ic_bar_response = ath_bar_response;
1197 ic->ic_update_chw = ath_update_chw;
1198 #endif /* ATH_ENABLE_11N */
1200 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
1202 * There's one vendor bitmap entry in the RX radiotap
1203 * header; make sure that's taken into account.
1205 ieee80211_radiotap_attachv(ic,
1206 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 0,
1207 ATH_TX_RADIOTAP_PRESENT,
1208 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 1,
1209 ATH_RX_RADIOTAP_PRESENT);
1212 * No vendor bitmap/extensions are present.
1214 ieee80211_radiotap_attach(ic,
1215 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
1216 ATH_TX_RADIOTAP_PRESENT,
1217 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
1218 ATH_RX_RADIOTAP_PRESENT);
1219 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
1222 * Setup the ALQ logging if required
1224 #ifdef ATH_DEBUG_ALQ
1225 if_ath_alq_init(&sc->sc_alq, device_get_nameunit(sc->sc_dev));
1226 if_ath_alq_setcfg(&sc->sc_alq,
1227 sc->sc_ah->ah_macVersion,
1228 sc->sc_ah->ah_macRev,
1229 sc->sc_ah->ah_phyRev,
1230 sc->sc_ah->ah_magic);
1234 * Setup dynamic sysctl's now that country code and
1235 * regdomain are available from the hal.
1237 ath_sysctlattach(sc);
1238 ath_sysctl_stats_attach(sc);
1239 ath_sysctl_hal_attach(sc);
1242 ieee80211_announce(ic);
1246 * Put it to sleep for now.
1249 ath_power_setpower(sc, HAL_PM_FULL_SLEEP);
1256 ath_txdma_teardown(sc);
1257 ath_rxdma_teardown(sc);
1263 * To work around scoping issues with CURVNET_SET/CURVNET_RESTORE..
1265 if (ifp != NULL && ifp->if_vnet) {
1266 CURVNET_SET(ifp->if_vnet);
1269 } else if (ifp != NULL)
1276 ath_detach(struct ath_softc *sc)
1278 struct ifnet *ifp = sc->sc_ifp;
1280 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1281 __func__, ifp->if_flags);
1284 * NB: the order of these is important:
1285 * o stop the chip so no more interrupts will fire
1286 * o call the 802.11 layer before detaching the hal to
1287 * insure callbacks into the driver to delete global
1288 * key cache entries can be handled
1289 * o free the taskqueue which drains any pending tasks
1290 * o reclaim the tx queue data structures after calling
1291 * the 802.11 layer as we'll get called back to reclaim
1292 * node state and potentially want to use them
1293 * o to cleanup the tx queues the hal is called, so detach
1295 * Other than that, it's straightforward...
1299 * XXX Wake the hardware up first. ath_stop() will still
1300 * wake it up first, but I'd rather do it here just to
1301 * ensure it's awake.
1304 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1305 ath_power_setpower(sc, HAL_PM_AWAKE);
1309 * Stop things cleanly.
1313 ieee80211_ifdetach(ifp->if_l2com);
1314 taskqueue_free(sc->sc_tq);
1315 #ifdef ATH_TX99_DIAG
1316 if (sc->sc_tx99 != NULL)
1317 sc->sc_tx99->detach(sc->sc_tx99);
1319 ath_rate_detach(sc->sc_rc);
1320 #ifdef ATH_DEBUG_ALQ
1321 if_ath_alq_tidyup(&sc->sc_alq);
1323 ath_lna_div_detach(sc);
1324 ath_btcoex_detach(sc);
1325 ath_spectral_detach(sc);
1328 ath_txdma_teardown(sc);
1329 ath_rxdma_teardown(sc);
1331 ath_hal_detach(sc->sc_ah); /* NB: sets chip in full sleep */
1333 CURVNET_SET(ifp->if_vnet);
1341 * MAC address handling for multiple BSS on the same radio.
1342 * The first vap uses the MAC address from the EEPROM. For
1343 * subsequent vap's we set the U/L bit (bit 1) in the MAC
1344 * address and use the next six bits as an index.
1347 assign_address(struct ath_softc *sc, uint8_t mac[IEEE80211_ADDR_LEN], int clone)
1351 if (clone && sc->sc_hasbmask) {
1352 /* NB: we only do this if h/w supports multiple bssid */
1353 for (i = 0; i < 8; i++)
1354 if ((sc->sc_bssidmask & (1<<i)) == 0)
1357 mac[0] |= (i << 2)|0x2;
1360 sc->sc_bssidmask |= 1<<i;
1361 sc->sc_hwbssidmask[0] &= ~mac[0];
1367 reclaim_address(struct ath_softc *sc, const uint8_t mac[IEEE80211_ADDR_LEN])
1369 int i = mac[0] >> 2;
1372 if (i != 0 || --sc->sc_nbssid0 == 0) {
1373 sc->sc_bssidmask &= ~(1<<i);
1374 /* recalculate bssid mask from remaining addresses */
1376 for (i = 1; i < 8; i++)
1377 if (sc->sc_bssidmask & (1<<i))
1378 mask &= ~((i<<2)|0x2);
1379 sc->sc_hwbssidmask[0] |= mask;
1384 * Assign a beacon xmit slot. We try to space out
1385 * assignments so when beacons are staggered the
1386 * traffic coming out of the cab q has maximal time
1387 * to go out before the next beacon is scheduled.
1390 assign_bslot(struct ath_softc *sc)
1395 for (slot = 0; slot < ATH_BCBUF; slot++)
1396 if (sc->sc_bslot[slot] == NULL) {
1397 if (sc->sc_bslot[(slot+1)%ATH_BCBUF] == NULL &&
1398 sc->sc_bslot[(slot-1)%ATH_BCBUF] == NULL)
1401 /* NB: keep looking for a double slot */
1406 static struct ieee80211vap *
1407 ath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1408 enum ieee80211_opmode opmode, int flags,
1409 const uint8_t bssid[IEEE80211_ADDR_LEN],
1410 const uint8_t mac0[IEEE80211_ADDR_LEN])
1412 struct ath_softc *sc = ic->ic_ifp->if_softc;
1413 struct ath_vap *avp;
1414 struct ieee80211vap *vap;
1415 uint8_t mac[IEEE80211_ADDR_LEN];
1416 int needbeacon, error;
1417 enum ieee80211_opmode ic_opmode;
1419 avp = (struct ath_vap *) malloc(sizeof(struct ath_vap),
1420 M_80211_VAP, M_WAITOK | M_ZERO);
1422 IEEE80211_ADDR_COPY(mac, mac0);
1425 ic_opmode = opmode; /* default to opmode of new vap */
1427 case IEEE80211_M_STA:
1428 if (sc->sc_nstavaps != 0) { /* XXX only 1 for now */
1429 device_printf(sc->sc_dev, "only 1 sta vap supported\n");
1434 * With multiple vaps we must fall back
1435 * to s/w beacon miss handling.
1437 flags |= IEEE80211_CLONE_NOBEACONS;
1439 if (flags & IEEE80211_CLONE_NOBEACONS) {
1441 * Station mode w/o beacons are implemented w/ AP mode.
1443 ic_opmode = IEEE80211_M_HOSTAP;
1446 case IEEE80211_M_IBSS:
1447 if (sc->sc_nvaps != 0) { /* XXX only 1 for now */
1448 device_printf(sc->sc_dev,
1449 "only 1 ibss vap supported\n");
1454 case IEEE80211_M_AHDEMO:
1455 #ifdef IEEE80211_SUPPORT_TDMA
1456 if (flags & IEEE80211_CLONE_TDMA) {
1457 if (sc->sc_nvaps != 0) {
1458 device_printf(sc->sc_dev,
1459 "only 1 tdma vap supported\n");
1463 flags |= IEEE80211_CLONE_NOBEACONS;
1467 case IEEE80211_M_MONITOR:
1468 if (sc->sc_nvaps != 0 && ic->ic_opmode != opmode) {
1470 * Adopt existing mode. Adding a monitor or ahdemo
1471 * vap to an existing configuration is of dubious
1472 * value but should be ok.
1474 /* XXX not right for monitor mode */
1475 ic_opmode = ic->ic_opmode;
1478 case IEEE80211_M_HOSTAP:
1479 case IEEE80211_M_MBSS:
1482 case IEEE80211_M_WDS:
1483 if (sc->sc_nvaps != 0 && ic->ic_opmode == IEEE80211_M_STA) {
1484 device_printf(sc->sc_dev,
1485 "wds not supported in sta mode\n");
1489 * Silently remove any request for a unique
1490 * bssid; WDS vap's always share the local
1493 flags &= ~IEEE80211_CLONE_BSSID;
1494 if (sc->sc_nvaps == 0)
1495 ic_opmode = IEEE80211_M_HOSTAP;
1497 ic_opmode = ic->ic_opmode;
1500 device_printf(sc->sc_dev, "unknown opmode %d\n", opmode);
1504 * Check that a beacon buffer is available; the code below assumes it.
1506 if (needbeacon & TAILQ_EMPTY(&sc->sc_bbuf)) {
1507 device_printf(sc->sc_dev, "no beacon buffer available\n");
1512 if (opmode == IEEE80211_M_HOSTAP || opmode == IEEE80211_M_MBSS) {
1513 assign_address(sc, mac, flags & IEEE80211_CLONE_BSSID);
1514 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1518 /* XXX can't hold mutex across if_alloc */
1520 error = ieee80211_vap_setup(ic, vap, name, unit, opmode, flags,
1524 device_printf(sc->sc_dev, "%s: error %d creating vap\n",
1529 /* h/w crypto support */
1530 vap->iv_key_alloc = ath_key_alloc;
1531 vap->iv_key_delete = ath_key_delete;
1532 vap->iv_key_set = ath_key_set;
1533 vap->iv_key_update_begin = ath_key_update_begin;
1534 vap->iv_key_update_end = ath_key_update_end;
1536 /* override various methods */
1537 avp->av_recv_mgmt = vap->iv_recv_mgmt;
1538 vap->iv_recv_mgmt = ath_recv_mgmt;
1539 vap->iv_reset = ath_reset_vap;
1540 vap->iv_update_beacon = ath_beacon_update;
1541 avp->av_newstate = vap->iv_newstate;
1542 vap->iv_newstate = ath_newstate;
1543 avp->av_bmiss = vap->iv_bmiss;
1544 vap->iv_bmiss = ath_bmiss_vap;
1546 avp->av_node_ps = vap->iv_node_ps;
1547 vap->iv_node_ps = ath_node_powersave;
1549 avp->av_set_tim = vap->iv_set_tim;
1550 vap->iv_set_tim = ath_node_set_tim;
1552 avp->av_recv_pspoll = vap->iv_recv_pspoll;
1553 vap->iv_recv_pspoll = ath_node_recv_pspoll;
1555 /* Set default parameters */
1558 * Anything earlier than some AR9300 series MACs don't
1559 * support a smaller MPDU density.
1561 vap->iv_ampdu_density = IEEE80211_HTCAP_MPDUDENSITY_8;
1563 * All NICs can handle the maximum size, however
1564 * AR5416 based MACs can only TX aggregates w/ RTS
1565 * protection when the total aggregate size is <= 8k.
1566 * However, for now that's enforced by the TX path.
1568 vap->iv_ampdu_rxmax = IEEE80211_HTCAP_MAXRXAMPDU_64K;
1573 * Allocate beacon state and setup the q for buffered
1574 * multicast frames. We know a beacon buffer is
1575 * available because we checked above.
1577 avp->av_bcbuf = TAILQ_FIRST(&sc->sc_bbuf);
1578 TAILQ_REMOVE(&sc->sc_bbuf, avp->av_bcbuf, bf_list);
1579 if (opmode != IEEE80211_M_IBSS || !sc->sc_hasveol) {
1581 * Assign the vap to a beacon xmit slot. As above
1582 * this cannot fail to find a free one.
1584 avp->av_bslot = assign_bslot(sc);
1585 KASSERT(sc->sc_bslot[avp->av_bslot] == NULL,
1586 ("beacon slot %u not empty", avp->av_bslot));
1587 sc->sc_bslot[avp->av_bslot] = vap;
1590 if (sc->sc_hastsfadd && sc->sc_nbcnvaps > 0) {
1592 * Multple vaps are to transmit beacons and we
1593 * have h/w support for TSF adjusting; enable
1594 * use of staggered beacons.
1596 sc->sc_stagbeacons = 1;
1598 ath_txq_init(sc, &avp->av_mcastq, ATH_TXQ_SWQ);
1601 ic->ic_opmode = ic_opmode;
1602 if (opmode != IEEE80211_M_WDS) {
1604 if (opmode == IEEE80211_M_STA)
1606 if (opmode == IEEE80211_M_MBSS)
1609 switch (ic_opmode) {
1610 case IEEE80211_M_IBSS:
1611 sc->sc_opmode = HAL_M_IBSS;
1613 case IEEE80211_M_STA:
1614 sc->sc_opmode = HAL_M_STA;
1616 case IEEE80211_M_AHDEMO:
1617 #ifdef IEEE80211_SUPPORT_TDMA
1618 if (vap->iv_caps & IEEE80211_C_TDMA) {
1620 /* NB: disable tsf adjust */
1621 sc->sc_stagbeacons = 0;
1624 * NB: adhoc demo mode is a pseudo mode; to the hal it's
1629 case IEEE80211_M_HOSTAP:
1630 case IEEE80211_M_MBSS:
1631 sc->sc_opmode = HAL_M_HOSTAP;
1633 case IEEE80211_M_MONITOR:
1634 sc->sc_opmode = HAL_M_MONITOR;
1637 /* XXX should not happen */
1640 if (sc->sc_hastsfadd) {
1642 * Configure whether or not TSF adjust should be done.
1644 ath_hal_settsfadjust(sc->sc_ah, sc->sc_stagbeacons);
1646 if (flags & IEEE80211_CLONE_NOBEACONS) {
1648 * Enable s/w beacon miss handling.
1654 /* complete setup */
1655 ieee80211_vap_attach(vap, ath_media_change, ieee80211_media_status);
1658 reclaim_address(sc, mac);
1659 ath_hal_setbssidmask(sc->sc_ah, sc->sc_hwbssidmask);
1661 free(avp, M_80211_VAP);
1667 ath_vap_delete(struct ieee80211vap *vap)
1669 struct ieee80211com *ic = vap->iv_ic;
1670 struct ifnet *ifp = ic->ic_ifp;
1671 struct ath_softc *sc = ifp->if_softc;
1672 struct ath_hal *ah = sc->sc_ah;
1673 struct ath_vap *avp = ATH_VAP(vap);
1676 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1679 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
1680 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1682 * Quiesce the hardware while we remove the vap. In
1683 * particular we need to reclaim all references to
1684 * the vap state by any frames pending on the tx queues.
1686 ath_hal_intrset(ah, 0); /* disable interrupts */
1687 /* XXX Do all frames from all vaps/nodes need draining here? */
1688 ath_stoprecv(sc, 1); /* stop recv side */
1689 ath_draintxq(sc, ATH_RESET_DEFAULT); /* stop hw xmit side */
1692 /* .. leave the hardware awake for now. */
1694 ieee80211_vap_detach(vap);
1697 * XXX Danger Will Robinson! Danger!
1699 * Because ieee80211_vap_detach() can queue a frame (the station
1700 * diassociate message?) after we've drained the TXQ and
1701 * flushed the software TXQ, we will end up with a frame queued
1702 * to a node whose vap is about to be freed.
1704 * To work around this, flush the hardware/software again.
1705 * This may be racy - the ath task may be running and the packet
1706 * may be being scheduled between sw->hw txq. Tsk.
1708 * TODO: figure out why a new node gets allocated somewhere around
1709 * here (after the ath_tx_swq() call; and after an ath_stop_locked()
1713 ath_draintxq(sc, ATH_RESET_DEFAULT);
1717 * Reclaim beacon state. Note this must be done before
1718 * the vap instance is reclaimed as we may have a reference
1719 * to it in the buffer for the beacon frame.
1721 if (avp->av_bcbuf != NULL) {
1722 if (avp->av_bslot != -1) {
1723 sc->sc_bslot[avp->av_bslot] = NULL;
1726 ath_beacon_return(sc, avp->av_bcbuf);
1727 avp->av_bcbuf = NULL;
1728 if (sc->sc_nbcnvaps == 0) {
1729 sc->sc_stagbeacons = 0;
1730 if (sc->sc_hastsfadd)
1731 ath_hal_settsfadjust(sc->sc_ah, 0);
1734 * Reclaim any pending mcast frames for the vap.
1736 ath_tx_draintxq(sc, &avp->av_mcastq);
1739 * Update bookkeeping.
1741 if (vap->iv_opmode == IEEE80211_M_STA) {
1743 if (sc->sc_nstavaps == 0 && sc->sc_swbmiss)
1745 } else if (vap->iv_opmode == IEEE80211_M_HOSTAP ||
1746 vap->iv_opmode == IEEE80211_M_MBSS) {
1747 reclaim_address(sc, vap->iv_myaddr);
1748 ath_hal_setbssidmask(ah, sc->sc_hwbssidmask);
1749 if (vap->iv_opmode == IEEE80211_M_MBSS)
1752 if (vap->iv_opmode != IEEE80211_M_WDS)
1754 #ifdef IEEE80211_SUPPORT_TDMA
1755 /* TDMA operation ceases when the last vap is destroyed */
1756 if (sc->sc_tdma && sc->sc_nvaps == 0) {
1761 free(avp, M_80211_VAP);
1763 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1765 * Restart rx+tx machines if still running (RUNNING will
1766 * be reset if we just destroyed the last vap).
1768 if (ath_startrecv(sc) != 0)
1769 if_printf(ifp, "%s: unable to restart recv logic\n",
1771 if (sc->sc_beacons) { /* restart beacons */
1772 #ifdef IEEE80211_SUPPORT_TDMA
1774 ath_tdma_config(sc, NULL);
1777 ath_beacon_config(sc, NULL);
1779 ath_hal_intrset(ah, sc->sc_imask);
1782 /* Ok, let the hardware asleep. */
1783 ath_power_restore_power_state(sc);
1788 ath_suspend(struct ath_softc *sc)
1790 struct ifnet *ifp = sc->sc_ifp;
1791 struct ieee80211com *ic = ifp->if_l2com;
1793 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1794 __func__, ifp->if_flags);
1796 sc->sc_resume_up = (ifp->if_flags & IFF_UP) != 0;
1798 ieee80211_suspend_all(ic);
1800 * NB: don't worry about putting the chip in low power
1801 * mode; pci will power off our socket on suspend and
1802 * CardBus detaches the device.
1804 * XXX TODO: well, that's great, except for non-cardbus
1809 * XXX This doesn't wait until all pending taskqueue
1810 * items and parallel transmit/receive/other threads
1813 ath_hal_intrset(sc->sc_ah, 0);
1814 taskqueue_block(sc->sc_tq);
1817 callout_stop(&sc->sc_cal_ch);
1821 * XXX ensure sc_invalid is 1
1824 /* Disable the PCIe PHY, complete with workarounds */
1825 ath_hal_enablepcie(sc->sc_ah, 1, 1);
1829 * Reset the key cache since some parts do not reset the
1830 * contents on resume. First we clear all entries, then
1831 * re-load keys that the 802.11 layer assumes are setup
1835 ath_reset_keycache(struct ath_softc *sc)
1837 struct ifnet *ifp = sc->sc_ifp;
1838 struct ieee80211com *ic = ifp->if_l2com;
1839 struct ath_hal *ah = sc->sc_ah;
1843 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1844 for (i = 0; i < sc->sc_keymax; i++)
1845 ath_hal_keyreset(ah, i);
1846 ath_power_restore_power_state(sc);
1848 ieee80211_crypto_reload_keys(ic);
1852 * Fetch the current chainmask configuration based on the current
1853 * operating channel and options.
1856 ath_update_chainmasks(struct ath_softc *sc, struct ieee80211_channel *chan)
1860 * Set TX chainmask to the currently configured chainmask;
1861 * the TX chainmask depends upon the current operating mode.
1863 sc->sc_cur_rxchainmask = sc->sc_rxchainmask;
1864 if (IEEE80211_IS_CHAN_HT(chan)) {
1865 sc->sc_cur_txchainmask = sc->sc_txchainmask;
1867 sc->sc_cur_txchainmask = 1;
1870 DPRINTF(sc, ATH_DEBUG_RESET,
1871 "%s: TX chainmask is now 0x%x, RX is now 0x%x\n",
1873 sc->sc_cur_txchainmask,
1874 sc->sc_cur_rxchainmask);
1878 ath_resume(struct ath_softc *sc)
1880 struct ifnet *ifp = sc->sc_ifp;
1881 struct ieee80211com *ic = ifp->if_l2com;
1882 struct ath_hal *ah = sc->sc_ah;
1885 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1886 __func__, ifp->if_flags);
1888 /* Re-enable PCIe, re-enable the PCIe bus */
1889 ath_hal_enablepcie(ah, 0, 0);
1892 * Must reset the chip before we reload the
1893 * keycache as we were powered down on suspend.
1895 ath_update_chainmasks(sc,
1896 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan);
1897 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
1898 sc->sc_cur_rxchainmask);
1900 /* Ensure we set the current power state to on */
1902 ath_power_setselfgen(sc, HAL_PM_AWAKE);
1903 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1904 ath_power_setpower(sc, HAL_PM_AWAKE);
1907 ath_hal_reset(ah, sc->sc_opmode,
1908 sc->sc_curchan != NULL ? sc->sc_curchan : ic->ic_curchan,
1910 ath_reset_keycache(sc);
1913 sc->sc_rx_stopped = 1;
1914 sc->sc_rx_resetted = 1;
1917 /* Let DFS at it in case it's a DFS channel */
1918 ath_dfs_radar_enable(sc, ic->ic_curchan);
1920 /* Let spectral at in case spectral is enabled */
1921 ath_spectral_enable(sc, ic->ic_curchan);
1924 * Let bluetooth coexistence at in case it's needed for this channel
1926 ath_btcoex_enable(sc, ic->ic_curchan);
1929 * If we're doing TDMA, enforce the TXOP limitation for chips that
1932 if (sc->sc_hasenforcetxop && sc->sc_tdma)
1933 ath_hal_setenforcetxop(sc->sc_ah, 1);
1935 ath_hal_setenforcetxop(sc->sc_ah, 0);
1937 /* Restore the LED configuration */
1939 ath_hal_setledstate(ah, HAL_LED_INIT);
1941 if (sc->sc_resume_up)
1942 ieee80211_resume_all(ic);
1945 ath_power_restore_power_state(sc);
1952 ath_shutdown(struct ath_softc *sc)
1954 struct ifnet *ifp = sc->sc_ifp;
1956 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
1957 __func__, ifp->if_flags);
1960 /* NB: no point powering down chip as we're about to reboot */
1964 * Interrupt handler. Most of the actual processing is deferred.
1969 struct ath_softc *sc = arg;
1970 struct ifnet *ifp = sc->sc_ifp;
1971 struct ath_hal *ah = sc->sc_ah;
1976 * If we're inside a reset path, just print a warning and
1977 * clear the ISR. The reset routine will finish it for us.
1980 if (sc->sc_inreset_cnt) {
1982 ath_hal_getisr(ah, &status); /* clear ISR */
1983 ath_hal_intrset(ah, 0); /* disable further intr's */
1984 DPRINTF(sc, ATH_DEBUG_ANY,
1985 "%s: in reset, ignoring: status=0x%x\n",
1991 if (sc->sc_invalid) {
1993 * The hardware is not ready/present, don't touch anything.
1994 * Note this can happen early on if the IRQ is shared.
1996 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
2000 if (!ath_hal_intrpend(ah)) { /* shared irq, not for us */
2006 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2009 if ((ifp->if_flags & IFF_UP) == 0 ||
2010 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2013 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
2014 __func__, ifp->if_flags);
2015 ath_hal_getisr(ah, &status); /* clear ISR */
2016 ath_hal_intrset(ah, 0); /* disable further intr's */
2020 ath_power_restore_power_state(sc);
2026 * Figure out the reason(s) for the interrupt. Note
2027 * that the hal returns a pseudo-ISR that may include
2028 * bits we haven't explicitly enabled so we mask the
2029 * value to insure we only process bits we requested.
2031 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
2032 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
2033 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1, "ath_intr: mask=0x%.8x", status);
2034 #ifdef ATH_DEBUG_ALQ
2035 if_ath_alq_post_intr(&sc->sc_alq, status, ah->ah_intrstate,
2037 #endif /* ATH_DEBUG_ALQ */
2038 #ifdef ATH_KTR_INTR_DEBUG
2039 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 5,
2040 "ath_intr: ISR=0x%.8x, ISR_S0=0x%.8x, ISR_S1=0x%.8x, ISR_S2=0x%.8x, ISR_S5=0x%.8x",
2041 ah->ah_intrstate[0],
2042 ah->ah_intrstate[1],
2043 ah->ah_intrstate[2],
2044 ah->ah_intrstate[3],
2045 ah->ah_intrstate[6]);
2048 /* Squirrel away SYNC interrupt debugging */
2049 if (ah->ah_syncstate != 0) {
2051 for (i = 0; i < 32; i++)
2052 if (ah->ah_syncstate & (i << i))
2053 sc->sc_intr_stats.sync_intr[i]++;
2056 status &= sc->sc_imask; /* discard unasked for bits */
2058 /* Short-circuit un-handled interrupts */
2059 if (status == 0x0) {
2063 ath_power_restore_power_state(sc);
2070 * Take a note that we're inside the interrupt handler, so
2071 * the reset routines know to wait.
2077 * Handle the interrupt. We won't run concurrent with the reset
2078 * or channel change routines as they'll wait for sc_intr_cnt
2079 * to be 0 before continuing.
2081 if (status & HAL_INT_FATAL) {
2082 sc->sc_stats.ast_hardware++;
2083 ath_hal_intrset(ah, 0); /* disable intr's until reset */
2084 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask);
2086 if (status & HAL_INT_SWBA) {
2088 * Software beacon alert--time to send a beacon.
2089 * Handle beacon transmission directly; deferring
2090 * this is too slow to meet timing constraints
2093 #ifdef IEEE80211_SUPPORT_TDMA
2095 if (sc->sc_tdmaswba == 0) {
2096 struct ieee80211com *ic = ifp->if_l2com;
2097 struct ieee80211vap *vap =
2098 TAILQ_FIRST(&ic->ic_vaps);
2099 ath_tdma_beacon_send(sc, vap);
2101 vap->iv_tdma->tdma_bintval;
2107 ath_beacon_proc(sc, 0);
2108 #ifdef IEEE80211_SUPPORT_SUPERG
2110 * Schedule the rx taskq in case there's no
2111 * traffic so any frames held on the staging
2112 * queue are aged and potentially flushed.
2114 sc->sc_rx.recv_sched(sc, 1);
2118 if (status & HAL_INT_RXEOL) {
2120 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXEOL");
2121 if (! sc->sc_isedma) {
2124 * NB: the hardware should re-read the link when
2125 * RXE bit is written, but it doesn't work at
2126 * least on older hardware revs.
2128 sc->sc_stats.ast_rxeol++;
2130 * Disable RXEOL/RXORN - prevent an interrupt
2131 * storm until the PCU logic can be reset.
2132 * In case the interface is reset some other
2133 * way before "sc_kickpcu" is called, don't
2134 * modify sc_imask - that way if it is reset
2135 * by a call to ath_reset() somehow, the
2136 * interrupt mask will be correctly reprogrammed.
2138 imask = sc->sc_imask;
2139 imask &= ~(HAL_INT_RXEOL | HAL_INT_RXORN);
2140 ath_hal_intrset(ah, imask);
2142 * Only blank sc_rxlink if we've not yet kicked
2145 * This isn't entirely correct - the correct solution
2146 * would be to have a PCU lock and engage that for
2147 * the duration of the PCU fiddling; which would include
2148 * running the RX process. Otherwise we could end up
2149 * messing up the RX descriptor chain and making the
2150 * RX desc list much shorter.
2152 if (! sc->sc_kickpcu)
2153 sc->sc_rxlink = NULL;
2158 * Enqueue an RX proc to handle whatever
2159 * is in the RX queue.
2160 * This will then kick the PCU if required.
2162 sc->sc_rx.recv_sched(sc, 1);
2164 if (status & HAL_INT_TXURN) {
2165 sc->sc_stats.ast_txurn++;
2166 /* bump tx trigger level */
2167 ath_hal_updatetxtriglevel(ah, AH_TRUE);
2170 * Handle both the legacy and RX EDMA interrupt bits.
2171 * Note that HAL_INT_RXLP is also HAL_INT_RXDESC.
2173 if (status & (HAL_INT_RX | HAL_INT_RXHP | HAL_INT_RXLP)) {
2174 sc->sc_stats.ast_rx_intr++;
2175 sc->sc_rx.recv_sched(sc, 1);
2177 if (status & HAL_INT_TX) {
2178 sc->sc_stats.ast_tx_intr++;
2180 * Grab all the currently set bits in the HAL txq bitmap
2181 * and blank them. This is the only place we should be
2184 if (! sc->sc_isedma) {
2187 ath_hal_gettxintrtxqs(sc->sc_ah, &txqs);
2188 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 3,
2189 "ath_intr: TX; txqs=0x%08x, txq_active was 0x%08x, now 0x%08x",
2192 sc->sc_txq_active | txqs);
2193 sc->sc_txq_active |= txqs;
2196 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
2198 if (status & HAL_INT_BMISS) {
2199 sc->sc_stats.ast_bmiss++;
2200 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
2202 if (status & HAL_INT_GTT)
2203 sc->sc_stats.ast_tx_timeout++;
2204 if (status & HAL_INT_CST)
2205 sc->sc_stats.ast_tx_cst++;
2206 if (status & HAL_INT_MIB) {
2207 sc->sc_stats.ast_mib++;
2210 * Disable interrupts until we service the MIB
2211 * interrupt; otherwise it will continue to fire.
2213 ath_hal_intrset(ah, 0);
2215 * Let the hal handle the event. We assume it will
2216 * clear whatever condition caused the interrupt.
2218 ath_hal_mibevent(ah, &sc->sc_halstats);
2220 * Don't reset the interrupt if we've just
2221 * kicked the PCU, or we may get a nested
2222 * RXEOL before the rxproc has had a chance
2225 if (sc->sc_kickpcu == 0)
2226 ath_hal_intrset(ah, sc->sc_imask);
2229 if (status & HAL_INT_RXORN) {
2230 /* NB: hal marks HAL_INT_FATAL when RXORN is fatal */
2231 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_intr: RXORN");
2232 sc->sc_stats.ast_rxorn++;
2234 if (status & HAL_INT_TSFOOR) {
2235 device_printf(sc->sc_dev, "%s: TSFOOR\n", __func__);
2236 sc->sc_syncbeacon = 1;
2244 ath_power_restore_power_state(sc);
2249 ath_fatal_proc(void *arg, int pending)
2251 struct ath_softc *sc = arg;
2252 struct ifnet *ifp = sc->sc_ifp;
2257 if_printf(ifp, "hardware error; resetting\n");
2259 * Fatal errors are unrecoverable. Typically these
2260 * are caused by DMA errors. Collect h/w state from
2261 * the hal so we can diagnose what's going on.
2263 if (ath_hal_getfatalstate(sc->sc_ah, &sp, &len)) {
2264 KASSERT(len >= 6*sizeof(u_int32_t), ("len %u bytes", len));
2266 if_printf(ifp, "0x%08x 0x%08x 0x%08x, 0x%08x 0x%08x 0x%08x\n",
2267 state[0], state[1] , state[2], state[3],
2268 state[4], state[5]);
2270 ath_reset(ifp, ATH_RESET_NOLOSS);
2274 ath_bmiss_vap(struct ieee80211vap *vap)
2276 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
2279 * Workaround phantom bmiss interrupts by sanity-checking
2280 * the time of our last rx'd frame. If it is within the
2281 * beacon miss interval then ignore the interrupt. If it's
2282 * truly a bmiss we'll get another interrupt soon and that'll
2283 * be dispatched up for processing. Note this applies only
2284 * for h/w beacon miss events.
2288 * XXX TODO: Just read the TSF during the interrupt path;
2289 * that way we don't have to wake up again just to read it
2293 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2296 if ((vap->iv_flags_ext & IEEE80211_FEXT_SWBMISS) == 0) {
2297 struct ifnet *ifp = vap->iv_ic->ic_ifp;
2298 struct ath_softc *sc = ifp->if_softc;
2299 u_int64_t lastrx = sc->sc_lastrx;
2300 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
2301 /* XXX should take a locked ref to iv_bss */
2302 u_int bmisstimeout =
2303 vap->iv_bmissthreshold * vap->iv_bss->ni_intval * 1024;
2305 DPRINTF(sc, ATH_DEBUG_BEACON,
2306 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
2307 __func__, (unsigned long long) tsf,
2308 (unsigned long long)(tsf - lastrx),
2309 (unsigned long long) lastrx, bmisstimeout);
2311 if (tsf - lastrx <= bmisstimeout) {
2312 sc->sc_stats.ast_bmiss_phantom++;
2315 ath_power_restore_power_state(sc);
2323 * There's no need to keep the hardware awake during the call
2327 ath_power_restore_power_state(sc);
2331 * Attempt to force a beacon resync.
2333 sc->sc_syncbeacon = 1;
2335 ATH_VAP(vap)->av_bmiss(vap);
2338 /* XXX this needs a force wakeup! */
2340 ath_hal_gethangstate(struct ath_hal *ah, uint32_t mask, uint32_t *hangs)
2345 if (!ath_hal_getdiagstate(ah, HAL_DIAG_CHECK_HANGS, &mask, sizeof(mask), &sp, &rsize))
2347 KASSERT(rsize == sizeof(uint32_t), ("resultsize %u", rsize));
2348 *hangs = *(uint32_t *)sp;
2353 ath_bmiss_proc(void *arg, int pending)
2355 struct ath_softc *sc = arg;
2356 struct ifnet *ifp = sc->sc_ifp;
2359 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
2362 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2365 ath_beacon_miss(sc);
2368 * Do a reset upon any becaon miss event.
2370 * It may be a non-recognised RX clear hang which needs a reset
2373 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0) {
2374 ath_reset(ifp, ATH_RESET_NOLOSS);
2375 if_printf(ifp, "bb hang detected (0x%x), resetting\n", hangs);
2377 ath_reset(ifp, ATH_RESET_NOLOSS);
2378 ieee80211_beacon_miss(ifp->if_l2com);
2381 /* Force a beacon resync, in case they've drifted */
2382 sc->sc_syncbeacon = 1;
2385 ath_power_restore_power_state(sc);
2390 * Handle TKIP MIC setup to deal hardware that doesn't do MIC
2391 * calcs together with WME. If necessary disable the crypto
2392 * hardware and mark the 802.11 state so keys will be setup
2393 * with the MIC work done in software.
2396 ath_settkipmic(struct ath_softc *sc)
2398 struct ifnet *ifp = sc->sc_ifp;
2399 struct ieee80211com *ic = ifp->if_l2com;
2401 if ((ic->ic_cryptocaps & IEEE80211_CRYPTO_TKIP) && !sc->sc_wmetkipmic) {
2402 if (ic->ic_flags & IEEE80211_F_WME) {
2403 ath_hal_settkipmic(sc->sc_ah, AH_FALSE);
2404 ic->ic_cryptocaps &= ~IEEE80211_CRYPTO_TKIPMIC;
2406 ath_hal_settkipmic(sc->sc_ah, AH_TRUE);
2407 ic->ic_cryptocaps |= IEEE80211_CRYPTO_TKIPMIC;
2415 struct ath_softc *sc = (struct ath_softc *) arg;
2416 struct ifnet *ifp = sc->sc_ifp;
2417 struct ieee80211com *ic = ifp->if_l2com;
2418 struct ath_hal *ah = sc->sc_ah;
2421 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
2422 __func__, ifp->if_flags);
2426 * Force the sleep state awake.
2428 ath_power_setselfgen(sc, HAL_PM_AWAKE);
2429 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2430 ath_power_setpower(sc, HAL_PM_AWAKE);
2433 * Stop anything previously setup. This is safe
2434 * whether this is the first time through or not.
2436 ath_stop_locked(ifp);
2439 * The basic interface to setting the hardware in a good
2440 * state is ``reset''. On return the hardware is known to
2441 * be powered up and with interrupts disabled. This must
2442 * be followed by initialization of the appropriate bits
2443 * and then setup of the interrupt mask.
2446 ath_update_chainmasks(sc, ic->ic_curchan);
2447 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2448 sc->sc_cur_rxchainmask);
2450 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_FALSE, &status)) {
2451 if_printf(ifp, "unable to reset hardware; hal status %u\n",
2458 sc->sc_rx_stopped = 1;
2459 sc->sc_rx_resetted = 1;
2462 ath_chan_change(sc, ic->ic_curchan);
2464 /* Let DFS at it in case it's a DFS channel */
2465 ath_dfs_radar_enable(sc, ic->ic_curchan);
2467 /* Let spectral at in case spectral is enabled */
2468 ath_spectral_enable(sc, ic->ic_curchan);
2471 * Let bluetooth coexistence at in case it's needed for this channel
2473 ath_btcoex_enable(sc, ic->ic_curchan);
2476 * If we're doing TDMA, enforce the TXOP limitation for chips that
2479 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2480 ath_hal_setenforcetxop(sc->sc_ah, 1);
2482 ath_hal_setenforcetxop(sc->sc_ah, 0);
2485 * Likewise this is set during reset so update
2486 * state cached in the driver.
2488 sc->sc_diversity = ath_hal_getdiversity(ah);
2489 sc->sc_lastlongcal = 0;
2490 sc->sc_resetcal = 1;
2491 sc->sc_lastcalreset = 0;
2493 sc->sc_lastshortcal = 0;
2494 sc->sc_doresetcal = AH_FALSE;
2496 * Beacon timers were cleared here; give ath_newstate()
2497 * a hint that the beacon timers should be poked when
2498 * things transition to the RUN state.
2503 * Setup the hardware after reset: the key cache
2504 * is filled as needed and the receive engine is
2505 * set going. Frame transmit is handled entirely
2506 * in the frame output path; there's nothing to do
2507 * here except setup the interrupt mask.
2509 if (ath_startrecv(sc) != 0) {
2510 if_printf(ifp, "unable to start recv logic\n");
2511 ath_power_restore_power_state(sc);
2517 * Enable interrupts.
2519 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
2520 | HAL_INT_RXORN | HAL_INT_TXURN
2521 | HAL_INT_FATAL | HAL_INT_GLOBAL;
2524 * Enable RX EDMA bits. Note these overlap with
2525 * HAL_INT_RX and HAL_INT_RXDESC respectively.
2528 sc->sc_imask |= (HAL_INT_RXHP | HAL_INT_RXLP);
2531 * If we're an EDMA NIC, we don't care about RXEOL.
2532 * Writing a new descriptor in will simply restart
2535 if (! sc->sc_isedma)
2536 sc->sc_imask |= HAL_INT_RXEOL;
2539 * Enable MIB interrupts when there are hardware phy counters.
2540 * Note we only do this (at the moment) for station mode.
2542 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
2543 sc->sc_imask |= HAL_INT_MIB;
2546 * XXX add capability for this.
2548 * If we're in STA mode (and maybe IBSS?) then register for
2549 * TSFOOR interrupts.
2551 if (ic->ic_opmode == IEEE80211_M_STA)
2552 sc->sc_imask |= HAL_INT_TSFOOR;
2554 /* Enable global TX timeout and carrier sense timeout if available */
2555 if (ath_hal_gtxto_supported(ah))
2556 sc->sc_imask |= HAL_INT_GTT;
2558 DPRINTF(sc, ATH_DEBUG_RESET, "%s: imask=0x%x\n",
2559 __func__, sc->sc_imask);
2561 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2562 callout_reset(&sc->sc_wd_ch, hz, ath_watchdog, sc);
2563 ath_hal_intrset(ah, sc->sc_imask);
2565 ath_power_restore_power_state(sc);
2568 #ifdef ATH_TX99_DIAG
2569 if (sc->sc_tx99 != NULL)
2570 sc->sc_tx99->start(sc->sc_tx99);
2573 ieee80211_start_all(ic); /* start all vap's */
2577 ath_stop_locked(struct ifnet *ifp)
2579 struct ath_softc *sc = ifp->if_softc;
2580 struct ath_hal *ah = sc->sc_ah;
2582 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
2583 __func__, sc->sc_invalid, ifp->if_flags);
2585 ATH_LOCK_ASSERT(sc);
2588 * Wake the hardware up before fiddling with it.
2590 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2592 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2594 * Shutdown the hardware and driver:
2595 * reset 802.11 state machine
2597 * disable interrupts
2598 * turn off the radio
2599 * clear transmit machinery
2600 * clear receive machinery
2601 * drain and release tx queues
2602 * reclaim beacon resources
2603 * power down hardware
2605 * Note that some of this work is not possible if the
2606 * hardware is gone (invalid).
2608 #ifdef ATH_TX99_DIAG
2609 if (sc->sc_tx99 != NULL)
2610 sc->sc_tx99->stop(sc->sc_tx99);
2612 callout_stop(&sc->sc_wd_ch);
2613 sc->sc_wd_timer = 0;
2614 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2615 if (!sc->sc_invalid) {
2616 if (sc->sc_softled) {
2617 callout_stop(&sc->sc_ledtimer);
2618 ath_hal_gpioset(ah, sc->sc_ledpin,
2620 sc->sc_blinking = 0;
2622 ath_hal_intrset(ah, 0);
2624 /* XXX we should stop RX regardless of whether it's valid */
2625 if (!sc->sc_invalid) {
2626 ath_stoprecv(sc, 1);
2627 ath_hal_phydisable(ah);
2629 sc->sc_rxlink = NULL;
2630 ath_draintxq(sc, ATH_RESET_DEFAULT);
2631 ath_beacon_free(sc); /* XXX not needed */
2634 /* And now, restore the current power state */
2635 ath_power_restore_power_state(sc);
2639 * Wait until all pending TX/RX has completed.
2641 * This waits until all existing transmit, receive and interrupts
2642 * have completed. It's assumed that the caller has first
2643 * grabbed the reset lock so it doesn't try to do overlapping
2646 #define MAX_TXRX_ITERATIONS 100
2648 ath_txrx_stop_locked(struct ath_softc *sc)
2650 int i = MAX_TXRX_ITERATIONS;
2652 ATH_UNLOCK_ASSERT(sc);
2653 ATH_PCU_LOCK_ASSERT(sc);
2656 * Sleep until all the pending operations have completed.
2658 * The caller must ensure that reset has been incremented
2659 * or the pending operations may continue being queued.
2661 while (sc->sc_rxproc_cnt || sc->sc_txproc_cnt ||
2662 sc->sc_txstart_cnt || sc->sc_intr_cnt) {
2665 msleep(sc, &sc->sc_pcu_mtx, 0, "ath_txrx_stop",
2666 msecs_to_ticks(10));
2671 device_printf(sc->sc_dev,
2672 "%s: didn't finish after %d iterations\n",
2673 __func__, MAX_TXRX_ITERATIONS);
2675 #undef MAX_TXRX_ITERATIONS
2679 ath_txrx_stop(struct ath_softc *sc)
2681 ATH_UNLOCK_ASSERT(sc);
2682 ATH_PCU_UNLOCK_ASSERT(sc);
2685 ath_txrx_stop_locked(sc);
2691 ath_txrx_start(struct ath_softc *sc)
2694 taskqueue_unblock(sc->sc_tq);
2698 * Grab the reset lock, and wait around until noone else
2699 * is trying to do anything with it.
2701 * This is totally horrible but we can't hold this lock for
2702 * long enough to do TX/RX or we end up with net80211/ip stack
2703 * LORs and eventual deadlock.
2705 * "dowait" signals whether to spin, waiting for the reset
2706 * lock count to reach 0. This should (for now) only be used
2707 * during the reset path, as the rest of the code may not
2708 * be locking-reentrant enough to behave correctly.
2710 * Another, cleaner way should be found to serialise all of
2713 #define MAX_RESET_ITERATIONS 25
2715 ath_reset_grablock(struct ath_softc *sc, int dowait)
2718 int i = MAX_RESET_ITERATIONS;
2720 ATH_PCU_LOCK_ASSERT(sc);
2722 if (sc->sc_inreset_cnt == 0) {
2732 * 1 tick is likely not enough time for long calibrations
2733 * to complete. So we should wait quite a while.
2735 pause("ath_reset_grablock", msecs_to_ticks(100));
2741 * We always increment the refcounter, regardless
2742 * of whether we succeeded to get it in an exclusive
2745 sc->sc_inreset_cnt++;
2748 device_printf(sc->sc_dev,
2749 "%s: didn't finish after %d iterations\n",
2750 __func__, MAX_RESET_ITERATIONS);
2753 device_printf(sc->sc_dev,
2754 "%s: warning, recursive reset path!\n",
2759 #undef MAX_RESET_ITERATIONS
2762 * XXX TODO: write ath_reset_releaselock
2766 ath_stop(struct ifnet *ifp)
2768 struct ath_softc *sc = ifp->if_softc;
2771 ath_stop_locked(ifp);
2776 * Reset the hardware w/o losing operational state. This is
2777 * basically a more efficient way of doing ath_stop, ath_init,
2778 * followed by state transitions to the current 802.11
2779 * operational state. Used to recover from various errors and
2780 * to reset or reload hardware state.
2783 ath_reset(struct ifnet *ifp, ATH_RESET_TYPE reset_type)
2785 struct ath_softc *sc = ifp->if_softc;
2786 struct ieee80211com *ic = ifp->if_l2com;
2787 struct ath_hal *ah = sc->sc_ah;
2791 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
2793 /* Ensure ATH_LOCK isn't held; ath_rx_proc can't be locked */
2794 ATH_PCU_UNLOCK_ASSERT(sc);
2795 ATH_UNLOCK_ASSERT(sc);
2797 /* Try to (stop any further TX/RX from occuring */
2798 taskqueue_block(sc->sc_tq);
2801 * Wake the hardware up.
2804 ath_power_set_power_state(sc, HAL_PM_AWAKE);
2810 * Grab the reset lock before TX/RX is stopped.
2812 * This is needed to ensure that when the TX/RX actually does finish,
2813 * no further TX/RX/reset runs in parallel with this.
2815 if (ath_reset_grablock(sc, 1) == 0) {
2816 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
2820 /* disable interrupts */
2821 ath_hal_intrset(ah, 0);
2824 * Now, ensure that any in progress TX/RX completes before we
2827 ath_txrx_stop_locked(sc);
2832 * Regardless of whether we're doing a no-loss flush or
2833 * not, stop the PCU and handle what's in the RX queue.
2834 * That way frames aren't dropped which shouldn't be.
2836 ath_stoprecv(sc, (reset_type != ATH_RESET_NOLOSS));
2840 * Should now wait for pending TX/RX to complete
2841 * and block future ones from occuring. This needs to be
2842 * done before the TX queue is drained.
2844 ath_draintxq(sc, reset_type); /* stop xmit side */
2846 ath_settkipmic(sc); /* configure TKIP MIC handling */
2847 /* NB: indicate channel change so we do a full reset */
2848 ath_update_chainmasks(sc, ic->ic_curchan);
2849 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
2850 sc->sc_cur_rxchainmask);
2851 if (!ath_hal_reset(ah, sc->sc_opmode, ic->ic_curchan, AH_TRUE, &status))
2852 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
2854 sc->sc_diversity = ath_hal_getdiversity(ah);
2857 sc->sc_rx_stopped = 1;
2858 sc->sc_rx_resetted = 1;
2861 /* Let DFS at it in case it's a DFS channel */
2862 ath_dfs_radar_enable(sc, ic->ic_curchan);
2864 /* Let spectral at in case spectral is enabled */
2865 ath_spectral_enable(sc, ic->ic_curchan);
2868 * Let bluetooth coexistence at in case it's needed for this channel
2870 ath_btcoex_enable(sc, ic->ic_curchan);
2873 * If we're doing TDMA, enforce the TXOP limitation for chips that
2876 if (sc->sc_hasenforcetxop && sc->sc_tdma)
2877 ath_hal_setenforcetxop(sc->sc_ah, 1);
2879 ath_hal_setenforcetxop(sc->sc_ah, 0);
2881 if (ath_startrecv(sc) != 0) /* restart recv */
2882 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
2884 * We may be doing a reset in response to an ioctl
2885 * that changes the channel so update any state that
2886 * might change as a result.
2888 ath_chan_change(sc, ic->ic_curchan);
2889 if (sc->sc_beacons) { /* restart beacons */
2890 #ifdef IEEE80211_SUPPORT_TDMA
2892 ath_tdma_config(sc, NULL);
2895 ath_beacon_config(sc, NULL);
2899 * Release the reset lock and re-enable interrupts here.
2900 * If an interrupt was being processed in ath_intr(),
2901 * it would disable interrupts at this point. So we have
2902 * to atomically enable interrupts and decrement the
2903 * reset counter - this way ath_intr() doesn't end up
2904 * disabling interrupts without a corresponding enable
2905 * in the rest or channel change path.
2907 * Grab the TX reference in case we need to transmit.
2908 * That way a parallel transmit doesn't.
2911 sc->sc_inreset_cnt--;
2912 sc->sc_txstart_cnt++;
2913 /* XXX only do this if sc_inreset_cnt == 0? */
2914 ath_hal_intrset(ah, sc->sc_imask);
2918 * TX and RX can be started here. If it were started with
2919 * sc_inreset_cnt > 0, the TX and RX path would abort.
2920 * Thus if this is a nested call through the reset or
2921 * channel change code, TX completion will occur but
2922 * RX completion and ath_start / ath_tx_start will not
2926 /* Restart TX/RX as needed */
2929 /* XXX TODO: we need to hold the tx refcount here! */
2931 /* Restart TX completion and pending TX */
2932 if (reset_type == ATH_RESET_NOLOSS) {
2933 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
2934 if (ATH_TXQ_SETUP(sc, i)) {
2935 ATH_TXQ_LOCK(&sc->sc_txq[i]);
2936 ath_txq_restart_dma(sc, &sc->sc_txq[i]);
2937 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
2940 ath_txq_sched(sc, &sc->sc_txq[i]);
2947 * This may have been set during an ath_start() call which
2948 * set this once it detected a concurrent TX was going on.
2951 IF_LOCK(&ifp->if_snd);
2952 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2953 IF_UNLOCK(&ifp->if_snd);
2956 ath_power_restore_power_state(sc);
2960 sc->sc_txstart_cnt--;
2963 /* Handle any frames in the TX queue */
2965 * XXX should this be done by the caller, rather than
2968 ath_tx_kick(sc); /* restart xmit */
2973 ath_reset_vap(struct ieee80211vap *vap, u_long cmd)
2975 struct ieee80211com *ic = vap->iv_ic;
2976 struct ifnet *ifp = ic->ic_ifp;
2977 struct ath_softc *sc = ifp->if_softc;
2978 struct ath_hal *ah = sc->sc_ah;
2981 case IEEE80211_IOC_TXPOWER:
2983 * If per-packet TPC is enabled, then we have nothing
2984 * to do; otherwise we need to force the global limit.
2985 * All this can happen directly; no need to reset.
2987 if (!ath_hal_gettpc(ah))
2988 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
2991 /* XXX? Full or NOLOSS? */
2992 return ath_reset(ifp, ATH_RESET_FULL);
2996 _ath_getbuf_locked(struct ath_softc *sc, ath_buf_type_t btype)
3000 ATH_TXBUF_LOCK_ASSERT(sc);
3002 if (btype == ATH_BUFTYPE_MGMT)
3003 bf = TAILQ_FIRST(&sc->sc_txbuf_mgmt);
3005 bf = TAILQ_FIRST(&sc->sc_txbuf);
3008 sc->sc_stats.ast_tx_getnobuf++;
3010 if (bf->bf_flags & ATH_BUF_BUSY) {
3011 sc->sc_stats.ast_tx_getbusybuf++;
3016 if (bf != NULL && (bf->bf_flags & ATH_BUF_BUSY) == 0) {
3017 if (btype == ATH_BUFTYPE_MGMT)
3018 TAILQ_REMOVE(&sc->sc_txbuf_mgmt, bf, bf_list);
3020 TAILQ_REMOVE(&sc->sc_txbuf, bf, bf_list);
3024 * This shuldn't happen; however just to be
3025 * safe print a warning and fudge the txbuf
3028 if (sc->sc_txbuf_cnt < 0) {
3029 device_printf(sc->sc_dev,
3030 "%s: sc_txbuf_cnt < 0?\n",
3032 sc->sc_txbuf_cnt = 0;
3039 /* XXX should check which list, mgmt or otherwise */
3040 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: %s\n", __func__,
3041 TAILQ_FIRST(&sc->sc_txbuf) == NULL ?
3042 "out of xmit buffers" : "xmit buffer busy");
3046 /* XXX TODO: should do this at buffer list initialisation */
3047 /* XXX (then, ensure the buffer has the right flag set) */
3049 if (btype == ATH_BUFTYPE_MGMT)
3050 bf->bf_flags |= ATH_BUF_MGMT;
3052 bf->bf_flags &= (~ATH_BUF_MGMT);
3054 /* Valid bf here; clear some basic fields */
3055 bf->bf_next = NULL; /* XXX just to be sure */
3056 bf->bf_last = NULL; /* XXX again, just to be sure */
3057 bf->bf_comp = NULL; /* XXX again, just to be sure */
3058 bzero(&bf->bf_state, sizeof(bf->bf_state));
3061 * Track the descriptor ID only if doing EDMA
3063 if (sc->sc_isedma) {
3064 bf->bf_descid = sc->sc_txbuf_descid;
3065 sc->sc_txbuf_descid++;
3072 * When retrying a software frame, buffers marked ATH_BUF_BUSY
3073 * can't be thrown back on the queue as they could still be
3074 * in use by the hardware.
3076 * This duplicates the buffer, or returns NULL.
3078 * The descriptor is also copied but the link pointers and
3079 * the DMA segments aren't copied; this frame should thus
3080 * be again passed through the descriptor setup/chain routines
3081 * so the link is correct.
3083 * The caller must free the buffer using ath_freebuf().
3086 ath_buf_clone(struct ath_softc *sc, struct ath_buf *bf)
3088 struct ath_buf *tbf;
3090 tbf = ath_getbuf(sc,
3091 (bf->bf_flags & ATH_BUF_MGMT) ?
3092 ATH_BUFTYPE_MGMT : ATH_BUFTYPE_NORMAL);
3094 return NULL; /* XXX failure? Why? */
3097 tbf->bf_next = NULL;
3098 tbf->bf_nseg = bf->bf_nseg;
3099 tbf->bf_flags = bf->bf_flags & ATH_BUF_FLAGS_CLONE;
3100 tbf->bf_status = bf->bf_status;
3101 tbf->bf_m = bf->bf_m;
3102 tbf->bf_node = bf->bf_node;
3103 KASSERT((bf->bf_node != NULL), ("%s: bf_node=NULL!", __func__));
3104 /* will be setup by the chain/setup function */
3105 tbf->bf_lastds = NULL;
3106 /* for now, last == self */
3108 tbf->bf_comp = bf->bf_comp;
3110 /* NOTE: DMA segments will be setup by the setup/chain functions */
3112 /* The caller has to re-init the descriptor + links */
3115 * Free the DMA mapping here, before we NULL the mbuf.
3116 * We must only call bus_dmamap_unload() once per mbuf chain
3117 * or behaviour is undefined.
3119 if (bf->bf_m != NULL) {
3121 * XXX is this POSTWRITE call required?
3123 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3124 BUS_DMASYNC_POSTWRITE);
3125 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3132 memcpy(&tbf->bf_state, &bf->bf_state, sizeof(bf->bf_state));
3138 ath_getbuf(struct ath_softc *sc, ath_buf_type_t btype)
3143 bf = _ath_getbuf_locked(sc, btype);
3145 * If a mgmt buffer was requested but we're out of those,
3146 * try requesting a normal one.
3148 if (bf == NULL && btype == ATH_BUFTYPE_MGMT)
3149 bf = _ath_getbuf_locked(sc, ATH_BUFTYPE_NORMAL);
3150 ATH_TXBUF_UNLOCK(sc);
3152 struct ifnet *ifp = sc->sc_ifp;
3154 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: stop queue\n", __func__);
3155 sc->sc_stats.ast_tx_qstop++;
3156 IF_LOCK(&ifp->if_snd);
3157 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3158 IF_UNLOCK(&ifp->if_snd);
3164 ath_qflush(struct ifnet *ifp)
3171 * Transmit a single frame.
3173 * net80211 will free the node reference if the transmit
3174 * fails, so don't free the node reference here.
3177 ath_transmit(struct ifnet *ifp, struct mbuf *m)
3179 struct ieee80211com *ic = ifp->if_l2com;
3180 struct ath_softc *sc = ic->ic_ifp->if_softc;
3181 struct ieee80211_node *ni;
3188 * Tell the reset path that we're currently transmitting.
3191 if (sc->sc_inreset_cnt > 0) {
3192 DPRINTF(sc, ATH_DEBUG_XMIT,
3193 "%s: sc_inreset_cnt > 0; bailing\n", __func__);
3195 IF_LOCK(&ifp->if_snd);
3196 sc->sc_stats.ast_tx_qstop++;
3197 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3198 IF_UNLOCK(&ifp->if_snd);
3199 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_start_task: OACTIVE, finish");
3200 return (ENOBUFS); /* XXX should be EINVAL or? */
3202 sc->sc_txstart_cnt++;
3205 /* Wake the hardware up already */
3207 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3210 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: start");
3212 * Grab the TX lock - it's ok to do this here; we haven't
3213 * yet started transmitting.
3218 * Node reference, if there's one.
3220 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
3223 * Enforce how deep a node queue can get.
3225 * XXX it would be nicer if we kept an mbuf queue per
3226 * node and only whacked them into ath_bufs when we
3227 * are ready to schedule some traffic from them.
3228 * .. that may come later.
3230 * XXX we should also track the per-node hardware queue
3231 * depth so it is easy to limit the _SUM_ of the swq and
3232 * hwq frames. Since we only schedule two HWQ frames
3233 * at a time, this should be OK for now.
3235 if ((!(m->m_flags & M_EAPOL)) &&
3236 (ATH_NODE(ni)->an_swq_depth > sc->sc_txq_node_maxdepth)) {
3237 sc->sc_stats.ast_tx_nodeq_overflow++;
3245 * Check how many TX buffers are available.
3247 * If this is for non-EAPOL traffic, just leave some
3248 * space free in order for buffer cloning and raw
3249 * frame transmission to occur.
3251 * If it's for EAPOL traffic, ignore this for now.
3252 * Management traffic will be sent via the raw transmit
3253 * method which bypasses this check.
3255 * This is needed to ensure that EAPOL frames during
3256 * (re) keying have a chance to go out.
3258 * See kern/138379 for more information.
3260 if ((!(m->m_flags & M_EAPOL)) &&
3261 (sc->sc_txbuf_cnt <= sc->sc_txq_data_minfree)) {
3262 sc->sc_stats.ast_tx_nobuf++;
3270 * Grab a TX buffer and associated resources.
3272 * If it's an EAPOL frame, allocate a MGMT ath_buf.
3273 * That way even with temporary buffer exhaustion due to
3274 * the data path doesn't leave us without the ability
3275 * to transmit management frames.
3277 * Otherwise allocate a normal buffer.
3279 if (m->m_flags & M_EAPOL)
3280 bf = ath_getbuf(sc, ATH_BUFTYPE_MGMT);
3282 bf = ath_getbuf(sc, ATH_BUFTYPE_NORMAL);
3286 * If we failed to allocate a buffer, fail.
3288 * We shouldn't fail normally, due to the check
3291 sc->sc_stats.ast_tx_nobuf++;
3292 IF_LOCK(&ifp->if_snd);
3293 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
3294 IF_UNLOCK(&ifp->if_snd);
3302 * At this point we have a buffer; so we need to free it
3303 * if we hit any error conditions.
3307 * Check for fragmentation. If this frame
3308 * has been broken up verify we have enough
3309 * buffers to send all the fragments so all
3313 if ((m->m_flags & M_FRAG) &&
3314 !ath_txfrag_setup(sc, &frags, m, ni)) {
3315 DPRINTF(sc, ATH_DEBUG_XMIT,
3316 "%s: out of txfrag buffers\n", __func__);
3317 sc->sc_stats.ast_tx_nofrag++;
3318 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3324 * At this point if we have any TX fragments, then we will
3325 * have bumped the node reference once for each of those.
3329 * XXX Is there anything actually _enforcing_ that the
3330 * fragments are being transmitted in one hit, rather than
3331 * being interleaved with other transmissions on that
3334 * The ATH TX output lock is the only thing serialising this
3339 * Calculate the "next fragment" length field in ath_buf
3340 * in order to let the transmit path know enough about
3341 * what to next write to the hardware.
3343 if (m->m_flags & M_FRAG) {
3344 struct ath_buf *fbf = bf;
3345 struct ath_buf *n_fbf = NULL;
3346 struct mbuf *fm = m->m_nextpkt;
3349 * We need to walk the list of fragments and set
3350 * the next size to the following buffer.
3351 * However, the first buffer isn't in the frag
3352 * list, so we have to do some gymnastics here.
3354 TAILQ_FOREACH(n_fbf, &frags, bf_list) {
3355 fbf->bf_nextfraglen = fm->m_pkthdr.len;
3362 * Bump the ifp output counter.
3364 * XXX should use atomics?
3366 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
3369 * Pass the frame to the h/w for transmission.
3370 * Fragmented frames have each frag chained together
3371 * with m_nextpkt. We know there are sufficient ath_buf's
3372 * to send all the frags because of work done by
3373 * ath_txfrag_setup. We leave m_nextpkt set while
3374 * calling ath_tx_start so it can use it to extend the
3375 * the tx duration to cover the subsequent frag and
3376 * so it can reclaim all the mbufs in case of an error;
3377 * ath_tx_start clears m_nextpkt once it commits to
3378 * handing the frame to the hardware.
3380 * Note: if this fails, then the mbufs are freed but
3381 * not the node reference.
3383 next = m->m_nextpkt;
3384 if (ath_tx_start(sc, ni, bf, m)) {
3386 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
3391 ath_returnbuf_head(sc, bf);
3393 * Free the rest of the node references and
3394 * buffers for the fragment list.
3396 ath_txfrag_cleanup(sc, &frags, ni);
3397 ATH_TXBUF_UNLOCK(sc);
3403 * Check here if the node is in power save state.
3405 ath_tx_update_tim(sc, ni, 1);
3409 * Beware of state changing between frags.
3410 * XXX check sta power-save state?
3412 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) {
3413 DPRINTF(sc, ATH_DEBUG_XMIT,
3414 "%s: flush fragmented packet, state %s\n",
3416 ieee80211_state_name[ni->ni_vap->iv_state]);
3422 bf = TAILQ_FIRST(&frags);
3423 KASSERT(bf != NULL, ("no buf for txfrag"));
3424 TAILQ_REMOVE(&frags, bf, bf_list);
3429 * Bump watchdog timer.
3431 sc->sc_wd_timer = 5;
3437 * Finished transmitting!
3440 sc->sc_txstart_cnt--;
3443 /* Sleep the hardware if required */
3445 ath_power_restore_power_state(sc);
3448 ATH_KTR(sc, ATH_KTR_TX, 0, "ath_transmit: finished");
3454 ath_media_change(struct ifnet *ifp)
3456 int error = ieee80211_media_change(ifp);
3457 /* NB: only the fixed rate can change and that doesn't need a reset */
3458 return (error == ENETRESET ? 0 : error);
3462 * Block/unblock tx+rx processing while a key change is done.
3463 * We assume the caller serializes key management operations
3464 * so we only need to worry about synchronization with other
3465 * uses that originate in the driver.
3468 ath_key_update_begin(struct ieee80211vap *vap)
3470 struct ifnet *ifp = vap->iv_ic->ic_ifp;
3471 struct ath_softc *sc = ifp->if_softc;
3473 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
3474 taskqueue_block(sc->sc_tq);
3478 ath_key_update_end(struct ieee80211vap *vap)
3480 struct ifnet *ifp = vap->iv_ic->ic_ifp;
3481 struct ath_softc *sc = ifp->if_softc;
3483 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
3484 taskqueue_unblock(sc->sc_tq);
3488 ath_update_promisc(struct ifnet *ifp)
3490 struct ath_softc *sc = ifp->if_softc;
3493 /* configure rx filter */
3495 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3496 rfilt = ath_calcrxfilter(sc);
3497 ath_hal_setrxfilter(sc->sc_ah, rfilt);
3498 ath_power_restore_power_state(sc);
3501 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x\n", __func__, rfilt);
3505 * Driver-internal mcast update call.
3507 * Assumes the hardware is already awake.
3510 ath_update_mcast_hw(struct ath_softc *sc)
3512 struct ifnet *ifp = sc->sc_ifp;
3515 /* calculate and install multicast filter */
3516 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
3517 struct ifmultiaddr *ifma;
3519 * Merge multicast addresses to form the hardware filter.
3521 mfilt[0] = mfilt[1] = 0;
3522 if_maddr_rlock(ifp); /* XXX need some fiddling to remove? */
3523 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3528 /* calculate XOR of eight 6bit values */
3529 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
3530 val = LE_READ_4(dl + 0);
3531 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3532 val = LE_READ_4(dl + 3);
3533 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
3535 mfilt[pos / 32] |= (1 << (pos % 32));
3537 if_maddr_runlock(ifp);
3539 mfilt[0] = mfilt[1] = ~0;
3541 ath_hal_setmcastfilter(sc->sc_ah, mfilt[0], mfilt[1]);
3543 DPRINTF(sc, ATH_DEBUG_MODE, "%s: MC filter %08x:%08x\n",
3544 __func__, mfilt[0], mfilt[1]);
3548 * Called from the net80211 layer - force the hardware
3549 * awake before operating.
3552 ath_update_mcast(struct ifnet *ifp)
3554 struct ath_softc *sc = ifp->if_softc;
3557 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3560 ath_update_mcast_hw(sc);
3563 ath_power_restore_power_state(sc);
3568 ath_mode_init(struct ath_softc *sc)
3570 struct ifnet *ifp = sc->sc_ifp;
3571 struct ath_hal *ah = sc->sc_ah;
3574 /* configure rx filter */
3575 rfilt = ath_calcrxfilter(sc);
3576 ath_hal_setrxfilter(ah, rfilt);
3578 /* configure operational mode */
3579 ath_hal_setopmode(ah);
3581 DPRINTF(sc, ATH_DEBUG_STATE | ATH_DEBUG_MODE,
3582 "%s: ah=%p, ifp=%p, if_addr=%p\n",
3586 (ifp == NULL) ? NULL : ifp->if_addr);
3588 /* handle any link-level address change */
3589 ath_hal_setmac(ah, IF_LLADDR(ifp));
3591 /* calculate and install multicast filter */
3592 ath_update_mcast_hw(sc);
3596 * Set the slot time based on the current setting.
3599 ath_setslottime(struct ath_softc *sc)
3601 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
3602 struct ath_hal *ah = sc->sc_ah;
3605 if (IEEE80211_IS_CHAN_HALF(ic->ic_curchan))
3607 else if (IEEE80211_IS_CHAN_QUARTER(ic->ic_curchan))
3609 else if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
3610 /* honor short/long slot time only in 11g */
3611 /* XXX shouldn't honor on pure g or turbo g channel */
3612 if (ic->ic_flags & IEEE80211_F_SHSLOT)
3613 usec = HAL_SLOT_TIME_9;
3615 usec = HAL_SLOT_TIME_20;
3617 usec = HAL_SLOT_TIME_9;
3619 DPRINTF(sc, ATH_DEBUG_RESET,
3620 "%s: chan %u MHz flags 0x%x %s slot, %u usec\n",
3621 __func__, ic->ic_curchan->ic_freq, ic->ic_curchan->ic_flags,
3622 ic->ic_flags & IEEE80211_F_SHSLOT ? "short" : "long", usec);
3624 /* Wake up the hardware first before updating the slot time */
3626 ath_power_set_power_state(sc, HAL_PM_AWAKE);
3627 ath_hal_setslottime(ah, usec);
3628 ath_power_restore_power_state(sc);
3629 sc->sc_updateslot = OK;
3634 * Callback from the 802.11 layer to update the
3635 * slot time based on the current setting.
3638 ath_updateslot(struct ifnet *ifp)
3640 struct ath_softc *sc = ifp->if_softc;
3641 struct ieee80211com *ic = ifp->if_l2com;
3644 * When not coordinating the BSS, change the hardware
3645 * immediately. For other operation we defer the change
3646 * until beacon updates have propagated to the stations.
3648 * XXX sc_updateslot isn't changed behind a lock?
3650 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3651 ic->ic_opmode == IEEE80211_M_MBSS)
3652 sc->sc_updateslot = UPDATE;
3654 ath_setslottime(sc);
3658 * Append the contents of src to dst; both queues
3659 * are assumed to be locked.
3662 ath_txqmove(struct ath_txq *dst, struct ath_txq *src)
3665 ATH_TXQ_LOCK_ASSERT(src);
3666 ATH_TXQ_LOCK_ASSERT(dst);
3668 TAILQ_CONCAT(&dst->axq_q, &src->axq_q, bf_list);
3669 dst->axq_link = src->axq_link;
3670 src->axq_link = NULL;
3671 dst->axq_depth += src->axq_depth;
3672 dst->axq_aggr_depth += src->axq_aggr_depth;
3674 src->axq_aggr_depth = 0;
3678 * Reset the hardware, with no loss.
3680 * This can't be used for a general case reset.
3683 ath_reset_proc(void *arg, int pending)
3685 struct ath_softc *sc = arg;
3686 struct ifnet *ifp = sc->sc_ifp;
3689 if_printf(ifp, "%s: resetting\n", __func__);
3691 ath_reset(ifp, ATH_RESET_NOLOSS);
3695 * Reset the hardware after detecting beacons have stopped.
3698 ath_bstuck_proc(void *arg, int pending)
3700 struct ath_softc *sc = arg;
3701 struct ifnet *ifp = sc->sc_ifp;
3704 if (ath_hal_gethangstate(sc->sc_ah, 0xff, &hangs) && hangs != 0)
3705 if_printf(ifp, "bb hang detected (0x%x)\n", hangs);
3707 #ifdef ATH_DEBUG_ALQ
3708 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_STUCK_BEACON))
3709 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_STUCK_BEACON, 0, NULL);
3712 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
3714 sc->sc_stats.ast_bstuck++;
3716 * This assumes that there's no simultaneous channel mode change
3719 ath_reset(ifp, ATH_RESET_NOLOSS);
3723 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3725 bus_addr_t *paddr = (bus_addr_t*) arg;
3726 KASSERT(error == 0, ("error %u on bus_dma callback", error));
3727 *paddr = segs->ds_addr;
3731 * Allocate the descriptors and appropriate DMA tag/setup.
3733 * For some situations (eg EDMA TX completion), there isn't a requirement
3734 * for the ath_buf entries to be allocated.
3737 ath_descdma_alloc_desc(struct ath_softc *sc,
3738 struct ath_descdma *dd, ath_bufhead *head,
3739 const char *name, int ds_size, int ndesc)
3741 #define DS2PHYS(_dd, _ds) \
3742 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
3743 #define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \
3744 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0)
3745 struct ifnet *ifp = sc->sc_ifp;
3748 dd->dd_descsize = ds_size;
3750 DPRINTF(sc, ATH_DEBUG_RESET,
3751 "%s: %s DMA: %u desc, %d bytes per descriptor\n",
3752 __func__, name, ndesc, dd->dd_descsize);
3755 dd->dd_desc_len = dd->dd_descsize * ndesc;
3758 * Merlin work-around:
3759 * Descriptors that cross the 4KB boundary can't be used.
3760 * Assume one skipped descriptor per 4KB page.
3762 if (! ath_hal_split4ktrans(sc->sc_ah)) {
3763 int numpages = dd->dd_desc_len / 4096;
3764 dd->dd_desc_len += ds_size * numpages;
3768 * Setup DMA descriptor area.
3770 * BUS_DMA_ALLOCNOW is not used; we never use bounce
3771 * buffers for the descriptors themselves.
3773 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
3774 PAGE_SIZE, 0, /* alignment, bounds */
3775 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
3776 BUS_SPACE_MAXADDR, /* highaddr */
3777 NULL, NULL, /* filter, filterarg */
3778 dd->dd_desc_len, /* maxsize */
3780 dd->dd_desc_len, /* maxsegsize */
3782 NULL, /* lockfunc */
3786 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
3790 /* allocate descriptors */
3791 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
3792 BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
3795 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
3796 "error %u\n", ndesc, dd->dd_name, error);
3800 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
3801 dd->dd_desc, dd->dd_desc_len,
3802 ath_load_cb, &dd->dd_desc_paddr,
3805 if_printf(ifp, "unable to map %s descriptors, error %u\n",
3806 dd->dd_name, error);
3810 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
3811 __func__, dd->dd_name, (uint8_t *) dd->dd_desc,
3812 (u_long) dd->dd_desc_len, (caddr_t) dd->dd_desc_paddr,
3813 /*XXX*/ (u_long) dd->dd_desc_len);
3818 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3820 bus_dma_tag_destroy(dd->dd_dmat);
3821 memset(dd, 0, sizeof(*dd));
3824 #undef ATH_DESC_4KB_BOUND_CHECK
3828 ath_descdma_setup(struct ath_softc *sc,
3829 struct ath_descdma *dd, ath_bufhead *head,
3830 const char *name, int ds_size, int nbuf, int ndesc)
3832 #define DS2PHYS(_dd, _ds) \
3833 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
3834 #define ATH_DESC_4KB_BOUND_CHECK(_daddr, _len) \
3835 ((((u_int32_t)(_daddr) & 0xFFF) > (0x1000 - (_len))) ? 1 : 0)
3836 struct ifnet *ifp = sc->sc_ifp;
3839 int i, bsize, error;
3841 /* Allocate descriptors */
3842 error = ath_descdma_alloc_desc(sc, dd, head, name, ds_size,
3845 /* Assume any errors during allocation were dealt with */
3850 ds = (uint8_t *) dd->dd_desc;
3852 /* allocate rx buffers */
3853 bsize = sizeof(struct ath_buf) * nbuf;
3854 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
3856 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
3857 dd->dd_name, bsize);
3863 for (i = 0; i < nbuf; i++, bf++, ds += (ndesc * dd->dd_descsize)) {
3864 bf->bf_desc = (struct ath_desc *) ds;
3865 bf->bf_daddr = DS2PHYS(dd, ds);
3866 if (! ath_hal_split4ktrans(sc->sc_ah)) {
3868 * Merlin WAR: Skip descriptor addresses which
3869 * cause 4KB boundary crossing along any point
3870 * in the descriptor.
3872 if (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr,
3874 /* Start at the next page */
3875 ds += 0x1000 - (bf->bf_daddr & 0xFFF);
3876 bf->bf_desc = (struct ath_desc *) ds;
3877 bf->bf_daddr = DS2PHYS(dd, ds);
3880 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
3883 if_printf(ifp, "unable to create dmamap for %s "
3884 "buffer %u, error %u\n", dd->dd_name, i, error);
3885 ath_descdma_cleanup(sc, dd, head);
3888 bf->bf_lastds = bf->bf_desc; /* Just an initial value */
3889 TAILQ_INSERT_TAIL(head, bf, bf_list);
3893 * XXX TODO: ensure that ds doesn't overflow the descriptor
3894 * allocation otherwise weird stuff will occur and crash your
3898 /* XXX this should likely just call ath_descdma_cleanup() */
3900 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3901 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3902 bus_dma_tag_destroy(dd->dd_dmat);
3903 memset(dd, 0, sizeof(*dd));
3906 #undef ATH_DESC_4KB_BOUND_CHECK
3910 * Allocate ath_buf entries but no descriptor contents.
3912 * This is for RX EDMA where the descriptors are the header part of
3916 ath_descdma_setup_rx_edma(struct ath_softc *sc,
3917 struct ath_descdma *dd, ath_bufhead *head,
3918 const char *name, int nbuf, int rx_status_len)
3920 struct ifnet *ifp = sc->sc_ifp;
3922 int i, bsize, error;
3924 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers\n",
3925 __func__, name, nbuf);
3929 * This is (mostly) purely for show. We're not allocating any actual
3930 * descriptors here as EDMA RX has the descriptor be part
3933 * However, dd_desc_len is used by ath_descdma_free() to determine
3934 * whether we have already freed this DMA mapping.
3936 dd->dd_desc_len = rx_status_len * nbuf;
3937 dd->dd_descsize = rx_status_len;
3939 /* allocate rx buffers */
3940 bsize = sizeof(struct ath_buf) * nbuf;
3941 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
3943 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
3944 dd->dd_name, bsize);
3951 for (i = 0; i < nbuf; i++, bf++) {
3954 bf->bf_lastds = NULL; /* Just an initial value */
3956 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
3959 if_printf(ifp, "unable to create dmamap for %s "
3960 "buffer %u, error %u\n", dd->dd_name, i, error);
3961 ath_descdma_cleanup(sc, dd, head);
3964 TAILQ_INSERT_TAIL(head, bf, bf_list);
3968 memset(dd, 0, sizeof(*dd));
3973 ath_descdma_cleanup(struct ath_softc *sc,
3974 struct ath_descdma *dd, ath_bufhead *head)
3977 struct ieee80211_node *ni;
3980 if (dd->dd_dmamap != 0) {
3981 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
3982 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
3983 bus_dma_tag_destroy(dd->dd_dmat);
3987 TAILQ_FOREACH(bf, head, bf_list) {
3990 * XXX warn if there's buffers here.
3991 * XXX it should have been freed by the
3995 if (do_warning == 0) {
3997 device_printf(sc->sc_dev,
3998 "%s: %s: mbuf should've been"
3999 " unmapped/freed!\n",
4003 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
4004 BUS_DMASYNC_POSTREAD);
4005 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
4009 if (bf->bf_dmamap != NULL) {
4010 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
4011 bf->bf_dmamap = NULL;
4017 * Reclaim node reference.
4019 ieee80211_free_node(ni);
4027 if (dd->dd_bufptr != NULL)
4028 free(dd->dd_bufptr, M_ATHDEV);
4029 memset(dd, 0, sizeof(*dd));
4033 ath_desc_alloc(struct ath_softc *sc)
4037 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
4038 "tx", sc->sc_tx_desclen, ath_txbuf, ATH_MAX_SCATTER);
4042 sc->sc_txbuf_cnt = ath_txbuf;
4044 error = ath_descdma_setup(sc, &sc->sc_txdma_mgmt, &sc->sc_txbuf_mgmt,
4045 "tx_mgmt", sc->sc_tx_desclen, ath_txbuf_mgmt,
4048 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
4053 * XXX mark txbuf_mgmt frames with ATH_BUF_MGMT, so the
4054 * flag doesn't have to be set in ath_getbuf_locked().
4057 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
4058 "beacon", sc->sc_tx_desclen, ATH_BCBUF, 1);
4060 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
4061 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
4062 &sc->sc_txbuf_mgmt);
4069 ath_desc_free(struct ath_softc *sc)
4072 if (sc->sc_bdma.dd_desc_len != 0)
4073 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
4074 if (sc->sc_txdma.dd_desc_len != 0)
4075 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
4076 if (sc->sc_txdma_mgmt.dd_desc_len != 0)
4077 ath_descdma_cleanup(sc, &sc->sc_txdma_mgmt,
4078 &sc->sc_txbuf_mgmt);
4081 static struct ieee80211_node *
4082 ath_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN])
4084 struct ieee80211com *ic = vap->iv_ic;
4085 struct ath_softc *sc = ic->ic_ifp->if_softc;
4086 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
4087 struct ath_node *an;
4089 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
4094 ath_rate_node_init(sc, an);
4096 /* Setup the mutex - there's no associd yet so set the name to NULL */
4097 snprintf(an->an_name, sizeof(an->an_name), "%s: node %p",
4098 device_get_nameunit(sc->sc_dev), an);
4099 mtx_init(&an->an_mtx, an->an_name, NULL, MTX_DEF);
4101 /* XXX setup ath_tid */
4102 ath_tx_tid_init(sc, an);
4104 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__, mac, ":", an);
4105 return &an->an_node;
4109 ath_node_cleanup(struct ieee80211_node *ni)
4111 struct ieee80211com *ic = ni->ni_ic;
4112 struct ath_softc *sc = ic->ic_ifp->if_softc;
4114 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
4115 ni->ni_macaddr, ":", ATH_NODE(ni));
4117 /* Cleanup ath_tid, free unused bufs, unlink bufs in TXQ */
4118 ath_tx_node_flush(sc, ATH_NODE(ni));
4119 ath_rate_node_cleanup(sc, ATH_NODE(ni));
4120 sc->sc_node_cleanup(ni);
4124 ath_node_free(struct ieee80211_node *ni)
4126 struct ieee80211com *ic = ni->ni_ic;
4127 struct ath_softc *sc = ic->ic_ifp->if_softc;
4129 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: an %p\n", __func__,
4130 ni->ni_macaddr, ":", ATH_NODE(ni));
4131 mtx_destroy(&ATH_NODE(ni)->an_mtx);
4132 sc->sc_node_free(ni);
4136 ath_node_getsignal(const struct ieee80211_node *ni, int8_t *rssi, int8_t *noise)
4138 struct ieee80211com *ic = ni->ni_ic;
4139 struct ath_softc *sc = ic->ic_ifp->if_softc;
4140 struct ath_hal *ah = sc->sc_ah;
4142 *rssi = ic->ic_node_getrssi(ni);
4143 if (ni->ni_chan != IEEE80211_CHAN_ANYC)
4144 *noise = ath_hal_getchannoise(ah, ni->ni_chan);
4146 *noise = -95; /* nominally correct */
4150 * Set the default antenna.
4153 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
4155 struct ath_hal *ah = sc->sc_ah;
4157 /* XXX block beacon interrupts */
4158 ath_hal_setdefantenna(ah, antenna);
4159 if (sc->sc_defant != antenna)
4160 sc->sc_stats.ast_ant_defswitch++;
4161 sc->sc_defant = antenna;
4162 sc->sc_rxotherant = 0;
4166 ath_txq_init(struct ath_softc *sc, struct ath_txq *txq, int qnum)
4168 txq->axq_qnum = qnum;
4171 txq->axq_aggr_depth = 0;
4172 txq->axq_intrcnt = 0;
4173 txq->axq_link = NULL;
4174 txq->axq_softc = sc;
4175 TAILQ_INIT(&txq->axq_q);
4176 TAILQ_INIT(&txq->axq_tidq);
4177 TAILQ_INIT(&txq->fifo.axq_q);
4178 ATH_TXQ_LOCK_INIT(sc, txq);
4182 * Setup a h/w transmit queue.
4184 static struct ath_txq *
4185 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
4187 #define N(a) (sizeof(a)/sizeof(a[0]))
4188 struct ath_hal *ah = sc->sc_ah;
4192 memset(&qi, 0, sizeof(qi));
4193 qi.tqi_subtype = subtype;
4194 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
4195 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
4196 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
4198 * Enable interrupts only for EOL and DESC conditions.
4199 * We mark tx descriptors to receive a DESC interrupt
4200 * when a tx queue gets deep; otherwise waiting for the
4201 * EOL to reap descriptors. Note that this is done to
4202 * reduce interrupt load and this only defers reaping
4203 * descriptors, never transmitting frames. Aside from
4204 * reducing interrupts this also permits more concurrency.
4205 * The only potential downside is if the tx queue backs
4206 * up in which case the top half of the kernel may backup
4207 * due to a lack of tx descriptors.
4210 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE |
4211 HAL_TXQ_TXOKINT_ENABLE;
4213 qi.tqi_qflags = HAL_TXQ_TXEOLINT_ENABLE |
4214 HAL_TXQ_TXDESCINT_ENABLE;
4216 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
4219 * NB: don't print a message, this happens
4220 * normally on parts with too few tx queues
4224 if (qnum >= N(sc->sc_txq)) {
4225 device_printf(sc->sc_dev,
4226 "hal qnum %u out of range, max %zu!\n",
4227 qnum, N(sc->sc_txq));
4228 ath_hal_releasetxqueue(ah, qnum);
4231 if (!ATH_TXQ_SETUP(sc, qnum)) {
4232 ath_txq_init(sc, &sc->sc_txq[qnum], qnum);
4233 sc->sc_txqsetup |= 1<<qnum;
4235 return &sc->sc_txq[qnum];
4240 * Setup a hardware data transmit queue for the specified
4241 * access control. The hal may not support all requested
4242 * queues in which case it will return a reference to a
4243 * previously setup queue. We record the mapping from ac's
4244 * to h/w queues for use by ath_tx_start and also track
4245 * the set of h/w queues being used to optimize work in the
4246 * transmit interrupt handler and related routines.
4249 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
4251 #define N(a) (sizeof(a)/sizeof(a[0]))
4252 struct ath_txq *txq;
4254 if (ac >= N(sc->sc_ac2q)) {
4255 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
4256 ac, N(sc->sc_ac2q));
4259 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
4262 sc->sc_ac2q[ac] = txq;
4270 * Update WME parameters for a transmit queue.
4273 ath_txq_update(struct ath_softc *sc, int ac)
4275 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
4276 #define ATH_TXOP_TO_US(v) (v<<5)
4277 struct ifnet *ifp = sc->sc_ifp;
4278 struct ieee80211com *ic = ifp->if_l2com;
4279 struct ath_txq *txq = sc->sc_ac2q[ac];
4280 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
4281 struct ath_hal *ah = sc->sc_ah;
4284 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
4285 #ifdef IEEE80211_SUPPORT_TDMA
4288 * AIFS is zero so there's no pre-transmit wait. The
4289 * burst time defines the slot duration and is configured
4290 * through net80211. The QCU is setup to not do post-xmit
4291 * back off, lockout all lower-priority QCU's, and fire
4292 * off the DMA beacon alert timer which is setup based
4293 * on the slot configuration.
4295 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4296 | HAL_TXQ_TXERRINT_ENABLE
4297 | HAL_TXQ_TXURNINT_ENABLE
4298 | HAL_TXQ_TXEOLINT_ENABLE
4300 | HAL_TXQ_BACKOFF_DISABLE
4301 | HAL_TXQ_ARB_LOCKOUT_GLOBAL
4305 qi.tqi_readyTime = sc->sc_tdmaslotlen;
4306 qi.tqi_burstTime = qi.tqi_readyTime;
4310 * XXX shouldn't this just use the default flags
4311 * used in the previous queue setup?
4313 qi.tqi_qflags = HAL_TXQ_TXOKINT_ENABLE
4314 | HAL_TXQ_TXERRINT_ENABLE
4315 | HAL_TXQ_TXDESCINT_ENABLE
4316 | HAL_TXQ_TXURNINT_ENABLE
4317 | HAL_TXQ_TXEOLINT_ENABLE
4319 qi.tqi_aifs = wmep->wmep_aifsn;
4320 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
4321 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
4322 qi.tqi_readyTime = 0;
4323 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
4324 #ifdef IEEE80211_SUPPORT_TDMA
4328 DPRINTF(sc, ATH_DEBUG_RESET,
4329 "%s: Q%u qflags 0x%x aifs %u cwmin %u cwmax %u burstTime %u\n",
4330 __func__, txq->axq_qnum, qi.tqi_qflags,
4331 qi.tqi_aifs, qi.tqi_cwmin, qi.tqi_cwmax, qi.tqi_burstTime);
4333 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
4334 if_printf(ifp, "unable to update hardware queue "
4335 "parameters for %s traffic!\n",
4336 ieee80211_wme_acnames[ac]);
4339 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
4342 #undef ATH_TXOP_TO_US
4343 #undef ATH_EXPONENT_TO_VALUE
4347 * Callback from the 802.11 layer to update WME parameters.
4350 ath_wme_update(struct ieee80211com *ic)
4352 struct ath_softc *sc = ic->ic_ifp->if_softc;
4354 return !ath_txq_update(sc, WME_AC_BE) ||
4355 !ath_txq_update(sc, WME_AC_BK) ||
4356 !ath_txq_update(sc, WME_AC_VI) ||
4357 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
4361 * Reclaim resources for a setup queue.
4364 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
4367 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
4368 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
4369 ATH_TXQ_LOCK_DESTROY(txq);
4373 * Reclaim all tx queue resources.
4376 ath_tx_cleanup(struct ath_softc *sc)
4380 ATH_TXBUF_LOCK_DESTROY(sc);
4381 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4382 if (ATH_TXQ_SETUP(sc, i))
4383 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
4387 * Return h/w rate index for an IEEE rate (w/o basic rate bit)
4388 * using the current rates in sc_rixmap.
4391 ath_tx_findrix(const struct ath_softc *sc, uint8_t rate)
4393 int rix = sc->sc_rixmap[rate];
4394 /* NB: return lowest rix for invalid rate */
4395 return (rix == 0xff ? 0 : rix);
4399 ath_tx_update_stats(struct ath_softc *sc, struct ath_tx_status *ts,
4402 struct ieee80211_node *ni = bf->bf_node;
4403 struct ifnet *ifp = sc->sc_ifp;
4404 struct ieee80211com *ic = ifp->if_l2com;
4407 if (ts->ts_status == 0) {
4408 u_int8_t txant = ts->ts_antenna;
4409 sc->sc_stats.ast_ant_tx[txant]++;
4410 sc->sc_ant_tx[txant]++;
4411 if (ts->ts_finaltsi != 0)
4412 sc->sc_stats.ast_tx_altrate++;
4413 pri = M_WME_GETAC(bf->bf_m);
4414 if (pri >= WME_AC_VO)
4415 ic->ic_wme.wme_hipri_traffic++;
4416 if ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)
4417 ni->ni_inact = ni->ni_inact_reload;
4419 if (ts->ts_status & HAL_TXERR_XRETRY)
4420 sc->sc_stats.ast_tx_xretries++;
4421 if (ts->ts_status & HAL_TXERR_FIFO)
4422 sc->sc_stats.ast_tx_fifoerr++;
4423 if (ts->ts_status & HAL_TXERR_FILT)
4424 sc->sc_stats.ast_tx_filtered++;
4425 if (ts->ts_status & HAL_TXERR_XTXOP)
4426 sc->sc_stats.ast_tx_xtxop++;
4427 if (ts->ts_status & HAL_TXERR_TIMER_EXPIRED)
4428 sc->sc_stats.ast_tx_timerexpired++;
4430 if (bf->bf_m->m_flags & M_FF)
4431 sc->sc_stats.ast_ff_txerr++;
4433 /* XXX when is this valid? */
4434 if (ts->ts_flags & HAL_TX_DESC_CFG_ERR)
4435 sc->sc_stats.ast_tx_desccfgerr++;
4437 * This can be valid for successful frame transmission!
4438 * If there's a TX FIFO underrun during aggregate transmission,
4439 * the MAC will pad the rest of the aggregate with delimiters.
4440 * If a BA is returned, the frame is marked as "OK" and it's up
4441 * to the TX completion code to notice which frames weren't
4442 * successfully transmitted.
4444 if (ts->ts_flags & HAL_TX_DATA_UNDERRUN)
4445 sc->sc_stats.ast_tx_data_underrun++;
4446 if (ts->ts_flags & HAL_TX_DELIM_UNDERRUN)
4447 sc->sc_stats.ast_tx_delim_underrun++;
4449 sr = ts->ts_shortretry;
4450 lr = ts->ts_longretry;
4451 sc->sc_stats.ast_tx_shortretry += sr;
4452 sc->sc_stats.ast_tx_longretry += lr;
4457 * The default completion. If fail is 1, this means
4458 * "please don't retry the frame, and just return -1 status
4459 * to the net80211 stack.
4462 ath_tx_default_comp(struct ath_softc *sc, struct ath_buf *bf, int fail)
4464 struct ath_tx_status *ts = &bf->bf_status.ds_txstat;
4470 st = ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) ?
4471 ts->ts_status : HAL_TXERR_XRETRY;
4474 if (bf->bf_state.bfs_dobaw)
4475 device_printf(sc->sc_dev,
4476 "%s: bf %p: seqno %d: dobaw should've been cleared!\n",
4479 SEQNO(bf->bf_state.bfs_seqno));
4481 if (bf->bf_next != NULL)
4482 device_printf(sc->sc_dev,
4483 "%s: bf %p: seqno %d: bf_next not NULL!\n",
4486 SEQNO(bf->bf_state.bfs_seqno));
4489 * Check if the node software queue is empty; if so
4490 * then clear the TIM.
4492 * This needs to be done before the buffer is freed as
4493 * otherwise the node reference will have been released
4494 * and the node may not actually exist any longer.
4496 * XXX I don't like this belonging here, but it's cleaner
4497 * to do it here right now then all the other places
4498 * where ath_tx_default_comp() is called.
4500 * XXX TODO: during drain, ensure that the callback is
4501 * being called so we get a chance to update the TIM.
4505 ath_tx_update_tim(sc, bf->bf_node, 0);
4510 * Do any tx complete callback. Note this must
4511 * be done before releasing the node reference.
4512 * This will free the mbuf, release the net80211
4513 * node and recycle the ath_buf.
4515 ath_tx_freebuf(sc, bf, st);
4519 * Update rate control with the given completion status.
4522 ath_tx_update_ratectrl(struct ath_softc *sc, struct ieee80211_node *ni,
4523 struct ath_rc_series *rc, struct ath_tx_status *ts, int frmlen,
4524 int nframes, int nbad)
4526 struct ath_node *an;
4528 /* Only for unicast frames */
4533 ATH_NODE_UNLOCK_ASSERT(an);
4535 if ((ts->ts_status & HAL_TXERR_FILT) == 0) {
4537 ath_rate_tx_complete(sc, an, rc, ts, frmlen, nframes, nbad);
4538 ATH_NODE_UNLOCK(an);
4543 * Process the completion of the given buffer.
4545 * This calls the rate control update and then the buffer completion.
4546 * This will either free the buffer or requeue it. In any case, the
4547 * bf pointer should be treated as invalid after this function is called.
4550 ath_tx_process_buf_completion(struct ath_softc *sc, struct ath_txq *txq,
4551 struct ath_tx_status *ts, struct ath_buf *bf)
4553 struct ieee80211_node *ni = bf->bf_node;
4555 ATH_TX_UNLOCK_ASSERT(sc);
4556 ATH_TXQ_UNLOCK_ASSERT(txq);
4558 /* If unicast frame, update general statistics */
4560 /* update statistics */
4561 ath_tx_update_stats(sc, ts, bf);
4565 * Call the completion handler.
4566 * The completion handler is responsible for
4567 * calling the rate control code.
4569 * Frames with no completion handler get the
4570 * rate control code called here.
4572 if (bf->bf_comp == NULL) {
4573 if ((ts->ts_status & HAL_TXERR_FILT) == 0 &&
4574 (bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0) {
4576 * XXX assume this isn't an aggregate
4579 ath_tx_update_ratectrl(sc, ni,
4580 bf->bf_state.bfs_rc, ts,
4581 bf->bf_state.bfs_pktlen, 1,
4582 (ts->ts_status == 0 ? 0 : 1));
4584 ath_tx_default_comp(sc, bf, 0);
4586 bf->bf_comp(sc, bf, 0);
4592 * Process completed xmit descriptors from the specified queue.
4593 * Kick the packet scheduler if needed. This can occur from this
4597 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq, int dosched)
4599 struct ath_hal *ah = sc->sc_ah;
4601 struct ath_desc *ds;
4602 struct ath_tx_status *ts;
4603 struct ieee80211_node *ni;
4604 #ifdef IEEE80211_SUPPORT_SUPERG
4605 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
4606 #endif /* IEEE80211_SUPPORT_SUPERG */
4610 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
4611 __func__, txq->axq_qnum,
4612 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4615 ATH_KTR(sc, ATH_KTR_TXCOMP, 4,
4616 "ath_tx_processq: txq=%u head %p link %p depth %p",
4618 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
4625 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
4626 bf = TAILQ_FIRST(&txq->axq_q);
4628 ATH_TXQ_UNLOCK(txq);
4631 ds = bf->bf_lastds; /* XXX must be setup correctly! */
4632 ts = &bf->bf_status.ds_txstat;
4634 status = ath_hal_txprocdesc(ah, ds, ts);
4636 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
4637 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4639 else if ((sc->sc_debug & ATH_DEBUG_RESET) && (dosched == 0))
4640 ath_printtxbuf(sc, bf, txq->axq_qnum, 0,
4643 #ifdef ATH_DEBUG_ALQ
4644 if (if_ath_alq_checkdebug(&sc->sc_alq,
4645 ATH_ALQ_EDMA_TXSTATUS)) {
4646 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS,
4647 sc->sc_tx_statuslen,
4652 if (status == HAL_EINPROGRESS) {
4653 ATH_KTR(sc, ATH_KTR_TXCOMP, 3,
4654 "ath_tx_processq: txq=%u, bf=%p ds=%p, HAL_EINPROGRESS",
4655 txq->axq_qnum, bf, ds);
4656 ATH_TXQ_UNLOCK(txq);
4659 ATH_TXQ_REMOVE(txq, bf, bf_list);
4664 if (txq->axq_qnum != bf->bf_state.bfs_tx_queue) {
4665 device_printf(sc->sc_dev,
4666 "%s: TXQ=%d: bf=%p, bfs_tx_queue=%d\n",
4670 bf->bf_state.bfs_tx_queue);
4672 if (txq->axq_qnum != bf->bf_last->bf_state.bfs_tx_queue) {
4673 device_printf(sc->sc_dev,
4674 "%s: TXQ=%d: bf_last=%p, bfs_tx_queue=%d\n",
4678 bf->bf_last->bf_state.bfs_tx_queue);
4682 if (txq->axq_depth > 0) {
4684 * More frames follow. Mark the buffer busy
4685 * so it's not re-used while the hardware may
4686 * still re-read the link field in the descriptor.
4688 * Use the last buffer in an aggregate as that
4689 * is where the hardware may be - intermediate
4690 * descriptors won't be "busy".
4692 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
4694 txq->axq_link = NULL;
4696 bf->bf_last->bf_flags |= ATH_BUF_BUSY;
4698 if (bf->bf_state.bfs_aggr)
4699 txq->axq_aggr_depth--;
4703 ATH_KTR(sc, ATH_KTR_TXCOMP, 5,
4704 "ath_tx_processq: txq=%u, bf=%p, ds=%p, ni=%p, ts_status=0x%08x",
4705 txq->axq_qnum, bf, ds, ni, ts->ts_status);
4707 * If unicast frame was ack'd update RSSI,
4708 * including the last rx time used to
4709 * workaround phantom bmiss interrupts.
4711 if (ni != NULL && ts->ts_status == 0 &&
4712 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) {
4714 sc->sc_stats.ast_tx_rssi = ts->ts_rssi;
4715 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
4718 ATH_TXQ_UNLOCK(txq);
4721 * Update statistics and call completion
4723 ath_tx_process_buf_completion(sc, txq, ts, bf);
4725 /* XXX at this point, bf and ni may be totally invalid */
4727 #ifdef IEEE80211_SUPPORT_SUPERG
4729 * Flush fast-frame staging queue when traffic slows.
4731 if (txq->axq_depth <= 1)
4732 ieee80211_ff_flush(ic, txq->axq_ac);
4735 /* Kick the software TXQ scheduler */
4738 ath_txq_sched(sc, txq);
4742 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4743 "ath_tx_processq: txq=%u: done",
4749 #define TXQACTIVE(t, q) ( (t) & (1 << (q)))
4752 * Deferred processing of transmit interrupt; special-cased
4753 * for a single hardware transmit queue (e.g. 5210 and 5211).
4756 ath_tx_proc_q0(void *arg, int npending)
4758 struct ath_softc *sc = arg;
4759 struct ifnet *ifp = sc->sc_ifp;
4763 sc->sc_txproc_cnt++;
4764 txqs = sc->sc_txq_active;
4765 sc->sc_txq_active &= ~txqs;
4769 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4772 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4773 "ath_tx_proc_q0: txqs=0x%08x", txqs);
4775 if (TXQACTIVE(txqs, 0) && ath_tx_processq(sc, &sc->sc_txq[0], 1))
4776 /* XXX why is lastrx updated in tx code? */
4777 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4778 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4779 ath_tx_processq(sc, sc->sc_cabq, 1);
4780 IF_LOCK(&ifp->if_snd);
4781 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4782 IF_UNLOCK(&ifp->if_snd);
4783 sc->sc_wd_timer = 0;
4786 ath_led_event(sc, sc->sc_txrix);
4789 sc->sc_txproc_cnt--;
4793 ath_power_restore_power_state(sc);
4800 * Deferred processing of transmit interrupt; special-cased
4801 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
4804 ath_tx_proc_q0123(void *arg, int npending)
4806 struct ath_softc *sc = arg;
4807 struct ifnet *ifp = sc->sc_ifp;
4812 sc->sc_txproc_cnt++;
4813 txqs = sc->sc_txq_active;
4814 sc->sc_txq_active &= ~txqs;
4818 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4821 ATH_KTR(sc, ATH_KTR_TXCOMP, 1,
4822 "ath_tx_proc_q0123: txqs=0x%08x", txqs);
4825 * Process each active queue.
4828 if (TXQACTIVE(txqs, 0))
4829 nacked += ath_tx_processq(sc, &sc->sc_txq[0], 1);
4830 if (TXQACTIVE(txqs, 1))
4831 nacked += ath_tx_processq(sc, &sc->sc_txq[1], 1);
4832 if (TXQACTIVE(txqs, 2))
4833 nacked += ath_tx_processq(sc, &sc->sc_txq[2], 1);
4834 if (TXQACTIVE(txqs, 3))
4835 nacked += ath_tx_processq(sc, &sc->sc_txq[3], 1);
4836 if (TXQACTIVE(txqs, sc->sc_cabq->axq_qnum))
4837 ath_tx_processq(sc, sc->sc_cabq, 1);
4839 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4841 IF_LOCK(&ifp->if_snd);
4842 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4843 IF_UNLOCK(&ifp->if_snd);
4844 sc->sc_wd_timer = 0;
4847 ath_led_event(sc, sc->sc_txrix);
4850 sc->sc_txproc_cnt--;
4854 ath_power_restore_power_state(sc);
4861 * Deferred processing of transmit interrupt.
4864 ath_tx_proc(void *arg, int npending)
4866 struct ath_softc *sc = arg;
4867 struct ifnet *ifp = sc->sc_ifp;
4872 sc->sc_txproc_cnt++;
4873 txqs = sc->sc_txq_active;
4874 sc->sc_txq_active &= ~txqs;
4878 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4881 ATH_KTR(sc, ATH_KTR_TXCOMP, 1, "ath_tx_proc: txqs=0x%08x", txqs);
4884 * Process each active queue.
4887 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
4888 if (ATH_TXQ_SETUP(sc, i) && TXQACTIVE(txqs, i))
4889 nacked += ath_tx_processq(sc, &sc->sc_txq[i], 1);
4891 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
4893 /* XXX check this inside of IF_LOCK? */
4894 IF_LOCK(&ifp->if_snd);
4895 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4896 IF_UNLOCK(&ifp->if_snd);
4897 sc->sc_wd_timer = 0;
4900 ath_led_event(sc, sc->sc_txrix);
4903 sc->sc_txproc_cnt--;
4907 ath_power_restore_power_state(sc);
4915 * Deferred processing of TXQ rescheduling.
4918 ath_txq_sched_tasklet(void *arg, int npending)
4920 struct ath_softc *sc = arg;
4923 /* XXX is skipping ok? */
4926 if (sc->sc_inreset_cnt > 0) {
4927 device_printf(sc->sc_dev,
4928 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
4933 sc->sc_txproc_cnt++;
4937 ath_power_set_power_state(sc, HAL_PM_AWAKE);
4941 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
4942 if (ATH_TXQ_SETUP(sc, i)) {
4943 ath_txq_sched(sc, &sc->sc_txq[i]);
4949 ath_power_restore_power_state(sc);
4953 sc->sc_txproc_cnt--;
4958 ath_returnbuf_tail(struct ath_softc *sc, struct ath_buf *bf)
4961 ATH_TXBUF_LOCK_ASSERT(sc);
4963 if (bf->bf_flags & ATH_BUF_MGMT)
4964 TAILQ_INSERT_TAIL(&sc->sc_txbuf_mgmt, bf, bf_list);
4966 TAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
4968 if (sc->sc_txbuf_cnt > ath_txbuf) {
4969 device_printf(sc->sc_dev,
4970 "%s: sc_txbuf_cnt > %d?\n",
4973 sc->sc_txbuf_cnt = ath_txbuf;
4979 ath_returnbuf_head(struct ath_softc *sc, struct ath_buf *bf)
4982 ATH_TXBUF_LOCK_ASSERT(sc);
4984 if (bf->bf_flags & ATH_BUF_MGMT)
4985 TAILQ_INSERT_HEAD(&sc->sc_txbuf_mgmt, bf, bf_list);
4987 TAILQ_INSERT_HEAD(&sc->sc_txbuf, bf, bf_list);
4989 if (sc->sc_txbuf_cnt > ATH_TXBUF) {
4990 device_printf(sc->sc_dev,
4991 "%s: sc_txbuf_cnt > %d?\n",
4994 sc->sc_txbuf_cnt = ATH_TXBUF;
5000 * Free the holding buffer if it exists
5003 ath_txq_freeholdingbuf(struct ath_softc *sc, struct ath_txq *txq)
5005 ATH_TXBUF_UNLOCK_ASSERT(sc);
5006 ATH_TXQ_LOCK_ASSERT(txq);
5008 if (txq->axq_holdingbf == NULL)
5011 txq->axq_holdingbf->bf_flags &= ~ATH_BUF_BUSY;
5014 ath_returnbuf_tail(sc, txq->axq_holdingbf);
5015 ATH_TXBUF_UNLOCK(sc);
5017 txq->axq_holdingbf = NULL;
5021 * Add this buffer to the holding queue, freeing the previous
5025 ath_txq_addholdingbuf(struct ath_softc *sc, struct ath_buf *bf)
5027 struct ath_txq *txq;
5029 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
5031 ATH_TXBUF_UNLOCK_ASSERT(sc);
5032 ATH_TXQ_LOCK_ASSERT(txq);
5034 /* XXX assert ATH_BUF_BUSY is set */
5036 /* XXX assert the tx queue is under the max number */
5037 if (bf->bf_state.bfs_tx_queue > HAL_NUM_TX_QUEUES) {
5038 device_printf(sc->sc_dev, "%s: bf=%p: invalid tx queue (%d)\n",
5041 bf->bf_state.bfs_tx_queue);
5042 bf->bf_flags &= ~ATH_BUF_BUSY;
5043 ath_returnbuf_tail(sc, bf);
5046 ath_txq_freeholdingbuf(sc, txq);
5047 txq->axq_holdingbf = bf;
5051 * Return a buffer to the pool and update the 'busy' flag on the
5052 * previous 'tail' entry.
5054 * This _must_ only be called when the buffer is involved in a completed
5055 * TX. The logic is that if it was part of an active TX, the previous
5056 * buffer on the list is now not involved in a halted TX DMA queue, waiting
5057 * for restart (eg for TDMA.)
5059 * The caller must free the mbuf and recycle the node reference.
5061 * XXX This method of handling busy / holding buffers is insanely stupid.
5062 * It requires bf_state.bfs_tx_queue to be correctly assigned. It would
5063 * be much nicer if buffers in the processq() methods would instead be
5064 * always completed there (pushed onto a txq or ath_bufhead) so we knew
5065 * exactly what hardware queue they came from in the first place.
5068 ath_freebuf(struct ath_softc *sc, struct ath_buf *bf)
5070 struct ath_txq *txq;
5072 txq = &sc->sc_txq[bf->bf_state.bfs_tx_queue];
5074 KASSERT((bf->bf_node == NULL), ("%s: bf->bf_node != NULL\n", __func__));
5075 KASSERT((bf->bf_m == NULL), ("%s: bf->bf_m != NULL\n", __func__));
5078 * If this buffer is busy, push it onto the holding queue.
5080 if (bf->bf_flags & ATH_BUF_BUSY) {
5082 ath_txq_addholdingbuf(sc, bf);
5083 ATH_TXQ_UNLOCK(txq);
5088 * Not a busy buffer, so free normally
5091 ath_returnbuf_tail(sc, bf);
5092 ATH_TXBUF_UNLOCK(sc);
5096 * This is currently used by ath_tx_draintxq() and
5097 * ath_tx_tid_free_pkts().
5099 * It recycles a single ath_buf.
5102 ath_tx_freebuf(struct ath_softc *sc, struct ath_buf *bf, int status)
5104 struct ieee80211_node *ni = bf->bf_node;
5105 struct mbuf *m0 = bf->bf_m;
5108 * Make sure that we only sync/unload if there's an mbuf.
5109 * If not (eg we cloned a buffer), the unload will have already
5112 if (bf->bf_m != NULL) {
5113 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
5114 BUS_DMASYNC_POSTWRITE);
5115 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
5121 /* Free the buffer, it's not needed any longer */
5122 ath_freebuf(sc, bf);
5124 /* Pass the buffer back to net80211 - completing it */
5125 ieee80211_tx_complete(ni, m0, status);
5128 static struct ath_buf *
5129 ath_tx_draintxq_get_one(struct ath_softc *sc, struct ath_txq *txq)
5133 ATH_TXQ_LOCK_ASSERT(txq);
5136 * Drain the FIFO queue first, then if it's
5137 * empty, move to the normal frame queue.
5139 bf = TAILQ_FIRST(&txq->fifo.axq_q);
5142 * Is it the last buffer in this set?
5143 * Decrement the FIFO counter.
5145 if (bf->bf_flags & ATH_BUF_FIFOEND) {
5146 if (txq->axq_fifo_depth == 0) {
5147 device_printf(sc->sc_dev,
5148 "%s: Q%d: fifo_depth=0, fifo.axq_depth=%d?\n",
5151 txq->fifo.axq_depth);
5153 txq->axq_fifo_depth--;
5155 ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list);
5162 if (txq->axq_fifo_depth != 0 || txq->fifo.axq_depth != 0) {
5163 device_printf(sc->sc_dev,
5164 "%s: Q%d: fifo_depth=%d, fifo.axq_depth=%d\n",
5167 txq->axq_fifo_depth,
5168 txq->fifo.axq_depth);
5172 * Now drain the pending queue.
5174 bf = TAILQ_FIRST(&txq->axq_q);
5176 txq->axq_link = NULL;
5179 ATH_TXQ_REMOVE(txq, bf, bf_list);
5184 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
5187 struct ath_hal *ah = sc->sc_ah;
5193 * NB: this assumes output has been stopped and
5194 * we do not need to block ath_tx_proc
5196 for (ix = 0;; ix++) {
5198 bf = ath_tx_draintxq_get_one(sc, txq);
5200 ATH_TXQ_UNLOCK(txq);
5203 if (bf->bf_state.bfs_aggr)
5204 txq->axq_aggr_depth--;
5206 if (sc->sc_debug & ATH_DEBUG_RESET) {
5207 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
5211 * EDMA operation has a TX completion FIFO
5212 * separate from the TX descriptor, so this
5213 * method of checking the "completion" status
5216 if (! sc->sc_isedma) {
5217 status = (ath_hal_txprocdesc(ah,
5219 &bf->bf_status.ds_txstat) == HAL_OK);
5221 ath_printtxbuf(sc, bf, txq->axq_qnum, ix, status);
5222 ieee80211_dump_pkt(ic, mtod(bf->bf_m, const uint8_t *),
5223 bf->bf_m->m_len, 0, -1);
5225 #endif /* ATH_DEBUG */
5227 * Since we're now doing magic in the completion
5228 * functions, we -must- call it for aggregation
5229 * destinations or BAW tracking will get upset.
5232 * Clear ATH_BUF_BUSY; the completion handler
5233 * will free the buffer.
5235 ATH_TXQ_UNLOCK(txq);
5236 bf->bf_flags &= ~ATH_BUF_BUSY;
5238 bf->bf_comp(sc, bf, 1);
5240 ath_tx_default_comp(sc, bf, 1);
5244 * Free the holding buffer if it exists
5247 ath_txq_freeholdingbuf(sc, txq);
5248 ATH_TXQ_UNLOCK(txq);
5251 * Drain software queued frames which are on
5254 ath_tx_txq_drain(sc, txq);
5258 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
5260 struct ath_hal *ah = sc->sc_ah;
5262 ATH_TXQ_LOCK_ASSERT(txq);
5264 DPRINTF(sc, ATH_DEBUG_RESET,
5265 "%s: tx queue [%u] %p, active=%d, hwpending=%d, flags 0x%08x, "
5266 "link %p, holdingbf=%p\n",
5269 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
5270 (int) (!! ath_hal_txqenabled(ah, txq->axq_qnum)),
5271 (int) ath_hal_numtxpending(ah, txq->axq_qnum),
5274 txq->axq_holdingbf);
5276 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
5277 /* We've stopped TX DMA, so mark this as stopped. */
5278 txq->axq_flags &= ~ATH_TXQ_PUTRUNNING;
5281 if ((sc->sc_debug & ATH_DEBUG_RESET)
5282 && (txq->axq_holdingbf != NULL)) {
5283 ath_printtxbuf(sc, txq->axq_holdingbf, txq->axq_qnum, 0, 0);
5289 ath_stoptxdma(struct ath_softc *sc)
5291 struct ath_hal *ah = sc->sc_ah;
5294 /* XXX return value */
5298 if (!sc->sc_invalid) {
5299 /* don't touch the hardware if marked invalid */
5300 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
5301 __func__, sc->sc_bhalq,
5302 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq),
5305 /* stop the beacon queue */
5306 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
5308 /* Stop the data queues */
5309 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
5310 if (ATH_TXQ_SETUP(sc, i)) {
5311 ATH_TXQ_LOCK(&sc->sc_txq[i]);
5312 ath_tx_stopdma(sc, &sc->sc_txq[i]);
5313 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
5323 ath_tx_dump(struct ath_softc *sc, struct ath_txq *txq)
5325 struct ath_hal *ah = sc->sc_ah;
5329 if (! (sc->sc_debug & ATH_DEBUG_RESET))
5332 device_printf(sc->sc_dev, "%s: Q%d: begin\n",
5333 __func__, txq->axq_qnum);
5334 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) {
5335 ath_printtxbuf(sc, bf, txq->axq_qnum, i,
5336 ath_hal_txprocdesc(ah, bf->bf_lastds,
5337 &bf->bf_status.ds_txstat) == HAL_OK);
5340 device_printf(sc->sc_dev, "%s: Q%d: end\n",
5341 __func__, txq->axq_qnum);
5343 #endif /* ATH_DEBUG */
5346 * Drain the transmit queues and reclaim resources.
5349 ath_legacy_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
5351 struct ath_hal *ah = sc->sc_ah;
5352 struct ifnet *ifp = sc->sc_ifp;
5354 struct ath_buf *bf_last;
5356 (void) ath_stoptxdma(sc);
5359 * Dump the queue contents
5361 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
5363 * XXX TODO: should we just handle the completed TX frames
5364 * here, whether or not the reset is a full one or not?
5366 if (ATH_TXQ_SETUP(sc, i)) {
5368 if (sc->sc_debug & ATH_DEBUG_RESET)
5369 ath_tx_dump(sc, &sc->sc_txq[i]);
5370 #endif /* ATH_DEBUG */
5371 if (reset_type == ATH_RESET_NOLOSS) {
5372 ath_tx_processq(sc, &sc->sc_txq[i], 0);
5373 ATH_TXQ_LOCK(&sc->sc_txq[i]);
5375 * Free the holding buffer; DMA is now
5378 ath_txq_freeholdingbuf(sc, &sc->sc_txq[i]);
5380 * Setup the link pointer to be the
5381 * _last_ buffer/descriptor in the list.
5382 * If there's nothing in the list, set it
5385 bf_last = ATH_TXQ_LAST(&sc->sc_txq[i],
5387 if (bf_last != NULL) {
5388 ath_hal_gettxdesclinkptr(ah,
5390 &sc->sc_txq[i].axq_link);
5392 sc->sc_txq[i].axq_link = NULL;
5394 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
5396 ath_tx_draintxq(sc, &sc->sc_txq[i]);
5400 if (sc->sc_debug & ATH_DEBUG_RESET) {
5401 struct ath_buf *bf = TAILQ_FIRST(&sc->sc_bbuf);
5402 if (bf != NULL && bf->bf_m != NULL) {
5403 ath_printtxbuf(sc, bf, sc->sc_bhalq, 0,
5404 ath_hal_txprocdesc(ah, bf->bf_lastds,
5405 &bf->bf_status.ds_txstat) == HAL_OK);
5406 ieee80211_dump_pkt(ifp->if_l2com,
5407 mtod(bf->bf_m, const uint8_t *), bf->bf_m->m_len,
5411 #endif /* ATH_DEBUG */
5412 IF_LOCK(&ifp->if_snd);
5413 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5414 IF_UNLOCK(&ifp->if_snd);
5415 sc->sc_wd_timer = 0;
5419 * Update internal state after a channel change.
5422 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
5424 enum ieee80211_phymode mode;
5427 * Change channels and update the h/w rate map
5428 * if we're switching; e.g. 11a to 11b/g.
5430 mode = ieee80211_chan2mode(chan);
5431 if (mode != sc->sc_curmode)
5432 ath_setcurmode(sc, mode);
5433 sc->sc_curchan = chan;
5437 * Set/change channels. If the channel is really being changed,
5438 * it's done by resetting the chip. To accomplish this we must
5439 * first cleanup any pending DMA, then restart stuff after a la
5443 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
5445 struct ifnet *ifp = sc->sc_ifp;
5446 struct ieee80211com *ic = ifp->if_l2com;
5447 struct ath_hal *ah = sc->sc_ah;
5450 /* Treat this as an interface reset */
5451 ATH_PCU_UNLOCK_ASSERT(sc);
5452 ATH_UNLOCK_ASSERT(sc);
5454 /* (Try to) stop TX/RX from occuring */
5455 taskqueue_block(sc->sc_tq);
5459 /* Disable interrupts */
5460 ath_hal_intrset(ah, 0);
5462 /* Stop new RX/TX/interrupt completion */
5463 if (ath_reset_grablock(sc, 1) == 0) {
5464 device_printf(sc->sc_dev, "%s: concurrent reset! Danger!\n",
5468 /* Stop pending RX/TX completion */
5469 ath_txrx_stop_locked(sc);
5473 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz, flags 0x%x)\n",
5474 __func__, ieee80211_chan2ieee(ic, chan),
5475 chan->ic_freq, chan->ic_flags);
5476 if (chan != sc->sc_curchan) {
5479 * To switch channels clear any pending DMA operations;
5480 * wait long enough for the RX fifo to drain, reset the
5481 * hardware at the new frequency, and then re-enable
5482 * the relevant bits of the h/w.
5485 ath_hal_intrset(ah, 0); /* disable interrupts */
5487 ath_stoprecv(sc, 1); /* turn off frame recv */
5489 * First, handle completed TX/RX frames.
5492 ath_draintxq(sc, ATH_RESET_NOLOSS);
5494 * Next, flush the non-scheduled frames.
5496 ath_draintxq(sc, ATH_RESET_FULL); /* clear pending tx frames */
5498 ath_update_chainmasks(sc, chan);
5499 ath_hal_setchainmasks(sc->sc_ah, sc->sc_cur_txchainmask,
5500 sc->sc_cur_rxchainmask);
5501 if (!ath_hal_reset(ah, sc->sc_opmode, chan, AH_TRUE, &status)) {
5502 if_printf(ifp, "%s: unable to reset "
5503 "channel %u (%u MHz, flags 0x%x), hal status %u\n",
5504 __func__, ieee80211_chan2ieee(ic, chan),
5505 chan->ic_freq, chan->ic_flags, status);
5509 sc->sc_diversity = ath_hal_getdiversity(ah);
5512 sc->sc_rx_stopped = 1;
5513 sc->sc_rx_resetted = 1;
5516 /* Let DFS at it in case it's a DFS channel */
5517 ath_dfs_radar_enable(sc, chan);
5519 /* Let spectral at in case spectral is enabled */
5520 ath_spectral_enable(sc, chan);
5523 * Let bluetooth coexistence at in case it's needed for this
5526 ath_btcoex_enable(sc, ic->ic_curchan);
5529 * If we're doing TDMA, enforce the TXOP limitation for chips
5532 if (sc->sc_hasenforcetxop && sc->sc_tdma)
5533 ath_hal_setenforcetxop(sc->sc_ah, 1);
5535 ath_hal_setenforcetxop(sc->sc_ah, 0);
5538 * Re-enable rx framework.
5540 if (ath_startrecv(sc) != 0) {
5541 if_printf(ifp, "%s: unable to restart recv logic\n",
5548 * Change channels and update the h/w rate map
5549 * if we're switching; e.g. 11a to 11b/g.
5551 ath_chan_change(sc, chan);
5554 * Reset clears the beacon timers; reset them
5557 if (sc->sc_beacons) { /* restart beacons */
5558 #ifdef IEEE80211_SUPPORT_TDMA
5560 ath_tdma_config(sc, NULL);
5563 ath_beacon_config(sc, NULL);
5567 * Re-enable interrupts.
5570 ath_hal_intrset(ah, sc->sc_imask);
5576 sc->sc_inreset_cnt--;
5577 /* XXX only do this if sc_inreset_cnt == 0? */
5578 ath_hal_intrset(ah, sc->sc_imask);
5581 IF_LOCK(&ifp->if_snd);
5582 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5583 IF_UNLOCK(&ifp->if_snd);
5585 /* XXX ath_start? */
5591 * Periodically recalibrate the PHY to account
5592 * for temperature/environment changes.
5595 ath_calibrate(void *arg)
5597 struct ath_softc *sc = arg;
5598 struct ath_hal *ah = sc->sc_ah;
5599 struct ifnet *ifp = sc->sc_ifp;
5600 struct ieee80211com *ic = ifp->if_l2com;
5601 HAL_BOOL longCal, isCalDone = AH_TRUE;
5602 HAL_BOOL aniCal, shortCal = AH_FALSE;
5605 ATH_LOCK_ASSERT(sc);
5608 * Force the hardware awake for ANI work.
5610 ath_power_set_power_state(sc, HAL_PM_AWAKE);
5612 /* Skip trying to do this if we're in reset */
5613 if (sc->sc_inreset_cnt)
5616 if (ic->ic_flags & IEEE80211_F_SCAN) /* defer, off channel */
5618 longCal = (ticks - sc->sc_lastlongcal >= ath_longcalinterval*hz);
5619 aniCal = (ticks - sc->sc_lastani >= ath_anicalinterval*hz/1000);
5620 if (sc->sc_doresetcal)
5621 shortCal = (ticks - sc->sc_lastshortcal >= ath_shortcalinterval*hz/1000);
5623 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: shortCal=%d; longCal=%d; aniCal=%d\n", __func__, shortCal, longCal, aniCal);
5625 sc->sc_stats.ast_ani_cal++;
5626 sc->sc_lastani = ticks;
5627 ath_hal_ani_poll(ah, sc->sc_curchan);
5631 sc->sc_stats.ast_per_cal++;
5632 sc->sc_lastlongcal = ticks;
5633 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
5635 * Rfgain is out of bounds, reset the chip
5636 * to load new gain values.
5638 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
5639 "%s: rfgain change\n", __func__);
5640 sc->sc_stats.ast_per_rfgain++;
5641 sc->sc_resetcal = 0;
5642 sc->sc_doresetcal = AH_TRUE;
5643 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
5644 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
5645 ath_power_restore_power_state(sc);
5649 * If this long cal is after an idle period, then
5650 * reset the data collection state so we start fresh.
5652 if (sc->sc_resetcal) {
5653 (void) ath_hal_calreset(ah, sc->sc_curchan);
5654 sc->sc_lastcalreset = ticks;
5655 sc->sc_lastshortcal = ticks;
5656 sc->sc_resetcal = 0;
5657 sc->sc_doresetcal = AH_TRUE;
5661 /* Only call if we're doing a short/long cal, not for ANI calibration */
5662 if (shortCal || longCal) {
5663 isCalDone = AH_FALSE;
5664 if (ath_hal_calibrateN(ah, sc->sc_curchan, longCal, &isCalDone)) {
5667 * Calibrate noise floor data again in case of change.
5669 ath_hal_process_noisefloor(ah);
5672 DPRINTF(sc, ATH_DEBUG_ANY,
5673 "%s: calibration of channel %u failed\n",
5674 __func__, sc->sc_curchan->ic_freq);
5675 sc->sc_stats.ast_per_calfail++;
5678 sc->sc_lastshortcal = ticks;
5683 * Use a shorter interval to potentially collect multiple
5684 * data samples required to complete calibration. Once
5685 * we're told the work is done we drop back to a longer
5686 * interval between requests. We're more aggressive doing
5687 * work when operating as an AP to improve operation right
5690 sc->sc_lastshortcal = ticks;
5691 nextcal = ath_shortcalinterval*hz/1000;
5692 if (sc->sc_opmode != HAL_M_HOSTAP)
5694 sc->sc_doresetcal = AH_TRUE;
5696 /* nextcal should be the shortest time for next event */
5697 nextcal = ath_longcalinterval*hz;
5698 if (sc->sc_lastcalreset == 0)
5699 sc->sc_lastcalreset = sc->sc_lastlongcal;
5700 else if (ticks - sc->sc_lastcalreset >= ath_resetcalinterval*hz)
5701 sc->sc_resetcal = 1; /* setup reset next trip */
5702 sc->sc_doresetcal = AH_FALSE;
5704 /* ANI calibration may occur more often than short/long/resetcal */
5705 if (ath_anicalinterval > 0)
5706 nextcal = MIN(nextcal, ath_anicalinterval*hz/1000);
5709 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: next +%u (%sisCalDone)\n",
5710 __func__, nextcal, isCalDone ? "" : "!");
5711 callout_reset(&sc->sc_cal_ch, nextcal, ath_calibrate, sc);
5713 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: calibration disabled\n",
5715 /* NB: don't rearm timer */
5718 * Restore power state now that we're done.
5720 ath_power_restore_power_state(sc);
5724 ath_scan_start(struct ieee80211com *ic)
5726 struct ifnet *ifp = ic->ic_ifp;
5727 struct ath_softc *sc = ifp->if_softc;
5728 struct ath_hal *ah = sc->sc_ah;
5731 /* XXX calibration timer? */
5734 sc->sc_scanning = 1;
5735 sc->sc_syncbeacon = 0;
5736 rfilt = ath_calcrxfilter(sc);
5740 ath_hal_setrxfilter(ah, rfilt);
5741 ath_hal_setassocid(ah, ifp->if_broadcastaddr, 0);
5744 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0\n",
5745 __func__, rfilt, ether_sprintf(ifp->if_broadcastaddr));
5749 ath_scan_end(struct ieee80211com *ic)
5751 struct ifnet *ifp = ic->ic_ifp;
5752 struct ath_softc *sc = ifp->if_softc;
5753 struct ath_hal *ah = sc->sc_ah;
5757 sc->sc_scanning = 0;
5758 rfilt = ath_calcrxfilter(sc);
5762 ath_hal_setrxfilter(ah, rfilt);
5763 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5765 ath_hal_process_noisefloor(ah);
5768 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5769 __func__, rfilt, ether_sprintf(sc->sc_curbssid),
5773 #ifdef ATH_ENABLE_11N
5775 * For now, just do a channel change.
5777 * Later, we'll go through the hard slog of suspending tx/rx, changing rate
5778 * control state and resetting the hardware without dropping frames out
5781 * The unfortunate trouble here is making absolutely sure that the
5782 * channel width change has propagated enough so the hardware
5783 * absolutely isn't handed bogus frames for it's current operating
5784 * mode. (Eg, 40MHz frames in 20MHz mode.) Since TX and RX can and
5785 * does occur in parallel, we need to make certain we've blocked
5786 * any further ongoing TX (and RX, that can cause raw TX)
5787 * before we do this.
5790 ath_update_chw(struct ieee80211com *ic)
5792 struct ifnet *ifp = ic->ic_ifp;
5793 struct ath_softc *sc = ifp->if_softc;
5795 DPRINTF(sc, ATH_DEBUG_STATE, "%s: called\n", __func__);
5796 ath_set_channel(ic);
5798 #endif /* ATH_ENABLE_11N */
5801 ath_set_channel(struct ieee80211com *ic)
5803 struct ifnet *ifp = ic->ic_ifp;
5804 struct ath_softc *sc = ifp->if_softc;
5807 ath_power_set_power_state(sc, HAL_PM_AWAKE);
5810 (void) ath_chan_set(sc, ic->ic_curchan);
5812 * If we are returning to our bss channel then mark state
5813 * so the next recv'd beacon's tsf will be used to sync the
5814 * beacon timers. Note that since we only hear beacons in
5815 * sta/ibss mode this has no effect in other operating modes.
5818 if (!sc->sc_scanning && ic->ic_curchan == ic->ic_bsschan)
5819 sc->sc_syncbeacon = 1;
5820 ath_power_restore_power_state(sc);
5825 * Walk the vap list and check if there any vap's in RUN state.
5828 ath_isanyrunningvaps(struct ieee80211vap *this)
5830 struct ieee80211com *ic = this->iv_ic;
5831 struct ieee80211vap *vap;
5833 IEEE80211_LOCK_ASSERT(ic);
5835 TAILQ_FOREACH(vap, &ic->ic_vaps, iv_next) {
5836 if (vap != this && vap->iv_state >= IEEE80211_S_RUN)
5843 ath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
5845 struct ieee80211com *ic = vap->iv_ic;
5846 struct ath_softc *sc = ic->ic_ifp->if_softc;
5847 struct ath_vap *avp = ATH_VAP(vap);
5848 struct ath_hal *ah = sc->sc_ah;
5849 struct ieee80211_node *ni = NULL;
5850 int i, error, stamode;
5852 int csa_run_transition = 0;
5853 enum ieee80211_state ostate = vap->iv_state;
5855 static const HAL_LED_STATE leds[] = {
5856 HAL_LED_INIT, /* IEEE80211_S_INIT */
5857 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
5858 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
5859 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
5860 HAL_LED_RUN, /* IEEE80211_S_CAC */
5861 HAL_LED_RUN, /* IEEE80211_S_RUN */
5862 HAL_LED_RUN, /* IEEE80211_S_CSA */
5863 HAL_LED_RUN, /* IEEE80211_S_SLEEP */
5866 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
5867 ieee80211_state_name[ostate],
5868 ieee80211_state_name[nstate]);
5871 * net80211 _should_ have the comlock asserted at this point.
5872 * There are some comments around the calls to vap->iv_newstate
5873 * which indicate that it (newstate) may end up dropping the
5874 * lock. This and the subsequent lock assert check after newstate
5875 * are an attempt to catch these and figure out how/why.
5877 IEEE80211_LOCK_ASSERT(ic);
5879 /* Before we touch the hardware - wake it up */
5882 * If the NIC is in anything other than SLEEP state,
5883 * we need to ensure that self-generated frames are
5884 * set for PWRMGT=0. Otherwise we may end up with
5885 * strange situations.
5887 * XXX TODO: is this actually the case? :-)
5889 if (nstate != IEEE80211_S_SLEEP)
5890 ath_power_setselfgen(sc, HAL_PM_AWAKE);
5893 * Now, wake the thing up.
5895 ath_power_set_power_state(sc, HAL_PM_AWAKE);
5898 * And stop the calibration callout whilst we have
5901 callout_stop(&sc->sc_cal_ch);
5904 if (ostate == IEEE80211_S_CSA && nstate == IEEE80211_S_RUN)
5905 csa_run_transition = 1;
5907 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
5909 if (nstate == IEEE80211_S_SCAN) {
5911 * Scanning: turn off beacon miss and don't beacon.
5912 * Mark beacon state so when we reach RUN state we'll
5913 * [re]setup beacons. Unblock the task q thread so
5914 * deferred interrupt processing is done.
5917 /* Ensure we stay awake during scan */
5919 ath_power_setselfgen(sc, HAL_PM_AWAKE);
5920 ath_power_setpower(sc, HAL_PM_AWAKE);
5924 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
5925 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
5927 taskqueue_unblock(sc->sc_tq);
5930 ni = ieee80211_ref_node(vap->iv_bss);
5931 rfilt = ath_calcrxfilter(sc);
5932 stamode = (vap->iv_opmode == IEEE80211_M_STA ||
5933 vap->iv_opmode == IEEE80211_M_AHDEMO ||
5934 vap->iv_opmode == IEEE80211_M_IBSS);
5937 * XXX Dont need to do this (and others) if we've transitioned
5940 if (stamode && nstate == IEEE80211_S_RUN) {
5941 sc->sc_curaid = ni->ni_associd;
5942 IEEE80211_ADDR_COPY(sc->sc_curbssid, ni->ni_bssid);
5943 ath_hal_setassocid(ah, sc->sc_curbssid, sc->sc_curaid);
5945 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s aid 0x%x\n",
5946 __func__, rfilt, ether_sprintf(sc->sc_curbssid), sc->sc_curaid);
5947 ath_hal_setrxfilter(ah, rfilt);
5949 /* XXX is this to restore keycache on resume? */
5950 if (vap->iv_opmode != IEEE80211_M_STA &&
5951 (vap->iv_flags & IEEE80211_F_PRIVACY)) {
5952 for (i = 0; i < IEEE80211_WEP_NKID; i++)
5953 if (ath_hal_keyisvalid(ah, i))
5954 ath_hal_keysetmac(ah, i, ni->ni_bssid);
5958 * Invoke the parent method to do net80211 work.
5960 error = avp->av_newstate(vap, nstate, arg);
5965 * See above: ensure av_newstate() doesn't drop the lock
5968 IEEE80211_LOCK_ASSERT(ic);
5970 if (nstate == IEEE80211_S_RUN) {
5971 /* NB: collect bss node again, it may have changed */
5972 ieee80211_free_node(ni);
5973 ni = ieee80211_ref_node(vap->iv_bss);
5975 DPRINTF(sc, ATH_DEBUG_STATE,
5976 "%s(RUN): iv_flags 0x%08x bintvl %d bssid %s "
5977 "capinfo 0x%04x chan %d\n", __func__,
5978 vap->iv_flags, ni->ni_intval, ether_sprintf(ni->ni_bssid),
5979 ni->ni_capinfo, ieee80211_chan2ieee(ic, ic->ic_curchan));
5981 switch (vap->iv_opmode) {
5982 #ifdef IEEE80211_SUPPORT_TDMA
5983 case IEEE80211_M_AHDEMO:
5984 if ((vap->iv_caps & IEEE80211_C_TDMA) == 0)
5988 case IEEE80211_M_HOSTAP:
5989 case IEEE80211_M_IBSS:
5990 case IEEE80211_M_MBSS:
5992 * Allocate and setup the beacon frame.
5994 * Stop any previous beacon DMA. This may be
5995 * necessary, for example, when an ibss merge
5996 * causes reconfiguration; there will be a state
5997 * transition from RUN->RUN that means we may
5998 * be called with beacon transmission active.
6000 ath_hal_stoptxdma(ah, sc->sc_bhalq);
6002 error = ath_beacon_alloc(sc, ni);
6006 * If joining an adhoc network defer beacon timer
6007 * configuration to the next beacon frame so we
6008 * have a current TSF to use. Otherwise we're
6009 * starting an ibss/bss so there's no need to delay;
6010 * if this is the first vap moving to RUN state, then
6011 * beacon state needs to be [re]configured.
6013 if (vap->iv_opmode == IEEE80211_M_IBSS &&
6014 ni->ni_tstamp.tsf != 0) {
6015 sc->sc_syncbeacon = 1;
6016 } else if (!sc->sc_beacons) {
6017 #ifdef IEEE80211_SUPPORT_TDMA
6018 if (vap->iv_caps & IEEE80211_C_TDMA)
6019 ath_tdma_config(sc, vap);
6022 ath_beacon_config(sc, vap);
6026 case IEEE80211_M_STA:
6028 * Defer beacon timer configuration to the next
6029 * beacon frame so we have a current TSF to use
6030 * (any TSF collected when scanning is likely old).
6031 * However if it's due to a CSA -> RUN transition,
6032 * force a beacon update so we pick up a lack of
6033 * beacons from an AP in CAC and thus force a
6036 * And, there's also corner cases here where
6037 * after a scan, the AP may have disappeared.
6038 * In that case, we may not receive an actual
6039 * beacon to update the beacon timer and thus we
6040 * won't get notified of the missing beacons.
6042 if (ostate != IEEE80211_S_RUN &&
6043 ostate != IEEE80211_S_SLEEP) {
6044 DPRINTF(sc, ATH_DEBUG_BEACON,
6045 "%s: STA; syncbeacon=1\n", __func__);
6046 sc->sc_syncbeacon = 1;
6048 if (csa_run_transition)
6049 ath_beacon_config(sc, vap);
6054 * Reconfigure beacons during reset; as otherwise
6055 * we won't get the beacon timers reprogrammed
6056 * after a reset and thus we won't pick up a
6057 * beacon miss interrupt.
6059 * Hopefully we'll see a beacon before the BMISS
6060 * timer fires (too often), leading to a STA
6066 case IEEE80211_M_MONITOR:
6068 * Monitor mode vaps have only INIT->RUN and RUN->RUN
6069 * transitions so we must re-enable interrupts here to
6070 * handle the case of a single monitor mode vap.
6072 ath_hal_intrset(ah, sc->sc_imask);
6074 case IEEE80211_M_WDS:
6080 * Let the hal process statistics collected during a
6081 * scan so it can provide calibrated noise floor data.
6083 ath_hal_process_noisefloor(ah);
6085 * Reset rssi stats; maybe not the best place...
6087 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
6088 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
6089 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
6092 * Force awake for RUN mode.
6095 ath_power_setselfgen(sc, HAL_PM_AWAKE);
6096 ath_power_setpower(sc, HAL_PM_AWAKE);
6099 * Finally, start any timers and the task q thread
6100 * (in case we didn't go through SCAN state).
6102 if (ath_longcalinterval != 0) {
6103 /* start periodic recalibration timer */
6104 callout_reset(&sc->sc_cal_ch, 1, ath_calibrate, sc);
6106 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
6107 "%s: calibration disabled\n", __func__);
6111 taskqueue_unblock(sc->sc_tq);
6112 } else if (nstate == IEEE80211_S_INIT) {
6114 * If there are no vaps left in RUN state then
6115 * shutdown host/driver operation:
6116 * o disable interrupts
6117 * o disable the task queue thread
6118 * o mark beacon processing as stopped
6120 if (!ath_isanyrunningvaps(vap)) {
6121 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
6122 /* disable interrupts */
6123 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
6124 taskqueue_block(sc->sc_tq);
6127 #ifdef IEEE80211_SUPPORT_TDMA
6128 ath_hal_setcca(ah, AH_TRUE);
6130 } else if (nstate == IEEE80211_S_SLEEP) {
6131 /* We're going to sleep, so transition appropriately */
6132 /* For now, only do this if we're a single STA vap */
6133 if (sc->sc_nvaps == 1 &&
6134 vap->iv_opmode == IEEE80211_M_STA) {
6135 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: syncbeacon=%d\n", __func__, sc->sc_syncbeacon);
6138 * Always at least set the self-generated
6139 * frame config to set PWRMGT=1.
6141 ath_power_setselfgen(sc, HAL_PM_NETWORK_SLEEP);
6144 * If we're not syncing beacons, transition
6147 * We stay awake if syncbeacon > 0 in case
6148 * we need to listen for some beacons otherwise
6149 * our beacon timer config may be wrong.
6151 if (sc->sc_syncbeacon == 0) {
6152 ath_power_setpower(sc, HAL_PM_NETWORK_SLEEP);
6158 ieee80211_free_node(ni);
6161 * Restore the power state - either to what it was, or
6162 * to network_sleep if it's alright.
6165 ath_power_restore_power_state(sc);
6171 * Allocate a key cache slot to the station so we can
6172 * setup a mapping from key index to node. The key cache
6173 * slot is needed for managing antenna state and for
6174 * compression when stations do not use crypto. We do
6175 * it uniliaterally here; if crypto is employed this slot
6176 * will be reassigned.
6179 ath_setup_stationkey(struct ieee80211_node *ni)
6181 struct ieee80211vap *vap = ni->ni_vap;
6182 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
6183 ieee80211_keyix keyix, rxkeyix;
6185 /* XXX should take a locked ref to vap->iv_bss */
6186 if (!ath_key_alloc(vap, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
6188 * Key cache is full; we'll fall back to doing
6189 * the more expensive lookup in software. Note
6190 * this also means no h/w compression.
6192 /* XXX msg+statistic */
6195 ni->ni_ucastkey.wk_keyix = keyix;
6196 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
6197 /* NB: must mark device key to get called back on delete */
6198 ni->ni_ucastkey.wk_flags |= IEEE80211_KEY_DEVKEY;
6199 IEEE80211_ADDR_COPY(ni->ni_ucastkey.wk_macaddr, ni->ni_macaddr);
6200 /* NB: this will create a pass-thru key entry */
6201 ath_keyset(sc, vap, &ni->ni_ucastkey, vap->iv_bss);
6206 * Setup driver-specific state for a newly associated node.
6207 * Note that we're called also on a re-associate, the isnew
6208 * param tells us if this is the first time or not.
6211 ath_newassoc(struct ieee80211_node *ni, int isnew)
6213 struct ath_node *an = ATH_NODE(ni);
6214 struct ieee80211vap *vap = ni->ni_vap;
6215 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc;
6216 const struct ieee80211_txparam *tp = ni->ni_txparms;
6218 an->an_mcastrix = ath_tx_findrix(sc, tp->mcastrate);
6219 an->an_mgmtrix = ath_tx_findrix(sc, tp->mgmtrate);
6221 DPRINTF(sc, ATH_DEBUG_NODE, "%s: %6D: reassoc; isnew=%d, is_powersave=%d\n",
6226 an->an_is_powersave);
6229 ath_rate_newassoc(sc, an, isnew);
6230 ATH_NODE_UNLOCK(an);
6233 (vap->iv_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey &&
6234 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
6235 ath_setup_stationkey(ni);
6238 * If we're reassociating, make sure that any paused queues
6241 * Now, we may hvae frames in the hardware queue for this node.
6242 * So if we are reassociating and there are frames in the queue,
6243 * we need to go through the cleanup path to ensure that they're
6244 * marked as non-aggregate.
6247 DPRINTF(sc, ATH_DEBUG_NODE,
6248 "%s: %6D: reassoc; is_powersave=%d\n",
6252 an->an_is_powersave);
6254 /* XXX for now, we can't hold the lock across assoc */
6255 ath_tx_node_reassoc(sc, an);
6257 /* XXX for now, we can't hold the lock across wakeup */
6258 if (an->an_is_powersave)
6259 ath_tx_node_wakeup(sc, an);
6264 ath_setregdomain(struct ieee80211com *ic, struct ieee80211_regdomain *reg,
6265 int nchans, struct ieee80211_channel chans[])
6267 struct ath_softc *sc = ic->ic_ifp->if_softc;
6268 struct ath_hal *ah = sc->sc_ah;
6271 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
6272 "%s: rd %u cc %u location %c%s\n",
6273 __func__, reg->regdomain, reg->country, reg->location,
6274 reg->ecm ? " ecm" : "");
6276 status = ath_hal_set_channels(ah, chans, nchans,
6277 reg->country, reg->regdomain);
6278 if (status != HAL_OK) {
6279 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: failed, status %u\n",
6281 return EINVAL; /* XXX */
6288 ath_getradiocaps(struct ieee80211com *ic,
6289 int maxchans, int *nchans, struct ieee80211_channel chans[])
6291 struct ath_softc *sc = ic->ic_ifp->if_softc;
6292 struct ath_hal *ah = sc->sc_ah;
6294 DPRINTF(sc, ATH_DEBUG_REGDOMAIN, "%s: use rd %u cc %d\n",
6295 __func__, SKU_DEBUG, CTRY_DEFAULT);
6297 /* XXX check return */
6298 (void) ath_hal_getchannels(ah, chans, maxchans, nchans,
6299 HAL_MODE_ALL, CTRY_DEFAULT, SKU_DEBUG, AH_TRUE);
6304 ath_getchannels(struct ath_softc *sc)
6306 struct ifnet *ifp = sc->sc_ifp;
6307 struct ieee80211com *ic = ifp->if_l2com;
6308 struct ath_hal *ah = sc->sc_ah;
6312 * Collect channel set based on EEPROM contents.
6314 status = ath_hal_init_channels(ah, ic->ic_channels, IEEE80211_CHAN_MAX,
6315 &ic->ic_nchans, HAL_MODE_ALL, CTRY_DEFAULT, SKU_NONE, AH_TRUE);
6316 if (status != HAL_OK) {
6317 if_printf(ifp, "%s: unable to collect channel list from hal, "
6318 "status %d\n", __func__, status);
6321 (void) ath_hal_getregdomain(ah, &sc->sc_eerd);
6322 ath_hal_getcountrycode(ah, &sc->sc_eecc); /* NB: cannot fail */
6323 /* XXX map Atheros sku's to net80211 SKU's */
6324 /* XXX net80211 types too small */
6325 ic->ic_regdomain.regdomain = (uint16_t) sc->sc_eerd;
6326 ic->ic_regdomain.country = (uint16_t) sc->sc_eecc;
6327 ic->ic_regdomain.isocc[0] = ' '; /* XXX don't know */
6328 ic->ic_regdomain.isocc[1] = ' ';
6330 ic->ic_regdomain.ecm = 1;
6331 ic->ic_regdomain.location = 'I';
6333 DPRINTF(sc, ATH_DEBUG_REGDOMAIN,
6334 "%s: eeprom rd %u cc %u (mapped rd %u cc %u) location %c%s\n",
6335 __func__, sc->sc_eerd, sc->sc_eecc,
6336 ic->ic_regdomain.regdomain, ic->ic_regdomain.country,
6337 ic->ic_regdomain.location, ic->ic_regdomain.ecm ? " ecm" : "");
6342 ath_rate_setup(struct ath_softc *sc, u_int mode)
6344 struct ath_hal *ah = sc->sc_ah;
6345 const HAL_RATE_TABLE *rt;
6348 case IEEE80211_MODE_11A:
6349 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
6351 case IEEE80211_MODE_HALF:
6352 rt = ath_hal_getratetable(ah, HAL_MODE_11A_HALF_RATE);
6354 case IEEE80211_MODE_QUARTER:
6355 rt = ath_hal_getratetable(ah, HAL_MODE_11A_QUARTER_RATE);
6357 case IEEE80211_MODE_11B:
6358 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
6360 case IEEE80211_MODE_11G:
6361 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
6363 case IEEE80211_MODE_TURBO_A:
6364 rt = ath_hal_getratetable(ah, HAL_MODE_108A);
6366 case IEEE80211_MODE_TURBO_G:
6367 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
6369 case IEEE80211_MODE_STURBO_A:
6370 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
6372 case IEEE80211_MODE_11NA:
6373 rt = ath_hal_getratetable(ah, HAL_MODE_11NA_HT20);
6375 case IEEE80211_MODE_11NG:
6376 rt = ath_hal_getratetable(ah, HAL_MODE_11NG_HT20);
6379 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
6383 sc->sc_rates[mode] = rt;
6384 return (rt != NULL);
6388 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
6390 #define N(a) (sizeof(a)/sizeof(a[0]))
6391 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
6392 static const struct {
6393 u_int rate; /* tx/rx 802.11 rate */
6394 u_int16_t timeOn; /* LED on time (ms) */
6395 u_int16_t timeOff; /* LED off time (ms) */
6411 /* XXX half/quarter rates */
6413 const HAL_RATE_TABLE *rt;
6416 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
6417 rt = sc->sc_rates[mode];
6418 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
6419 for (i = 0; i < rt->rateCount; i++) {
6420 uint8_t ieeerate = rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
6421 if (rt->info[i].phy != IEEE80211_T_HT)
6422 sc->sc_rixmap[ieeerate] = i;
6424 sc->sc_rixmap[ieeerate | IEEE80211_RATE_MCS] = i;
6426 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
6427 for (i = 0; i < N(sc->sc_hwmap); i++) {
6428 if (i >= rt->rateCount) {
6429 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
6430 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
6433 sc->sc_hwmap[i].ieeerate =
6434 rt->info[i].dot11Rate & IEEE80211_RATE_VAL;
6435 if (rt->info[i].phy == IEEE80211_T_HT)
6436 sc->sc_hwmap[i].ieeerate |= IEEE80211_RATE_MCS;
6437 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
6438 if (rt->info[i].shortPreamble ||
6439 rt->info[i].phy == IEEE80211_T_OFDM)
6440 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6441 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags;
6442 for (j = 0; j < N(blinkrates)-1; j++)
6443 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
6445 /* NB: this uses the last entry if the rate isn't found */
6446 /* XXX beware of overlow */
6447 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
6448 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
6450 sc->sc_currates = rt;
6451 sc->sc_curmode = mode;
6453 * All protection frames are transmited at 2Mb/s for
6454 * 11g, otherwise at 1Mb/s.
6456 if (mode == IEEE80211_MODE_11G)
6457 sc->sc_protrix = ath_tx_findrix(sc, 2*2);
6459 sc->sc_protrix = ath_tx_findrix(sc, 2*1);
6460 /* NB: caller is responsible for resetting rate control state */
6465 ath_watchdog(void *arg)
6467 struct ath_softc *sc = arg;
6470 ATH_LOCK_ASSERT(sc);
6472 if (sc->sc_wd_timer != 0 && --sc->sc_wd_timer == 0) {
6473 struct ifnet *ifp = sc->sc_ifp;
6476 ath_power_set_power_state(sc, HAL_PM_AWAKE);
6478 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) &&
6480 if_printf(ifp, "%s hang detected (0x%x)\n",
6481 hangs & 0xff ? "bb" : "mac", hangs);
6483 if_printf(ifp, "device timeout\n");
6485 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
6486 sc->sc_stats.ast_watchdog++;
6488 ath_power_restore_power_state(sc);
6492 * We can't hold the lock across the ath_reset() call.
6494 * And since this routine can't hold a lock and sleep,
6495 * do the reset deferred.
6498 taskqueue_enqueue(sc->sc_tq, &sc->sc_resettask);
6501 callout_schedule(&sc->sc_wd_ch, hz);
6505 * Fetch the rate control statistics for the given node.
6508 ath_ioctl_ratestats(struct ath_softc *sc, struct ath_rateioctl *rs)
6510 struct ath_node *an;
6511 struct ieee80211com *ic = sc->sc_ifp->if_l2com;
6512 struct ieee80211_node *ni;
6515 /* Perform a lookup on the given node */
6516 ni = ieee80211_find_node(&ic->ic_sta, rs->is_u.macaddr);
6522 /* Lock the ath_node */
6526 /* Fetch the rate control stats for this node */
6527 error = ath_rate_fetch_node_stats(sc, an, rs);
6529 /* No matter what happens here, just drop through */
6531 /* Unlock the ath_node */
6532 ATH_NODE_UNLOCK(an);
6534 /* Unref the node */
6535 ieee80211_node_decref(ni);
6543 * Diagnostic interface to the HAL. This is used by various
6544 * tools to do things like retrieve register contents for
6545 * debugging. The mechanism is intentionally opaque so that
6546 * it can change frequently w/o concern for compatiblity.
6549 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
6551 struct ath_hal *ah = sc->sc_ah;
6552 u_int id = ad->ad_id & ATH_DIAG_ID;
6553 void *indata = NULL;
6554 void *outdata = NULL;
6555 u_int32_t insize = ad->ad_in_size;
6556 u_int32_t outsize = ad->ad_out_size;
6559 if (ad->ad_id & ATH_DIAG_IN) {
6563 indata = malloc(insize, M_TEMP, M_NOWAIT);
6564 if (indata == NULL) {
6568 error = copyin(ad->ad_in_data, indata, insize);
6572 if (ad->ad_id & ATH_DIAG_DYN) {
6574 * Allocate a buffer for the results (otherwise the HAL
6575 * returns a pointer to a buffer where we can read the
6576 * results). Note that we depend on the HAL leaving this
6577 * pointer for us to use below in reclaiming the buffer;
6578 * may want to be more defensive.
6580 outdata = malloc(outsize, M_TEMP, M_NOWAIT);
6581 if (outdata == NULL) {
6589 if (id != HAL_DIAG_REGS)
6590 ath_power_set_power_state(sc, HAL_PM_AWAKE);
6593 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
6594 if (outsize < ad->ad_out_size)
6595 ad->ad_out_size = outsize;
6596 if (outdata != NULL)
6597 error = copyout(outdata, ad->ad_out_data,
6604 if (id != HAL_DIAG_REGS)
6605 ath_power_restore_power_state(sc);
6609 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
6610 free(indata, M_TEMP);
6611 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
6612 free(outdata, M_TEMP);
6615 #endif /* ATH_DIAGAPI */
6618 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
6620 #define IS_RUNNING(ifp) \
6621 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
6622 struct ath_softc *sc = ifp->if_softc;
6623 struct ieee80211com *ic = ifp->if_l2com;
6624 struct ifreq *ifr = (struct ifreq *)data;
6625 const HAL_RATE_TABLE *rt;
6630 if (IS_RUNNING(ifp)) {
6632 * To avoid rescanning another access point,
6633 * do not call ath_init() here. Instead,
6634 * only reflect promisc mode settings.
6637 ath_power_set_power_state(sc, HAL_PM_AWAKE);
6639 ath_power_restore_power_state(sc);
6641 } else if (ifp->if_flags & IFF_UP) {
6643 * Beware of being called during attach/detach
6644 * to reset promiscuous mode. In that case we
6645 * will still be marked UP but not RUNNING.
6646 * However trying to re-init the interface
6647 * is the wrong thing to do as we've already
6648 * torn down much of our state. There's
6649 * probably a better way to deal with this.
6651 if (!sc->sc_invalid)
6652 ath_init(sc); /* XXX lose error */
6655 ath_stop_locked(ifp);
6656 if (!sc->sc_invalid)
6657 ath_power_setpower(sc, HAL_PM_FULL_SLEEP);
6663 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
6666 /* NB: embed these numbers to get a consistent view */
6667 sc->sc_stats.ast_tx_packets = ifp->if_get_counter(ifp,
6668 IFCOUNTER_OPACKETS);
6669 sc->sc_stats.ast_rx_packets = ifp->if_get_counter(ifp,
6670 IFCOUNTER_IPACKETS);
6671 sc->sc_stats.ast_tx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgtxrssi);
6672 sc->sc_stats.ast_rx_rssi = ATH_RSSI(sc->sc_halstats.ns_avgrssi);
6673 #ifdef IEEE80211_SUPPORT_TDMA
6674 sc->sc_stats.ast_tdma_tsfadjp = TDMA_AVG(sc->sc_avgtsfdeltap);
6675 sc->sc_stats.ast_tdma_tsfadjm = TDMA_AVG(sc->sc_avgtsfdeltam);
6677 rt = sc->sc_currates;
6678 sc->sc_stats.ast_tx_rate =
6679 rt->info[sc->sc_txrix].dot11Rate &~ IEEE80211_RATE_BASIC;
6680 if (rt->info[sc->sc_txrix].phy & IEEE80211_T_HT)
6681 sc->sc_stats.ast_tx_rate |= IEEE80211_RATE_MCS;
6682 return copyout(&sc->sc_stats,
6683 ifr->ifr_data, sizeof (sc->sc_stats));
6684 case SIOCGATHAGSTATS:
6685 return copyout(&sc->sc_aggr_stats,
6686 ifr->ifr_data, sizeof (sc->sc_aggr_stats));
6688 error = priv_check(curthread, PRIV_DRIVER);
6690 memset(&sc->sc_stats, 0, sizeof(sc->sc_stats));
6691 memset(&sc->sc_aggr_stats, 0,
6692 sizeof(sc->sc_aggr_stats));
6693 memset(&sc->sc_intr_stats, 0,
6694 sizeof(sc->sc_intr_stats));
6699 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
6701 case SIOCGATHPHYERR:
6702 error = ath_ioctl_phyerr(sc,(struct ath_diag*) ifr);
6705 case SIOCGATHSPECTRAL:
6706 error = ath_ioctl_spectral(sc,(struct ath_diag*) ifr);
6708 case SIOCGATHNODERATESTATS:
6709 error = ath_ioctl_ratestats(sc, (struct ath_rateioctl *) ifr);
6712 error = ether_ioctl(ifp, cmd, data);
6723 * Announce various information on device/driver attach.
6726 ath_announce(struct ath_softc *sc)
6728 struct ifnet *ifp = sc->sc_ifp;
6729 struct ath_hal *ah = sc->sc_ah;
6731 if_printf(ifp, "AR%s mac %d.%d RF%s phy %d.%d\n",
6732 ath_hal_mac_name(ah), ah->ah_macVersion, ah->ah_macRev,
6733 ath_hal_rf_name(ah), ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
6734 if_printf(ifp, "2GHz radio: 0x%.4x; 5GHz radio: 0x%.4x\n",
6735 ah->ah_analog2GhzRev, ah->ah_analog5GhzRev);
6738 for (i = 0; i <= WME_AC_VO; i++) {
6739 struct ath_txq *txq = sc->sc_ac2q[i];
6740 if_printf(ifp, "Use hw queue %u for %s traffic\n",
6741 txq->axq_qnum, ieee80211_wme_acnames[i]);
6743 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
6744 sc->sc_cabq->axq_qnum);
6745 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
6747 if (ath_rxbuf != ATH_RXBUF)
6748 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
6749 if (ath_txbuf != ATH_TXBUF)
6750 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
6751 if (sc->sc_mcastkey && bootverbose)
6752 if_printf(ifp, "using multicast key search\n");
6756 ath_dfs_tasklet(void *p, int npending)
6758 struct ath_softc *sc = (struct ath_softc *) p;
6759 struct ifnet *ifp = sc->sc_ifp;
6760 struct ieee80211com *ic = ifp->if_l2com;
6763 * If previous processing has found a radar event,
6764 * signal this to the net80211 layer to begin DFS
6767 if (ath_dfs_process_radar_event(sc, sc->sc_curchan)) {
6768 /* DFS event found, initiate channel change */
6770 * XXX doesn't currently tell us whether the event
6771 * XXX was found in the primary or extension
6775 ieee80211_dfs_notify_radar(ic, sc->sc_curchan);
6776 IEEE80211_UNLOCK(ic);
6781 * Enable/disable power save. This must be called with
6782 * no TX driver locks currently held, so it should only
6783 * be called from the RX path (which doesn't hold any
6787 ath_node_powersave(struct ieee80211_node *ni, int enable)
6790 struct ath_node *an = ATH_NODE(ni);
6791 struct ieee80211com *ic = ni->ni_ic;
6792 struct ath_softc *sc = ic->ic_ifp->if_softc;
6793 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6795 /* XXX and no TXQ locks should be held here */
6797 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE, "%s: %6D: enable=%d\n",
6803 /* Suspend or resume software queue handling */
6805 ath_tx_node_sleep(sc, an);
6807 ath_tx_node_wakeup(sc, an);
6809 /* Update net80211 state */
6810 avp->av_node_ps(ni, enable);
6812 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6814 /* Update net80211 state */
6815 avp->av_node_ps(ni, enable);
6816 #endif/* ATH_SW_PSQ */
6820 * Notification from net80211 that the powersave queue state has
6823 * Since the software queue also may have some frames:
6825 * + if the node software queue has frames and the TID state
6826 * is 0, we set the TIM;
6827 * + if the node and the stack are both empty, we clear the TIM bit.
6828 * + If the stack tries to set the bit, always set it.
6829 * + If the stack tries to clear the bit, only clear it if the
6830 * software queue in question is also cleared.
6832 * TODO: this is called during node teardown; so let's ensure this
6833 * is all correctly handled and that the TIM bit is cleared.
6834 * It may be that the node flush is called _AFTER_ the net80211
6835 * stack clears the TIM.
6837 * Here is the racy part. Since it's possible >1 concurrent,
6838 * overlapping TXes will appear complete with a TX completion in
6839 * another thread, it's possible that the concurrent TIM calls will
6840 * clash. We can't hold the node lock here because setting the
6841 * TIM grabs the net80211 comlock and this may cause a LOR.
6842 * The solution is either to totally serialise _everything_ at
6843 * this point (ie, all TX, completion and any reset/flush go into
6844 * one taskqueue) or a new "ath TIM lock" needs to be created that
6845 * just wraps the driver state change and this call to avp->av_set_tim().
6847 * The same race exists in the net80211 power save queue handling
6848 * as well. Since multiple transmitting threads may queue frames
6849 * into the driver, as well as ps-poll and the driver transmitting
6850 * frames (and thus clearing the psq), it's quite possible that
6851 * a packet entering the PSQ and a ps-poll being handled will
6852 * race, causing the TIM to be cleared and not re-set.
6855 ath_node_set_tim(struct ieee80211_node *ni, int enable)
6858 struct ieee80211com *ic = ni->ni_ic;
6859 struct ath_softc *sc = ic->ic_ifp->if_softc;
6860 struct ath_node *an = ATH_NODE(ni);
6861 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6865 an->an_stack_psq = enable;
6868 * This will get called for all operating modes,
6869 * even if avp->av_set_tim is unset.
6870 * It's currently set for hostap/ibss modes; but
6871 * the same infrastructure is used for both STA
6872 * and AP/IBSS node power save.
6874 if (avp->av_set_tim == NULL) {
6880 * If setting the bit, always set it here.
6881 * If clearing the bit, only clear it if the
6882 * software queue is also empty.
6884 * If the node has left power save, just clear the TIM
6885 * bit regardless of the state of the power save queue.
6887 * XXX TODO: although atomics are used, it's quite possible
6888 * that a race will occur between this and setting/clearing
6889 * in another thread. TX completion will occur always in
6890 * one thread, however setting/clearing the TIM bit can come
6891 * from a variety of different process contexts!
6893 if (enable && an->an_tim_set == 1) {
6894 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6895 "%s: %6D: enable=%d, tim_set=1, ignoring\n",
6901 } else if (enable) {
6902 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6903 "%s: %6D: enable=%d, enabling TIM\n",
6910 changed = avp->av_set_tim(ni, enable);
6911 } else if (an->an_swq_depth == 0) {
6913 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6914 "%s: %6D: enable=%d, an_swq_depth == 0, disabling\n",
6921 changed = avp->av_set_tim(ni, enable);
6922 } else if (! an->an_is_powersave) {
6924 * disable regardless; the node isn't in powersave now
6926 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6927 "%s: %6D: enable=%d, an_pwrsave=0, disabling\n",
6934 changed = avp->av_set_tim(ni, enable);
6937 * psq disable, node is currently in powersave, node
6938 * software queue isn't empty, so don't clear the TIM bit
6942 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
6943 "%s: %6D: enable=%d, an_swq_depth > 0, ignoring\n",
6953 struct ath_vap *avp = ATH_VAP(ni->ni_vap);
6956 * Some operating modes don't set av_set_tim(), so don't
6959 if (avp->av_set_tim == NULL)
6962 return (avp->av_set_tim(ni, enable));
6963 #endif /* ATH_SW_PSQ */
6967 * Set or update the TIM from the software queue.
6969 * Check the software queue depth before attempting to do lock
6970 * anything; that avoids trying to obtain the lock. Then,
6971 * re-check afterwards to ensure nothing has changed in the
6974 * set: This is designed to be called from the TX path, after
6975 * a frame has been queued; to see if the swq > 0.
6977 * clear: This is designed to be called from the buffer completion point
6978 * (right now it's ath_tx_default_comp()) where the state of
6979 * a software queue has changed.
6981 * It makes sense to place it at buffer free / completion rather
6982 * than after each software queue operation, as there's no real
6983 * point in churning the TIM bit as the last frames in the software
6984 * queue are transmitted. If they fail and we retry them, we'd
6985 * just be setting the TIM bit again anyway.
6988 ath_tx_update_tim(struct ath_softc *sc, struct ieee80211_node *ni,
6992 struct ath_node *an;
6993 struct ath_vap *avp;
6995 /* Don't do this for broadcast/etc frames */
7000 avp = ATH_VAP(ni->ni_vap);
7003 * And for operating modes without the TIM handler set, let's
7006 if (avp->av_set_tim == NULL)
7009 ATH_TX_LOCK_ASSERT(sc);
7012 if (an->an_is_powersave &&
7013 an->an_tim_set == 0 &&
7014 an->an_swq_depth != 0) {
7015 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7016 "%s: %6D: swq_depth>0, tim_set=0, set!\n",
7021 (void) avp->av_set_tim(ni, 1);
7025 * Don't bother grabbing the lock unless the queue is empty.
7027 if (&an->an_swq_depth != 0)
7030 if (an->an_is_powersave &&
7031 an->an_stack_psq == 0 &&
7032 an->an_tim_set == 1 &&
7033 an->an_swq_depth == 0) {
7034 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7035 "%s: %6D: swq_depth=0, tim_set=1, psq_set=0,"
7041 (void) avp->av_set_tim(ni, 0);
7046 #endif /* ATH_SW_PSQ */
7050 * Received a ps-poll frame from net80211.
7052 * Here we get a chance to serve out a software-queued frame ourselves
7053 * before we punt it to net80211 to transmit us one itself - either
7054 * because there's traffic in the net80211 psq, or a NULL frame to
7055 * indicate there's nothing else.
7058 ath_node_recv_pspoll(struct ieee80211_node *ni, struct mbuf *m)
7061 struct ath_node *an;
7062 struct ath_vap *avp;
7063 struct ieee80211com *ic = ni->ni_ic;
7064 struct ath_softc *sc = ic->ic_ifp->if_softc;
7072 * Unassociated (temporary node) station.
7074 if (ni->ni_associd == 0)
7078 * We do have an active node, so let's begin looking into it.
7081 avp = ATH_VAP(ni->ni_vap);
7084 * For now, we just call the original ps-poll method.
7085 * Once we're ready to flip this on:
7087 * + Set leak to 1, as no matter what we're going to have
7089 * + Check the software queue and if there's something in it,
7090 * schedule the highest TID thas has traffic from this node.
7091 * Then make sure we schedule the software scheduler to
7092 * run so it picks up said frame.
7094 * That way whatever happens, we'll at least send _a_ frame
7095 * to the given node.
7097 * Again, yes, it's crappy QoS if the node has multiple
7098 * TIDs worth of traffic - but let's get it working first
7099 * before we optimise it.
7101 * Also yes, there's definitely latency here - we're not
7102 * direct dispatching to the hardware in this path (and
7103 * we're likely being called from the packet receive path,
7104 * so going back into TX may be a little hairy!) but again
7105 * I'd like to get this working first before optimising
7112 * Legacy - we're called and the node isn't asleep.
7115 if (! an->an_is_powersave) {
7116 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7117 "%s: %6D: not in powersave?\n",
7122 avp->av_recv_pspoll(ni, m);
7127 * We're in powersave.
7131 an->an_leak_count = 1;
7134 * Now, if there's no frames in the node, just punt to
7137 * Don't bother checking if the TIM bit is set, we really
7138 * only care if there are any frames here!
7140 if (an->an_swq_depth == 0) {
7142 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7143 "%s: %6D: SWQ empty; punting to net80211\n",
7147 avp->av_recv_pspoll(ni, m);
7152 * Ok, let's schedule the highest TID that has traffic
7153 * and then schedule something.
7155 for (tid = IEEE80211_TID_SIZE - 1; tid >= 0; tid--) {
7156 struct ath_tid *atid = &an->an_tid[tid];
7160 if (atid->axq_depth == 0)
7162 ath_tx_tid_sched(sc, atid);
7164 * XXX we could do a direct call to the TXQ
7165 * scheduler code here to optimise latency
7166 * at the expense of a REALLY deep callstack.
7169 taskqueue_enqueue(sc->sc_tq, &sc->sc_txqtask);
7170 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7171 "%s: %6D: leaking frame to TID %d\n",
7182 * XXX nothing in the TIDs at this point? Eek.
7184 DPRINTF(sc, ATH_DEBUG_NODE_PWRSAVE,
7185 "%s: %6D: TIDs empty, but ath_node showed traffic?!\n",
7189 avp->av_recv_pspoll(ni, m);
7191 avp->av_recv_pspoll(ni, m);
7192 #endif /* ATH_SW_PSQ */
7195 MODULE_VERSION(if_ath, 1);
7196 MODULE_DEPEND(if_ath, wlan, 1, 1, 1); /* 802.11 media layer */
7197 #if defined(IEEE80211_ALQ) || defined(AH_DEBUG_ALQ) || defined(ATH_DEBUG_ALQ)
7198 MODULE_DEPEND(if_ath, alq, 1, 1, 1);