2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
41 * Driver for the Atheros Wireless LAN controller.
43 * This software is derived from work of Atsushi Onoe; his contribution
44 * is greatly appreciated.
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/sysctl.h>
53 #include <sys/malloc.h>
55 #include <sys/mutex.h>
56 #include <sys/kernel.h>
57 #include <sys/socket.h>
58 #include <sys/sockio.h>
59 #include <sys/errno.h>
60 #include <sys/callout.h>
62 #include <sys/endian.h>
63 #include <sys/kthread.h>
64 #include <sys/taskqueue.h>
66 #include <machine/bus.h>
69 #include <net/if_dl.h>
70 #include <net/if_media.h>
71 #include <net/if_types.h>
72 #include <net/if_arp.h>
73 #include <net/ethernet.h>
74 #include <net/if_llc.h>
76 #include <net80211/ieee80211_var.h>
81 #include <netinet/in.h>
82 #include <netinet/if_ether.h>
86 #include <dev/ath/if_athvar.h>
87 #include <contrib/dev/ath/ah_desc.h>
88 #include <contrib/dev/ath/ah_devid.h> /* XXX for softled */
91 #include <dev/ath/ath_tx99/ath_tx99.h>
94 /* unaligned little endian access */
95 #define LE_READ_2(p) \
97 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8)))
98 #define LE_READ_4(p) \
100 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \
101 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24)))
109 static void ath_init(void *);
110 static void ath_stop_locked(struct ifnet *);
111 static void ath_stop(struct ifnet *);
112 static void ath_start(struct ifnet *);
113 static int ath_reset(struct ifnet *);
114 static int ath_media_change(struct ifnet *);
115 static void ath_watchdog(struct ifnet *);
116 static int ath_ioctl(struct ifnet *, u_long, caddr_t);
117 static void ath_fatal_proc(void *, int);
118 static void ath_rxorn_proc(void *, int);
119 static void ath_bmiss_proc(void *, int);
120 static int ath_key_alloc(struct ieee80211com *,
121 const struct ieee80211_key *,
122 ieee80211_keyix *, ieee80211_keyix *);
123 static int ath_key_delete(struct ieee80211com *,
124 const struct ieee80211_key *);
125 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *,
126 const u_int8_t mac[IEEE80211_ADDR_LEN]);
127 static void ath_key_update_begin(struct ieee80211com *);
128 static void ath_key_update_end(struct ieee80211com *);
129 static void ath_mode_init(struct ath_softc *);
130 static void ath_setslottime(struct ath_softc *);
131 static void ath_updateslot(struct ifnet *);
132 static int ath_beaconq_setup(struct ath_hal *);
133 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *);
134 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *);
135 static void ath_beacon_proc(void *, int);
136 static void ath_bstuck_proc(void *, int);
137 static void ath_beacon_free(struct ath_softc *);
138 static void ath_beacon_config(struct ath_softc *);
139 static void ath_descdma_cleanup(struct ath_softc *sc,
140 struct ath_descdma *, ath_bufhead *);
141 static int ath_desc_alloc(struct ath_softc *);
142 static void ath_desc_free(struct ath_softc *);
143 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *);
144 static void ath_node_free(struct ieee80211_node *);
145 static u_int8_t ath_node_getrssi(const struct ieee80211_node *);
146 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *);
147 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
148 struct ieee80211_node *ni,
149 int subtype, int rssi, u_int32_t rstamp);
150 static void ath_setdefantenna(struct ath_softc *, u_int);
151 static void ath_rx_proc(void *, int);
152 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
153 static int ath_tx_setup(struct ath_softc *, int, int);
154 static int ath_wme_update(struct ieee80211com *);
155 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
156 static void ath_tx_cleanup(struct ath_softc *);
157 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *,
158 struct ath_buf *, struct mbuf *);
159 static void ath_tx_proc_q0(void *, int);
160 static void ath_tx_proc_q0123(void *, int);
161 static void ath_tx_proc(void *, int);
162 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
163 static void ath_draintxq(struct ath_softc *);
164 static void ath_stoprecv(struct ath_softc *);
165 static int ath_startrecv(struct ath_softc *);
166 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
167 static void ath_next_scan(void *);
168 static void ath_calibrate(void *);
169 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int);
170 static void ath_setup_stationkey(struct ieee80211_node *);
171 static void ath_newassoc(struct ieee80211_node *, int);
172 static int ath_getchannels(struct ath_softc *, u_int cc,
173 HAL_BOOL outdoor, HAL_BOOL xchanmode);
174 static void ath_led_event(struct ath_softc *, int);
175 static void ath_update_txpow(struct ath_softc *);
177 static int ath_rate_setup(struct ath_softc *, u_int mode);
178 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
180 static void ath_sysctlattach(struct ath_softc *);
181 static void ath_bpfattach(struct ath_softc *);
182 static void ath_announce(struct ath_softc *);
184 SYSCTL_DECL(_hw_ath);
186 /* XXX validate sysctl values */
187 static int ath_dwelltime = 200; /* 5 channels/second */
188 SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime,
189 0, "channel dwell time (ms) for AP/station scanning");
190 static int ath_calinterval = 30; /* calibrate every 30 secs */
191 SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval,
192 0, "chip calibration interval (secs)");
193 static int ath_outdoor = AH_TRUE; /* outdoor operation */
194 SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor,
195 0, "outdoor operation");
196 TUNABLE_INT("hw.ath.outdoor", &ath_outdoor);
197 static int ath_xchanmode = AH_TRUE; /* extended channel use */
198 SYSCTL_INT(_hw_ath, OID_AUTO, xchanmode, CTLFLAG_RD, &ath_xchanmode,
199 0, "extended channel mode");
200 TUNABLE_INT("hw.ath.xchanmode", &ath_xchanmode);
201 static int ath_countrycode = CTRY_DEFAULT; /* country code */
202 SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode,
204 TUNABLE_INT("hw.ath.countrycode", &ath_countrycode);
205 static int ath_regdomain = 0; /* regulatory domain */
206 SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain,
207 0, "regulatory domain");
209 static int ath_rxbuf = ATH_RXBUF; /* # rx buffers to allocate */
210 SYSCTL_INT(_hw_ath, OID_AUTO, rxbuf, CTLFLAG_RD, &ath_rxbuf,
211 0, "rx buffers allocated");
212 TUNABLE_INT("hw.ath.rxbuf", &ath_rxbuf);
213 static int ath_txbuf = ATH_TXBUF; /* # tx buffers to allocate */
214 SYSCTL_INT(_hw_ath, OID_AUTO, txbuf, CTLFLAG_RD, &ath_txbuf,
215 0, "tx buffers allocated");
216 TUNABLE_INT("hw.ath.txbuf", &ath_txbuf);
219 static int ath_debug = 0;
220 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug,
221 0, "control debugging printfs");
222 TUNABLE_INT("hw.ath.debug", &ath_debug);
224 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
225 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */
226 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */
227 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */
228 ATH_DEBUG_RATE = 0x00000010, /* rate control */
229 ATH_DEBUG_RESET = 0x00000020, /* reset processing */
230 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */
231 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */
232 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */
233 ATH_DEBUG_INTR = 0x00001000, /* ISR */
234 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */
235 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */
236 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */
237 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */
238 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */
239 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */
240 ATH_DEBUG_NODE = 0x00080000, /* node management */
241 ATH_DEBUG_LED = 0x00100000, /* led management */
242 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */
243 ATH_DEBUG_ANY = 0xffffffff
245 #define IFF_DUMPPKTS(sc, m) \
246 ((sc->sc_debug & (m)) || \
247 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
248 #define DPRINTF(sc, m, fmt, ...) do { \
249 if (sc->sc_debug & (m)) \
250 printf(fmt, __VA_ARGS__); \
252 #define KEYPRINTF(sc, ix, hk, mac) do { \
253 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \
254 ath_keyprint(__func__, ix, hk, mac); \
256 static void ath_printrxbuf(struct ath_buf *bf, int);
257 static void ath_printtxbuf(struct ath_buf *bf, int);
259 #define IFF_DUMPPKTS(sc, m) \
260 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
261 #define DPRINTF(m, fmt, ...)
262 #define KEYPRINTF(sc, k, ix, mac)
265 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
268 ath_attach(u_int16_t devid, struct ath_softc *sc)
271 struct ieee80211com *ic = &sc->sc_ic;
272 struct ath_hal *ah = NULL;
276 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
278 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
280 device_printf(sc->sc_dev, "can not if_alloc()\n");
285 /* set these up early for if_printf use */
286 if_initname(ifp, device_get_name(sc->sc_dev),
287 device_get_unit(sc->sc_dev));
289 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status);
291 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
296 if (ah->ah_abi != HAL_ABI_VERSION) {
297 if_printf(ifp, "HAL ABI mismatch detected "
298 "(HAL:0x%x != driver:0x%x)\n",
299 ah->ah_abi, HAL_ABI_VERSION);
304 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
307 * Check if the MAC has multi-rate retry support.
308 * We do this by trying to setup a fake extended
309 * descriptor. MAC's that don't have support will
310 * return false w/o doing anything. MAC's that do
311 * support it will return true w/o doing anything.
313 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
316 * Check if the device has hardware counters for PHY
317 * errors. If so we need to enable the MIB interrupt
318 * so we can act on stat triggers.
320 if (ath_hal_hwphycounters(ah))
324 * Get the hardware key cache size.
326 sc->sc_keymax = ath_hal_keycachesize(ah);
327 if (sc->sc_keymax > ATH_KEYMAX) {
328 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
329 ATH_KEYMAX, sc->sc_keymax);
330 sc->sc_keymax = ATH_KEYMAX;
333 * Reset the key cache since some parts do not
334 * reset the contents on initial power up.
336 for (i = 0; i < sc->sc_keymax; i++)
337 ath_hal_keyreset(ah, i);
339 * Mark key cache slots associated with global keys
340 * as in use. If we knew TKIP was not to be used we
341 * could leave the +32, +64, and +32+64 slots free.
342 * XXX only for splitmic.
344 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
345 setbit(sc->sc_keymap, i);
346 setbit(sc->sc_keymap, i+32);
347 setbit(sc->sc_keymap, i+64);
348 setbit(sc->sc_keymap, i+32+64);
352 * Collect the channel list using the default country
353 * code and including outdoor channels. The 802.11 layer
354 * is resposible for filtering this list based on settings
357 error = ath_getchannels(sc, ath_countrycode,
358 ath_outdoor, ath_xchanmode);
363 * Setup rate tables for all potential media types.
365 ath_rate_setup(sc, IEEE80211_MODE_11A);
366 ath_rate_setup(sc, IEEE80211_MODE_11B);
367 ath_rate_setup(sc, IEEE80211_MODE_11G);
368 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
369 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
370 /* NB: setup here so ath_rate_update is happy */
371 ath_setcurmode(sc, IEEE80211_MODE_11A);
374 * Allocate tx+rx descriptors and populate the lists.
376 error = ath_desc_alloc(sc);
378 if_printf(ifp, "failed to allocate descriptors: %d\n", error);
381 callout_init(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0);
382 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE);
384 ATH_TXBUF_LOCK_INIT(sc);
386 sc->sc_tq = taskqueue_create("ath_taskq", M_NOWAIT,
387 taskqueue_thread_enqueue, &sc->sc_tq);
388 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET,
389 "%s taskq", ifp->if_xname);
391 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc);
392 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc);
393 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc);
394 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
395 TASK_INIT(&sc->sc_bstucktask, 0, ath_bstuck_proc, sc);
398 * Allocate hardware transmit queues: one queue for
399 * beacon frames and one data queue for each QoS
400 * priority. Note that the hal handles reseting
401 * these queues at the needed time.
405 sc->sc_bhalq = ath_beaconq_setup(ah);
406 if (sc->sc_bhalq == (u_int) -1) {
407 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
411 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
412 if (sc->sc_cabq == NULL) {
413 if_printf(ifp, "unable to setup CAB xmit queue!\n");
417 /* NB: insure BK queue is the lowest priority h/w queue */
418 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
419 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
420 ieee80211_wme_acnames[WME_AC_BK]);
424 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
425 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
426 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
428 * Not enough hardware tx queues to properly do WME;
429 * just punt and assign them all to the same h/w queue.
430 * We could do a better job of this if, for example,
431 * we allocate queues when we switch from station to
434 if (sc->sc_ac2q[WME_AC_VI] != NULL)
435 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
436 if (sc->sc_ac2q[WME_AC_BE] != NULL)
437 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
438 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
439 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
440 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
444 * Special case certain configurations. Note the
445 * CAB queue is handled by these specially so don't
446 * include them when checking the txq setup mask.
448 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
450 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
453 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
456 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
461 * Setup rate control. Some rate control modules
462 * call back to change the anntena state so expose
463 * the necessary entry points.
464 * XXX maybe belongs in struct ath_ratectrl?
466 sc->sc_setdefantenna = ath_setdefantenna;
467 sc->sc_rc = ath_rate_attach(sc);
468 if (sc->sc_rc == NULL) {
475 sc->sc_ledon = 0; /* low true */
476 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
477 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE);
479 * Auto-enable soft led processing for IBM cards and for
480 * 5211 minipci cards. Users can also manually enable/disable
481 * support with a sysctl.
483 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
484 if (sc->sc_softled) {
485 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin);
486 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
490 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
491 ifp->if_start = ath_start;
492 ifp->if_watchdog = ath_watchdog;
493 ifp->if_ioctl = ath_ioctl;
494 ifp->if_init = ath_init;
495 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
496 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
497 IFQ_SET_READY(&ifp->if_snd);
500 ic->ic_reset = ath_reset;
501 ic->ic_newassoc = ath_newassoc;
502 ic->ic_updateslot = ath_updateslot;
503 ic->ic_wme.wme_update = ath_wme_update;
504 /* XXX not right but it's not used anywhere important */
505 ic->ic_phytype = IEEE80211_T_OFDM;
506 ic->ic_opmode = IEEE80211_M_STA;
508 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
509 | IEEE80211_C_HOSTAP /* hostap mode */
510 | IEEE80211_C_MONITOR /* monitor mode */
511 | IEEE80211_C_AHDEMO /* adhoc demo mode */
512 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
513 | IEEE80211_C_SHSLOT /* short slot time supported */
514 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
517 * Query the hal to figure out h/w crypto support.
519 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
520 ic->ic_caps |= IEEE80211_C_WEP;
521 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
522 ic->ic_caps |= IEEE80211_C_AES;
523 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
524 ic->ic_caps |= IEEE80211_C_AES_CCM;
525 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
526 ic->ic_caps |= IEEE80211_C_CKIP;
527 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
528 ic->ic_caps |= IEEE80211_C_TKIP;
530 * Check if h/w does the MIC and/or whether the
531 * separate key cache entries are required to
532 * handle both tx+rx MIC keys.
534 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
535 ic->ic_caps |= IEEE80211_C_TKIPMIC;
536 if (ath_hal_tkipsplit(ah))
539 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
540 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
542 * TPC support can be done either with a global cap or
543 * per-packet support. The latter is not available on
544 * all parts. We're a bit pedantic here as all parts
545 * support a global cap.
547 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah))
548 ic->ic_caps |= IEEE80211_C_TXPMGT;
551 * Mark WME capability only if we have sufficient
552 * hardware queues to do proper priority scheduling.
554 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
555 ic->ic_caps |= IEEE80211_C_WME;
557 * Check for misc other capabilities.
559 if (ath_hal_hasbursting(ah))
560 ic->ic_caps |= IEEE80211_C_BURST;
563 * Indicate we need the 802.11 header padded to a
564 * 32-bit boundary for 4-address and QoS frames.
566 ic->ic_flags |= IEEE80211_F_DATAPAD;
569 * Query the hal about antenna support.
571 sc->sc_defant = ath_hal_getdefantenna(ah);
574 * Not all chips have the VEOL support we want to
575 * use with IBSS beacons; check here for it.
577 sc->sc_hasveol = ath_hal_hasveol(ah);
579 /* get mac address from hardware */
580 ath_hal_getmac(ah, ic->ic_myaddr);
582 /* call MI attach routine. */
583 ieee80211_ifattach(ic);
584 sc->sc_opmode = ic->ic_opmode;
585 /* override default methods */
586 ic->ic_node_alloc = ath_node_alloc;
587 sc->sc_node_free = ic->ic_node_free;
588 ic->ic_node_free = ath_node_free;
589 ic->ic_node_getrssi = ath_node_getrssi;
590 sc->sc_recv_mgmt = ic->ic_recv_mgmt;
591 ic->ic_recv_mgmt = ath_recv_mgmt;
592 sc->sc_newstate = ic->ic_newstate;
593 ic->ic_newstate = ath_newstate;
594 ic->ic_crypto.cs_max_keyix = sc->sc_keymax;
595 ic->ic_crypto.cs_key_alloc = ath_key_alloc;
596 ic->ic_crypto.cs_key_delete = ath_key_delete;
597 ic->ic_crypto.cs_key_set = ath_key_set;
598 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin;
599 ic->ic_crypto.cs_key_update_end = ath_key_update_end;
600 /* complete initialization */
601 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status);
605 * Setup dynamic sysctl's now that country code and
606 * regdomain are available from the hal.
608 ath_sysctlattach(sc);
611 ieee80211_announce(ic);
627 ath_detach(struct ath_softc *sc)
629 struct ifnet *ifp = sc->sc_ifp;
631 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
632 __func__, ifp->if_flags);
637 * NB: the order of these is important:
638 * o call the 802.11 layer before detaching the hal to
639 * insure callbacks into the driver to delete global
640 * key cache entries can be handled
641 * o reclaim the tx queue data structures after calling
642 * the 802.11 layer as we'll get called back to reclaim
643 * node state and potentially want to use them
644 * o to cleanup the tx queues the hal is called, so detach
646 * Other than that, it's straightforward...
648 ieee80211_ifdetach(&sc->sc_ic);
650 if (sc->sc_tx99 != NULL)
651 sc->sc_tx99->detach(sc->sc_tx99);
653 taskqueue_free(sc->sc_tq);
654 ath_rate_detach(sc->sc_rc);
657 ath_hal_detach(sc->sc_ah);
664 ath_suspend(struct ath_softc *sc)
666 struct ifnet *ifp = sc->sc_ifp;
668 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
669 __func__, ifp->if_flags);
675 ath_resume(struct ath_softc *sc)
677 struct ifnet *ifp = sc->sc_ifp;
679 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
680 __func__, ifp->if_flags);
682 if (ifp->if_flags & IFF_UP) {
684 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
687 if (sc->sc_softled) {
688 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
689 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
694 ath_shutdown(struct ath_softc *sc)
696 struct ifnet *ifp = sc->sc_ifp;
698 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
699 __func__, ifp->if_flags);
705 * Interrupt handler. Most of the actual processing is deferred.
710 struct ath_softc *sc = arg;
711 struct ifnet *ifp = sc->sc_ifp;
712 struct ath_hal *ah = sc->sc_ah;
715 if (sc->sc_invalid) {
717 * The hardware is not ready/present, don't touch anything.
718 * Note this can happen early on if the IRQ is shared.
720 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
723 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */
725 if (!((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags &
727 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
728 __func__, ifp->if_flags);
729 ath_hal_getisr(ah, &status); /* clear ISR */
730 ath_hal_intrset(ah, 0); /* disable further intr's */
734 * Figure out the reason(s) for the interrupt. Note
735 * that the hal returns a pseudo-ISR that may include
736 * bits we haven't explicitly enabled so we mask the
737 * value to insure we only process bits we requested.
739 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
740 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
741 status &= sc->sc_imask; /* discard unasked for bits */
742 if (status & HAL_INT_FATAL) {
744 * Fatal errors are unrecoverable. Typically
745 * these are caused by DMA errors. Unfortunately
746 * the exact reason is not (presently) returned
749 sc->sc_stats.ast_hardware++;
750 ath_hal_intrset(ah, 0); /* disable intr's until reset */
751 taskqueue_enqueue(sc->sc_tq, &sc->sc_fataltask);
752 } else if (status & HAL_INT_RXORN) {
753 sc->sc_stats.ast_rxorn++;
754 ath_hal_intrset(ah, 0); /* disable intr's until reset */
755 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxorntask);
757 if (status & HAL_INT_SWBA) {
759 * Software beacon alert--time to send a beacon.
760 * Handle beacon transmission directly; deferring
761 * this is too slow to meet timing constraints
764 ath_beacon_proc(sc, 0);
766 if (status & HAL_INT_RXEOL) {
768 * NB: the hardware should re-read the link when
769 * RXE bit is written, but it doesn't work at
770 * least on older hardware revs.
772 sc->sc_stats.ast_rxeol++;
773 sc->sc_rxlink = NULL;
775 if (status & HAL_INT_TXURN) {
776 sc->sc_stats.ast_txurn++;
777 /* bump tx trigger level */
778 ath_hal_updatetxtriglevel(ah, AH_TRUE);
780 if (status & HAL_INT_RX)
781 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
782 if (status & HAL_INT_TX)
783 taskqueue_enqueue(sc->sc_tq, &sc->sc_txtask);
784 if (status & HAL_INT_BMISS) {
785 sc->sc_stats.ast_bmiss++;
786 taskqueue_enqueue(sc->sc_tq, &sc->sc_bmisstask);
788 if (status & HAL_INT_MIB) {
789 sc->sc_stats.ast_mib++;
791 * Disable interrupts until we service the MIB
792 * interrupt; otherwise it will continue to fire.
794 ath_hal_intrset(ah, 0);
796 * Let the hal handle the event. We assume it will
797 * clear whatever condition caused the interrupt.
799 ath_hal_mibevent(ah, &sc->sc_halstats);
800 ath_hal_intrset(ah, sc->sc_imask);
806 ath_fatal_proc(void *arg, int pending)
808 struct ath_softc *sc = arg;
809 struct ifnet *ifp = sc->sc_ifp;
811 if_printf(ifp, "hardware error; resetting\n");
816 ath_rxorn_proc(void *arg, int pending)
818 struct ath_softc *sc = arg;
819 struct ifnet *ifp = sc->sc_ifp;
821 if_printf(ifp, "rx FIFO overrun; resetting\n");
826 ath_bmiss_proc(void *arg, int pending)
828 struct ath_softc *sc = arg;
829 struct ieee80211com *ic = &sc->sc_ic;
831 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
832 KASSERT(ic->ic_opmode == IEEE80211_M_STA,
833 ("unexpect operating mode %u", ic->ic_opmode));
834 if (ic->ic_state == IEEE80211_S_RUN) {
835 u_int64_t lastrx = sc->sc_lastrx;
836 u_int64_t tsf = ath_hal_gettsf64(sc->sc_ah);
838 ic->ic_bmissthreshold * ic->ic_bss->ni_intval * 1024;
840 DPRINTF(sc, ATH_DEBUG_BEACON,
841 "%s: tsf %llu lastrx %lld (%llu) bmiss %u\n",
842 __func__, (unsigned long long) tsf,
843 (unsigned long long)(tsf - lastrx),
844 (unsigned long long) lastrx, bmisstimeout);
846 * Workaround phantom bmiss interrupts by sanity-checking
847 * the time of our last rx'd frame. If it is within the
848 * beacon miss interval then ignore the interrupt. If it's
849 * truly a bmiss we'll get another interrupt soon and that'll
850 * be dispatched up for processing.
852 if (tsf - lastrx > bmisstimeout) {
854 ieee80211_beacon_miss(ic);
857 sc->sc_stats.ast_bmiss_phantom++;
862 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan)
864 #define N(a) (sizeof(a) / sizeof(a[0]))
865 static const u_int modeflags[] = {
866 0, /* IEEE80211_MODE_AUTO */
867 CHANNEL_A, /* IEEE80211_MODE_11A */
868 CHANNEL_B, /* IEEE80211_MODE_11B */
869 CHANNEL_PUREG, /* IEEE80211_MODE_11G */
870 0, /* IEEE80211_MODE_FH */
871 CHANNEL_T, /* IEEE80211_MODE_TURBO_A */
872 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */
874 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan);
876 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode));
877 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode));
878 return modeflags[mode];
885 struct ath_softc *sc = (struct ath_softc *) arg;
886 struct ieee80211com *ic = &sc->sc_ic;
887 struct ifnet *ifp = sc->sc_ifp;
888 struct ath_hal *ah = sc->sc_ah;
891 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
892 __func__, ifp->if_flags);
896 * Stop anything previously setup. This is safe
897 * whether this is the first time through or not.
899 ath_stop_locked(ifp);
902 * The basic interface to setting the hardware in a good
903 * state is ``reset''. On return the hardware is known to
904 * be powered up and with interrupts disabled. This must
905 * be followed by initialization of the appropriate bits
906 * and then setup of the interrupt mask.
908 sc->sc_curchan.channel = ic->ic_curchan->ic_freq;
909 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan);
910 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_FALSE, &status)) {
911 if_printf(ifp, "unable to reset hardware; hal status %u\n",
917 * This is needed only to setup initial state
918 * but it's best done after a reset.
920 ath_update_txpow(sc);
922 * Likewise this is set during reset so update
923 * state cached in the driver.
925 sc->sc_diversity = ath_hal_getdiversity(ah);
928 * Setup the hardware after reset: the key cache
929 * is filled as needed and the receive engine is
930 * set going. Frame transmit is handled entirely
931 * in the frame output path; there's nothing to do
932 * here except setup the interrupt mask.
934 if (ath_startrecv(sc) != 0) {
935 if_printf(ifp, "unable to start recv logic\n");
942 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
943 | HAL_INT_RXEOL | HAL_INT_RXORN
944 | HAL_INT_FATAL | HAL_INT_GLOBAL;
946 * Enable MIB interrupts when there are hardware phy counters.
947 * Note we only do this (at the moment) for station mode.
949 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
950 sc->sc_imask |= HAL_INT_MIB;
951 ath_hal_intrset(ah, sc->sc_imask);
953 ifp->if_drv_flags |= IFF_DRV_RUNNING;
954 ic->ic_state = IEEE80211_S_INIT;
957 * The hardware should be ready to go now so it's safe
958 * to kick the 802.11 state machine as it's likely to
959 * immediately call back to us to send mgmt frames.
961 ath_chan_change(sc, ic->ic_curchan);
963 if (sc->sc_tx99 != NULL)
964 sc->sc_tx99->start(sc->sc_tx99);
967 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
968 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
969 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
971 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
977 ath_stop_locked(struct ifnet *ifp)
979 struct ath_softc *sc = ifp->if_softc;
980 struct ieee80211com *ic = &sc->sc_ic;
981 struct ath_hal *ah = sc->sc_ah;
983 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
984 __func__, sc->sc_invalid, ifp->if_flags);
987 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
989 * Shutdown the hardware and driver:
990 * reset 802.11 state machine
994 * clear transmit machinery
995 * clear receive machinery
996 * drain and release tx queues
997 * reclaim beacon resources
998 * power down hardware
1000 * Note that some of this work is not possible if the
1001 * hardware is gone (invalid).
1003 #ifdef ATH_TX99_DIAG
1004 if (sc->sc_tx99 != NULL)
1005 sc->sc_tx99->stop(sc->sc_tx99);
1007 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1008 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1010 if (!sc->sc_invalid) {
1011 if (sc->sc_softled) {
1012 callout_stop(&sc->sc_ledtimer);
1013 ath_hal_gpioset(ah, sc->sc_ledpin,
1015 sc->sc_blinking = 0;
1017 ath_hal_intrset(ah, 0);
1020 if (!sc->sc_invalid) {
1022 ath_hal_phydisable(ah);
1024 sc->sc_rxlink = NULL;
1025 IFQ_DRV_PURGE(&ifp->if_snd);
1026 ath_beacon_free(sc);
1031 ath_stop(struct ifnet *ifp)
1033 struct ath_softc *sc = ifp->if_softc;
1036 ath_stop_locked(ifp);
1037 if (!sc->sc_invalid) {
1039 * Set the chip in full sleep mode. Note that we are
1040 * careful to do this only when bringing the interface
1041 * completely to a stop. When the chip is in this state
1042 * it must be carefully woken up or references to
1043 * registers in the PCI clock domain may freeze the bus
1044 * (and system). This varies by chip and is mostly an
1045 * issue with newer parts that go to sleep more quickly.
1047 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP, 0);
1053 * Reset the hardware w/o losing operational state. This is
1054 * basically a more efficient way of doing ath_stop, ath_init,
1055 * followed by state transitions to the current 802.11
1056 * operational state. Used to recover from various errors and
1057 * to reset or reload hardware state.
1060 ath_reset(struct ifnet *ifp)
1062 struct ath_softc *sc = ifp->if_softc;
1063 struct ieee80211com *ic = &sc->sc_ic;
1064 struct ath_hal *ah = sc->sc_ah;
1065 struct ieee80211_channel *c;
1069 * Convert to a HAL channel description with the flags
1070 * constrained to reflect the current operating mode.
1073 sc->sc_curchan.channel = c->ic_freq;
1074 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c);
1076 ath_hal_intrset(ah, 0); /* disable interrupts */
1077 ath_draintxq(sc); /* stop xmit side */
1078 ath_stoprecv(sc); /* stop recv side */
1079 /* NB: indicate channel change so we do a full reset */
1080 if (!ath_hal_reset(ah, sc->sc_opmode, &sc->sc_curchan, AH_TRUE, &status))
1081 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
1083 ath_update_txpow(sc); /* update tx power state */
1084 sc->sc_diversity = ath_hal_getdiversity(ah);
1085 if (ath_startrecv(sc) != 0) /* restart recv */
1086 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
1088 * We may be doing a reset in response to an ioctl
1089 * that changes the channel so update any state that
1090 * might change as a result.
1092 ath_chan_change(sc, c);
1093 if (ic->ic_state == IEEE80211_S_RUN)
1094 ath_beacon_config(sc); /* restart beacons */
1095 ath_hal_intrset(ah, sc->sc_imask);
1097 ath_start(ifp); /* restart xmit */
1102 ath_start(struct ifnet *ifp)
1104 struct ath_softc *sc = ifp->if_softc;
1105 struct ath_hal *ah = sc->sc_ah;
1106 struct ieee80211com *ic = &sc->sc_ic;
1107 struct ieee80211_node *ni;
1110 struct ieee80211_frame *wh;
1111 struct ether_header *eh;
1113 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
1117 * Grab a TX buffer and associated resources.
1120 bf = STAILQ_FIRST(&sc->sc_txbuf);
1122 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
1123 ATH_TXBUF_UNLOCK(sc);
1125 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: out of xmit buffers\n",
1127 sc->sc_stats.ast_tx_qstop++;
1128 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1132 * Poll the management queue for frames; they
1133 * have priority over normal data frames.
1135 IF_DEQUEUE(&ic->ic_mgtq, m);
1138 * No data frames go out unless we're associated.
1140 if (ic->ic_state != IEEE80211_S_RUN) {
1141 DPRINTF(sc, ATH_DEBUG_XMIT,
1142 "%s: discard data packet, state %s\n",
1144 ieee80211_state_name[ic->ic_state]);
1145 sc->sc_stats.ast_tx_discard++;
1147 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1148 ATH_TXBUF_UNLOCK(sc);
1151 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */
1154 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1155 ATH_TXBUF_UNLOCK(sc);
1159 * Find the node for the destination so we can do
1160 * things like power save and fast frames aggregation.
1162 if (m->m_len < sizeof(struct ether_header) &&
1163 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) {
1164 ic->ic_stats.is_tx_nobuf++; /* XXX */
1168 eh = mtod(m, struct ether_header *);
1169 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1171 /* NB: ieee80211_find_txnode does stat+msg */
1175 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) &&
1176 (m->m_flags & M_PWR_SAV) == 0) {
1178 * Station in power save mode; pass the frame
1179 * to the 802.11 layer and continue. We'll get
1180 * the frame back when the time is right.
1182 ieee80211_pwrsave(ic, ni, m);
1185 /* calculate priority so we can find the tx queue */
1186 if (ieee80211_classify(ic, m, ni)) {
1187 DPRINTF(sc, ATH_DEBUG_XMIT,
1188 "%s: discard, classification failure\n",
1196 * Encapsulate the packet in prep for transmission.
1198 m = ieee80211_encap(ic, m, ni);
1200 DPRINTF(sc, ATH_DEBUG_XMIT,
1201 "%s: encapsulation failure\n",
1203 sc->sc_stats.ast_tx_encap++;
1208 * Hack! The referenced node pointer is in the
1209 * rcvif field of the packet header. This is
1210 * placed there by ieee80211_mgmt_output because
1211 * we need to hold the reference with the frame
1212 * and there's no other way (other than packet
1213 * tags which we consider too expensive to use)
1216 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1217 m->m_pkthdr.rcvif = NULL;
1219 wh = mtod(m, struct ieee80211_frame *);
1220 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1221 IEEE80211_FC0_SUBTYPE_PROBE_RESP) {
1222 /* fill time stamp */
1226 tsf = ath_hal_gettsf64(ah);
1227 /* XXX: adjust 100us delay to xmit */
1229 tstamp = (u_int32_t *)&wh[1];
1230 tstamp[0] = htole32(tsf & 0xffffffff);
1231 tstamp[1] = htole32(tsf >> 32);
1233 sc->sc_stats.ast_tx_mgmt++;
1236 if (ath_tx_start(sc, ni, bf, m)) {
1241 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1242 ATH_TXBUF_UNLOCK(sc);
1244 ieee80211_free_node(ni);
1248 sc->sc_tx_timer = 5;
1254 ath_media_change(struct ifnet *ifp)
1256 #define IS_UP(ifp) \
1257 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
1260 error = ieee80211_media_change(ifp);
1261 if (error == ENETRESET) {
1262 struct ath_softc *sc = ifp->if_softc;
1263 struct ieee80211com *ic = &sc->sc_ic;
1265 if (ic->ic_opmode == IEEE80211_M_AHDEMO) {
1267 * Adhoc demo mode is just ibss mode w/o beacons
1268 * (mostly). The hal knows nothing about it;
1269 * tell it we're operating in ibss mode.
1271 sc->sc_opmode = HAL_M_IBSS;
1273 sc->sc_opmode = ic->ic_opmode;
1275 ath_init(ifp->if_softc); /* XXX lose error */
1284 ath_keyprint(const char *tag, u_int ix,
1285 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1287 static const char *ciphers[] = {
1297 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]);
1298 for (i = 0, n = hk->kv_len; i < n; i++)
1299 printf("%02x", hk->kv_val[i]);
1300 printf(" mac %s", ether_sprintf(mac));
1301 if (hk->kv_type == HAL_CIPHER_TKIP) {
1303 for (i = 0; i < sizeof(hk->kv_mic); i++)
1304 printf("%02x", hk->kv_mic[i]);
1311 * Set a TKIP key into the hardware. This handles the
1312 * potential distribution of key state to multiple key
1313 * cache slots for TKIP.
1316 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k,
1317 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1319 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV)
1320 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN];
1321 struct ath_hal *ah = sc->sc_ah;
1323 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP,
1324 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher));
1325 KASSERT(sc->sc_splitmic, ("key cache !split"));
1326 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) {
1328 * TX key goes at first index, RX key at the rx index.
1329 * The hal handles the MIC keys at index+64.
1331 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic));
1332 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid);
1333 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid))
1336 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1337 KEYPRINTF(sc, k->wk_keyix+32, hk, mac);
1338 /* XXX delete tx key on failure? */
1339 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac);
1340 } else if (k->wk_flags & IEEE80211_KEY_XR) {
1342 * TX/RX key goes at first index.
1343 * The hal handles the MIC keys are index+64.
1345 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ?
1346 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic));
1347 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1348 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1351 #undef IEEE80211_KEY_XR
1355 * Set a net80211 key into the hardware. This handles the
1356 * potential distribution of key state to multiple key
1357 * cache slots for TKIP with hardware MIC support.
1360 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k,
1361 const u_int8_t mac0[IEEE80211_ADDR_LEN],
1362 struct ieee80211_node *bss)
1364 #define N(a) (sizeof(a)/sizeof(a[0]))
1365 static const u_int8_t ciphermap[] = {
1366 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */
1367 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */
1368 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */
1369 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */
1370 (u_int8_t) -1, /* 4 is not allocated */
1371 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */
1372 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */
1374 struct ath_hal *ah = sc->sc_ah;
1375 const struct ieee80211_cipher *cip = k->wk_cipher;
1376 u_int8_t gmac[IEEE80211_ADDR_LEN];
1377 const u_int8_t *mac;
1380 memset(&hk, 0, sizeof(hk));
1382 * Software crypto uses a "clear key" so non-crypto
1383 * state kept in the key cache are maintained and
1384 * so that rx frames have an entry to match.
1386 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) {
1387 KASSERT(cip->ic_cipher < N(ciphermap),
1388 ("invalid cipher type %u", cip->ic_cipher));
1389 hk.kv_type = ciphermap[cip->ic_cipher];
1390 hk.kv_len = k->wk_keylen;
1391 memcpy(hk.kv_val, k->wk_key, k->wk_keylen);
1393 hk.kv_type = HAL_CIPHER_CLR;
1395 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) {
1397 * Group keys on hardware that supports multicast frame
1398 * key search use a mac that is the sender's address with
1399 * the high bit set instead of the app-specified address.
1401 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr);
1407 if (hk.kv_type == HAL_CIPHER_TKIP &&
1408 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 &&
1410 return ath_keyset_tkip(sc, k, &hk, mac);
1412 KEYPRINTF(sc, k->wk_keyix, &hk, mac);
1413 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac);
1419 * Allocate tx/rx key slots for TKIP. We allocate two slots for
1420 * each key, one for decrypt/encrypt and the other for the MIC.
1423 key_alloc_2pair(struct ath_softc *sc,
1424 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
1426 #define N(a) (sizeof(a)/sizeof(a[0]))
1429 KASSERT(sc->sc_splitmic, ("key cache !split"));
1430 /* XXX could optimize */
1431 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
1432 u_int8_t b = sc->sc_keymap[i];
1435 * One or more slots in this byte are free.
1443 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */
1444 if (isset(sc->sc_keymap, keyix+32) ||
1445 isset(sc->sc_keymap, keyix+64) ||
1446 isset(sc->sc_keymap, keyix+32+64)) {
1447 /* full pair unavailable */
1449 if (keyix == (i+1)*NBBY) {
1450 /* no slots were appropriate, advance */
1455 setbit(sc->sc_keymap, keyix);
1456 setbit(sc->sc_keymap, keyix+64);
1457 setbit(sc->sc_keymap, keyix+32);
1458 setbit(sc->sc_keymap, keyix+32+64);
1459 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1460 "%s: key pair %u,%u %u,%u\n",
1461 __func__, keyix, keyix+64,
1462 keyix+32, keyix+32+64);
1464 *rxkeyix = keyix+32;
1468 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
1474 * Allocate a single key cache slot.
1477 key_alloc_single(struct ath_softc *sc,
1478 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix)
1480 #define N(a) (sizeof(a)/sizeof(a[0]))
1483 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */
1484 for (i = 0; i < N(sc->sc_keymap); i++) {
1485 u_int8_t b = sc->sc_keymap[i];
1488 * One or more slots are free.
1493 setbit(sc->sc_keymap, keyix);
1494 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n",
1496 *txkeyix = *rxkeyix = keyix;
1500 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__);
1506 * Allocate one or more key cache slots for a uniacst key. The
1507 * key itself is needed only to identify the cipher. For hardware
1508 * TKIP with split cipher+MIC keys we allocate two key cache slot
1509 * pairs so that we can setup separate TX and RX MIC keys. Note
1510 * that the MIC key for a TKIP key at slot i is assumed by the
1511 * hardware to be at slot i+64. This limits TKIP keys to the first
1515 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k,
1516 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix)
1518 struct ath_softc *sc = ic->ic_ifp->if_softc;
1521 * Group key allocation must be handled specially for
1522 * parts that do not support multicast key cache search
1523 * functionality. For those parts the key id must match
1524 * the h/w key index so lookups find the right key. On
1525 * parts w/ the key search facility we install the sender's
1526 * mac address (with the high bit set) and let the hardware
1527 * find the key w/o using the key id. This is preferred as
1528 * it permits us to support multiple users for adhoc and/or
1529 * multi-station operation.
1531 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) {
1532 if (!(&ic->ic_nw_keys[0] <= k &&
1533 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) {
1534 /* should not happen */
1535 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1536 "%s: bogus group key\n", __func__);
1540 * XXX we pre-allocate the global keys so
1541 * have no way to check if they've already been allocated.
1543 *keyix = *rxkeyix = k - ic->ic_nw_keys;
1548 * We allocate two pair for TKIP when using the h/w to do
1549 * the MIC. For everything else, including software crypto,
1550 * we allocate a single entry. Note that s/w crypto requires
1551 * a pass-through slot on the 5211 and 5212. The 5210 does
1552 * not support pass-through cache entries and we map all
1553 * those requests to slot 0.
1555 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
1556 return key_alloc_single(sc, keyix, rxkeyix);
1557 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP &&
1558 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) {
1559 return key_alloc_2pair(sc, keyix, rxkeyix);
1561 return key_alloc_single(sc, keyix, rxkeyix);
1566 * Delete an entry in the key cache allocated by ath_key_alloc.
1569 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
1571 struct ath_softc *sc = ic->ic_ifp->if_softc;
1572 struct ath_hal *ah = sc->sc_ah;
1573 const struct ieee80211_cipher *cip = k->wk_cipher;
1574 u_int keyix = k->wk_keyix;
1576 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix);
1578 ath_hal_keyreset(ah, keyix);
1580 * Handle split tx/rx keying required for TKIP with h/w MIC.
1582 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1583 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic)
1584 ath_hal_keyreset(ah, keyix+32); /* RX key */
1585 if (keyix >= IEEE80211_WEP_NKID) {
1587 * Don't touch keymap entries for global keys so
1588 * they are never considered for dynamic allocation.
1590 clrbit(sc->sc_keymap, keyix);
1591 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1592 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 &&
1594 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */
1595 clrbit(sc->sc_keymap, keyix+32); /* RX key */
1596 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */
1603 * Set the key cache contents for the specified key. Key cache
1604 * slot(s) must already have been allocated by ath_key_alloc.
1607 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
1608 const u_int8_t mac[IEEE80211_ADDR_LEN])
1610 struct ath_softc *sc = ic->ic_ifp->if_softc;
1612 return ath_keyset(sc, k, mac, ic->ic_bss);
1616 * Block/unblock tx+rx processing while a key change is done.
1617 * We assume the caller serializes key management operations
1618 * so we only need to worry about synchronization with other
1619 * uses that originate in the driver.
1622 ath_key_update_begin(struct ieee80211com *ic)
1624 struct ifnet *ifp = ic->ic_ifp;
1625 struct ath_softc *sc = ifp->if_softc;
1627 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1629 tasklet_disable(&sc->sc_rxtq);
1631 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
1635 ath_key_update_end(struct ieee80211com *ic)
1637 struct ifnet *ifp = ic->ic_ifp;
1638 struct ath_softc *sc = ifp->if_softc;
1640 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1641 IF_UNLOCK(&ifp->if_snd);
1643 tasklet_enable(&sc->sc_rxtq);
1648 * Calculate the receive filter according to the
1649 * operating mode and state:
1651 * o always accept unicast, broadcast, and multicast traffic
1652 * o maintain current state of phy error reception (the hal
1653 * may enable phy error frames for noise immunity work)
1654 * o probe request frames are accepted only when operating in
1655 * hostap, adhoc, or monitor modes
1656 * o enable promiscuous mode according to the interface state
1658 * - when operating in adhoc mode so the 802.11 layer creates
1659 * node table entries for peers,
1660 * - when operating in station mode for collecting rssi data when
1661 * the station is otherwise quiet, or
1665 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state)
1667 struct ieee80211com *ic = &sc->sc_ic;
1668 struct ath_hal *ah = sc->sc_ah;
1669 struct ifnet *ifp = sc->sc_ifp;
1672 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR)
1673 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
1674 if (ic->ic_opmode != IEEE80211_M_STA)
1675 rfilt |= HAL_RX_FILTER_PROBEREQ;
1676 if (ic->ic_opmode != IEEE80211_M_HOSTAP &&
1677 (ifp->if_flags & IFF_PROMISC))
1678 rfilt |= HAL_RX_FILTER_PROM;
1679 if (ic->ic_opmode == IEEE80211_M_STA ||
1680 ic->ic_opmode == IEEE80211_M_IBSS ||
1681 state == IEEE80211_S_SCAN)
1682 rfilt |= HAL_RX_FILTER_BEACON;
1687 ath_mode_init(struct ath_softc *sc)
1689 struct ieee80211com *ic = &sc->sc_ic;
1690 struct ath_hal *ah = sc->sc_ah;
1691 struct ifnet *ifp = sc->sc_ifp;
1692 u_int32_t rfilt, mfilt[2], val;
1694 struct ifmultiaddr *ifma;
1696 /* configure rx filter */
1697 rfilt = ath_calcrxfilter(sc, ic->ic_state);
1698 ath_hal_setrxfilter(ah, rfilt);
1700 /* configure operational mode */
1701 ath_hal_setopmode(ah);
1704 * Handle any link-level address change. Note that we only
1705 * need to force ic_myaddr; any other addresses are handled
1706 * as a byproduct of the ifnet code marking the interface
1709 * XXX should get from lladdr instead of arpcom but that's more work
1711 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp));
1712 ath_hal_setmac(ah, ic->ic_myaddr);
1714 /* calculate and install multicast filter */
1715 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
1716 mfilt[0] = mfilt[1] = 0;
1718 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1721 /* calculate XOR of eight 6bit values */
1722 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
1723 val = LE_READ_4(dl + 0);
1724 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1725 val = LE_READ_4(dl + 3);
1726 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1728 mfilt[pos / 32] |= (1 << (pos % 32));
1730 IF_ADDR_UNLOCK(ifp);
1732 mfilt[0] = mfilt[1] = ~0;
1734 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]);
1735 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n",
1736 __func__, rfilt, mfilt[0], mfilt[1]);
1740 * Set the slot time based on the current setting.
1743 ath_setslottime(struct ath_softc *sc)
1745 struct ieee80211com *ic = &sc->sc_ic;
1746 struct ath_hal *ah = sc->sc_ah;
1748 if (ic->ic_flags & IEEE80211_F_SHSLOT)
1749 ath_hal_setslottime(ah, HAL_SLOT_TIME_9);
1751 ath_hal_setslottime(ah, HAL_SLOT_TIME_20);
1752 sc->sc_updateslot = OK;
1756 * Callback from the 802.11 layer to update the
1757 * slot time based on the current setting.
1760 ath_updateslot(struct ifnet *ifp)
1762 struct ath_softc *sc = ifp->if_softc;
1763 struct ieee80211com *ic = &sc->sc_ic;
1766 * When not coordinating the BSS, change the hardware
1767 * immediately. For other operation we defer the change
1768 * until beacon updates have propagated to the stations.
1770 if (ic->ic_opmode == IEEE80211_M_HOSTAP)
1771 sc->sc_updateslot = UPDATE;
1773 ath_setslottime(sc);
1777 * Setup a h/w transmit queue for beacons.
1780 ath_beaconq_setup(struct ath_hal *ah)
1784 memset(&qi, 0, sizeof(qi));
1785 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
1786 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
1787 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
1788 /* NB: for dynamic turbo, don't enable any other interrupts */
1789 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1790 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
1794 * Setup the transmit queue parameters for the beacon queue.
1797 ath_beaconq_config(struct ath_softc *sc)
1799 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
1800 struct ieee80211com *ic = &sc->sc_ic;
1801 struct ath_hal *ah = sc->sc_ah;
1804 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
1805 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1807 * Always burst out beacon and CAB traffic.
1809 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
1810 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
1811 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
1813 struct wmeParams *wmep =
1814 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
1816 * Adhoc mode; important thing is to use 2x cwmin.
1818 qi.tqi_aifs = wmep->wmep_aifsn;
1819 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
1820 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
1823 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
1824 device_printf(sc->sc_dev, "unable to update parameters for "
1825 "beacon hardware queue!\n");
1828 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
1831 #undef ATH_EXPONENT_TO_VALUE
1835 * Allocate and setup an initial beacon frame.
1838 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
1840 struct ieee80211com *ic = ni->ni_ic;
1845 bf = STAILQ_FIRST(&sc->sc_bbuf);
1847 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__);
1848 sc->sc_stats.ast_be_nombuf++; /* XXX */
1849 return ENOMEM; /* XXX */
1852 * NB: the beacon data buffer must be 32-bit aligned;
1853 * we assume the mbuf routines will return us something
1854 * with this alignment (perhaps should assert).
1856 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff);
1858 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n",
1860 sc->sc_stats.ast_be_nombuf++;
1863 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
1864 bf->bf_segs, &bf->bf_nseg,
1868 bf->bf_node = ieee80211_ref_node(ni);
1876 * Setup the beacon frame for transmit.
1879 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
1881 #define USE_SHPREAMBLE(_ic) \
1882 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
1883 == IEEE80211_F_SHPREAMBLE)
1884 struct ieee80211_node *ni = bf->bf_node;
1885 struct ieee80211com *ic = ni->ni_ic;
1886 struct mbuf *m = bf->bf_m;
1887 struct ath_hal *ah = sc->sc_ah;
1888 struct ath_desc *ds;
1890 const HAL_RATE_TABLE *rt;
1893 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n",
1894 __func__, m, m->m_len);
1896 /* setup descriptors */
1899 flags = HAL_TXDESC_NOACK;
1900 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
1901 ds->ds_link = bf->bf_daddr; /* self-linked */
1902 flags |= HAL_TXDESC_VEOL;
1904 * Let hardware handle antenna switching.
1906 antenna = sc->sc_txantenna;
1910 * Switch antenna every 4 beacons.
1911 * XXX assumes two antenna
1913 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
1916 KASSERT(bf->bf_nseg == 1,
1917 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
1918 ds->ds_data = bf->bf_segs[0].ds_addr;
1920 * Calculate rate code.
1921 * XXX everything at min xmit rate
1923 rix = sc->sc_minrateix;
1924 rt = sc->sc_currates;
1925 rate = rt->info[rix].rateCode;
1926 if (USE_SHPREAMBLE(ic))
1927 rate |= rt->info[rix].shortPreamble;
1928 ath_hal_setuptxdesc(ah, ds
1929 , m->m_len + IEEE80211_CRC_LEN /* frame length */
1930 , sizeof(struct ieee80211_frame)/* header length */
1931 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
1932 , ni->ni_txpower /* txpower XXX */
1933 , rate, 1 /* series 0 rate/tries */
1934 , HAL_TXKEYIX_INVALID /* no encryption */
1935 , antenna /* antenna mode */
1936 , flags /* no ack, veol for beacons */
1937 , 0 /* rts/cts rate */
1938 , 0 /* rts/cts duration */
1940 /* NB: beacon's BufLen must be a multiple of 4 bytes */
1941 ath_hal_filltxdesc(ah, ds
1942 , roundup(m->m_len, 4) /* buffer length */
1943 , AH_TRUE /* first segment */
1944 , AH_TRUE /* last segment */
1945 , ds /* first descriptor */
1947 #undef USE_SHPREAMBLE
1951 * Transmit a beacon frame at SWBA. Dynamic updates to the
1952 * frame contents are done as needed and the slot time is
1953 * also adjusted based on current state.
1956 ath_beacon_proc(void *arg, int pending)
1958 struct ath_softc *sc = arg;
1959 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
1960 struct ieee80211_node *ni = bf->bf_node;
1961 struct ieee80211com *ic = ni->ni_ic;
1962 struct ath_hal *ah = sc->sc_ah;
1964 int ncabq, error, otherant;
1966 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n",
1969 if (ic->ic_opmode == IEEE80211_M_STA ||
1970 ic->ic_opmode == IEEE80211_M_MONITOR ||
1971 bf == NULL || bf->bf_m == NULL) {
1972 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n",
1973 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL);
1977 * Check if the previous beacon has gone out. If
1978 * not don't don't try to post another, skip this
1979 * period and wait for the next. Missed beacons
1980 * indicate a problem and should not occur. If we
1981 * miss too many consecutive beacons reset the device.
1983 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
1984 sc->sc_bmisscount++;
1985 DPRINTF(sc, ATH_DEBUG_BEACON_PROC,
1986 "%s: missed %u consecutive beacons\n",
1987 __func__, sc->sc_bmisscount);
1988 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */
1989 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
1992 if (sc->sc_bmisscount != 0) {
1993 DPRINTF(sc, ATH_DEBUG_BEACON,
1994 "%s: resume beacon xmit after %u misses\n",
1995 __func__, sc->sc_bmisscount);
1996 sc->sc_bmisscount = 0;
2000 * Update dynamic beacon contents. If this returns
2001 * non-zero then we need to remap the memory because
2002 * the beacon frame changed size (probably because
2003 * of the TIM bitmap).
2006 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum);
2007 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) {
2008 /* XXX too conservative? */
2009 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2010 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
2011 bf->bf_segs, &bf->bf_nseg,
2014 if_printf(ic->ic_ifp,
2015 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
2022 * Handle slot time change when a non-ERP station joins/leaves
2023 * an 11g network. The 802.11 layer notifies us via callback,
2024 * we mark updateslot, then wait one beacon before effecting
2025 * the change. This gives associated stations at least one
2026 * beacon interval to note the state change.
2029 if (sc->sc_updateslot == UPDATE)
2030 sc->sc_updateslot = COMMIT; /* commit next beacon */
2031 else if (sc->sc_updateslot == COMMIT)
2032 ath_setslottime(sc); /* commit change to h/w */
2035 * Check recent per-antenna transmit statistics and flip
2036 * the default antenna if noticeably more frames went out
2037 * on the non-default antenna.
2038 * XXX assumes 2 anntenae
2040 otherant = sc->sc_defant & 1 ? 2 : 1;
2041 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
2042 ath_setdefantenna(sc, otherant);
2043 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
2046 * Construct tx descriptor.
2048 ath_beacon_setup(sc, bf);
2051 * Stop any current dma and put the new frame on the queue.
2052 * This should never fail since we check above that no frames
2053 * are still pending on the queue.
2055 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
2056 DPRINTF(sc, ATH_DEBUG_ANY,
2057 "%s: beacon queue %u did not stop?\n",
2058 __func__, sc->sc_bhalq);
2060 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
2063 * Enable the CAB queue before the beacon queue to
2064 * insure cab frames are triggered by this beacon.
2066 if (ncabq != 0 && (sc->sc_boff.bo_tim[4] & 1)) /* NB: only at DTIM */
2067 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum);
2068 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
2069 ath_hal_txstart(ah, sc->sc_bhalq);
2070 DPRINTF(sc, ATH_DEBUG_BEACON_PROC,
2071 "%s: TXDP[%u] = %p (%p)\n", __func__,
2072 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc);
2074 sc->sc_stats.ast_be_xmit++;
2078 * Reset the hardware after detecting beacons have stopped.
2081 ath_bstuck_proc(void *arg, int pending)
2083 struct ath_softc *sc = arg;
2084 struct ifnet *ifp = sc->sc_ifp;
2086 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
2092 * Reclaim beacon resources.
2095 ath_beacon_free(struct ath_softc *sc)
2099 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
2100 if (bf->bf_m != NULL) {
2101 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2105 if (bf->bf_node != NULL) {
2106 ieee80211_free_node(bf->bf_node);
2113 * Configure the beacon and sleep timers.
2115 * When operating as an AP this resets the TSF and sets
2116 * up the hardware to notify us when we need to issue beacons.
2118 * When operating in station mode this sets up the beacon
2119 * timers according to the timestamp of the last received
2120 * beacon and the current TSF, configures PCF and DTIM
2121 * handling, programs the sleep registers so the hardware
2122 * will wakeup in time to receive beacons, and configures
2123 * the beacon miss handling so we'll receive a BMISS
2124 * interrupt when we stop seeing beacons from the AP
2125 * we've associated with.
2128 ath_beacon_config(struct ath_softc *sc)
2130 #define TSF_TO_TU(_h,_l) \
2131 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
2133 struct ath_hal *ah = sc->sc_ah;
2134 struct ieee80211com *ic = &sc->sc_ic;
2135 struct ieee80211_node *ni = ic->ic_bss;
2136 u_int32_t nexttbtt, intval, tsftu;
2139 /* extract tstamp from last beacon and convert to TU */
2140 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4),
2141 LE_READ_4(ni->ni_tstamp.data));
2142 /* NB: the beacon interval is kept internally in TU's */
2143 intval = ni->ni_intval & HAL_BEACON_PERIOD;
2144 if (nexttbtt == 0) /* e.g. for ap mode */
2146 else if (intval) /* NB: can be 0 for monitor mode */
2147 nexttbtt = roundup(nexttbtt, intval);
2148 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
2149 __func__, nexttbtt, intval, ni->ni_intval);
2150 if (ic->ic_opmode == IEEE80211_M_STA) {
2151 HAL_BEACON_STATE bs;
2152 int dtimperiod, dtimcount;
2153 int cfpperiod, cfpcount;
2156 * Setup dtim and cfp parameters according to
2157 * last beacon we received (which may be none).
2159 dtimperiod = ni->ni_dtim_period;
2160 if (dtimperiod <= 0) /* NB: 0 if not known */
2162 dtimcount = ni->ni_dtim_count;
2163 if (dtimcount >= dtimperiod) /* NB: sanity check */
2164 dtimcount = 0; /* XXX? */
2165 cfpperiod = 1; /* NB: no PCF support yet */
2168 * Pull nexttbtt forward to reflect the current
2169 * TSF and calculate dtim+cfp state for the result.
2171 tsf = ath_hal_gettsf64(ah);
2172 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
2175 if (--dtimcount < 0) {
2176 dtimcount = dtimperiod - 1;
2178 cfpcount = cfpperiod - 1;
2180 } while (nexttbtt < tsftu);
2181 memset(&bs, 0, sizeof(bs));
2182 bs.bs_intval = intval;
2183 bs.bs_nexttbtt = nexttbtt;
2184 bs.bs_dtimperiod = dtimperiod*intval;
2185 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
2186 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
2187 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
2188 bs.bs_cfpmaxduration = 0;
2191 * The 802.11 layer records the offset to the DTIM
2192 * bitmap while receiving beacons; use it here to
2193 * enable h/w detection of our AID being marked in
2194 * the bitmap vector (to indicate frames for us are
2195 * pending at the AP).
2196 * XXX do DTIM handling in s/w to WAR old h/w bugs
2197 * XXX enable based on h/w rev for newer chips
2199 bs.bs_timoffset = ni->ni_timoff;
2202 * Calculate the number of consecutive beacons to miss
2203 * before taking a BMISS interrupt. The configuration
2204 * is specified in ms, so we need to convert that to
2205 * TU's and then calculate based on the beacon interval.
2206 * Note that we clamp the result to at most 10 beacons.
2208 bs.bs_bmissthreshold = ic->ic_bmissthreshold;
2209 if (bs.bs_bmissthreshold > 10)
2210 bs.bs_bmissthreshold = 10;
2211 else if (bs.bs_bmissthreshold <= 0)
2212 bs.bs_bmissthreshold = 1;
2215 * Calculate sleep duration. The configuration is
2216 * given in ms. We insure a multiple of the beacon
2217 * period is used. Also, if the sleep duration is
2218 * greater than the DTIM period then it makes senses
2219 * to make it a multiple of that.
2221 * XXX fixed at 100ms
2223 bs.bs_sleepduration =
2224 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
2225 if (bs.bs_sleepduration > bs.bs_dtimperiod)
2226 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
2228 DPRINTF(sc, ATH_DEBUG_BEACON,
2229 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n"
2236 , bs.bs_bmissthreshold
2237 , bs.bs_sleepduration
2239 , bs.bs_cfpmaxduration
2243 ath_hal_intrset(ah, 0);
2244 ath_hal_beacontimers(ah, &bs);
2245 sc->sc_imask |= HAL_INT_BMISS;
2246 ath_hal_intrset(ah, sc->sc_imask);
2248 ath_hal_intrset(ah, 0);
2249 if (nexttbtt == intval)
2250 intval |= HAL_BEACON_RESET_TSF;
2251 if (ic->ic_opmode == IEEE80211_M_IBSS) {
2253 * In IBSS mode enable the beacon timers but only
2254 * enable SWBA interrupts if we need to manually
2255 * prepare beacon frames. Otherwise we use a
2256 * self-linked tx descriptor and let the hardware
2259 intval |= HAL_BEACON_ENA;
2260 if (!sc->sc_hasveol)
2261 sc->sc_imask |= HAL_INT_SWBA;
2262 if ((intval & HAL_BEACON_RESET_TSF) == 0) {
2264 * Pull nexttbtt forward to reflect
2267 tsf = ath_hal_gettsf64(ah);
2268 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
2271 } while (nexttbtt < tsftu);
2273 ath_beaconq_config(sc);
2274 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
2276 * In AP mode we enable the beacon timers and
2277 * SWBA interrupts to prepare beacon frames.
2279 intval |= HAL_BEACON_ENA;
2280 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
2281 ath_beaconq_config(sc);
2283 ath_hal_beaconinit(ah, nexttbtt, intval);
2284 sc->sc_bmisscount = 0;
2285 ath_hal_intrset(ah, sc->sc_imask);
2287 * When using a self-linked beacon descriptor in
2288 * ibss mode load it once here.
2290 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
2291 ath_beacon_proc(sc, 0);
2293 sc->sc_syncbeacon = 0;
2299 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2301 bus_addr_t *paddr = (bus_addr_t*) arg;
2302 KASSERT(error == 0, ("error %u on bus_dma callback", error));
2303 *paddr = segs->ds_addr;
2307 ath_descdma_setup(struct ath_softc *sc,
2308 struct ath_descdma *dd, ath_bufhead *head,
2309 const char *name, int nbuf, int ndesc)
2311 #define DS2PHYS(_dd, _ds) \
2312 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2313 struct ifnet *ifp = sc->sc_ifp;
2314 struct ath_desc *ds;
2316 int i, bsize, error;
2318 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n",
2319 __func__, name, nbuf, ndesc);
2322 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2325 * Setup DMA descriptor area.
2327 error = bus_dma_tag_create(NULL, /* parent */
2328 PAGE_SIZE, 0, /* alignment, bounds */
2329 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2330 BUS_SPACE_MAXADDR, /* highaddr */
2331 NULL, NULL, /* filter, filterarg */
2332 dd->dd_desc_len, /* maxsize */
2334 BUS_SPACE_MAXADDR, /* maxsegsize */
2335 BUS_DMA_ALLOCNOW, /* flags */
2336 NULL, /* lockfunc */
2340 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
2344 /* allocate descriptors */
2345 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap);
2347 if_printf(ifp, "unable to create dmamap for %s descriptors, "
2348 "error %u\n", dd->dd_name, error);
2352 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
2353 BUS_DMA_NOWAIT, &dd->dd_dmamap);
2355 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
2356 "error %u\n", nbuf * ndesc, dd->dd_name, error);
2360 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
2361 dd->dd_desc, dd->dd_desc_len,
2362 ath_load_cb, &dd->dd_desc_paddr,
2365 if_printf(ifp, "unable to map %s descriptors, error %u\n",
2366 dd->dd_name, error);
2371 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
2372 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len,
2373 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len);
2375 /* allocate rx buffers */
2376 bsize = sizeof(struct ath_buf) * nbuf;
2377 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
2379 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
2380 dd->dd_name, bsize);
2386 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2388 bf->bf_daddr = DS2PHYS(dd, ds);
2389 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
2392 if_printf(ifp, "unable to create dmamap for %s "
2393 "buffer %u, error %u\n", dd->dd_name, i, error);
2394 ath_descdma_cleanup(sc, dd, head);
2397 STAILQ_INSERT_TAIL(head, bf, bf_list);
2401 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2403 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2405 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2407 bus_dma_tag_destroy(dd->dd_dmat);
2408 memset(dd, 0, sizeof(*dd));
2414 ath_descdma_cleanup(struct ath_softc *sc,
2415 struct ath_descdma *dd, ath_bufhead *head)
2418 struct ieee80211_node *ni;
2420 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2421 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2422 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2423 bus_dma_tag_destroy(dd->dd_dmat);
2425 STAILQ_FOREACH(bf, head, bf_list) {
2430 if (bf->bf_dmamap != NULL) {
2431 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
2432 bf->bf_dmamap = NULL;
2438 * Reclaim node reference.
2440 ieee80211_free_node(ni);
2445 free(dd->dd_bufptr, M_ATHDEV);
2446 memset(dd, 0, sizeof(*dd));
2450 ath_desc_alloc(struct ath_softc *sc)
2454 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
2455 "rx", ath_rxbuf, 1);
2459 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
2460 "tx", ath_txbuf, ATH_TXDESC);
2462 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2466 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
2469 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2470 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2477 ath_desc_free(struct ath_softc *sc)
2480 if (sc->sc_bdma.dd_desc_len != 0)
2481 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
2482 if (sc->sc_txdma.dd_desc_len != 0)
2483 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2484 if (sc->sc_rxdma.dd_desc_len != 0)
2485 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2488 static struct ieee80211_node *
2489 ath_node_alloc(struct ieee80211_node_table *nt)
2491 struct ieee80211com *ic = nt->nt_ic;
2492 struct ath_softc *sc = ic->ic_ifp->if_softc;
2493 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
2494 struct ath_node *an;
2496 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
2501 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER;
2502 ath_rate_node_init(sc, an);
2504 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an);
2505 return &an->an_node;
2509 ath_node_free(struct ieee80211_node *ni)
2511 struct ieee80211com *ic = ni->ni_ic;
2512 struct ath_softc *sc = ic->ic_ifp->if_softc;
2514 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni);
2516 ath_rate_node_cleanup(sc, ATH_NODE(ni));
2517 sc->sc_node_free(ni);
2521 ath_node_getrssi(const struct ieee80211_node *ni)
2523 #define HAL_EP_RND(x, mul) \
2524 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
2525 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi;
2529 * When only one frame is received there will be no state in
2530 * avgrssi so fallback on the value recorded by the 802.11 layer.
2532 if (avgrssi != ATH_RSSI_DUMMY_MARKER)
2533 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER);
2536 /* NB: theoretically we shouldn't need this, but be paranoid */
2537 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi;
2542 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
2544 struct ath_hal *ah = sc->sc_ah;
2547 struct ath_desc *ds;
2552 * NB: by assigning a page to the rx dma buffer we
2553 * implicitly satisfy the Atheros requirement that
2554 * this buffer be cache-line-aligned and sized to be
2555 * multiple of the cache line size. Not doing this
2556 * causes weird stuff to happen (for the 5210 at least).
2558 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2560 DPRINTF(sc, ATH_DEBUG_ANY,
2561 "%s: no mbuf/cluster\n", __func__);
2562 sc->sc_stats.ast_rx_nombuf++;
2566 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
2568 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
2570 bf->bf_segs, &bf->bf_nseg,
2573 DPRINTF(sc, ATH_DEBUG_ANY,
2574 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
2576 sc->sc_stats.ast_rx_busdma++;
2579 KASSERT(bf->bf_nseg == 1,
2580 ("multi-segment packet; nseg %u", bf->bf_nseg));
2582 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
2585 * Setup descriptors. For receive we always terminate
2586 * the descriptor list with a self-linked entry so we'll
2587 * not get overrun under high load (as can happen with a
2588 * 5212 when ANI processing enables PHY error frames).
2590 * To insure the last descriptor is self-linked we create
2591 * each descriptor as self-linked and add it to the end. As
2592 * each additional descriptor is added the previous self-linked
2593 * entry is ``fixed'' naturally. This should be safe even
2594 * if DMA is happening. When processing RX interrupts we
2595 * never remove/process the last, self-linked, entry on the
2596 * descriptor list. This insures the hardware always has
2597 * someplace to write a new frame.
2600 ds->ds_link = bf->bf_daddr; /* link to self */
2601 ds->ds_data = bf->bf_segs[0].ds_addr;
2602 ath_hal_setuprxdesc(ah, ds
2603 , m->m_len /* buffer size */
2607 if (sc->sc_rxlink != NULL)
2608 *sc->sc_rxlink = bf->bf_daddr;
2609 sc->sc_rxlink = &ds->ds_link;
2614 * Extend 15-bit time stamp from rx descriptor to
2615 * a full 64-bit TSF using the specified TSF.
2617 static __inline u_int64_t
2618 ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf)
2620 if ((tsf & 0x7fff) < rstamp)
2622 return ((tsf &~ 0x7fff) | rstamp);
2626 * Intercept management frames to collect beacon rssi data
2627 * and to do ibss merges.
2630 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
2631 struct ieee80211_node *ni,
2632 int subtype, int rssi, u_int32_t rstamp)
2634 struct ath_softc *sc = ic->ic_ifp->if_softc;
2637 * Call up first so subsequent work can use information
2638 * potentially stored in the node (e.g. for ibss merge).
2640 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp);
2642 case IEEE80211_FC0_SUBTYPE_BEACON:
2643 /* update rssi statistics for use by the hal */
2644 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
2645 if (sc->sc_syncbeacon &&
2646 ni == ic->ic_bss && ic->ic_state == IEEE80211_S_RUN) {
2648 * Resync beacon timers using the tsf of the beacon
2649 * frame we just received.
2651 ath_beacon_config(sc);
2654 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
2655 if (ic->ic_opmode == IEEE80211_M_IBSS &&
2656 ic->ic_state == IEEE80211_S_RUN) {
2657 u_int64_t tsf = ath_extend_tsf(rstamp,
2658 ath_hal_gettsf64(sc->sc_ah));
2660 * Handle ibss merge as needed; check the tsf on the
2661 * frame before attempting the merge. The 802.11 spec
2662 * says the station should change it's bssid to match
2663 * the oldest station with the same ssid, where oldest
2664 * is determined by the tsf. Note that hardware
2665 * reconfiguration happens through callback to
2666 * ath_newstate as the state machine will go from
2667 * RUN -> RUN when this happens.
2669 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
2670 DPRINTF(sc, ATH_DEBUG_STATE,
2671 "ibss merge, rstamp %u tsf %ju "
2672 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
2673 (uintmax_t)ni->ni_tstamp.tsf);
2674 (void) ieee80211_ibss_merge(ni);
2682 * Set the default antenna.
2685 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
2687 struct ath_hal *ah = sc->sc_ah;
2689 /* XXX block beacon interrupts */
2690 ath_hal_setdefantenna(ah, antenna);
2691 if (sc->sc_defant != antenna)
2692 sc->sc_stats.ast_ant_defswitch++;
2693 sc->sc_defant = antenna;
2694 sc->sc_rxotherant = 0;
2698 ath_rx_tap(struct ath_softc *sc, struct mbuf *m,
2699 const struct ath_desc *ds, u_int64_t tsf, int16_t nf)
2703 KASSERT(sc->sc_drvbpf != NULL, ("no tap"));
2706 * Discard anything shorter than an ack or cts.
2708 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) {
2709 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n",
2710 __func__, m->m_pkthdr.len);
2711 sc->sc_stats.ast_rx_tooshort++;
2714 sc->sc_rx_th.wr_tsf = htole64(
2715 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf));
2716 rix = ds->ds_rxstat.rs_rate;
2717 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
2718 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC)
2719 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
2720 /* XXX propagate other error flags from descriptor */
2721 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
2722 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf;
2723 sc->sc_rx_th.wr_antnoise = nf;
2724 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna;
2726 bpf_mtap2(sc->sc_drvbpf, &sc->sc_rx_th, sc->sc_rx_th_len, m);
2732 ath_rx_proc(void *arg, int npending)
2734 #define PA2DESC(_sc, _pa) \
2735 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
2736 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
2737 struct ath_softc *sc = arg;
2739 struct ieee80211com *ic = &sc->sc_ic;
2740 struct ifnet *ifp = sc->sc_ifp;
2741 struct ath_hal *ah = sc->sc_ah;
2742 struct ath_desc *ds;
2744 struct ieee80211_node *ni;
2745 struct ath_node *an;
2746 int len, type, ngood;
2752 NET_LOCK_GIANT(); /* XXX */
2754 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
2756 nf = ath_hal_getchannoise(ah, &sc->sc_curchan);
2757 tsf = ath_hal_gettsf64(ah);
2759 bf = STAILQ_FIRST(&sc->sc_rxbuf);
2760 if (bf == NULL) { /* NB: shouldn't happen */
2761 if_printf(ifp, "%s: no buffer!\n", __func__);
2765 if (ds->ds_link == bf->bf_daddr) {
2766 /* NB: never process the self-linked entry at the end */
2770 if (m == NULL) { /* NB: shouldn't happen */
2771 if_printf(ifp, "%s: no mbuf!\n", __func__);
2774 /* XXX sync descriptor memory */
2776 * Must provide the virtual address of the current
2777 * descriptor, the physical address, and the virtual
2778 * address of the next descriptor in the h/w chain.
2779 * This allows the HAL to look ahead to see if the
2780 * hardware is done with a descriptor by checking the
2781 * done bit in the following descriptor and the address
2782 * of the current descriptor the DMA engine is working
2783 * on. All this is necessary because of our use of
2784 * a self-linked list to avoid rx overruns.
2786 status = ath_hal_rxprocdesc(ah, ds,
2787 bf->bf_daddr, PA2DESC(sc, ds->ds_link));
2789 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
2790 ath_printrxbuf(bf, status == HAL_OK);
2792 if (status == HAL_EINPROGRESS)
2794 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
2795 if (ds->ds_rxstat.rs_more) {
2797 * Frame spans multiple descriptors; this
2798 * cannot happen yet as we don't support
2799 * jumbograms. If not in monitor mode,
2800 * discard the frame.
2802 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2803 sc->sc_stats.ast_rx_toobig++;
2806 /* fall thru for monitor mode handling... */
2807 } else if (ds->ds_rxstat.rs_status != 0) {
2808 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC)
2809 sc->sc_stats.ast_rx_crcerr++;
2810 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO)
2811 sc->sc_stats.ast_rx_fifoerr++;
2812 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) {
2813 sc->sc_stats.ast_rx_phyerr++;
2814 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f;
2815 sc->sc_stats.ast_rx_phy[phyerr]++;
2818 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) {
2820 * Decrypt error. If the error occurred
2821 * because there was no hardware key, then
2822 * let the frame through so the upper layers
2823 * can process it. This is necessary for 5210
2824 * parts which have no way to setup a ``clear''
2827 * XXX do key cache faulting
2829 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID)
2831 sc->sc_stats.ast_rx_badcrypt++;
2833 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) {
2834 sc->sc_stats.ast_rx_badmic++;
2836 * Do minimal work required to hand off
2837 * the 802.11 header for notifcation.
2839 /* XXX frag's and qos frames */
2840 len = ds->ds_rxstat.rs_datalen;
2841 if (len >= sizeof (struct ieee80211_frame)) {
2842 bus_dmamap_sync(sc->sc_dmat,
2844 BUS_DMASYNC_POSTREAD);
2845 ieee80211_notify_michael_failure(ic,
2846 mtod(m, struct ieee80211_frame *),
2848 ds->ds_rxstat.rs_keyix-32 :
2849 ds->ds_rxstat.rs_keyix
2855 * When a tap is present pass error frames
2856 * that have been requested. By default we
2857 * pass decrypt+mic errors but others may be
2858 * interesting (e.g. crc).
2860 if (sc->sc_drvbpf != NULL &&
2861 (ds->ds_rxstat.rs_status & sc->sc_monpass)) {
2862 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2863 BUS_DMASYNC_POSTREAD);
2864 /* NB: bpf needs the mbuf length setup */
2865 len = ds->ds_rxstat.rs_datalen;
2866 m->m_pkthdr.len = m->m_len = len;
2867 (void) ath_rx_tap(sc, m, ds, tsf, nf);
2869 /* XXX pass MIC errors up for s/w reclaculation */
2874 * Sync and unmap the frame. At this point we're
2875 * committed to passing the mbuf somewhere so clear
2876 * bf_m; this means a new sk_buff must be allocated
2877 * when the rx descriptor is setup again to receive
2880 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2881 BUS_DMASYNC_POSTREAD);
2882 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2885 m->m_pkthdr.rcvif = ifp;
2886 len = ds->ds_rxstat.rs_datalen;
2887 m->m_pkthdr.len = m->m_len = len;
2889 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++;
2891 if (sc->sc_drvbpf != NULL && !ath_rx_tap(sc, m, ds, tsf, nf)) {
2892 m_freem(m); /* XXX reclaim */
2897 * From this point on we assume the frame is at least
2898 * as large as ieee80211_frame_min; verify that.
2900 if (len < IEEE80211_MIN_LEN) {
2901 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n",
2903 sc->sc_stats.ast_rx_tooshort++;
2908 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
2909 ieee80211_dump_pkt(mtod(m, caddr_t), len,
2910 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate,
2911 ds->ds_rxstat.rs_rssi);
2914 m_adj(m, -IEEE80211_CRC_LEN);
2917 * Locate the node for sender, track state, and then
2918 * pass the (referenced) node up to the 802.11 layer
2921 ni = ieee80211_find_rxnode_withkey(ic,
2922 mtod(m, const struct ieee80211_frame_min *),
2923 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ?
2924 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix);
2926 * Track rx rssi and do any rx antenna management.
2929 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi);
2930 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, ds->ds_rxstat.rs_rssi);
2932 * Send frame up for processing.
2934 type = ieee80211_input(ic, m, ni,
2935 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp);
2936 ieee80211_free_node(ni);
2937 if (sc->sc_diversity) {
2939 * When using fast diversity, change the default rx
2940 * antenna if diversity chooses the other antenna 3
2943 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) {
2944 if (++sc->sc_rxotherant >= 3)
2945 ath_setdefantenna(sc,
2946 ds->ds_rxstat.rs_antenna);
2948 sc->sc_rxotherant = 0;
2950 if (sc->sc_softled) {
2952 * Blink for any data frame. Otherwise do a
2953 * heartbeat-style blink when idle. The latter
2954 * is mainly for station mode where we depend on
2955 * periodic beacon frames to trigger the poll event.
2957 if (type == IEEE80211_FC0_TYPE_DATA) {
2958 sc->sc_rxrate = ds->ds_rxstat.rs_rate;
2959 ath_led_event(sc, ATH_LED_RX);
2960 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
2961 ath_led_event(sc, ATH_LED_POLL);
2964 * Arrange to update the last rx timestamp only for
2965 * frames from our ap when operating in station mode.
2966 * This assumes the rx key is always setup when associated.
2968 if (ic->ic_opmode == IEEE80211_M_STA &&
2969 ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID)
2972 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
2973 } while (ath_rxbuf_init(sc, bf) == 0);
2975 /* rx signal state monitoring */
2976 ath_hal_rxmonitor(ah, &sc->sc_halstats);
2978 sc->sc_lastrx = tsf;
2980 NET_UNLOCK_GIANT(); /* XXX */
2985 * Setup a h/w transmit queue.
2987 static struct ath_txq *
2988 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
2990 #define N(a) (sizeof(a)/sizeof(a[0]))
2991 struct ath_hal *ah = sc->sc_ah;
2995 memset(&qi, 0, sizeof(qi));
2996 qi.tqi_subtype = subtype;
2997 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
2998 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
2999 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
3001 * Enable interrupts only for EOL and DESC conditions.
3002 * We mark tx descriptors to receive a DESC interrupt
3003 * when a tx queue gets deep; otherwise waiting for the
3004 * EOL to reap descriptors. Note that this is done to
3005 * reduce interrupt load and this only defers reaping
3006 * descriptors, never transmitting frames. Aside from
3007 * reducing interrupts this also permits more concurrency.
3008 * The only potential downside is if the tx queue backs
3009 * up in which case the top half of the kernel may backup
3010 * due to a lack of tx descriptors.
3012 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | TXQ_FLAG_TXDESCINT_ENABLE;
3013 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
3016 * NB: don't print a message, this happens
3017 * normally on parts with too few tx queues
3021 if (qnum >= N(sc->sc_txq)) {
3022 device_printf(sc->sc_dev,
3023 "hal qnum %u out of range, max %zu!\n",
3024 qnum, N(sc->sc_txq));
3025 ath_hal_releasetxqueue(ah, qnum);
3028 if (!ATH_TXQ_SETUP(sc, qnum)) {
3029 struct ath_txq *txq = &sc->sc_txq[qnum];
3031 txq->axq_qnum = qnum;
3033 txq->axq_intrcnt = 0;
3034 txq->axq_link = NULL;
3035 STAILQ_INIT(&txq->axq_q);
3036 ATH_TXQ_LOCK_INIT(sc, txq);
3037 sc->sc_txqsetup |= 1<<qnum;
3039 return &sc->sc_txq[qnum];
3044 * Setup a hardware data transmit queue for the specified
3045 * access control. The hal may not support all requested
3046 * queues in which case it will return a reference to a
3047 * previously setup queue. We record the mapping from ac's
3048 * to h/w queues for use by ath_tx_start and also track
3049 * the set of h/w queues being used to optimize work in the
3050 * transmit interrupt handler and related routines.
3053 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
3055 #define N(a) (sizeof(a)/sizeof(a[0]))
3056 struct ath_txq *txq;
3058 if (ac >= N(sc->sc_ac2q)) {
3059 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
3060 ac, N(sc->sc_ac2q));
3063 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
3065 sc->sc_ac2q[ac] = txq;
3073 * Update WME parameters for a transmit queue.
3076 ath_txq_update(struct ath_softc *sc, int ac)
3078 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
3079 #define ATH_TXOP_TO_US(v) (v<<5)
3080 struct ieee80211com *ic = &sc->sc_ic;
3081 struct ath_txq *txq = sc->sc_ac2q[ac];
3082 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
3083 struct ath_hal *ah = sc->sc_ah;
3086 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
3087 qi.tqi_aifs = wmep->wmep_aifsn;
3088 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
3089 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
3090 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
3092 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
3093 device_printf(sc->sc_dev, "unable to update hardware queue "
3094 "parameters for %s traffic!\n",
3095 ieee80211_wme_acnames[ac]);
3098 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
3101 #undef ATH_TXOP_TO_US
3102 #undef ATH_EXPONENT_TO_VALUE
3106 * Callback from the 802.11 layer to update WME parameters.
3109 ath_wme_update(struct ieee80211com *ic)
3111 struct ath_softc *sc = ic->ic_ifp->if_softc;
3113 return !ath_txq_update(sc, WME_AC_BE) ||
3114 !ath_txq_update(sc, WME_AC_BK) ||
3115 !ath_txq_update(sc, WME_AC_VI) ||
3116 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
3120 * Reclaim resources for a setup queue.
3123 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
3126 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
3127 ATH_TXQ_LOCK_DESTROY(txq);
3128 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
3132 * Reclaim all tx queue resources.
3135 ath_tx_cleanup(struct ath_softc *sc)
3139 ATH_TXBUF_LOCK_DESTROY(sc);
3140 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3141 if (ATH_TXQ_SETUP(sc, i))
3142 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
3146 * Defragment an mbuf chain, returning at most maxfrags separate
3147 * mbufs+clusters. If this is not possible NULL is returned and
3148 * the original mbuf chain is left in it's present (potentially
3149 * modified) state. We use two techniques: collapsing consecutive
3150 * mbufs and replacing consecutive mbufs by a cluster.
3152 static struct mbuf *
3153 ath_defrag(struct mbuf *m0, int how, int maxfrags)
3155 struct mbuf *m, *n, *n2, **prev;
3159 * Calculate the current number of frags.
3162 for (m = m0; m != NULL; m = m->m_next)
3165 * First, try to collapse mbufs. Note that we always collapse
3166 * towards the front so we don't need to deal with moving the
3167 * pkthdr. This may be suboptimal if the first mbuf has much
3168 * less data than the following.
3176 if ((m->m_flags & M_RDONLY) == 0 &&
3177 n->m_len < M_TRAILINGSPACE(m)) {
3178 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len,
3180 m->m_len += n->m_len;
3181 m->m_next = n->m_next;
3183 if (--curfrags <= maxfrags)
3188 KASSERT(maxfrags > 1,
3189 ("maxfrags %u, but normal collapse failed", maxfrags));
3191 * Collapse consecutive mbufs to a cluster.
3193 prev = &m0->m_next; /* NB: not the first mbuf */
3194 while ((n = *prev) != NULL) {
3195 if ((n2 = n->m_next) != NULL &&
3196 n->m_len + n2->m_len < MCLBYTES) {
3197 m = m_getcl(how, MT_DATA, 0);
3200 bcopy(mtod(n, void *), mtod(m, void *), n->m_len);
3201 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len,
3203 m->m_len = n->m_len + n2->m_len;
3204 m->m_next = n2->m_next;
3208 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */
3211 * Still not there, try the normal collapse
3212 * again before we allocate another cluster.
3219 * No place where we can collapse to a cluster; punt.
3220 * This can occur if, for example, you request 2 frags
3221 * but the packet requires that both be clusters (we
3222 * never reallocate the first mbuf to avoid moving the
3230 * Return h/w rate index for an IEEE rate (w/o basic rate bit).
3233 ath_tx_findrix(const HAL_RATE_TABLE *rt, int rate)
3237 for (i = 0; i < rt->rateCount; i++)
3238 if ((rt->info[i].dot11Rate & IEEE80211_RATE_VAL) == rate)
3240 return 0; /* NB: lowest rate */
3244 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf,
3247 struct ieee80211com *ic = &sc->sc_ic;
3248 struct ath_hal *ah = sc->sc_ah;
3249 struct ifnet *ifp = sc->sc_ifp;
3250 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
3251 int i, error, iswep, ismcast, ismrr;
3252 int keyix, hdrlen, pktlen, try0;
3253 u_int8_t rix, txrate, ctsrate;
3254 u_int8_t cix = 0xff; /* NB: silence compiler */
3255 struct ath_desc *ds, *ds0;
3256 struct ath_txq *txq;
3257 struct ieee80211_frame *wh;
3258 u_int subtype, flags, ctsduration;
3260 const HAL_RATE_TABLE *rt;
3261 HAL_BOOL shortPreamble;
3262 struct ath_node *an;
3266 wh = mtod(m0, struct ieee80211_frame *);
3267 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
3268 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3269 hdrlen = ieee80211_anyhdrsize(wh);
3271 * Packet length must not include any
3272 * pad bytes; deduct them here.
3274 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
3277 const struct ieee80211_cipher *cip;
3278 struct ieee80211_key *k;
3281 * Construct the 802.11 header+trailer for an encrypted
3282 * frame. The only reason this can fail is because of an
3283 * unknown or unsupported cipher/key type.
3285 k = ieee80211_crypto_encap(ic, ni, m0);
3288 * This can happen when the key is yanked after the
3289 * frame was queued. Just discard the frame; the
3290 * 802.11 layer counts failures and provides
3291 * debugging/diagnostics.
3297 * Adjust the packet + header lengths for the crypto
3298 * additions and calculate the h/w key index. When
3299 * a s/w mic is done the frame will have had any mic
3300 * added to it prior to entry so skb->len above will
3301 * account for it. Otherwise we need to add it to the
3305 hdrlen += cip->ic_header;
3306 pktlen += cip->ic_header + cip->ic_trailer;
3307 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0)
3308 pktlen += cip->ic_miclen;
3309 keyix = k->wk_keyix;
3311 /* packet header may have moved, reset our local pointer */
3312 wh = mtod(m0, struct ieee80211_frame *);
3313 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
3315 * Use station key cache slot, if assigned.
3317 keyix = ni->ni_ucastkey.wk_keyix;
3318 if (keyix == IEEE80211_KEYIX_NONE)
3319 keyix = HAL_TXKEYIX_INVALID;
3321 keyix = HAL_TXKEYIX_INVALID;
3323 pktlen += IEEE80211_CRC_LEN;
3326 * Load the DMA map so any coalescing is done. This
3327 * also calculates the number of descriptors we need.
3329 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
3330 bf->bf_segs, &bf->bf_nseg,
3332 if (error == EFBIG) {
3333 /* XXX packet requires too many descriptors */
3334 bf->bf_nseg = ATH_TXDESC+1;
3335 } else if (error != 0) {
3336 sc->sc_stats.ast_tx_busdma++;
3341 * Discard null packets and check for packets that
3342 * require too many TX descriptors. We try to convert
3343 * the latter to a cluster.
3345 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */
3346 sc->sc_stats.ast_tx_linear++;
3347 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC);
3350 sc->sc_stats.ast_tx_nombuf++;
3354 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
3355 bf->bf_segs, &bf->bf_nseg,
3358 sc->sc_stats.ast_tx_busdma++;
3362 KASSERT(bf->bf_nseg <= ATH_TXDESC,
3363 ("too many segments after defrag; nseg %u", bf->bf_nseg));
3364 } else if (bf->bf_nseg == 0) { /* null packet, discard */
3365 sc->sc_stats.ast_tx_nodata++;
3369 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen);
3370 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
3372 bf->bf_node = ni; /* NB: held reference */
3374 /* setup descriptors */
3376 rt = sc->sc_currates;
3377 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
3380 * NB: the 802.11 layer marks whether or not we should
3381 * use short preamble based on the current mode and
3382 * negotiated parameters.
3384 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3385 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
3386 shortPreamble = AH_TRUE;
3387 sc->sc_stats.ast_tx_shortpre++;
3389 shortPreamble = AH_FALSE;
3393 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
3394 ismrr = 0; /* default no multi-rate retry*/
3396 * Calculate Atheros packet type from IEEE80211 packet header,
3397 * setup for rate calculations, and select h/w transmit queue.
3399 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
3400 case IEEE80211_FC0_TYPE_MGT:
3401 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3402 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
3403 atype = HAL_PKT_TYPE_BEACON;
3404 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3405 atype = HAL_PKT_TYPE_PROBE_RESP;
3406 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
3407 atype = HAL_PKT_TYPE_ATIM;
3409 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
3410 rix = sc->sc_minrateix;
3411 txrate = rt->info[rix].rateCode;
3413 txrate |= rt->info[rix].shortPreamble;
3414 try0 = ATH_TXMGTTRY;
3415 /* NB: force all management frames to highest queue */
3416 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3417 /* NB: force all management frames to highest queue */
3421 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3423 case IEEE80211_FC0_TYPE_CTL:
3424 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
3425 rix = sc->sc_minrateix;
3426 txrate = rt->info[rix].rateCode;
3428 txrate |= rt->info[rix].shortPreamble;
3429 try0 = ATH_TXMGTTRY;
3430 /* NB: force all ctl frames to highest queue */
3431 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3432 /* NB: force all ctl frames to highest queue */
3436 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3438 case IEEE80211_FC0_TYPE_DATA:
3439 atype = HAL_PKT_TYPE_NORMAL; /* default */
3441 * Data frames: multicast frames go out at a fixed rate,
3442 * otherwise consult the rate control module for the
3447 * Check mcast rate setting in case it's changed.
3448 * XXX move out of fastpath
3450 if (ic->ic_mcast_rate != sc->sc_mcastrate) {
3452 ath_tx_findrix(rt, ic->ic_mcast_rate);
3453 sc->sc_mcastrate = ic->ic_mcast_rate;
3455 rix = sc->sc_mcastrix;
3456 txrate = rt->info[rix].rateCode;
3458 txrate |= rt->info[rix].shortPreamble;
3461 ath_rate_findrate(sc, an, shortPreamble, pktlen,
3462 &rix, &try0, &txrate);
3463 sc->sc_txrate = txrate; /* for LED blinking */
3464 if (try0 != ATH_TXMAXTRY)
3468 * Default all non-QoS traffic to the background queue.
3470 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) {
3471 pri = M_WME_GETAC(m0);
3472 if (cap->cap_wmeParams[pri].wmep_noackPolicy) {
3473 flags |= HAL_TXDESC_NOACK;
3474 sc->sc_stats.ast_tx_noack++;
3480 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
3481 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
3486 txq = sc->sc_ac2q[pri];
3489 * When servicing one or more stations in power-save mode
3490 * multicast frames must be buffered until after the beacon.
3491 * We use the CAB queue for that.
3493 if (ismcast && ic->ic_ps_sta) {
3495 /* XXX? more bit in 802.11 frame header */
3499 * Calculate miscellaneous flags.
3502 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
3503 sc->sc_stats.ast_tx_noack++;
3504 } else if (pktlen > ic->ic_rtsthreshold) {
3505 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
3506 cix = rt->info[rix].controlRate;
3507 sc->sc_stats.ast_tx_rts++;
3511 * If 802.11g protection is enabled, determine whether
3512 * to use RTS/CTS or just CTS. Note that this is only
3513 * done for OFDM unicast frames.
3515 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
3516 rt->info[rix].phy == IEEE80211_T_OFDM &&
3517 (flags & HAL_TXDESC_NOACK) == 0) {
3518 /* XXX fragments must use CCK rates w/ protection */
3519 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3520 flags |= HAL_TXDESC_RTSENA;
3521 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3522 flags |= HAL_TXDESC_CTSENA;
3523 cix = rt->info[sc->sc_protrix].controlRate;
3524 sc->sc_stats.ast_tx_protect++;
3528 * Calculate duration. This logically belongs in the 802.11
3529 * layer but it lacks sufficient information to calculate it.
3531 if ((flags & HAL_TXDESC_NOACK) == 0 &&
3532 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
3535 * XXX not right with fragmentation.
3538 dur = rt->info[rix].spAckDuration;
3540 dur = rt->info[rix].lpAckDuration;
3541 *(u_int16_t *)wh->i_dur = htole16(dur);
3545 * Calculate RTS/CTS rate and duration if needed.
3548 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
3550 * CTS transmit rate is derived from the transmit rate
3551 * by looking in the h/w rate table. We must also factor
3552 * in whether or not a short preamble is to be used.
3554 /* NB: cix is set above where RTS/CTS is enabled */
3555 KASSERT(cix != 0xff, ("cix not setup"));
3556 ctsrate = rt->info[cix].rateCode;
3558 * Compute the transmit duration based on the frame
3559 * size and the size of an ACK frame. We call into the
3560 * HAL to do the computation since it depends on the
3561 * characteristics of the actual PHY being used.
3563 * NB: CTS is assumed the same size as an ACK so we can
3564 * use the precalculated ACK durations.
3566 if (shortPreamble) {
3567 ctsrate |= rt->info[cix].shortPreamble;
3568 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3569 ctsduration += rt->info[cix].spAckDuration;
3570 ctsduration += ath_hal_computetxtime(ah,
3571 rt, pktlen, rix, AH_TRUE);
3572 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3573 ctsduration += rt->info[rix].spAckDuration;
3575 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3576 ctsduration += rt->info[cix].lpAckDuration;
3577 ctsduration += ath_hal_computetxtime(ah,
3578 rt, pktlen, rix, AH_FALSE);
3579 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3580 ctsduration += rt->info[rix].lpAckDuration;
3583 * Must disable multi-rate retry when using RTS/CTS.
3586 try0 = ATH_TXMGTTRY; /* XXX */
3590 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
3591 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len,
3592 sc->sc_hwmap[txrate].ieeerate, -1);
3595 bpf_mtap(ic->ic_rawbpf, m0);
3596 if (sc->sc_drvbpf) {
3597 u_int64_t tsf = ath_hal_gettsf64(ah);
3599 sc->sc_tx_th.wt_tsf = htole64(tsf);
3600 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags;
3602 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3603 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate;
3604 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
3605 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
3607 bpf_mtap2(sc->sc_drvbpf,
3608 &sc->sc_tx_th, sc->sc_tx_th_len, m0);
3612 * Determine if a tx interrupt should be generated for
3613 * this descriptor. We take a tx interrupt to reap
3614 * descriptors when the h/w hits an EOL condition or
3615 * when the descriptor is specifically marked to generate
3616 * an interrupt. We periodically mark descriptors in this
3617 * way to insure timely replenishing of the supply needed
3618 * for sending frames. Defering interrupts reduces system
3619 * load and potentially allows more concurrent work to be
3620 * done but if done to aggressively can cause senders to
3623 * NB: use >= to deal with sc_txintrperiod changing
3624 * dynamically through sysctl.
3626 if (flags & HAL_TXDESC_INTREQ) {
3627 txq->axq_intrcnt = 0;
3628 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
3629 flags |= HAL_TXDESC_INTREQ;
3630 txq->axq_intrcnt = 0;
3634 * Formulate first tx descriptor with tx controls.
3636 /* XXX check return value? */
3637 ath_hal_setuptxdesc(ah, ds
3638 , pktlen /* packet length */
3639 , hdrlen /* header length */
3640 , atype /* Atheros packet type */
3641 , ni->ni_txpower /* txpower */
3642 , txrate, try0 /* series 0 rate/tries */
3643 , keyix /* key cache index */
3644 , sc->sc_txantenna /* antenna mode */
3646 , ctsrate /* rts/cts rate */
3647 , ctsduration /* rts/cts duration */
3649 bf->bf_flags = flags;
3651 * Setup the multi-rate retry state only when we're
3652 * going to use it. This assumes ath_hal_setuptxdesc
3653 * initializes the descriptors (so we don't have to)
3654 * when the hardware supports multi-rate retry and
3658 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix);
3661 * Fillin the remainder of the descriptor info.
3664 for (i = 0; i < bf->bf_nseg; i++, ds++) {
3665 ds->ds_data = bf->bf_segs[i].ds_addr;
3666 if (i == bf->bf_nseg - 1)
3669 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
3670 ath_hal_filltxdesc(ah, ds
3671 , bf->bf_segs[i].ds_len /* segment length */
3672 , i == 0 /* first segment */
3673 , i == bf->bf_nseg - 1 /* last segment */
3674 , ds0 /* first descriptor */
3676 DPRINTF(sc, ATH_DEBUG_XMIT,
3677 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
3678 __func__, i, ds->ds_link, ds->ds_data,
3679 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
3682 * Insert the frame on the outbound list and
3683 * pass it on to the hardware.
3686 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
3687 if (txq->axq_link == NULL) {
3688 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
3689 DPRINTF(sc, ATH_DEBUG_XMIT,
3690 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__,
3691 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc,
3694 *txq->axq_link = bf->bf_daddr;
3695 DPRINTF(sc, ATH_DEBUG_XMIT,
3696 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
3697 txq->axq_qnum, txq->axq_link,
3698 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth);
3700 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
3702 * The CAB queue is started from the SWBA handler since
3703 * frames only go out on DTIM and to avoid possible races.
3705 if (txq != sc->sc_cabq)
3706 ath_hal_txstart(ah, txq->axq_qnum);
3707 ATH_TXQ_UNLOCK(txq);
3713 * Process completed xmit descriptors from the specified queue.
3716 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
3718 struct ath_hal *ah = sc->sc_ah;
3719 struct ieee80211com *ic = &sc->sc_ic;
3721 struct ath_desc *ds, *ds0;
3722 struct ieee80211_node *ni;
3723 struct ath_node *an;
3724 int sr, lr, pri, nacked;
3727 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
3728 __func__, txq->axq_qnum,
3729 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
3734 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
3735 bf = STAILQ_FIRST(&txq->axq_q);
3737 txq->axq_link = NULL;
3738 ATH_TXQ_UNLOCK(txq);
3741 ds0 = &bf->bf_desc[0];
3742 ds = &bf->bf_desc[bf->bf_nseg - 1];
3743 status = ath_hal_txprocdesc(ah, ds);
3745 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
3746 ath_printtxbuf(bf, status == HAL_OK);
3748 if (status == HAL_EINPROGRESS) {
3749 ATH_TXQ_UNLOCK(txq);
3752 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3753 ATH_TXQ_UNLOCK(txq);
3758 if (ds->ds_txstat.ts_status == 0) {
3759 u_int8_t txant = ds->ds_txstat.ts_antenna;
3760 sc->sc_stats.ast_ant_tx[txant]++;
3761 sc->sc_ant_tx[txant]++;
3762 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
3763 sc->sc_stats.ast_tx_altrate++;
3764 sc->sc_stats.ast_tx_rssi =
3765 ds->ds_txstat.ts_rssi;
3766 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
3767 ds->ds_txstat.ts_rssi);
3768 pri = M_WME_GETAC(bf->bf_m);
3769 if (pri >= WME_AC_VO)
3770 ic->ic_wme.wme_hipri_traffic++;
3771 ni->ni_inact = ni->ni_inact_reload;
3773 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
3774 sc->sc_stats.ast_tx_xretries++;
3775 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
3776 sc->sc_stats.ast_tx_fifoerr++;
3777 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
3778 sc->sc_stats.ast_tx_filtered++;
3780 sr = ds->ds_txstat.ts_shortretry;
3781 lr = ds->ds_txstat.ts_longretry;
3782 sc->sc_stats.ast_tx_shortretry += sr;
3783 sc->sc_stats.ast_tx_longretry += lr;
3785 * Hand the descriptor to the rate control algorithm.
3787 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 &&
3788 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
3790 * If frame was ack'd update the last rx time
3791 * used to workaround phantom bmiss interrupts.
3793 if (ds->ds_txstat.ts_status == 0)
3795 ath_rate_tx_complete(sc, an, ds, ds0);
3798 * Reclaim reference to node.
3800 * NB: the node may be reclaimed here if, for example
3801 * this is a DEAUTH message that was sent and the
3802 * node was timed out due to inactivity.
3804 ieee80211_free_node(ni);
3806 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3807 BUS_DMASYNC_POSTWRITE);
3808 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3814 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
3815 ATH_TXBUF_UNLOCK(sc);
3821 txqactive(struct ath_hal *ah, int qnum)
3828 * Deferred processing of transmit interrupt; special-cased
3829 * for a single hardware transmit queue (e.g. 5210 and 5211).
3832 ath_tx_proc_q0(void *arg, int npending)
3834 struct ath_softc *sc = arg;
3835 struct ifnet *ifp = sc->sc_ifp;
3837 if (txqactive(sc->sc_ah, 0) && ath_tx_processq(sc, &sc->sc_txq[0]))
3838 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
3839 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
3840 ath_tx_processq(sc, sc->sc_cabq);
3841 ath_tx_processq(sc, sc->sc_cabq);
3842 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3843 sc->sc_tx_timer = 0;
3846 ath_led_event(sc, ATH_LED_TX);
3852 * Deferred processing of transmit interrupt; special-cased
3853 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
3856 ath_tx_proc_q0123(void *arg, int npending)
3858 struct ath_softc *sc = arg;
3859 struct ifnet *ifp = sc->sc_ifp;
3863 * Process each active queue.
3866 if (txqactive(sc->sc_ah, 0))
3867 nacked += ath_tx_processq(sc, &sc->sc_txq[0]);
3868 if (txqactive(sc->sc_ah, 1))
3869 nacked += ath_tx_processq(sc, &sc->sc_txq[1]);
3870 if (txqactive(sc->sc_ah, 2))
3871 nacked += ath_tx_processq(sc, &sc->sc_txq[2]);
3872 if (txqactive(sc->sc_ah, 3))
3873 nacked += ath_tx_processq(sc, &sc->sc_txq[3]);
3874 if (txqactive(sc->sc_ah, sc->sc_cabq->axq_qnum))
3875 ath_tx_processq(sc, sc->sc_cabq);
3877 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
3879 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3880 sc->sc_tx_timer = 0;
3883 ath_led_event(sc, ATH_LED_TX);
3889 * Deferred processing of transmit interrupt.
3892 ath_tx_proc(void *arg, int npending)
3894 struct ath_softc *sc = arg;
3895 struct ifnet *ifp = sc->sc_ifp;
3899 * Process each active queue.
3902 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3903 if (ATH_TXQ_SETUP(sc, i) && txqactive(sc->sc_ah, i))
3904 nacked += ath_tx_processq(sc, &sc->sc_txq[i]);
3906 sc->sc_lastrx = ath_hal_gettsf64(sc->sc_ah);
3908 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3909 sc->sc_tx_timer = 0;
3912 ath_led_event(sc, ATH_LED_TX);
3918 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
3920 struct ath_hal *ah = sc->sc_ah;
3921 struct ieee80211_node *ni;
3925 * NB: this assumes output has been stopped and
3926 * we do not need to block ath_tx_tasklet
3930 bf = STAILQ_FIRST(&txq->axq_q);
3932 txq->axq_link = NULL;
3933 ATH_TXQ_UNLOCK(txq);
3936 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3937 ATH_TXQ_UNLOCK(txq);
3939 if (sc->sc_debug & ATH_DEBUG_RESET)
3941 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK);
3942 #endif /* AR_DEBUG */
3943 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3950 * Reclaim node reference.
3952 ieee80211_free_node(ni);
3955 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
3956 ATH_TXBUF_UNLOCK(sc);
3961 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
3963 struct ath_hal *ah = sc->sc_ah;
3965 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
3966 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
3967 __func__, txq->axq_qnum,
3968 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
3973 * Drain the transmit queues and reclaim resources.
3976 ath_draintxq(struct ath_softc *sc)
3978 struct ath_hal *ah = sc->sc_ah;
3979 struct ifnet *ifp = sc->sc_ifp;
3982 /* XXX return value */
3983 if (!sc->sc_invalid) {
3984 /* don't touch the hardware if marked invalid */
3985 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
3986 DPRINTF(sc, ATH_DEBUG_RESET,
3987 "%s: beacon queue %p\n", __func__,
3988 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq));
3989 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3990 if (ATH_TXQ_SETUP(sc, i))
3991 ath_tx_stopdma(sc, &sc->sc_txq[i]);
3993 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3994 if (ATH_TXQ_SETUP(sc, i))
3995 ath_tx_draintxq(sc, &sc->sc_txq[i]);
3996 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3997 sc->sc_tx_timer = 0;
4001 * Disable the receive h/w in preparation for a reset.
4004 ath_stoprecv(struct ath_softc *sc)
4006 #define PA2DESC(_sc, _pa) \
4007 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
4008 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
4009 struct ath_hal *ah = sc->sc_ah;
4011 ath_hal_stoppcurecv(ah); /* disable PCU */
4012 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
4013 ath_hal_stopdmarecv(ah); /* disable DMA engine */
4014 DELAY(3000); /* 3ms is long enough for 1 frame */
4016 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
4019 printf("%s: rx queue %p, link %p\n", __func__,
4020 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink);
4021 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
4022 struct ath_desc *ds = bf->bf_desc;
4023 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
4024 bf->bf_daddr, PA2DESC(sc, ds->ds_link));
4025 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
4026 ath_printrxbuf(bf, status == HAL_OK);
4030 sc->sc_rxlink = NULL; /* just in case */
4035 * Enable the receive h/w following a reset.
4038 ath_startrecv(struct ath_softc *sc)
4040 struct ath_hal *ah = sc->sc_ah;
4043 sc->sc_rxlink = NULL;
4044 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
4045 int error = ath_rxbuf_init(sc, bf);
4047 DPRINTF(sc, ATH_DEBUG_RECV,
4048 "%s: ath_rxbuf_init failed %d\n",
4054 bf = STAILQ_FIRST(&sc->sc_rxbuf);
4055 ath_hal_putrxbuf(ah, bf->bf_daddr);
4056 ath_hal_rxena(ah); /* enable recv descriptors */
4057 ath_mode_init(sc); /* set filters, etc. */
4058 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
4063 * Update internal state after a channel change.
4066 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
4068 struct ieee80211com *ic = &sc->sc_ic;
4069 enum ieee80211_phymode mode;
4073 * Change channels and update the h/w rate map
4074 * if we're switching; e.g. 11a to 11b/g.
4076 mode = ieee80211_chan2mode(ic, chan);
4077 if (mode != sc->sc_curmode)
4078 ath_setcurmode(sc, mode);
4080 * Update BPF state. NB: ethereal et. al. don't handle
4081 * merged flags well so pick a unique mode for their use.
4083 if (IEEE80211_IS_CHAN_A(chan))
4084 flags = IEEE80211_CHAN_A;
4085 /* XXX 11g schizophrenia */
4086 else if (IEEE80211_IS_CHAN_G(chan) ||
4087 IEEE80211_IS_CHAN_PUREG(chan))
4088 flags = IEEE80211_CHAN_G;
4090 flags = IEEE80211_CHAN_B;
4091 if (IEEE80211_IS_CHAN_T(chan))
4092 flags |= IEEE80211_CHAN_TURBO;
4093 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
4094 htole16(chan->ic_freq);
4095 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
4100 * Set/change channels. If the channel is really being changed,
4101 * it's done by reseting the chip. To accomplish this we must
4102 * first cleanup any pending DMA, then restart stuff after a la
4106 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
4108 struct ath_hal *ah = sc->sc_ah;
4109 struct ieee80211com *ic = &sc->sc_ic;
4113 * Convert to a HAL channel description with
4114 * the flags constrained to reflect the current
4117 hchan.channel = chan->ic_freq;
4118 hchan.channelFlags = ath_chan2flags(ic, chan);
4120 DPRINTF(sc, ATH_DEBUG_RESET,
4121 "%s: %u (%u MHz, hal flags 0x%x) -> %u (%u MHz, hal flags 0x%x)\n",
4123 ath_hal_mhz2ieee(sc->sc_curchan.channel,
4124 sc->sc_curchan.channelFlags),
4125 sc->sc_curchan.channel, sc->sc_curchan.channelFlags,
4126 ath_hal_mhz2ieee(hchan.channel, hchan.channelFlags),
4127 hchan.channel, hchan.channelFlags);
4128 if (hchan.channel != sc->sc_curchan.channel ||
4129 hchan.channelFlags != sc->sc_curchan.channelFlags) {
4133 * To switch channels clear any pending DMA operations;
4134 * wait long enough for the RX fifo to drain, reset the
4135 * hardware at the new frequency, and then re-enable
4136 * the relevant bits of the h/w.
4138 ath_hal_intrset(ah, 0); /* disable interrupts */
4139 ath_draintxq(sc); /* clear pending tx frames */
4140 ath_stoprecv(sc); /* turn off frame recv */
4141 if (!ath_hal_reset(ah, sc->sc_opmode, &hchan, AH_TRUE, &status)) {
4142 if_printf(ic->ic_ifp, "%s: unable to reset "
4143 "channel %u (%u Mhz, flags 0x%x hal flags 0x%x)\n",
4144 __func__, ieee80211_chan2ieee(ic, chan),
4145 chan->ic_freq, chan->ic_flags, hchan.channelFlags);
4148 sc->sc_curchan = hchan;
4149 ath_update_txpow(sc); /* update tx power state */
4150 sc->sc_diversity = ath_hal_getdiversity(ah);
4153 * Re-enable rx framework.
4155 if (ath_startrecv(sc) != 0) {
4156 if_printf(ic->ic_ifp,
4157 "%s: unable to restart recv logic\n", __func__);
4162 * Change channels and update the h/w rate map
4163 * if we're switching; e.g. 11a to 11b/g.
4165 ic->ic_ibss_chan = chan;
4166 ath_chan_change(sc, chan);
4169 * Re-enable interrupts.
4171 ath_hal_intrset(ah, sc->sc_imask);
4177 ath_next_scan(void *arg)
4179 struct ath_softc *sc = arg;
4180 struct ieee80211com *ic = &sc->sc_ic;
4182 if (ic->ic_state == IEEE80211_S_SCAN)
4183 ieee80211_next_scan(ic);
4187 * Periodically recalibrate the PHY to account
4188 * for temperature/environment changes.
4191 ath_calibrate(void *arg)
4193 struct ath_softc *sc = arg;
4194 struct ath_hal *ah = sc->sc_ah;
4196 sc->sc_stats.ast_per_cal++;
4198 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
4200 * Rfgain is out of bounds, reset the chip
4201 * to load new gain values.
4203 DPRINTF(sc, ATH_DEBUG_CALIBRATE,
4204 "%s: rfgain change\n", __func__);
4205 sc->sc_stats.ast_per_rfgain++;
4206 ath_reset(sc->sc_ifp);
4208 if (!ath_hal_calibrate(ah, &sc->sc_curchan)) {
4209 DPRINTF(sc, ATH_DEBUG_ANY,
4210 "%s: calibration of channel %u failed\n",
4211 __func__, sc->sc_curchan.channel);
4212 sc->sc_stats.ast_per_calfail++;
4215 * Calibrate noise floor data again in case of change.
4217 ath_hal_process_noisefloor(ah);
4218 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, ath_calibrate, sc);
4222 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
4224 struct ifnet *ifp = ic->ic_ifp;
4225 struct ath_softc *sc = ifp->if_softc;
4226 struct ath_hal *ah = sc->sc_ah;
4227 struct ieee80211_node *ni;
4229 const u_int8_t *bssid;
4231 static const HAL_LED_STATE leds[] = {
4232 HAL_LED_INIT, /* IEEE80211_S_INIT */
4233 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
4234 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
4235 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
4236 HAL_LED_RUN, /* IEEE80211_S_RUN */
4239 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
4240 ieee80211_state_name[ic->ic_state],
4241 ieee80211_state_name[nstate]);
4243 callout_stop(&sc->sc_scan_ch);
4244 callout_stop(&sc->sc_cal_ch);
4245 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
4247 if (nstate == IEEE80211_S_INIT) {
4248 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4250 * NB: disable interrupts so we don't rx frames.
4252 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
4254 * Notify the rate control algorithm.
4256 ath_rate_newstate(sc, nstate);
4260 error = ath_chan_set(sc, ic->ic_curchan);
4263 rfilt = ath_calcrxfilter(sc, nstate);
4264 if (nstate == IEEE80211_S_SCAN)
4265 bssid = ifp->if_broadcastaddr;
4267 bssid = ni->ni_bssid;
4268 ath_hal_setrxfilter(ah, rfilt);
4269 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n",
4270 __func__, rfilt, ether_sprintf(bssid));
4272 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA)
4273 ath_hal_setassocid(ah, bssid, ni->ni_associd);
4275 ath_hal_setassocid(ah, bssid, 0);
4276 if (ic->ic_flags & IEEE80211_F_PRIVACY) {
4277 for (i = 0; i < IEEE80211_WEP_NKID; i++)
4278 if (ath_hal_keyisvalid(ah, i))
4279 ath_hal_keysetmac(ah, i, bssid);
4283 * Notify the rate control algorithm so rates
4284 * are setup should ath_beacon_alloc be called.
4286 ath_rate_newstate(sc, nstate);
4288 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
4289 /* nothing to do */;
4290 } else if (nstate == IEEE80211_S_RUN) {
4291 DPRINTF(sc, ATH_DEBUG_STATE,
4292 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s "
4293 "capinfo=0x%04x chan=%d\n"
4297 , ether_sprintf(ni->ni_bssid)
4299 , ieee80211_chan2ieee(ic, ic->ic_curchan));
4301 switch (ic->ic_opmode) {
4302 case IEEE80211_M_HOSTAP:
4303 case IEEE80211_M_IBSS:
4305 * Allocate and setup the beacon frame.
4307 * Stop any previous beacon DMA. This may be
4308 * necessary, for example, when an ibss merge
4309 * causes reconfiguration; there will be a state
4310 * transition from RUN->RUN that means we may
4311 * be called with beacon transmission active.
4313 ath_hal_stoptxdma(ah, sc->sc_bhalq);
4314 ath_beacon_free(sc);
4315 error = ath_beacon_alloc(sc, ni);
4319 * If joining an adhoc network defer beacon timer
4320 * configuration to the next beacon frame so we
4321 * have a current TSF to use. Otherwise we're
4322 * starting an ibss/bss so there's no need to delay.
4324 if (ic->ic_opmode == IEEE80211_M_IBSS &&
4325 ic->ic_bss->ni_tstamp.tsf != 0)
4326 sc->sc_syncbeacon = 1;
4328 ath_beacon_config(sc);
4330 case IEEE80211_M_STA:
4332 * Allocate a key cache slot to the station.
4334 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 &&
4336 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
4337 ath_setup_stationkey(ni);
4339 * Defer beacon timer configuration to the next
4340 * beacon frame so we have a current TSF to use
4341 * (any TSF collected when scanning is likely old).
4343 sc->sc_syncbeacon = 1;
4350 * Let the hal process statistics collected during a
4351 * scan so it can provide calibrated noise floor data.
4353 ath_hal_process_noisefloor(ah);
4355 * Reset rssi stats; maybe not the best place...
4357 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
4358 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
4359 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
4362 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
4363 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4367 * Invoke the parent method to complete the work.
4369 error = sc->sc_newstate(ic, nstate, arg);
4371 * Finally, start any timers.
4373 if (nstate == IEEE80211_S_RUN) {
4374 /* start periodic recalibration timer */
4375 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz,
4377 } else if (nstate == IEEE80211_S_SCAN) {
4378 /* start ap/neighbor scan timer */
4379 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000,
4387 * Allocate a key cache slot to the station so we can
4388 * setup a mapping from key index to node. The key cache
4389 * slot is needed for managing antenna state and for
4390 * compression when stations do not use crypto. We do
4391 * it uniliaterally here; if crypto is employed this slot
4392 * will be reassigned.
4395 ath_setup_stationkey(struct ieee80211_node *ni)
4397 struct ieee80211com *ic = ni->ni_ic;
4398 struct ath_softc *sc = ic->ic_ifp->if_softc;
4399 ieee80211_keyix keyix, rxkeyix;
4401 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) {
4403 * Key cache is full; we'll fall back to doing
4404 * the more expensive lookup in software. Note
4405 * this also means no h/w compression.
4407 /* XXX msg+statistic */
4410 ni->ni_ucastkey.wk_keyix = keyix;
4411 ni->ni_ucastkey.wk_rxkeyix = rxkeyix;
4412 /* NB: this will create a pass-thru key entry */
4413 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss);
4418 * Setup driver-specific state for a newly associated node.
4419 * Note that we're called also on a re-associate, the isnew
4420 * param tells us if this is the first time or not.
4423 ath_newassoc(struct ieee80211_node *ni, int isnew)
4425 struct ieee80211com *ic = ni->ni_ic;
4426 struct ath_softc *sc = ic->ic_ifp->if_softc;
4428 ath_rate_newassoc(sc, ATH_NODE(ni), isnew);
4430 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) {
4431 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE,
4432 ("new assoc with a unicast key already setup (keyix %u)",
4433 ni->ni_ucastkey.wk_keyix));
4434 ath_setup_stationkey(ni);
4439 ath_getchannels(struct ath_softc *sc, u_int cc,
4440 HAL_BOOL outdoor, HAL_BOOL xchanmode)
4442 struct ieee80211com *ic = &sc->sc_ic;
4443 struct ifnet *ifp = sc->sc_ifp;
4444 struct ath_hal *ah = sc->sc_ah;
4448 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL),
4450 if (chans == NULL) {
4451 if_printf(ifp, "unable to allocate channel table\n");
4454 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan,
4455 cc, HAL_MODE_ALL, outdoor, xchanmode)) {
4458 ath_hal_getregdomain(ah, &rd);
4459 if_printf(ifp, "unable to collect channel list from hal; "
4460 "regdomain likely %u country code %u\n", rd, cc);
4461 free(chans, M_TEMP);
4466 * Convert HAL channels to ieee80211 ones and insert
4467 * them in the table according to their channel number.
4469 for (i = 0; i < nchan; i++) {
4470 HAL_CHANNEL *c = &chans[i];
4471 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags);
4472 if (ix > IEEE80211_CHAN_MAX) {
4473 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n",
4474 ix, c->channel, c->channelFlags);
4477 /* NB: flags are known to be compatible */
4478 if (ic->ic_channels[ix].ic_freq == 0) {
4479 ic->ic_channels[ix].ic_freq = c->channel;
4480 ic->ic_channels[ix].ic_flags = c->channelFlags;
4482 /* channels overlap; e.g. 11g and 11b */
4483 ic->ic_channels[ix].ic_flags |= c->channelFlags;
4486 free(chans, M_TEMP);
4491 ath_led_done(void *arg)
4493 struct ath_softc *sc = arg;
4495 sc->sc_blinking = 0;
4499 * Turn the LED off: flip the pin and then set a timer so no
4500 * update will happen for the specified duration.
4503 ath_led_off(void *arg)
4505 struct ath_softc *sc = arg;
4507 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
4508 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc);
4512 * Blink the LED according to the specified on/off times.
4515 ath_led_blink(struct ath_softc *sc, int on, int off)
4517 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off);
4518 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon);
4519 sc->sc_blinking = 1;
4520 sc->sc_ledoff = off;
4521 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc);
4525 ath_led_event(struct ath_softc *sc, int event)
4528 sc->sc_ledevent = ticks; /* time of last event */
4529 if (sc->sc_blinking) /* don't interrupt active blink */
4533 ath_led_blink(sc, sc->sc_hwmap[0].ledon,
4534 sc->sc_hwmap[0].ledoff);
4537 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon,
4538 sc->sc_hwmap[sc->sc_txrate].ledoff);
4541 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon,
4542 sc->sc_hwmap[sc->sc_rxrate].ledoff);
4548 ath_update_txpow(struct ath_softc *sc)
4550 struct ieee80211com *ic = &sc->sc_ic;
4551 struct ath_hal *ah = sc->sc_ah;
4554 if (sc->sc_curtxpow != ic->ic_txpowlimit) {
4555 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
4556 /* read back in case value is clamped */
4557 ath_hal_gettxpowlimit(ah, &txpow);
4558 ic->ic_txpowlimit = sc->sc_curtxpow = txpow;
4561 * Fetch max tx power level for status requests.
4563 ath_hal_getmaxtxpow(sc->sc_ah, &txpow);
4564 ic->ic_bss->ni_txpower = txpow;
4568 rate_setup(struct ath_softc *sc,
4569 const HAL_RATE_TABLE *rt, struct ieee80211_rateset *rs)
4573 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) {
4574 DPRINTF(sc, ATH_DEBUG_ANY,
4575 "%s: rate table too small (%u > %u)\n",
4576 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE);
4577 maxrates = IEEE80211_RATE_MAXSIZE;
4579 maxrates = rt->rateCount;
4580 for (i = 0; i < maxrates; i++)
4581 rs->rs_rates[i] = rt->info[i].dot11Rate;
4582 rs->rs_nrates = maxrates;
4586 ath_rate_setup(struct ath_softc *sc, u_int mode)
4588 struct ath_hal *ah = sc->sc_ah;
4589 struct ieee80211com *ic = &sc->sc_ic;
4590 const HAL_RATE_TABLE *rt;
4593 case IEEE80211_MODE_11A:
4594 rt = ath_hal_getratetable(ah, HAL_MODE_11A);
4596 case IEEE80211_MODE_11B:
4597 rt = ath_hal_getratetable(ah, HAL_MODE_11B);
4599 case IEEE80211_MODE_11G:
4600 rt = ath_hal_getratetable(ah, HAL_MODE_11G);
4602 case IEEE80211_MODE_TURBO_A:
4603 /* XXX until static/dynamic turbo is fixed */
4604 rt = ath_hal_getratetable(ah, HAL_MODE_TURBO);
4606 case IEEE80211_MODE_TURBO_G:
4607 rt = ath_hal_getratetable(ah, HAL_MODE_108G);
4610 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
4614 sc->sc_rates[mode] = rt;
4616 rate_setup(sc, rt, &ic->ic_sup_rates[mode]);
4623 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
4625 #define N(a) (sizeof(a)/sizeof(a[0]))
4626 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
4627 static const struct {
4628 u_int rate; /* tx/rx 802.11 rate */
4629 u_int16_t timeOn; /* LED on time (ms) */
4630 u_int16_t timeOff; /* LED off time (ms) */
4647 const HAL_RATE_TABLE *rt;
4650 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
4651 rt = sc->sc_rates[mode];
4652 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
4653 for (i = 0; i < rt->rateCount; i++)
4654 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i;
4655 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
4656 for (i = 0; i < 32; i++) {
4657 u_int8_t ix = rt->rateCodeToIndex[i];
4659 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
4660 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
4663 sc->sc_hwmap[i].ieeerate =
4664 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL;
4665 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
4666 if (rt->info[ix].shortPreamble ||
4667 rt->info[ix].phy == IEEE80211_T_OFDM)
4668 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
4669 /* NB: receive frames include FCS */
4670 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags |
4671 IEEE80211_RADIOTAP_F_FCS;
4672 /* setup blink rate table to avoid per-packet lookup */
4673 for (j = 0; j < N(blinkrates)-1; j++)
4674 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
4676 /* NB: this uses the last entry if the rate isn't found */
4677 /* XXX beware of overlow */
4678 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
4679 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
4681 sc->sc_currates = rt;
4682 sc->sc_curmode = mode;
4684 * All protection frames are transmited at 2Mb/s for
4685 * 11g, otherwise at 1Mb/s.
4687 if (mode == IEEE80211_MODE_11G)
4688 sc->sc_protrix = ath_tx_findrix(rt, 2*2);
4690 sc->sc_protrix = ath_tx_findrix(rt, 2*1);
4691 /* rate index used to send management frames */
4692 sc->sc_minrateix = 0;
4694 * Setup multicast rate state.
4696 /* XXX layering violation */
4697 sc->sc_mcastrix = ath_tx_findrix(rt, sc->sc_ic.ic_mcast_rate);
4698 sc->sc_mcastrate = sc->sc_ic.ic_mcast_rate;
4699 /* NB: caller is responsible for reseting rate control state */
4705 ath_printrxbuf(struct ath_buf *bf, int done)
4707 struct ath_desc *ds;
4710 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
4711 printf("R%d (%p %p) L:%08x D:%08x %08x %08x %08x %08x %c\n",
4712 i, ds, (struct ath_desc *)bf->bf_daddr + i,
4713 ds->ds_link, ds->ds_data,
4714 ds->ds_ctl0, ds->ds_ctl1,
4715 ds->ds_hw[0], ds->ds_hw[1],
4716 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!');
4721 ath_printtxbuf(struct ath_buf *bf, int done)
4723 struct ath_desc *ds;
4726 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
4727 printf("T%d (%p %p) L:%08x D:%08x %08x %08x %08x %08x %08x %08x %c\n",
4728 i, ds, (struct ath_desc *)bf->bf_daddr + i,
4729 ds->ds_link, ds->ds_data,
4730 ds->ds_ctl0, ds->ds_ctl1,
4731 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3],
4732 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!');
4735 #endif /* AR_DEBUG */
4738 ath_watchdog(struct ifnet *ifp)
4740 struct ath_softc *sc = ifp->if_softc;
4741 struct ieee80211com *ic = &sc->sc_ic;
4744 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid)
4746 if (sc->sc_tx_timer) {
4747 if (--sc->sc_tx_timer == 0) {
4748 if_printf(ifp, "device timeout\n");
4751 sc->sc_stats.ast_watchdog++;
4755 ieee80211_watchdog(ic);
4759 * Diagnostic interface to the HAL. This is used by various
4760 * tools to do things like retrieve register contents for
4761 * debugging. The mechanism is intentionally opaque so that
4762 * it can change frequently w/o concern for compatiblity.
4765 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
4767 struct ath_hal *ah = sc->sc_ah;
4768 u_int id = ad->ad_id & ATH_DIAG_ID;
4769 void *indata = NULL;
4770 void *outdata = NULL;
4771 u_int32_t insize = ad->ad_in_size;
4772 u_int32_t outsize = ad->ad_out_size;
4775 if (ad->ad_id & ATH_DIAG_IN) {
4779 indata = malloc(insize, M_TEMP, M_NOWAIT);
4780 if (indata == NULL) {
4784 error = copyin(ad->ad_in_data, indata, insize);
4788 if (ad->ad_id & ATH_DIAG_DYN) {
4790 * Allocate a buffer for the results (otherwise the HAL
4791 * returns a pointer to a buffer where we can read the
4792 * results). Note that we depend on the HAL leaving this
4793 * pointer for us to use below in reclaiming the buffer;
4794 * may want to be more defensive.
4796 outdata = malloc(outsize, M_TEMP, M_NOWAIT);
4797 if (outdata == NULL) {
4802 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
4803 if (outsize < ad->ad_out_size)
4804 ad->ad_out_size = outsize;
4805 if (outdata != NULL)
4806 error = copyout(outdata, ad->ad_out_data,
4812 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
4813 free(indata, M_TEMP);
4814 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
4815 free(outdata, M_TEMP);
4820 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
4822 #define IS_RUNNING(ifp) \
4823 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
4824 struct ath_softc *sc = ifp->if_softc;
4825 struct ieee80211com *ic = &sc->sc_ic;
4826 struct ifreq *ifr = (struct ifreq *)data;
4832 if (IS_RUNNING(ifp)) {
4834 * To avoid rescanning another access point,
4835 * do not call ath_init() here. Instead,
4836 * only reflect promisc mode settings.
4839 } else if (ifp->if_flags & IFF_UP) {
4841 * Beware of being called during attach/detach
4842 * to reset promiscuous mode. In that case we
4843 * will still be marked UP but not RUNNING.
4844 * However trying to re-init the interface
4845 * is the wrong thing to do as we've already
4846 * torn down much of our state. There's
4847 * probably a better way to deal with this.
4849 if (!sc->sc_invalid && ic->ic_bss != NULL)
4850 ath_init(sc); /* XXX lose error */
4852 ath_stop_locked(ifp);
4857 * The upper layer has already installed/removed
4858 * the multicast address(es), just recalculate the
4859 * multicast filter for the card.
4861 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
4865 /* NB: embed these numbers to get a consistent view */
4866 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
4867 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
4868 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic);
4871 * NB: Drop the softc lock in case of a page fault;
4872 * we'll accept any potential inconsisentcy in the
4873 * statistics. The alternative is to copy the data
4874 * to a local structure.
4876 return copyout(&sc->sc_stats,
4877 ifr->ifr_data, sizeof (sc->sc_stats));
4879 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
4882 error = ieee80211_ioctl(ic, cmd, data);
4883 if (error == ENETRESET) {
4884 if (IS_RUNNING(ifp) &&
4885 ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
4886 ath_init(sc); /* XXX lose error */
4889 if (error == ERESTART)
4890 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0;
4899 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS)
4901 struct ath_softc *sc = arg1;
4902 u_int slottime = ath_hal_getslottime(sc->sc_ah);
4905 error = sysctl_handle_int(oidp, &slottime, 0, req);
4906 if (error || !req->newptr)
4908 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0;
4912 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS)
4914 struct ath_softc *sc = arg1;
4915 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah);
4918 error = sysctl_handle_int(oidp, &acktimeout, 0, req);
4919 if (error || !req->newptr)
4921 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0;
4925 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS)
4927 struct ath_softc *sc = arg1;
4928 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah);
4931 error = sysctl_handle_int(oidp, &ctstimeout, 0, req);
4932 if (error || !req->newptr)
4934 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0;
4938 ath_sysctl_softled(SYSCTL_HANDLER_ARGS)
4940 struct ath_softc *sc = arg1;
4941 int softled = sc->sc_softled;
4944 error = sysctl_handle_int(oidp, &softled, 0, req);
4945 if (error || !req->newptr)
4947 softled = (softled != 0);
4948 if (softled != sc->sc_softled) {
4950 /* NB: handle any sc_ledpin change */
4951 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
4952 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
4955 sc->sc_softled = softled;
4961 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS)
4963 struct ath_softc *sc = arg1;
4964 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah);
4967 error = sysctl_handle_int(oidp, &defantenna, 0, req);
4968 if (!error && req->newptr)
4969 ath_hal_setdefantenna(sc->sc_ah, defantenna);
4974 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS)
4976 struct ath_softc *sc = arg1;
4977 u_int diversity = ath_hal_getdiversity(sc->sc_ah);
4980 error = sysctl_handle_int(oidp, &diversity, 0, req);
4981 if (error || !req->newptr)
4983 if (!ath_hal_setdiversity(sc->sc_ah, diversity))
4985 sc->sc_diversity = diversity;
4990 ath_sysctl_diag(SYSCTL_HANDLER_ARGS)
4992 struct ath_softc *sc = arg1;
4996 if (!ath_hal_getdiag(sc->sc_ah, &diag))
4998 error = sysctl_handle_int(oidp, &diag, 0, req);
4999 if (error || !req->newptr)
5001 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0;
5005 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS)
5007 struct ath_softc *sc = arg1;
5008 struct ifnet *ifp = sc->sc_ifp;
5012 ath_hal_gettpscale(sc->sc_ah, &scale);
5013 error = sysctl_handle_int(oidp, &scale, 0, req);
5014 if (error || !req->newptr)
5016 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : ath_reset(ifp);
5020 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS)
5022 struct ath_softc *sc = arg1;
5023 u_int tpc = ath_hal_gettpc(sc->sc_ah);
5026 error = sysctl_handle_int(oidp, &tpc, 0, req);
5027 if (error || !req->newptr)
5029 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0;
5033 ath_sysctl_regdomain(SYSCTL_HANDLER_ARGS)
5035 struct ath_softc *sc = arg1;
5039 if (!ath_hal_getregdomain(sc->sc_ah, &rd))
5041 error = sysctl_handle_int(oidp, &rd, 0, req);
5042 if (error || !req->newptr)
5044 return !ath_hal_setregdomain(sc->sc_ah, rd) ? EINVAL : 0;
5048 ath_sysctlattach(struct ath_softc *sc)
5050 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
5051 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
5052 struct ath_hal *ah = sc->sc_ah;
5054 ath_hal_getcountrycode(sc->sc_ah, &sc->sc_countrycode);
5055 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5056 "countrycode", CTLFLAG_RD, &sc->sc_countrycode, 0,
5057 "EEPROM country code");
5058 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5059 "regdomain", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5060 ath_sysctl_regdomain, "I", "EEPROM regdomain code");
5061 sc->sc_debug = ath_debug;
5062 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5063 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
5064 "control debugging printfs");
5066 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5067 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5068 ath_sysctl_slottime, "I", "802.11 slot time (us)");
5069 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5070 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5071 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)");
5072 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5073 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5074 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)");
5075 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5076 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5077 ath_sysctl_softled, "I", "enable/disable software LED support");
5078 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5079 "ledpin", CTLFLAG_RW, &sc->sc_ledpin, 0,
5080 "GPIO pin connected to LED");
5081 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5082 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0,
5083 "setting to turn LED on");
5084 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5085 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0,
5086 "idle time for inactivity LED (ticks)");
5087 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5088 "txantenna", CTLFLAG_RW, &sc->sc_txantenna, 0,
5089 "tx antenna (0=auto)");
5090 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5091 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5092 ath_sysctl_rxantenna, "I", "default/rx antenna");
5093 if (ath_hal_hasdiversity(ah))
5094 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5095 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5096 ath_sysctl_diversity, "I", "antenna diversity");
5097 sc->sc_txintrperiod = ATH_TXINTR_PERIOD;
5098 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5099 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0,
5100 "tx descriptor batching");
5101 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5102 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5103 ath_sysctl_diag, "I", "h/w diagnostic control");
5104 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5105 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5106 ath_sysctl_tpscale, "I", "tx power scaling");
5107 if (ath_hal_hastpc(ah))
5108 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5109 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
5110 ath_sysctl_tpc, "I", "enable/disable per-packet TPC");
5111 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC;
5112 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
5113 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0,
5114 "mask of error frames to pass when monitoring");
5118 ath_bpfattach(struct ath_softc *sc)
5120 struct ifnet *ifp = sc->sc_ifp;
5122 bpfattach2(ifp, DLT_IEEE802_11_RADIO,
5123 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
5126 * Initialize constant fields.
5127 * XXX make header lengths a multiple of 32-bits so subsequent
5128 * headers are properly aligned; this is a kludge to keep
5129 * certain applications happy.
5131 * NB: the channel is setup each time we transition to the
5132 * RUN state to avoid filling it in for each frame.
5134 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t));
5135 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
5136 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT);
5138 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t));
5139 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
5140 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT);
5144 * Announce various information on device/driver attach.
5147 ath_announce(struct ath_softc *sc)
5149 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B)
5150 struct ifnet *ifp = sc->sc_ifp;
5151 struct ath_hal *ah = sc->sc_ah;
5154 if_printf(ifp, "mac %d.%d phy %d.%d",
5155 ah->ah_macVersion, ah->ah_macRev,
5156 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
5158 * Print radio revision(s). We check the wireless modes
5159 * to avoid falsely printing revs for inoperable parts.
5160 * Dual-band radio revs are returned in the 5Ghz rev number.
5162 ath_hal_getcountrycode(ah, &cc);
5163 modes = ath_hal_getwirelessmodes(ah, cc);
5164 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) {
5165 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev)
5166 printf(" 5ghz radio %d.%d 2ghz radio %d.%d",
5167 ah->ah_analog5GhzRev >> 4,
5168 ah->ah_analog5GhzRev & 0xf,
5169 ah->ah_analog2GhzRev >> 4,
5170 ah->ah_analog2GhzRev & 0xf);
5172 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
5173 ah->ah_analog5GhzRev & 0xf);
5175 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
5176 ah->ah_analog5GhzRev & 0xf);
5180 for (i = 0; i <= WME_AC_VO; i++) {
5181 struct ath_txq *txq = sc->sc_ac2q[i];
5182 if_printf(ifp, "Use hw queue %u for %s traffic\n",
5183 txq->axq_qnum, ieee80211_wme_acnames[i]);
5185 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
5186 sc->sc_cabq->axq_qnum);
5187 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
5189 if (ath_rxbuf != ATH_RXBUF)
5190 if_printf(ifp, "using %u rx buffers\n", ath_rxbuf);
5191 if (ath_txbuf != ATH_TXBUF)
5192 if_printf(ifp, "using %u tx buffers\n", ath_txbuf);
5193 #undef HAL_MODE_DUALBAND