2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
41 * Driver for the Atheros Wireless LAN controller.
43 * This software is derived from work of Atsushi Onoe; his contribution
44 * is greatly appreciated.
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/sysctl.h>
53 #include <sys/malloc.h>
55 #include <sys/mutex.h>
56 #include <sys/kernel.h>
57 #include <sys/socket.h>
58 #include <sys/sockio.h>
59 #include <sys/errno.h>
60 #include <sys/callout.h>
62 #include <sys/endian.h>
64 #include <machine/bus.h>
67 #include <net/if_dl.h>
68 #include <net/if_media.h>
69 #include <net/if_types.h>
70 #include <net/if_arp.h>
71 #include <net/ethernet.h>
72 #include <net/if_llc.h>
74 #include <net80211/ieee80211_var.h>
79 #include <netinet/in.h>
80 #include <netinet/if_ether.h>
84 #include <dev/ath/if_athvar.h>
85 #include <contrib/dev/ath/ah_desc.h>
86 #include <contrib/dev/ath/ah_devid.h> /* XXX for softled */
88 /* unaligned little endian access */
89 #define LE_READ_2(p) \
91 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8)))
92 #define LE_READ_4(p) \
94 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \
95 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24)))
103 static void ath_init(void *);
104 static void ath_stop_locked(struct ifnet *);
105 static void ath_stop(struct ifnet *);
106 static void ath_start(struct ifnet *);
107 static int ath_reset(struct ifnet *);
108 static int ath_media_change(struct ifnet *);
109 static void ath_watchdog(struct ifnet *);
110 static int ath_ioctl(struct ifnet *, u_long, caddr_t);
111 static void ath_fatal_proc(void *, int);
112 static void ath_rxorn_proc(void *, int);
113 static void ath_bmiss_proc(void *, int);
114 static int ath_key_alloc(struct ieee80211com *,
115 const struct ieee80211_key *);
116 static int ath_key_delete(struct ieee80211com *,
117 const struct ieee80211_key *);
118 static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *,
119 const u_int8_t mac[IEEE80211_ADDR_LEN]);
120 static void ath_key_update_begin(struct ieee80211com *);
121 static void ath_key_update_end(struct ieee80211com *);
122 static void ath_mode_init(struct ath_softc *);
123 static void ath_setslottime(struct ath_softc *);
124 static void ath_updateslot(struct ifnet *);
125 static int ath_beaconq_setup(struct ath_hal *);
126 static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *);
127 static void ath_beacon_setup(struct ath_softc *, struct ath_buf *);
128 static void ath_beacon_proc(void *, int);
129 static void ath_bstuck_proc(void *, int);
130 static void ath_beacon_free(struct ath_softc *);
131 static void ath_beacon_config(struct ath_softc *);
132 static void ath_descdma_cleanup(struct ath_softc *sc,
133 struct ath_descdma *, ath_bufhead *);
134 static int ath_desc_alloc(struct ath_softc *);
135 static void ath_desc_free(struct ath_softc *);
136 static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *);
137 static void ath_node_free(struct ieee80211_node *);
138 static u_int8_t ath_node_getrssi(const struct ieee80211_node *);
139 static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *);
140 static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
141 struct ieee80211_node *ni,
142 int subtype, int rssi, u_int32_t rstamp);
143 static void ath_setdefantenna(struct ath_softc *, u_int);
144 static void ath_rx_proc(void *, int);
145 static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype);
146 static int ath_tx_setup(struct ath_softc *, int, int);
147 static int ath_wme_update(struct ieee80211com *);
148 static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *);
149 static void ath_tx_cleanup(struct ath_softc *);
150 static int ath_tx_start(struct ath_softc *, struct ieee80211_node *,
151 struct ath_buf *, struct mbuf *);
152 static void ath_tx_proc_q0(void *, int);
153 static void ath_tx_proc_q0123(void *, int);
154 static void ath_tx_proc(void *, int);
155 static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *);
156 static void ath_draintxq(struct ath_softc *);
157 static void ath_stoprecv(struct ath_softc *);
158 static int ath_startrecv(struct ath_softc *);
159 static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *);
160 static void ath_next_scan(void *);
161 static void ath_calibrate(void *);
162 static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int);
163 static void ath_setup_stationkey(struct ieee80211_node *);
164 static void ath_newassoc(struct ieee80211com *,
165 struct ieee80211_node *, int);
166 static int ath_getchannels(struct ath_softc *, u_int cc,
167 HAL_BOOL outdoor, HAL_BOOL xchanmode);
168 static void ath_led_event(struct ath_softc *, int);
169 static void ath_update_txpow(struct ath_softc *);
171 static int ath_rate_setup(struct ath_softc *, u_int mode);
172 static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode);
174 static void ath_sysctlattach(struct ath_softc *);
175 static void ath_bpfattach(struct ath_softc *);
176 static void ath_announce(struct ath_softc *);
178 SYSCTL_DECL(_hw_ath);
180 /* XXX validate sysctl values */
181 static int ath_dwelltime = 200; /* 5 channels/second */
182 SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime,
183 0, "channel dwell time (ms) for AP/station scanning");
184 static int ath_calinterval = 30; /* calibrate every 30 secs */
185 SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval,
186 0, "chip calibration interval (secs)");
187 static int ath_outdoor = AH_TRUE; /* outdoor operation */
188 SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor,
189 0, "outdoor operation");
190 TUNABLE_INT("hw.ath.outdoor", &ath_outdoor);
191 static int ath_xchanmode = AH_TRUE; /* extended channel use */
192 SYSCTL_INT(_hw_ath, OID_AUTO, xchanmode, CTLFLAG_RD, &ath_xchanmode,
193 0, "extended channel mode");
194 TUNABLE_INT("hw.ath.xchanmode", &ath_xchanmode);
195 static int ath_countrycode = CTRY_DEFAULT; /* country code */
196 SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode,
198 TUNABLE_INT("hw.ath.countrycode", &ath_countrycode);
199 static int ath_regdomain = 0; /* regulatory domain */
200 SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain,
201 0, "regulatory domain");
204 static int ath_debug = 0;
205 SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug,
206 0, "control debugging printfs");
207 TUNABLE_INT("hw.ath.debug", &ath_debug);
209 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
210 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */
211 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */
212 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */
213 ATH_DEBUG_RATE = 0x00000010, /* rate control */
214 ATH_DEBUG_RESET = 0x00000020, /* reset processing */
215 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */
216 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */
217 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */
218 ATH_DEBUG_INTR = 0x00001000, /* ISR */
219 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */
220 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */
221 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */
222 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */
223 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */
224 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */
225 ATH_DEBUG_NODE = 0x00080000, /* node management */
226 ATH_DEBUG_LED = 0x00100000, /* led management */
227 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */
228 ATH_DEBUG_ANY = 0xffffffff
230 #define IFF_DUMPPKTS(sc, m) \
231 ((sc->sc_debug & (m)) || \
232 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
233 #define DPRINTF(sc, m, fmt, ...) do { \
234 if (sc->sc_debug & (m)) \
235 printf(fmt, __VA_ARGS__); \
237 #define KEYPRINTF(sc, ix, hk, mac) do { \
238 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \
239 ath_keyprint(__func__, ix, hk, mac); \
241 static void ath_printrxbuf(struct ath_buf *bf, int);
242 static void ath_printtxbuf(struct ath_buf *bf, int);
244 #define IFF_DUMPPKTS(sc, m) \
245 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2))
246 #define DPRINTF(m, fmt, ...)
247 #define KEYPRINTF(sc, k, ix, mac)
250 MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers");
253 ath_attach(u_int16_t devid, struct ath_softc *sc)
256 struct ieee80211com *ic = &sc->sc_ic;
257 struct ath_hal *ah = NULL;
261 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid);
263 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
265 device_printf(sc->sc_dev, "can not if_alloc()\n");
270 /* set these up early for if_printf use */
271 if_initname(ifp, device_get_name(sc->sc_dev),
272 device_get_unit(sc->sc_dev));
274 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status);
276 if_printf(ifp, "unable to attach hardware; HAL status %u\n",
281 if (ah->ah_abi != HAL_ABI_VERSION) {
282 if_printf(ifp, "HAL ABI mismatch detected "
283 "(HAL:0x%x != driver:0x%x)\n",
284 ah->ah_abi, HAL_ABI_VERSION);
289 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */
292 * Check if the MAC has multi-rate retry support.
293 * We do this by trying to setup a fake extended
294 * descriptor. MAC's that don't have support will
295 * return false w/o doing anything. MAC's that do
296 * support it will return true w/o doing anything.
298 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0);
301 * Check if the device has hardware counters for PHY
302 * errors. If so we need to enable the MIB interrupt
303 * so we can act on stat triggers.
305 if (ath_hal_hwphycounters(ah))
309 * Get the hardware key cache size.
311 sc->sc_keymax = ath_hal_keycachesize(ah);
312 if (sc->sc_keymax > ATH_KEYMAX) {
313 if_printf(ifp, "Warning, using only %u of %u key cache slots\n",
314 ATH_KEYMAX, sc->sc_keymax);
315 sc->sc_keymax = ATH_KEYMAX;
318 * Reset the key cache since some parts do not
319 * reset the contents on initial power up.
321 for (i = 0; i < sc->sc_keymax; i++)
322 ath_hal_keyreset(ah, i);
324 * Mark key cache slots associated with global keys
325 * as in use. If we knew TKIP was not to be used we
326 * could leave the +32, +64, and +32+64 slots free.
327 * XXX only for splitmic.
329 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
330 setbit(sc->sc_keymap, i);
331 setbit(sc->sc_keymap, i+32);
332 setbit(sc->sc_keymap, i+64);
333 setbit(sc->sc_keymap, i+32+64);
337 * Collect the channel list using the default country
338 * code and including outdoor channels. The 802.11 layer
339 * is resposible for filtering this list based on settings
342 error = ath_getchannels(sc, ath_countrycode,
343 ath_outdoor, ath_xchanmode);
347 * Setup dynamic sysctl's now that country code and
348 * regdomain are available from the hal.
350 ath_sysctlattach(sc);
353 * Setup rate tables for all potential media types.
355 ath_rate_setup(sc, IEEE80211_MODE_11A);
356 ath_rate_setup(sc, IEEE80211_MODE_11B);
357 ath_rate_setup(sc, IEEE80211_MODE_11G);
358 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A);
359 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G);
360 /* NB: setup here so ath_rate_update is happy */
361 ath_setcurmode(sc, IEEE80211_MODE_11A);
364 * Allocate tx+rx descriptors and populate the lists.
366 error = ath_desc_alloc(sc);
368 if_printf(ifp, "failed to allocate descriptors: %d\n", error);
371 callout_init(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0);
372 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE);
374 ATH_TXBUF_LOCK_INIT(sc);
376 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc);
377 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc);
378 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc);
379 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc);
380 TASK_INIT(&sc->sc_bstucktask, 0, ath_bstuck_proc, sc);
383 * Allocate hardware transmit queues: one queue for
384 * beacon frames and one data queue for each QoS
385 * priority. Note that the hal handles reseting
386 * these queues at the needed time.
390 sc->sc_bhalq = ath_beaconq_setup(ah);
391 if (sc->sc_bhalq == (u_int) -1) {
392 if_printf(ifp, "unable to setup a beacon xmit queue!\n");
396 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0);
397 if (sc->sc_cabq == NULL) {
398 if_printf(ifp, "unable to setup CAB xmit queue!\n");
402 /* NB: insure BK queue is the lowest priority h/w queue */
403 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) {
404 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n",
405 ieee80211_wme_acnames[WME_AC_BK]);
409 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) ||
410 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) ||
411 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) {
413 * Not enough hardware tx queues to properly do WME;
414 * just punt and assign them all to the same h/w queue.
415 * We could do a better job of this if, for example,
416 * we allocate queues when we switch from station to
419 if (sc->sc_ac2q[WME_AC_VI] != NULL)
420 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]);
421 if (sc->sc_ac2q[WME_AC_BE] != NULL)
422 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]);
423 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK];
424 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK];
425 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK];
429 * Special case certain configurations. Note the
430 * CAB queue is handled by these specially so don't
431 * include them when checking the txq setup mask.
433 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) {
435 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc);
438 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc);
441 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc);
446 * Setup rate control. Some rate control modules
447 * call back to change the anntena state so expose
448 * the necessary entry points.
449 * XXX maybe belongs in struct ath_ratectrl?
451 sc->sc_setdefantenna = ath_setdefantenna;
452 sc->sc_rc = ath_rate_attach(sc);
453 if (sc->sc_rc == NULL) {
460 sc->sc_ledon = 0; /* low true */
461 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */
462 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE);
464 * Auto-enable soft led processing for IBM cards and for
465 * 5211 minipci cards. Users can also manually enable/disable
466 * support with a sysctl.
468 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID);
469 if (sc->sc_softled) {
470 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin);
471 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon);
475 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST;
476 ifp->if_start = ath_start;
477 ifp->if_watchdog = ath_watchdog;
478 ifp->if_ioctl = ath_ioctl;
479 ifp->if_init = ath_init;
480 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
481 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
482 IFQ_SET_READY(&ifp->if_snd);
485 ic->ic_reset = ath_reset;
486 ic->ic_newassoc = ath_newassoc;
487 ic->ic_updateslot = ath_updateslot;
488 ic->ic_wme.wme_update = ath_wme_update;
489 /* XXX not right but it's not used anywhere important */
490 ic->ic_phytype = IEEE80211_T_OFDM;
491 ic->ic_opmode = IEEE80211_M_STA;
493 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */
494 | IEEE80211_C_HOSTAP /* hostap mode */
495 | IEEE80211_C_MONITOR /* monitor mode */
496 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
497 | IEEE80211_C_SHSLOT /* short slot time supported */
498 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
501 * Query the hal to figure out h/w crypto support.
503 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP))
504 ic->ic_caps |= IEEE80211_C_WEP;
505 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB))
506 ic->ic_caps |= IEEE80211_C_AES;
507 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM))
508 ic->ic_caps |= IEEE80211_C_AES_CCM;
509 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP))
510 ic->ic_caps |= IEEE80211_C_CKIP;
511 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) {
512 ic->ic_caps |= IEEE80211_C_TKIP;
514 * Check if h/w does the MIC and/or whether the
515 * separate key cache entries are required to
516 * handle both tx+rx MIC keys.
518 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC))
519 ic->ic_caps |= IEEE80211_C_TKIPMIC;
520 if (ath_hal_tkipsplit(ah))
523 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR);
524 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah);
526 * TPC support can be done either with a global cap or
527 * per-packet support. The latter is not available on
528 * all parts. We're a bit pedantic here as all parts
529 * support a global cap.
531 sc->sc_hastpc = ath_hal_hastpc(ah);
532 if (sc->sc_hastpc || ath_hal_hastxpowlimit(ah))
533 ic->ic_caps |= IEEE80211_C_TXPMGT;
536 * Mark WME capability only if we have sufficient
537 * hardware queues to do proper priority scheduling.
539 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK])
540 ic->ic_caps |= IEEE80211_C_WME;
542 * Check for misc other capabilities.
544 if (ath_hal_hasbursting(ah))
545 ic->ic_caps |= IEEE80211_C_BURST;
548 * Indicate we need the 802.11 header padded to a
549 * 32-bit boundary for 4-address and QoS frames.
551 ic->ic_flags |= IEEE80211_F_DATAPAD;
554 * Query the hal about antenna support.
556 if (ath_hal_hasdiversity(ah)) {
557 sc->sc_hasdiversity = 1;
558 sc->sc_diversity = ath_hal_getdiversity(ah);
560 sc->sc_defant = ath_hal_getdefantenna(ah);
563 * Not all chips have the VEOL support we want to
564 * use with IBSS beacons; check here for it.
566 sc->sc_hasveol = ath_hal_hasveol(ah);
568 /* get mac address from hardware */
569 ath_hal_getmac(ah, ic->ic_myaddr);
571 /* call MI attach routine. */
572 ieee80211_ifattach(ic);
573 /* override default methods */
574 ic->ic_node_alloc = ath_node_alloc;
575 sc->sc_node_free = ic->ic_node_free;
576 ic->ic_node_free = ath_node_free;
577 ic->ic_node_getrssi = ath_node_getrssi;
578 sc->sc_recv_mgmt = ic->ic_recv_mgmt;
579 ic->ic_recv_mgmt = ath_recv_mgmt;
580 sc->sc_newstate = ic->ic_newstate;
581 ic->ic_newstate = ath_newstate;
582 ic->ic_crypto.cs_key_alloc = ath_key_alloc;
583 ic->ic_crypto.cs_key_delete = ath_key_delete;
584 ic->ic_crypto.cs_key_set = ath_key_set;
585 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin;
586 ic->ic_crypto.cs_key_update_end = ath_key_update_end;
587 /* complete initialization */
588 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status);
593 ieee80211_announce(ic);
609 ath_detach(struct ath_softc *sc)
611 struct ifnet *ifp = sc->sc_ifp;
613 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
614 __func__, ifp->if_flags);
619 * NB: the order of these is important:
620 * o call the 802.11 layer before detaching the hal to
621 * insure callbacks into the driver to delete global
622 * key cache entries can be handled
623 * o reclaim the tx queue data structures after calling
624 * the 802.11 layer as we'll get called back to reclaim
625 * node state and potentially want to use them
626 * o to cleanup the tx queues the hal is called, so detach
628 * Other than that, it's straightforward...
630 ieee80211_ifdetach(&sc->sc_ic);
631 ath_rate_detach(sc->sc_rc);
634 ath_hal_detach(sc->sc_ah);
640 ath_suspend(struct ath_softc *sc)
642 struct ifnet *ifp = sc->sc_ifp;
644 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
645 __func__, ifp->if_flags);
651 ath_resume(struct ath_softc *sc)
653 struct ifnet *ifp = sc->sc_ifp;
655 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
656 __func__, ifp->if_flags);
658 if (ifp->if_flags & IFF_UP) {
660 if (ifp->if_flags & IFF_RUNNING)
663 if (sc->sc_softled) {
664 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
665 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
670 ath_shutdown(struct ath_softc *sc)
672 struct ifnet *ifp = sc->sc_ifp;
674 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n",
675 __func__, ifp->if_flags);
681 * Interrupt handler. Most of the actual processing is deferred.
686 struct ath_softc *sc = arg;
687 struct ifnet *ifp = sc->sc_ifp;
688 struct ath_hal *ah = sc->sc_ah;
691 if (sc->sc_invalid) {
693 * The hardware is not ready/present, don't touch anything.
694 * Note this can happen early on if the IRQ is shared.
696 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__);
699 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */
701 if ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) != (IFF_RUNNING|IFF_UP)) {
702 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
703 __func__, ifp->if_flags);
704 ath_hal_getisr(ah, &status); /* clear ISR */
705 ath_hal_intrset(ah, 0); /* disable further intr's */
709 * Figure out the reason(s) for the interrupt. Note
710 * that the hal returns a pseudo-ISR that may include
711 * bits we haven't explicitly enabled so we mask the
712 * value to insure we only process bits we requested.
714 ath_hal_getisr(ah, &status); /* NB: clears ISR too */
715 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status);
716 status &= sc->sc_imask; /* discard unasked for bits */
717 if (status & HAL_INT_FATAL) {
719 * Fatal errors are unrecoverable. Typically
720 * these are caused by DMA errors. Unfortunately
721 * the exact reason is not (presently) returned
724 sc->sc_stats.ast_hardware++;
725 ath_hal_intrset(ah, 0); /* disable intr's until reset */
726 taskqueue_enqueue(taskqueue_swi, &sc->sc_fataltask);
727 } else if (status & HAL_INT_RXORN) {
728 sc->sc_stats.ast_rxorn++;
729 ath_hal_intrset(ah, 0); /* disable intr's until reset */
730 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxorntask);
732 if (status & HAL_INT_SWBA) {
734 * Software beacon alert--time to send a beacon.
735 * Handle beacon transmission directly; deferring
736 * this is too slow to meet timing constraints
739 ath_beacon_proc(sc, 0);
741 if (status & HAL_INT_RXEOL) {
743 * NB: the hardware should re-read the link when
744 * RXE bit is written, but it doesn't work at
745 * least on older hardware revs.
747 sc->sc_stats.ast_rxeol++;
748 sc->sc_rxlink = NULL;
750 if (status & HAL_INT_TXURN) {
751 sc->sc_stats.ast_txurn++;
752 /* bump tx trigger level */
753 ath_hal_updatetxtriglevel(ah, AH_TRUE);
755 if (status & HAL_INT_RX)
756 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxtask);
757 if (status & HAL_INT_TX)
758 taskqueue_enqueue(taskqueue_swi, &sc->sc_txtask);
759 if (status & HAL_INT_BMISS) {
760 sc->sc_stats.ast_bmiss++;
761 taskqueue_enqueue(taskqueue_swi, &sc->sc_bmisstask);
763 if (status & HAL_INT_MIB) {
764 sc->sc_stats.ast_mib++;
766 * Disable interrupts until we service the MIB
767 * interrupt; otherwise it will continue to fire.
769 ath_hal_intrset(ah, 0);
771 * Let the hal handle the event. We assume it will
772 * clear whatever condition caused the interrupt.
775 &ATH_NODE(sc->sc_ic.ic_bss)->an_halstats);
776 ath_hal_intrset(ah, sc->sc_imask);
782 ath_fatal_proc(void *arg, int pending)
784 struct ath_softc *sc = arg;
785 struct ifnet *ifp = sc->sc_ifp;
787 if_printf(ifp, "hardware error; resetting\n");
792 ath_rxorn_proc(void *arg, int pending)
794 struct ath_softc *sc = arg;
795 struct ifnet *ifp = sc->sc_ifp;
797 if_printf(ifp, "rx FIFO overrun; resetting\n");
802 ath_bmiss_proc(void *arg, int pending)
804 struct ath_softc *sc = arg;
805 struct ieee80211com *ic = &sc->sc_ic;
807 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending);
808 KASSERT(ic->ic_opmode == IEEE80211_M_STA,
809 ("unexpect operating mode %u", ic->ic_opmode));
810 if (ic->ic_state == IEEE80211_S_RUN) {
812 * Rather than go directly to scan state, try to
813 * reassociate first. If that fails then the state
814 * machine will drop us into scanning after timing
815 * out waiting for a probe response.
818 ieee80211_new_state(ic, IEEE80211_S_ASSOC, -1);
824 ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan)
826 #define N(a) (sizeof(a) / sizeof(a[0]))
827 static const u_int modeflags[] = {
828 0, /* IEEE80211_MODE_AUTO */
829 CHANNEL_A, /* IEEE80211_MODE_11A */
830 CHANNEL_B, /* IEEE80211_MODE_11B */
831 CHANNEL_PUREG, /* IEEE80211_MODE_11G */
832 0, /* IEEE80211_MODE_FH */
833 CHANNEL_T, /* IEEE80211_MODE_TURBO_A */
834 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */
836 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan);
838 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode));
839 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode));
840 return modeflags[mode];
847 struct ath_softc *sc = (struct ath_softc *) arg;
848 struct ieee80211com *ic = &sc->sc_ic;
849 struct ifnet *ifp = sc->sc_ifp;
850 struct ieee80211_node *ni;
851 struct ath_hal *ah = sc->sc_ah;
854 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n",
855 __func__, ifp->if_flags);
859 * Stop anything previously setup. This is safe
860 * whether this is the first time through or not.
862 ath_stop_locked(ifp);
865 * The basic interface to setting the hardware in a good
866 * state is ``reset''. On return the hardware is known to
867 * be powered up and with interrupts disabled. This must
868 * be followed by initialization of the appropriate bits
869 * and then setup of the interrupt mask.
871 sc->sc_curchan.channel = ic->ic_ibss_chan->ic_freq;
872 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_ibss_chan);
873 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) {
874 if_printf(ifp, "unable to reset hardware; hal status %u\n",
880 * This is needed only to setup initial state
881 * but it's best done after a reset.
883 ath_update_txpow(sc);
886 * Setup the hardware after reset: the key cache
887 * is filled as needed and the receive engine is
888 * set going. Frame transmit is handled entirely
889 * in the frame output path; there's nothing to do
890 * here except setup the interrupt mask.
892 if (ath_startrecv(sc) != 0) {
893 if_printf(ifp, "unable to start recv logic\n");
900 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
901 | HAL_INT_RXEOL | HAL_INT_RXORN
902 | HAL_INT_FATAL | HAL_INT_GLOBAL;
904 * Enable MIB interrupts when there are hardware phy counters.
905 * Note we only do this (at the moment) for station mode.
907 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA)
908 sc->sc_imask |= HAL_INT_MIB;
909 ath_hal_intrset(ah, sc->sc_imask);
911 ifp->if_flags |= IFF_RUNNING;
912 ic->ic_state = IEEE80211_S_INIT;
915 * The hardware should be ready to go now so it's safe
916 * to kick the 802.11 state machine as it's likely to
917 * immediately call back to us to send mgmt frames.
920 ni->ni_chan = ic->ic_ibss_chan;
921 ath_chan_change(sc, ni->ni_chan);
922 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
923 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
924 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
926 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
932 ath_stop_locked(struct ifnet *ifp)
934 struct ath_softc *sc = ifp->if_softc;
935 struct ieee80211com *ic = &sc->sc_ic;
936 struct ath_hal *ah = sc->sc_ah;
938 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n",
939 __func__, sc->sc_invalid, ifp->if_flags);
942 if (ifp->if_flags & IFF_RUNNING) {
944 * Shutdown the hardware and driver:
945 * reset 802.11 state machine
949 * clear transmit machinery
950 * clear receive machinery
951 * drain and release tx queues
952 * reclaim beacon resources
953 * power down hardware
955 * Note that some of this work is not possible if the
956 * hardware is gone (invalid).
958 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
959 ifp->if_flags &= ~IFF_RUNNING;
961 if (!sc->sc_invalid) {
962 if (sc->sc_softled) {
963 callout_stop(&sc->sc_ledtimer);
964 ath_hal_gpioset(ah, sc->sc_ledpin,
968 ath_hal_intrset(ah, 0);
971 if (!sc->sc_invalid) {
973 ath_hal_phydisable(ah);
975 sc->sc_rxlink = NULL;
976 IFQ_DRV_PURGE(&ifp->if_snd);
982 ath_stop(struct ifnet *ifp)
984 struct ath_softc *sc = ifp->if_softc;
987 ath_stop_locked(ifp);
988 if (!sc->sc_invalid) {
990 * Set the chip in full sleep mode. Note that we are
991 * careful to do this only when bringing the interface
992 * completely to a stop. When the chip is in this state
993 * it must be carefully woken up or references to
994 * registers in the PCI clock domain may freeze the bus
995 * (and system). This varies by chip and is mostly an
996 * issue with newer parts that go to sleep more quickly.
998 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP, 0);
1004 * Reset the hardware w/o losing operational state. This is
1005 * basically a more efficient way of doing ath_stop, ath_init,
1006 * followed by state transitions to the current 802.11
1007 * operational state. Used to recover from various errors and
1008 * to reset or reload hardware state.
1011 ath_reset(struct ifnet *ifp)
1013 struct ath_softc *sc = ifp->if_softc;
1014 struct ieee80211com *ic = &sc->sc_ic;
1015 struct ath_hal *ah = sc->sc_ah;
1016 struct ieee80211_channel *c;
1020 * Convert to a HAL channel description with the flags
1021 * constrained to reflect the current operating mode.
1023 c = ic->ic_ibss_chan;
1024 sc->sc_curchan.channel = c->ic_freq;
1025 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c);
1027 ath_hal_intrset(ah, 0); /* disable interrupts */
1028 ath_draintxq(sc); /* stop xmit side */
1029 ath_stoprecv(sc); /* stop recv side */
1030 /* NB: indicate channel change so we do a full reset */
1031 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status))
1032 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n",
1034 ath_update_txpow(sc); /* update tx power state */
1035 if (ath_startrecv(sc) != 0) /* restart recv */
1036 if_printf(ifp, "%s: unable to start recv logic\n", __func__);
1038 * We may be doing a reset in response to an ioctl
1039 * that changes the channel so update any state that
1040 * might change as a result.
1042 ath_chan_change(sc, c);
1043 if (ic->ic_state == IEEE80211_S_RUN)
1044 ath_beacon_config(sc); /* restart beacons */
1045 ath_hal_intrset(ah, sc->sc_imask);
1047 ath_start(ifp); /* restart xmit */
1052 ath_start(struct ifnet *ifp)
1054 struct ath_softc *sc = ifp->if_softc;
1055 struct ath_hal *ah = sc->sc_ah;
1056 struct ieee80211com *ic = &sc->sc_ic;
1057 struct ieee80211_node *ni;
1060 struct ieee80211_frame *wh;
1061 struct ether_header *eh;
1063 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid)
1067 * Grab a TX buffer and associated resources.
1070 bf = STAILQ_FIRST(&sc->sc_txbuf);
1072 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list);
1073 ATH_TXBUF_UNLOCK(sc);
1075 DPRINTF(sc, ATH_DEBUG_ANY, "%s: out of xmit buffers\n",
1077 sc->sc_stats.ast_tx_qstop++;
1078 ifp->if_flags |= IFF_OACTIVE;
1082 * Poll the management queue for frames; they
1083 * have priority over normal data frames.
1085 IF_DEQUEUE(&ic->ic_mgtq, m);
1088 * No data frames go out unless we're associated.
1090 if (ic->ic_state != IEEE80211_S_RUN) {
1091 DPRINTF(sc, ATH_DEBUG_ANY,
1092 "%s: ignore data packet, state %u\n",
1093 __func__, ic->ic_state);
1094 sc->sc_stats.ast_tx_discard++;
1096 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1097 ATH_TXBUF_UNLOCK(sc);
1100 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */
1103 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1104 ATH_TXBUF_UNLOCK(sc);
1108 * Find the node for the destination so we can do
1109 * things like power save and fast frames aggregation.
1111 if (m->m_len < sizeof(struct ether_header) &&
1112 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) {
1113 ic->ic_stats.is_tx_nobuf++; /* XXX */
1117 eh = mtod(m, struct ether_header *);
1118 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1120 /* NB: ieee80211_find_txnode does stat+msg */
1124 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) &&
1125 (m->m_flags & M_PWR_SAV) == 0) {
1127 * Station in power save mode; pass the frame
1128 * to the 802.11 layer and continue. We'll get
1129 * the frame back when the time is right.
1131 ieee80211_pwrsave(ic, ni, m);
1134 /* calculate priority so we can find the tx queue */
1135 if (ieee80211_classify(ic, m, ni)) {
1136 DPRINTF(sc, ATH_DEBUG_XMIT,
1137 "%s: discard, classification failure\n",
1145 * Encapsulate the packet in prep for transmission.
1147 m = ieee80211_encap(ic, m, ni);
1149 DPRINTF(sc, ATH_DEBUG_ANY,
1150 "%s: encapsulation failure\n",
1152 sc->sc_stats.ast_tx_encap++;
1157 * Hack! The referenced node pointer is in the
1158 * rcvif field of the packet header. This is
1159 * placed there by ieee80211_mgmt_output because
1160 * we need to hold the reference with the frame
1161 * and there's no other way (other than packet
1162 * tags which we consider too expensive to use)
1165 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1166 m->m_pkthdr.rcvif = NULL;
1168 wh = mtod(m, struct ieee80211_frame *);
1169 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1170 IEEE80211_FC0_SUBTYPE_PROBE_RESP) {
1171 /* fill time stamp */
1175 tsf = ath_hal_gettsf64(ah);
1176 /* XXX: adjust 100us delay to xmit */
1178 tstamp = (u_int32_t *)&wh[1];
1179 tstamp[0] = htole32(tsf & 0xffffffff);
1180 tstamp[1] = htole32(tsf >> 32);
1182 sc->sc_stats.ast_tx_mgmt++;
1185 if (ath_tx_start(sc, ni, bf, m)) {
1190 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
1191 ATH_TXBUF_UNLOCK(sc);
1193 ieee80211_free_node(ni);
1197 sc->sc_tx_timer = 5;
1203 ath_media_change(struct ifnet *ifp)
1205 #define IS_UP(ifp) \
1206 ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP))
1209 error = ieee80211_media_change(ifp);
1210 if (error == ENETRESET) {
1212 ath_init(ifp->if_softc); /* XXX lose error */
1221 ath_keyprint(const char *tag, u_int ix,
1222 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1224 static const char *ciphers[] = {
1234 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]);
1235 for (i = 0, n = hk->kv_len; i < n; i++)
1236 printf("%02x", hk->kv_val[i]);
1237 printf(" mac %s", ether_sprintf(mac));
1238 if (hk->kv_type == HAL_CIPHER_TKIP) {
1240 for (i = 0; i < sizeof(hk->kv_mic); i++)
1241 printf("%02x", hk->kv_mic[i]);
1248 * Set a TKIP key into the hardware. This handles the
1249 * potential distribution of key state to multiple key
1250 * cache slots for TKIP.
1253 ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k,
1254 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN])
1256 #define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV)
1257 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN];
1258 struct ath_hal *ah = sc->sc_ah;
1260 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP,
1261 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher));
1262 KASSERT(sc->sc_splitmic, ("key cache !split"));
1263 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) {
1265 * TX key goes at first index, RX key at +32.
1266 * The hal handles the MIC keys at index+64.
1268 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic));
1269 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid);
1270 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid))
1273 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic));
1274 KEYPRINTF(sc, k->wk_keyix+32, hk, mac);
1275 /* XXX delete tx key on failure? */
1276 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac);
1277 } else if (k->wk_flags & IEEE80211_KEY_XR) {
1279 * TX/RX key goes at first index.
1280 * The hal handles the MIC keys are index+64.
1282 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ?
1283 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic));
1284 KEYPRINTF(sc, k->wk_keyix, hk, mac);
1285 return ath_hal_keyset(ah, k->wk_keyix, hk, mac);
1288 #undef IEEE80211_KEY_XR
1292 * Set a net80211 key into the hardware. This handles the
1293 * potential distribution of key state to multiple key
1294 * cache slots for TKIP with hardware MIC support.
1297 ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k,
1298 const u_int8_t mac0[IEEE80211_ADDR_LEN],
1299 struct ieee80211_node *bss)
1301 #define N(a) (sizeof(a)/sizeof(a[0]))
1302 static const u_int8_t ciphermap[] = {
1303 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */
1304 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */
1305 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */
1306 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */
1307 (u_int8_t) -1, /* 4 is not allocated */
1308 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */
1309 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */
1311 struct ath_hal *ah = sc->sc_ah;
1312 const struct ieee80211_cipher *cip = k->wk_cipher;
1313 u_int8_t gmac[IEEE80211_ADDR_LEN];
1314 const u_int8_t *mac;
1317 memset(&hk, 0, sizeof(hk));
1319 * Software crypto uses a "clear key" so non-crypto
1320 * state kept in the key cache are maintained and
1321 * so that rx frames have an entry to match.
1323 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) {
1324 KASSERT(cip->ic_cipher < N(ciphermap),
1325 ("invalid cipher type %u", cip->ic_cipher));
1326 hk.kv_type = ciphermap[cip->ic_cipher];
1327 hk.kv_len = k->wk_keylen;
1328 memcpy(hk.kv_val, k->wk_key, k->wk_keylen);
1330 hk.kv_type = HAL_CIPHER_CLR;
1332 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) {
1334 * Group keys on hardware that supports multicast frame
1335 * key search use a mac that is the sender's address with
1336 * the high bit set instead of the app-specified address.
1338 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr);
1344 if (hk.kv_type == HAL_CIPHER_TKIP &&
1345 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 &&
1347 return ath_keyset_tkip(sc, k, &hk, mac);
1349 KEYPRINTF(sc, k->wk_keyix, &hk, mac);
1350 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac);
1356 * Allocate tx/rx key slots for TKIP. We allocate two slots for
1357 * each key, one for decrypt/encrypt and the other for the MIC.
1360 key_alloc_2pair(struct ath_softc *sc)
1362 #define N(a) (sizeof(a)/sizeof(a[0]))
1365 KASSERT(sc->sc_splitmic, ("key cache !split"));
1366 /* XXX could optimize */
1367 for (i = 0; i < N(sc->sc_keymap)/4; i++) {
1368 u_int8_t b = sc->sc_keymap[i];
1371 * One or more slots in this byte are free.
1379 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */
1380 if (isset(sc->sc_keymap, keyix+32) ||
1381 isset(sc->sc_keymap, keyix+64) ||
1382 isset(sc->sc_keymap, keyix+32+64)) {
1383 /* full pair unavailable */
1385 if (keyix == (i+1)*NBBY) {
1386 /* no slots were appropriate, advance */
1391 setbit(sc->sc_keymap, keyix);
1392 setbit(sc->sc_keymap, keyix+64);
1393 setbit(sc->sc_keymap, keyix+32);
1394 setbit(sc->sc_keymap, keyix+32+64);
1395 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1396 "%s: key pair %u,%u %u,%u\n",
1397 __func__, keyix, keyix+64,
1398 keyix+32, keyix+32+64);
1402 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__);
1403 return IEEE80211_KEYIX_NONE;
1408 * Allocate a single key cache slot.
1411 key_alloc_single(struct ath_softc *sc)
1413 #define N(a) (sizeof(a)/sizeof(a[0]))
1416 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */
1417 for (i = 0; i < N(sc->sc_keymap); i++) {
1418 u_int8_t b = sc->sc_keymap[i];
1421 * One or more slots are free.
1426 setbit(sc->sc_keymap, keyix);
1427 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n",
1432 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__);
1433 return IEEE80211_KEYIX_NONE;
1438 * Allocate one or more key cache slots for a uniacst key. The
1439 * key itself is needed only to identify the cipher. For hardware
1440 * TKIP with split cipher+MIC keys we allocate two key cache slot
1441 * pairs so that we can setup separate TX and RX MIC keys. Note
1442 * that the MIC key for a TKIP key at slot i is assumed by the
1443 * hardware to be at slot i+64. This limits TKIP keys to the first
1447 ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k)
1449 struct ath_softc *sc = ic->ic_ifp->if_softc;
1452 * Group key allocation must be handled specially for
1453 * parts that do not support multicast key cache search
1454 * functionality. For those parts the key id must match
1455 * the h/w key index so lookups find the right key. On
1456 * parts w/ the key search facility we install the sender's
1457 * mac address (with the high bit set) and let the hardware
1458 * find the key w/o using the key id. This is preferred as
1459 * it permits us to support multiple users for adhoc and/or
1460 * multi-station operation.
1462 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) {
1465 if (!(&ic->ic_nw_keys[0] <= k &&
1466 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) {
1467 /* should not happen */
1468 DPRINTF(sc, ATH_DEBUG_KEYCACHE,
1469 "%s: bogus group key\n", __func__);
1470 return IEEE80211_KEYIX_NONE;
1472 keyix = k - ic->ic_nw_keys;
1474 * XXX we pre-allocate the global keys so
1475 * have no way to check if they've already been allocated.
1481 * We allocate two pair for TKIP when using the h/w to do
1482 * the MIC. For everything else, including software crypto,
1483 * we allocate a single entry. Note that s/w crypto requires
1484 * a pass-through slot on the 5211 and 5212. The 5210 does
1485 * not support pass-through cache entries and we map all
1486 * those requests to slot 0.
1488 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) {
1489 return key_alloc_single(sc);
1490 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP &&
1491 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) {
1492 return key_alloc_2pair(sc);
1494 return key_alloc_single(sc);
1499 * Delete an entry in the key cache allocated by ath_key_alloc.
1502 ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k)
1504 struct ath_softc *sc = ic->ic_ifp->if_softc;
1505 struct ath_hal *ah = sc->sc_ah;
1506 const struct ieee80211_cipher *cip = k->wk_cipher;
1507 struct ieee80211_node *ni;
1508 u_int keyix = k->wk_keyix;
1510 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix);
1512 ath_hal_keyreset(ah, keyix);
1514 * Check the key->node map and flush any ref.
1516 ni = sc->sc_keyixmap[keyix];
1518 ieee80211_free_node(ni);
1519 sc->sc_keyixmap[keyix] = NULL;
1522 * Handle split tx/rx keying required for TKIP with h/w MIC.
1524 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1525 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) {
1526 ath_hal_keyreset(ah, keyix+32); /* RX key */
1527 ni = sc->sc_keyixmap[keyix+32];
1528 if (ni != NULL) { /* as above... */
1529 ieee80211_free_node(ni);
1530 sc->sc_keyixmap[keyix+32] = NULL;
1533 if (keyix >= IEEE80211_WEP_NKID) {
1535 * Don't touch keymap entries for global keys so
1536 * they are never considered for dynamic allocation.
1538 clrbit(sc->sc_keymap, keyix);
1539 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP &&
1540 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 &&
1542 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */
1543 clrbit(sc->sc_keymap, keyix+32); /* RX key */
1544 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */
1551 * Set the key cache contents for the specified key. Key cache
1552 * slot(s) must already have been allocated by ath_key_alloc.
1555 ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k,
1556 const u_int8_t mac[IEEE80211_ADDR_LEN])
1558 struct ath_softc *sc = ic->ic_ifp->if_softc;
1560 return ath_keyset(sc, k, mac, ic->ic_bss);
1564 * Block/unblock tx+rx processing while a key change is done.
1565 * We assume the caller serializes key management operations
1566 * so we only need to worry about synchronization with other
1567 * uses that originate in the driver.
1570 ath_key_update_begin(struct ieee80211com *ic)
1572 struct ifnet *ifp = ic->ic_ifp;
1573 struct ath_softc *sc = ifp->if_softc;
1575 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1577 tasklet_disable(&sc->sc_rxtq);
1579 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */
1583 ath_key_update_end(struct ieee80211com *ic)
1585 struct ifnet *ifp = ic->ic_ifp;
1586 struct ath_softc *sc = ifp->if_softc;
1588 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__);
1589 IF_UNLOCK(&ifp->if_snd);
1591 tasklet_enable(&sc->sc_rxtq);
1596 * Calculate the receive filter according to the
1597 * operating mode and state:
1599 * o always accept unicast, broadcast, and multicast traffic
1600 * o maintain current state of phy error reception (the hal
1601 * may enable phy error frames for noise immunity work)
1602 * o probe request frames are accepted only when operating in
1603 * hostap, adhoc, or monitor modes
1604 * o enable promiscuous mode according to the interface state
1606 * - when operating in adhoc mode so the 802.11 layer creates
1607 * node table entries for peers,
1608 * - when operating in station mode for collecting rssi data when
1609 * the station is otherwise quiet, or
1613 ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state)
1615 struct ieee80211com *ic = &sc->sc_ic;
1616 struct ath_hal *ah = sc->sc_ah;
1617 struct ifnet *ifp = sc->sc_ifp;
1620 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR)
1621 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
1622 if (ic->ic_opmode != IEEE80211_M_STA)
1623 rfilt |= HAL_RX_FILTER_PROBEREQ;
1624 if (ic->ic_opmode != IEEE80211_M_HOSTAP &&
1625 (ifp->if_flags & IFF_PROMISC))
1626 rfilt |= HAL_RX_FILTER_PROM;
1627 if (ic->ic_opmode == IEEE80211_M_STA ||
1628 ic->ic_opmode == IEEE80211_M_IBSS ||
1629 state == IEEE80211_S_SCAN)
1630 rfilt |= HAL_RX_FILTER_BEACON;
1635 ath_mode_init(struct ath_softc *sc)
1637 struct ieee80211com *ic = &sc->sc_ic;
1638 struct ath_hal *ah = sc->sc_ah;
1639 struct ifnet *ifp = sc->sc_ifp;
1640 u_int32_t rfilt, mfilt[2], val;
1642 struct ifmultiaddr *ifma;
1644 /* configure rx filter */
1645 rfilt = ath_calcrxfilter(sc, ic->ic_state);
1646 ath_hal_setrxfilter(ah, rfilt);
1648 /* configure operational mode */
1649 ath_hal_setopmode(ah);
1652 * Handle any link-level address change. Note that we only
1653 * need to force ic_myaddr; any other addresses are handled
1654 * as a byproduct of the ifnet code marking the interface
1657 * XXX should get from lladdr instead of arpcom but that's more work
1659 IEEE80211_ADDR_COPY(ic->ic_myaddr, IFP2ENADDR(ifp));
1660 ath_hal_setmac(ah, ic->ic_myaddr);
1662 /* calculate and install multicast filter */
1663 if ((ifp->if_flags & IFF_ALLMULTI) == 0) {
1664 mfilt[0] = mfilt[1] = 0;
1665 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1668 /* calculate XOR of eight 6bit values */
1669 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
1670 val = LE_READ_4(dl + 0);
1671 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1672 val = LE_READ_4(dl + 3);
1673 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
1675 mfilt[pos / 32] |= (1 << (pos % 32));
1678 mfilt[0] = mfilt[1] = ~0;
1680 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]);
1681 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n",
1682 __func__, rfilt, mfilt[0], mfilt[1]);
1686 * Set the slot time based on the current setting.
1689 ath_setslottime(struct ath_softc *sc)
1691 struct ieee80211com *ic = &sc->sc_ic;
1692 struct ath_hal *ah = sc->sc_ah;
1694 if (ic->ic_flags & IEEE80211_F_SHSLOT)
1695 ath_hal_setslottime(ah, HAL_SLOT_TIME_9);
1697 ath_hal_setslottime(ah, HAL_SLOT_TIME_20);
1698 sc->sc_updateslot = OK;
1702 * Callback from the 802.11 layer to update the
1703 * slot time based on the current setting.
1706 ath_updateslot(struct ifnet *ifp)
1708 struct ath_softc *sc = ifp->if_softc;
1709 struct ieee80211com *ic = &sc->sc_ic;
1712 * When not coordinating the BSS, change the hardware
1713 * immediately. For other operation we defer the change
1714 * until beacon updates have propagated to the stations.
1716 if (ic->ic_opmode == IEEE80211_M_HOSTAP)
1717 sc->sc_updateslot = UPDATE;
1719 ath_setslottime(sc);
1723 * Setup a h/w transmit queue for beacons.
1726 ath_beaconq_setup(struct ath_hal *ah)
1730 memset(&qi, 0, sizeof(qi));
1731 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
1732 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
1733 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
1734 /* NB: for dynamic turbo, don't enable any other interrupts */
1735 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1736 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
1740 * Setup the transmit queue parameters for the beacon queue.
1743 ath_beaconq_config(struct ath_softc *sc)
1745 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
1746 struct ieee80211com *ic = &sc->sc_ic;
1747 struct ath_hal *ah = sc->sc_ah;
1750 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
1751 if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
1753 * Always burst out beacon and CAB traffic.
1755 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
1756 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
1757 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
1759 struct wmeParams *wmep =
1760 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE];
1762 * Adhoc mode; important thing is to use 2x cwmin.
1764 qi.tqi_aifs = wmep->wmep_aifsn;
1765 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
1766 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
1769 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
1770 device_printf(sc->sc_dev, "unable to update parameters for "
1771 "beacon hardware queue!\n");
1774 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
1777 #undef ATH_EXPONENT_TO_VALUE
1781 * Allocate and setup an initial beacon frame.
1784 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
1786 struct ieee80211com *ic = ni->ni_ic;
1791 bf = STAILQ_FIRST(&sc->sc_bbuf);
1793 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__);
1794 sc->sc_stats.ast_be_nombuf++; /* XXX */
1795 return ENOMEM; /* XXX */
1798 * NB: the beacon data buffer must be 32-bit aligned;
1799 * we assume the mbuf routines will return us something
1800 * with this alignment (perhaps should assert).
1802 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff);
1804 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n",
1806 sc->sc_stats.ast_be_nombuf++;
1809 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
1810 bf->bf_segs, &bf->bf_nseg,
1814 bf->bf_node = ieee80211_ref_node(ni);
1822 * Setup the beacon frame for transmit.
1825 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
1827 #define USE_SHPREAMBLE(_ic) \
1828 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
1829 == IEEE80211_F_SHPREAMBLE)
1830 struct ieee80211_node *ni = bf->bf_node;
1831 struct ieee80211com *ic = ni->ni_ic;
1832 struct mbuf *m = bf->bf_m;
1833 struct ath_hal *ah = sc->sc_ah;
1834 struct ath_node *an = ATH_NODE(ni);
1835 struct ath_desc *ds;
1839 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n",
1840 __func__, m, m->m_len);
1842 /* setup descriptors */
1845 flags = HAL_TXDESC_NOACK;
1846 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
1847 ds->ds_link = bf->bf_daddr; /* self-linked */
1848 flags |= HAL_TXDESC_VEOL;
1850 * Let hardware handle antenna switching.
1856 * Switch antenna every 4 beacons.
1857 * XXX assumes two antenna
1859 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
1862 KASSERT(bf->bf_nseg == 1,
1863 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
1864 ds->ds_data = bf->bf_segs[0].ds_addr;
1866 * Calculate rate code.
1867 * XXX everything at min xmit rate
1869 if (USE_SHPREAMBLE(ic))
1870 rate = an->an_tx_mgtratesp;
1872 rate = an->an_tx_mgtrate;
1873 ath_hal_setuptxdesc(ah, ds
1874 , m->m_len + IEEE80211_CRC_LEN /* frame length */
1875 , sizeof(struct ieee80211_frame)/* header length */
1876 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
1877 , ni->ni_txpower /* txpower XXX */
1878 , rate, 1 /* series 0 rate/tries */
1879 , HAL_TXKEYIX_INVALID /* no encryption */
1880 , antenna /* antenna mode */
1881 , flags /* no ack, veol for beacons */
1882 , 0 /* rts/cts rate */
1883 , 0 /* rts/cts duration */
1885 /* NB: beacon's BufLen must be a multiple of 4 bytes */
1886 ath_hal_filltxdesc(ah, ds
1887 , roundup(m->m_len, 4) /* buffer length */
1888 , AH_TRUE /* first segment */
1889 , AH_TRUE /* last segment */
1890 , ds /* first descriptor */
1892 #undef USE_SHPREAMBLE
1896 * Transmit a beacon frame at SWBA. Dynamic updates to the
1897 * frame contents are done as needed and the slot time is
1898 * also adjusted based on current state.
1901 ath_beacon_proc(void *arg, int pending)
1903 struct ath_softc *sc = arg;
1904 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf);
1905 struct ieee80211_node *ni = bf->bf_node;
1906 struct ieee80211com *ic = ni->ni_ic;
1907 struct ath_hal *ah = sc->sc_ah;
1909 int ncabq, error, otherant;
1911 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n",
1914 if (ic->ic_opmode == IEEE80211_M_STA ||
1915 ic->ic_opmode == IEEE80211_M_MONITOR ||
1916 bf == NULL || bf->bf_m == NULL) {
1917 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n",
1918 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL);
1922 * Check if the previous beacon has gone out. If
1923 * not don't don't try to post another, skip this
1924 * period and wait for the next. Missed beacons
1925 * indicate a problem and should not occur. If we
1926 * miss too many consecutive beacons reset the device.
1928 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
1929 sc->sc_bmisscount++;
1930 DPRINTF(sc, ATH_DEBUG_BEACON_PROC,
1931 "%s: missed %u consecutive beacons\n",
1932 __func__, sc->sc_bmisscount);
1933 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */
1934 taskqueue_enqueue(taskqueue_swi, &sc->sc_bstucktask);
1937 if (sc->sc_bmisscount != 0) {
1938 DPRINTF(sc, ATH_DEBUG_BEACON,
1939 "%s: resume beacon xmit after %u misses\n",
1940 __func__, sc->sc_bmisscount);
1941 sc->sc_bmisscount = 0;
1945 * Update dynamic beacon contents. If this returns
1946 * non-zero then we need to remap the memory because
1947 * the beacon frame changed size (probably because
1948 * of the TIM bitmap).
1951 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum);
1952 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) {
1953 /* XXX too conservative? */
1954 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
1955 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
1956 bf->bf_segs, &bf->bf_nseg,
1959 if_printf(ic->ic_ifp,
1960 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
1967 * Handle slot time change when a non-ERP station joins/leaves
1968 * an 11g network. The 802.11 layer notifies us via callback,
1969 * we mark updateslot, then wait one beacon before effecting
1970 * the change. This gives associated stations at least one
1971 * beacon interval to note the state change.
1974 if (sc->sc_updateslot == UPDATE)
1975 sc->sc_updateslot = COMMIT; /* commit next beacon */
1976 else if (sc->sc_updateslot == COMMIT)
1977 ath_setslottime(sc); /* commit change to h/w */
1980 * Check recent per-antenna transmit statistics and flip
1981 * the default antenna if noticeably more frames went out
1982 * on the non-default antenna.
1983 * XXX assumes 2 anntenae
1985 otherant = sc->sc_defant & 1 ? 2 : 1;
1986 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
1987 ath_setdefantenna(sc, otherant);
1988 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
1991 * Construct tx descriptor.
1993 ath_beacon_setup(sc, bf);
1996 * Stop any current dma and put the new frame on the queue.
1997 * This should never fail since we check above that no frames
1998 * are still pending on the queue.
2000 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
2001 DPRINTF(sc, ATH_DEBUG_ANY,
2002 "%s: beacon queue %u did not stop?\n",
2003 __func__, sc->sc_bhalq);
2005 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
2008 * Enable the CAB queue before the beacon queue to
2009 * insure cab frames are triggered by this beacon.
2011 if (sc->sc_boff.bo_tim[4] & 1) /* NB: only at DTIM */
2012 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum);
2013 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
2014 ath_hal_txstart(ah, sc->sc_bhalq);
2015 DPRINTF(sc, ATH_DEBUG_BEACON_PROC,
2016 "%s: TXDP[%u] = %p (%p)\n", __func__,
2017 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc);
2019 sc->sc_stats.ast_be_xmit++;
2023 * Reset the hardware after detecting beacons have stopped.
2026 ath_bstuck_proc(void *arg, int pending)
2028 struct ath_softc *sc = arg;
2029 struct ifnet *ifp = sc->sc_ifp;
2031 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n",
2037 * Reclaim beacon resources.
2040 ath_beacon_free(struct ath_softc *sc)
2044 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
2045 if (bf->bf_m != NULL) {
2046 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2050 if (bf->bf_node != NULL) {
2051 ieee80211_free_node(bf->bf_node);
2058 * Configure the beacon and sleep timers.
2060 * When operating as an AP this resets the TSF and sets
2061 * up the hardware to notify us when we need to issue beacons.
2063 * When operating in station mode this sets up the beacon
2064 * timers according to the timestamp of the last received
2065 * beacon and the current TSF, configures PCF and DTIM
2066 * handling, programs the sleep registers so the hardware
2067 * will wakeup in time to receive beacons, and configures
2068 * the beacon miss handling so we'll receive a BMISS
2069 * interrupt when we stop seeing beacons from the AP
2070 * we've associated with.
2073 ath_beacon_config(struct ath_softc *sc)
2075 #define TSF_TO_TU(_h,_l) (((_h) << 22) | ((_l) >> 10))
2076 struct ath_hal *ah = sc->sc_ah;
2077 struct ieee80211com *ic = &sc->sc_ic;
2078 struct ieee80211_node *ni = ic->ic_bss;
2079 u_int32_t nexttbtt, intval;
2081 /* extract tstamp from last beacon and convert to TU */
2082 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4),
2083 LE_READ_4(ni->ni_tstamp.data));
2084 /* NB: the beacon interval is kept internally in TU's */
2085 intval = ni->ni_intval & HAL_BEACON_PERIOD;
2086 if (nexttbtt == 0) /* e.g. for ap mode */
2088 else if (intval) /* NB: can be 0 for monitor mode */
2089 nexttbtt = roundup(nexttbtt, intval);
2090 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
2091 __func__, nexttbtt, intval, ni->ni_intval);
2092 if (ic->ic_opmode == IEEE80211_M_STA) {
2093 HAL_BEACON_STATE bs;
2096 int dtimperiod, dtimcount;
2097 int cfpperiod, cfpcount;
2100 * Setup dtim and cfp parameters according to
2101 * last beacon we received (which may be none).
2103 dtimperiod = ni->ni_dtim_period;
2104 if (dtimperiod <= 0) /* NB: 0 if not known */
2106 dtimcount = ni->ni_dtim_count;
2107 if (dtimcount >= dtimperiod) /* NB: sanity check */
2108 dtimcount = 0; /* XXX? */
2109 cfpperiod = 1; /* NB: no PCF support yet */
2113 * Pull nexttbtt forward to reflect the current
2114 * TSF and calculate dtim+cfp state for the result.
2116 tsf = ath_hal_gettsf64(ah);
2117 tsftu = TSF_TO_TU((u_int32_t)(tsf>>32), (u_int32_t)tsf) + FUDGE;
2120 if (--dtimcount < 0) {
2121 dtimcount = dtimperiod - 1;
2123 cfpcount = cfpperiod - 1;
2125 } while (nexttbtt < tsftu);
2127 memset(&bs, 0, sizeof(bs));
2128 bs.bs_intval = intval;
2129 bs.bs_nexttbtt = nexttbtt;
2130 bs.bs_dtimperiod = dtimperiod*intval;
2131 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
2132 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
2133 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
2134 bs.bs_cfpmaxduration = 0;
2137 * The 802.11 layer records the offset to the DTIM
2138 * bitmap while receiving beacons; use it here to
2139 * enable h/w detection of our AID being marked in
2140 * the bitmap vector (to indicate frames for us are
2141 * pending at the AP).
2142 * XXX do DTIM handling in s/w to WAR old h/w bugs
2143 * XXX enable based on h/w rev for newer chips
2145 bs.bs_timoffset = ni->ni_timoff;
2148 * Calculate the number of consecutive beacons to miss
2149 * before taking a BMISS interrupt. The configuration
2150 * is specified in ms, so we need to convert that to
2151 * TU's and then calculate based on the beacon interval.
2152 * Note that we clamp the result to at most 10 beacons.
2154 bs.bs_bmissthreshold = howmany(ic->ic_bmisstimeout, intval);
2155 if (bs.bs_bmissthreshold > 10)
2156 bs.bs_bmissthreshold = 10;
2157 else if (bs.bs_bmissthreshold <= 0)
2158 bs.bs_bmissthreshold = 1;
2161 * Calculate sleep duration. The configuration is
2162 * given in ms. We insure a multiple of the beacon
2163 * period is used. Also, if the sleep duration is
2164 * greater than the DTIM period then it makes senses
2165 * to make it a multiple of that.
2167 * XXX fixed at 100ms
2169 bs.bs_sleepduration =
2170 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
2171 if (bs.bs_sleepduration > bs.bs_dtimperiod)
2172 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
2174 DPRINTF(sc, ATH_DEBUG_BEACON,
2175 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n"
2182 , bs.bs_bmissthreshold
2183 , bs.bs_sleepduration
2185 , bs.bs_cfpmaxduration
2189 ath_hal_intrset(ah, 0);
2190 ath_hal_beacontimers(ah, &bs);
2191 sc->sc_imask |= HAL_INT_BMISS;
2192 ath_hal_intrset(ah, sc->sc_imask);
2194 ath_hal_intrset(ah, 0);
2195 if (nexttbtt == intval)
2196 intval |= HAL_BEACON_RESET_TSF;
2197 if (ic->ic_opmode == IEEE80211_M_IBSS) {
2199 * In IBSS mode enable the beacon timers but only
2200 * enable SWBA interrupts if we need to manually
2201 * prepare beacon frames. Otherwise we use a
2202 * self-linked tx descriptor and let the hardware
2205 intval |= HAL_BEACON_ENA;
2206 if (!sc->sc_hasveol)
2207 sc->sc_imask |= HAL_INT_SWBA;
2208 ath_beaconq_config(sc);
2209 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) {
2211 * In AP mode we enable the beacon timers and
2212 * SWBA interrupts to prepare beacon frames.
2214 intval |= HAL_BEACON_ENA;
2215 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
2216 ath_beaconq_config(sc);
2218 ath_hal_beaconinit(ah, nexttbtt, intval);
2219 sc->sc_bmisscount = 0;
2220 ath_hal_intrset(ah, sc->sc_imask);
2222 * When using a self-linked beacon descriptor in
2223 * ibss mode load it once here.
2225 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
2226 ath_beacon_proc(sc, 0);
2232 ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
2234 bus_addr_t *paddr = (bus_addr_t*) arg;
2235 KASSERT(error == 0, ("error %u on bus_dma callback", error));
2236 *paddr = segs->ds_addr;
2240 ath_descdma_setup(struct ath_softc *sc,
2241 struct ath_descdma *dd, ath_bufhead *head,
2242 const char *name, int nbuf, int ndesc)
2244 #define DS2PHYS(_dd, _ds) \
2245 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2246 struct ifnet *ifp = sc->sc_ifp;
2247 struct ath_desc *ds;
2249 int i, bsize, error;
2251 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n",
2252 __func__, name, nbuf, ndesc);
2255 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2258 * Setup DMA descriptor area.
2260 error = bus_dma_tag_create(NULL, /* parent */
2261 PAGE_SIZE, 0, /* alignment, bounds */
2262 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
2263 BUS_SPACE_MAXADDR, /* highaddr */
2264 NULL, NULL, /* filter, filterarg */
2265 dd->dd_desc_len, /* maxsize */
2267 BUS_SPACE_MAXADDR, /* maxsegsize */
2268 BUS_DMA_ALLOCNOW, /* flags */
2269 NULL, /* lockfunc */
2273 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name);
2277 /* allocate descriptors */
2278 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap);
2280 if_printf(ifp, "unable to create dmamap for %s descriptors, "
2281 "error %u\n", dd->dd_name, error);
2285 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc,
2286 BUS_DMA_NOWAIT, &dd->dd_dmamap);
2288 if_printf(ifp, "unable to alloc memory for %u %s descriptors, "
2289 "error %u\n", nbuf * ndesc, dd->dd_name, error);
2293 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap,
2294 dd->dd_desc, dd->dd_desc_len,
2295 ath_load_cb, &dd->dd_desc_paddr,
2298 if_printf(ifp, "unable to map %s descriptors, error %u\n",
2299 dd->dd_name, error);
2304 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n",
2305 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len,
2306 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len);
2308 /* allocate rx buffers */
2309 bsize = sizeof(struct ath_buf) * nbuf;
2310 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO);
2312 if_printf(ifp, "malloc of %s buffers failed, size %u\n",
2313 dd->dd_name, bsize);
2319 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2321 bf->bf_daddr = DS2PHYS(dd, ds);
2322 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT,
2325 if_printf(ifp, "unable to create dmamap for %s "
2326 "buffer %u, error %u\n", dd->dd_name, i, error);
2327 ath_descdma_cleanup(sc, dd, head);
2330 STAILQ_INSERT_TAIL(head, bf, bf_list);
2334 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2336 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2338 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2340 bus_dma_tag_destroy(dd->dd_dmat);
2341 memset(dd, 0, sizeof(*dd));
2347 ath_descdma_cleanup(struct ath_softc *sc,
2348 struct ath_descdma *dd, ath_bufhead *head)
2351 struct ieee80211_node *ni;
2353 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap);
2354 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap);
2355 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap);
2356 bus_dma_tag_destroy(dd->dd_dmat);
2358 STAILQ_FOREACH(bf, head, bf_list) {
2363 if (bf->bf_dmamap != NULL) {
2364 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap);
2365 bf->bf_dmamap = NULL;
2371 * Reclaim node reference.
2373 ieee80211_free_node(ni);
2378 free(dd->dd_bufptr, M_ATHDEV);
2379 memset(dd, 0, sizeof(*dd));
2383 ath_desc_alloc(struct ath_softc *sc)
2387 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
2388 "rx", ATH_RXBUF, 1);
2392 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
2393 "tx", ATH_TXBUF, ATH_TXDESC);
2395 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2399 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
2402 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2403 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2410 ath_desc_free(struct ath_softc *sc)
2413 if (sc->sc_bdma.dd_desc_len != 0)
2414 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
2415 if (sc->sc_txdma.dd_desc_len != 0)
2416 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
2417 if (sc->sc_rxdma.dd_desc_len != 0)
2418 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
2421 static struct ieee80211_node *
2422 ath_node_alloc(struct ieee80211_node_table *nt)
2424 struct ieee80211com *ic = nt->nt_ic;
2425 struct ath_softc *sc = ic->ic_ifp->if_softc;
2426 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space;
2427 struct ath_node *an;
2429 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO);
2434 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER;
2435 an->an_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
2436 an->an_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
2437 an->an_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
2438 ath_rate_node_init(sc, an);
2440 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an);
2441 return &an->an_node;
2445 ath_node_free(struct ieee80211_node *ni)
2447 struct ieee80211com *ic = ni->ni_ic;
2448 struct ath_softc *sc = ic->ic_ifp->if_softc;
2450 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni);
2452 ath_rate_node_cleanup(sc, ATH_NODE(ni));
2453 sc->sc_node_free(ni);
2457 ath_node_getrssi(const struct ieee80211_node *ni)
2459 #define HAL_EP_RND(x, mul) \
2460 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
2461 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi;
2465 * When only one frame is received there will be no state in
2466 * avgrssi so fallback on the value recorded by the 802.11 layer.
2468 if (avgrssi != ATH_RSSI_DUMMY_MARKER)
2469 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER);
2472 /* NB: theoretically we shouldn't need this, but be paranoid */
2473 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi;
2478 ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
2480 struct ath_hal *ah = sc->sc_ah;
2483 struct ath_desc *ds;
2488 * NB: by assigning a page to the rx dma buffer we
2489 * implicitly satisfy the Atheros requirement that
2490 * this buffer be cache-line-aligned and sized to be
2491 * multiple of the cache line size. Not doing this
2492 * causes weird stuff to happen (for the 5210 at least).
2494 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
2496 DPRINTF(sc, ATH_DEBUG_ANY,
2497 "%s: no mbuf/cluster\n", __func__);
2498 sc->sc_stats.ast_rx_nombuf++;
2502 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
2504 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
2506 bf->bf_segs, &bf->bf_nseg,
2509 DPRINTF(sc, ATH_DEBUG_ANY,
2510 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
2512 sc->sc_stats.ast_rx_busdma++;
2515 KASSERT(bf->bf_nseg == 1,
2516 ("multi-segment packet; nseg %u", bf->bf_nseg));
2518 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
2521 * Setup descriptors. For receive we always terminate
2522 * the descriptor list with a self-linked entry so we'll
2523 * not get overrun under high load (as can happen with a
2524 * 5212 when ANI processing enables PHY error frames).
2526 * To insure the last descriptor is self-linked we create
2527 * each descriptor as self-linked and add it to the end. As
2528 * each additional descriptor is added the previous self-linked
2529 * entry is ``fixed'' naturally. This should be safe even
2530 * if DMA is happening. When processing RX interrupts we
2531 * never remove/process the last, self-linked, entry on the
2532 * descriptor list. This insures the hardware always has
2533 * someplace to write a new frame.
2536 ds->ds_link = bf->bf_daddr; /* link to self */
2537 ds->ds_data = bf->bf_segs[0].ds_addr;
2538 ath_hal_setuprxdesc(ah, ds
2539 , m->m_len /* buffer size */
2543 if (sc->sc_rxlink != NULL)
2544 *sc->sc_rxlink = bf->bf_daddr;
2545 sc->sc_rxlink = &ds->ds_link;
2550 * Extend 15-bit time stamp from rx descriptor to
2551 * a full 64-bit TSF using the current h/w TSF.
2553 static __inline u_int64_t
2554 ath_extend_tsf(struct ath_hal *ah, u_int32_t rstamp)
2558 tsf = ath_hal_gettsf64(ah);
2559 if ((tsf & 0x7fff) < rstamp)
2561 return ((tsf &~ 0x7fff) | rstamp);
2565 * Intercept management frames to collect beacon rssi data
2566 * and to do ibss merges.
2569 ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m,
2570 struct ieee80211_node *ni,
2571 int subtype, int rssi, u_int32_t rstamp)
2573 struct ath_softc *sc = ic->ic_ifp->if_softc;
2576 * Call up first so subsequent work can use information
2577 * potentially stored in the node (e.g. for ibss merge).
2579 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp);
2581 case IEEE80211_FC0_SUBTYPE_BEACON:
2582 /* update rssi statistics for use by the hal */
2583 ATH_RSSI_LPF(ATH_NODE(ni)->an_halstats.ns_avgbrssi, rssi);
2585 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
2586 if (ic->ic_opmode == IEEE80211_M_IBSS &&
2587 ic->ic_state == IEEE80211_S_RUN) {
2588 u_int64_t tsf = ath_extend_tsf(sc->sc_ah, rstamp);
2590 * Handle ibss merge as needed; check the tsf on the
2591 * frame before attempting the merge. The 802.11 spec
2592 * says the station should change it's bssid to match
2593 * the oldest station with the same ssid, where oldest
2594 * is determined by the tsf. Note that hardware
2595 * reconfiguration happens through callback to
2596 * ath_newstate as the state machine will go from
2597 * RUN -> RUN when this happens.
2599 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
2600 DPRINTF(sc, ATH_DEBUG_STATE,
2601 "ibss merge, rstamp %u tsf %ju "
2602 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
2603 (uintmax_t)ni->ni_tstamp.tsf);
2604 (void) ieee80211_ibss_merge(ic, ni);
2612 * Set the default antenna.
2615 ath_setdefantenna(struct ath_softc *sc, u_int antenna)
2617 struct ath_hal *ah = sc->sc_ah;
2619 /* XXX block beacon interrupts */
2620 ath_hal_setdefantenna(ah, antenna);
2621 if (sc->sc_defant != antenna)
2622 sc->sc_stats.ast_ant_defswitch++;
2623 sc->sc_defant = antenna;
2624 sc->sc_rxotherant = 0;
2628 ath_rx_proc(void *arg, int npending)
2630 #define PA2DESC(_sc, _pa) \
2631 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
2632 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
2633 struct ath_softc *sc = arg;
2635 struct ieee80211com *ic = &sc->sc_ic;
2636 struct ifnet *ifp = sc->sc_ifp;
2637 struct ath_hal *ah = sc->sc_ah;
2638 struct ath_desc *ds;
2640 struct ieee80211_node *ni;
2641 struct ath_node *an;
2646 NET_LOCK_GIANT(); /* XXX */
2648 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
2650 bf = STAILQ_FIRST(&sc->sc_rxbuf);
2651 if (bf == NULL) { /* NB: shouldn't happen */
2652 if_printf(ifp, "%s: no buffer!\n", __func__);
2656 if (ds->ds_link == bf->bf_daddr) {
2657 /* NB: never process the self-linked entry at the end */
2661 if (m == NULL) { /* NB: shouldn't happen */
2662 if_printf(ifp, "%s: no mbuf!\n", __func__);
2665 /* XXX sync descriptor memory */
2667 * Must provide the virtual address of the current
2668 * descriptor, the physical address, and the virtual
2669 * address of the next descriptor in the h/w chain.
2670 * This allows the HAL to look ahead to see if the
2671 * hardware is done with a descriptor by checking the
2672 * done bit in the following descriptor and the address
2673 * of the current descriptor the DMA engine is working
2674 * on. All this is necessary because of our use of
2675 * a self-linked list to avoid rx overruns.
2677 status = ath_hal_rxprocdesc(ah, ds,
2678 bf->bf_daddr, PA2DESC(sc, ds->ds_link));
2680 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
2681 ath_printrxbuf(bf, status == HAL_OK);
2683 if (status == HAL_EINPROGRESS)
2685 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list);
2686 if (ds->ds_rxstat.rs_more) {
2688 * Frame spans multiple descriptors; this
2689 * cannot happen yet as we don't support
2690 * jumbograms. If not in monitor mode,
2691 * discard the frame.
2693 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
2694 sc->sc_stats.ast_rx_toobig++;
2697 /* fall thru for monitor mode handling... */
2698 } else if (ds->ds_rxstat.rs_status != 0) {
2699 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC)
2700 sc->sc_stats.ast_rx_crcerr++;
2701 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO)
2702 sc->sc_stats.ast_rx_fifoerr++;
2703 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) {
2704 sc->sc_stats.ast_rx_phyerr++;
2705 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f;
2706 sc->sc_stats.ast_rx_phy[phyerr]++;
2709 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) {
2711 * Decrypt error. If the error occurred
2712 * because there was no hardware key, then
2713 * let the frame through so the upper layers
2714 * can process it. This is necessary for 5210
2715 * parts which have no way to setup a ``clear''
2718 * XXX do key cache faulting
2720 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID)
2722 sc->sc_stats.ast_rx_badcrypt++;
2724 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) {
2725 sc->sc_stats.ast_rx_badmic++;
2727 * Do minimal work required to hand off
2728 * the 802.11 header for notifcation.
2730 /* XXX frag's and qos frames */
2731 len = ds->ds_rxstat.rs_datalen;
2732 if (len >= sizeof (struct ieee80211_frame)) {
2733 bus_dmamap_sync(sc->sc_dmat,
2735 BUS_DMASYNC_POSTREAD);
2736 ieee80211_notify_michael_failure(ic,
2737 mtod(m, struct ieee80211_frame *),
2739 ds->ds_rxstat.rs_keyix-32 :
2740 ds->ds_rxstat.rs_keyix
2746 * Reject error frames, we normally don't want
2747 * to see them in monitor mode (in monitor mode
2748 * allow through packets that have crypto problems).
2750 if ((ds->ds_rxstat.rs_status &~
2751 (HAL_RXERR_DECRYPT|HAL_RXERR_MIC)) ||
2752 sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR)
2757 * Sync and unmap the frame. At this point we're
2758 * committed to passing the mbuf somewhere so clear
2759 * bf_m; this means a new sk_buff must be allocated
2760 * when the rx descriptor is setup again to receive
2763 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
2764 BUS_DMASYNC_POSTREAD);
2765 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
2768 m->m_pkthdr.rcvif = ifp;
2769 len = ds->ds_rxstat.rs_datalen;
2770 m->m_pkthdr.len = m->m_len = len;
2772 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++;
2774 if (sc->sc_drvbpf) {
2778 * Discard anything shorter than an ack or cts.
2780 if (len < IEEE80211_ACK_LEN) {
2781 DPRINTF(sc, ATH_DEBUG_RECV,
2782 "%s: runt packet %d\n",
2784 sc->sc_stats.ast_rx_tooshort++;
2788 rix = ds->ds_rxstat.rs_rate;
2789 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
2790 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
2791 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi;
2792 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna;
2795 bpf_mtap2(sc->sc_drvbpf,
2796 &sc->sc_rx_th, sc->sc_rx_th_len, m);
2800 * From this point on we assume the frame is at least
2801 * as large as ieee80211_frame_min; verify that.
2803 if (len < IEEE80211_MIN_LEN) {
2804 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n",
2806 sc->sc_stats.ast_rx_tooshort++;
2811 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
2812 ieee80211_dump_pkt(mtod(m, caddr_t), len,
2813 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate,
2814 ds->ds_rxstat.rs_rssi);
2817 m_adj(m, -IEEE80211_CRC_LEN);
2820 * Locate the node for sender, track state, and then
2821 * pass the (referenced) node up to the 802.11 layer
2822 * for its use. If the sender is unknown spam the
2823 * frame; it'll be dropped where it's not wanted.
2825 if (ds->ds_rxstat.rs_keyix != HAL_RXKEYIX_INVALID &&
2826 (ni = sc->sc_keyixmap[ds->ds_rxstat.rs_keyix]) != NULL) {
2828 * Fast path: node is present in the key map;
2829 * grab a reference for processing the frame.
2831 an = ATH_NODE(ieee80211_ref_node(ni));
2832 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi);
2833 type = ieee80211_input(ic, m, ni,
2834 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp);
2837 * Locate the node for sender, track state, and then
2838 * pass the (referenced) node up to the 802.11 layer
2841 ni = ieee80211_find_rxnode(ic,
2842 mtod(m, const struct ieee80211_frame_min *));
2844 * Track rx rssi and do any rx antenna management.
2847 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi);
2849 * Send frame up for processing.
2851 type = ieee80211_input(ic, m, ni,
2852 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp);
2853 if (ni != ic->ic_bss) {
2856 * If the station has a key cache slot assigned
2857 * update the key->node mapping table.
2859 keyix = ni->ni_ucastkey.wk_keyix;
2860 if (keyix != IEEE80211_KEYIX_NONE &&
2861 sc->sc_keyixmap[keyix] == NULL)
2862 sc->sc_keyixmap[keyix] =
2863 ieee80211_ref_node(ni);
2866 ieee80211_free_node(ni);
2867 if (sc->sc_diversity) {
2869 * When using fast diversity, change the default rx
2870 * antenna if diversity chooses the other antenna 3
2873 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) {
2874 if (++sc->sc_rxotherant >= 3)
2875 ath_setdefantenna(sc,
2876 ds->ds_rxstat.rs_antenna);
2878 sc->sc_rxotherant = 0;
2880 if (sc->sc_softled) {
2882 * Blink for any data frame. Otherwise do a
2883 * heartbeat-style blink when idle. The latter
2884 * is mainly for station mode where we depend on
2885 * periodic beacon frames to trigger the poll event.
2887 if (type == IEEE80211_FC0_TYPE_DATA) {
2888 sc->sc_rxrate = ds->ds_rxstat.rs_rate;
2889 ath_led_event(sc, ATH_LED_RX);
2890 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
2891 ath_led_event(sc, ATH_LED_POLL);
2894 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
2895 } while (ath_rxbuf_init(sc, bf) == 0);
2897 /* rx signal state monitoring */
2898 ath_hal_rxmonitor(ah, &ATH_NODE(ic->ic_bss)->an_halstats);
2900 NET_UNLOCK_GIANT(); /* XXX */
2905 * Setup a h/w transmit queue.
2907 static struct ath_txq *
2908 ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
2910 #define N(a) (sizeof(a)/sizeof(a[0]))
2911 struct ath_hal *ah = sc->sc_ah;
2915 memset(&qi, 0, sizeof(qi));
2916 qi.tqi_subtype = subtype;
2917 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
2918 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
2919 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
2921 * Enable interrupts only for EOL and DESC conditions.
2922 * We mark tx descriptors to receive a DESC interrupt
2923 * when a tx queue gets deep; otherwise waiting for the
2924 * EOL to reap descriptors. Note that this is done to
2925 * reduce interrupt load and this only defers reaping
2926 * descriptors, never transmitting frames. Aside from
2927 * reducing interrupts this also permits more concurrency.
2928 * The only potential downside is if the tx queue backs
2929 * up in which case the top half of the kernel may backup
2930 * due to a lack of tx descriptors.
2932 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | TXQ_FLAG_TXDESCINT_ENABLE;
2933 qnum = ath_hal_setuptxqueue(ah, qtype, &qi);
2936 * NB: don't print a message, this happens
2937 * normally on parts with too few tx queues
2941 if (qnum >= N(sc->sc_txq)) {
2942 device_printf(sc->sc_dev,
2943 "hal qnum %u out of range, max %zu!\n",
2944 qnum, N(sc->sc_txq));
2945 ath_hal_releasetxqueue(ah, qnum);
2948 if (!ATH_TXQ_SETUP(sc, qnum)) {
2949 struct ath_txq *txq = &sc->sc_txq[qnum];
2951 txq->axq_qnum = qnum;
2953 txq->axq_intrcnt = 0;
2954 txq->axq_link = NULL;
2955 STAILQ_INIT(&txq->axq_q);
2956 ATH_TXQ_LOCK_INIT(sc, txq);
2957 sc->sc_txqsetup |= 1<<qnum;
2959 return &sc->sc_txq[qnum];
2964 * Setup a hardware data transmit queue for the specified
2965 * access control. The hal may not support all requested
2966 * queues in which case it will return a reference to a
2967 * previously setup queue. We record the mapping from ac's
2968 * to h/w queues for use by ath_tx_start and also track
2969 * the set of h/w queues being used to optimize work in the
2970 * transmit interrupt handler and related routines.
2973 ath_tx_setup(struct ath_softc *sc, int ac, int haltype)
2975 #define N(a) (sizeof(a)/sizeof(a[0]))
2976 struct ath_txq *txq;
2978 if (ac >= N(sc->sc_ac2q)) {
2979 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n",
2980 ac, N(sc->sc_ac2q));
2983 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype);
2985 sc->sc_ac2q[ac] = txq;
2993 * Update WME parameters for a transmit queue.
2996 ath_txq_update(struct ath_softc *sc, int ac)
2998 #define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1)
2999 #define ATH_TXOP_TO_US(v) (v<<5)
3000 struct ieee80211com *ic = &sc->sc_ic;
3001 struct ath_txq *txq = sc->sc_ac2q[ac];
3002 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac];
3003 struct ath_hal *ah = sc->sc_ah;
3006 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi);
3007 qi.tqi_aifs = wmep->wmep_aifsn;
3008 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
3009 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
3010 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit);
3012 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) {
3013 device_printf(sc->sc_dev, "unable to update hardware queue "
3014 "parameters for %s traffic!\n",
3015 ieee80211_wme_acnames[ac]);
3018 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */
3021 #undef ATH_TXOP_TO_US
3022 #undef ATH_EXPONENT_TO_VALUE
3026 * Callback from the 802.11 layer to update WME parameters.
3029 ath_wme_update(struct ieee80211com *ic)
3031 struct ath_softc *sc = ic->ic_ifp->if_softc;
3033 return !ath_txq_update(sc, WME_AC_BE) ||
3034 !ath_txq_update(sc, WME_AC_BK) ||
3035 !ath_txq_update(sc, WME_AC_VI) ||
3036 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0;
3040 * Reclaim resources for a setup queue.
3043 ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
3046 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum);
3047 ATH_TXQ_LOCK_DESTROY(txq);
3048 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
3052 * Reclaim all tx queue resources.
3055 ath_tx_cleanup(struct ath_softc *sc)
3059 ATH_TXBUF_LOCK_DESTROY(sc);
3060 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3061 if (ATH_TXQ_SETUP(sc, i))
3062 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
3066 * Defragment an mbuf chain, returning at most maxfrags separate
3067 * mbufs+clusters. If this is not possible NULL is returned and
3068 * the original mbuf chain is left in it's present (potentially
3069 * modified) state. We use two techniques: collapsing consecutive
3070 * mbufs and replacing consecutive mbufs by a cluster.
3072 static struct mbuf *
3073 ath_defrag(struct mbuf *m0, int how, int maxfrags)
3075 struct mbuf *m, *n, *n2, **prev;
3079 * Calculate the current number of frags.
3082 for (m = m0; m != NULL; m = m->m_next)
3085 * First, try to collapse mbufs. Note that we always collapse
3086 * towards the front so we don't need to deal with moving the
3087 * pkthdr. This may be suboptimal if the first mbuf has much
3088 * less data than the following.
3096 if ((m->m_flags & M_RDONLY) == 0 &&
3097 n->m_len < M_TRAILINGSPACE(m)) {
3098 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len,
3100 m->m_len += n->m_len;
3101 m->m_next = n->m_next;
3103 if (--curfrags <= maxfrags)
3108 KASSERT(maxfrags > 1,
3109 ("maxfrags %u, but normal collapse failed", maxfrags));
3111 * Collapse consecutive mbufs to a cluster.
3113 prev = &m0->m_next; /* NB: not the first mbuf */
3114 while ((n = *prev) != NULL) {
3115 if ((n2 = n->m_next) != NULL &&
3116 n->m_len + n2->m_len < MCLBYTES) {
3117 m = m_getcl(how, MT_DATA, 0);
3120 bcopy(mtod(n, void *), mtod(m, void *), n->m_len);
3121 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len,
3123 m->m_len = n->m_len + n2->m_len;
3124 m->m_next = n2->m_next;
3128 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */
3131 * Still not there, try the normal collapse
3132 * again before we allocate another cluster.
3139 * No place where we can collapse to a cluster; punt.
3140 * This can occur if, for example, you request 2 frags
3141 * but the packet requires that both be clusters (we
3142 * never reallocate the first mbuf to avoid moving the
3150 ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf,
3153 #define CTS_DURATION \
3154 ath_hal_computetxtime(ah, rt, IEEE80211_ACK_LEN, cix, AH_TRUE)
3155 #define updateCTSForBursting(_ah, _ds, _txq) \
3156 ath_hal_updateCTSForBursting(_ah, _ds, \
3157 _txq->axq_linkbuf != NULL ? _txq->axq_linkbuf->bf_desc : NULL, \
3158 _txq->axq_lastdsWithCTS, _txq->axq_gatingds, \
3159 txopLimit, CTS_DURATION)
3160 struct ieee80211com *ic = &sc->sc_ic;
3161 struct ath_hal *ah = sc->sc_ah;
3162 struct ifnet *ifp = sc->sc_ifp;
3163 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams;
3164 int i, error, iswep, ismcast, keyix, hdrlen, pktlen, try0;
3165 u_int8_t rix, txrate, ctsrate;
3166 u_int8_t cix = 0xff; /* NB: silence compiler */
3167 struct ath_desc *ds, *ds0;
3168 struct ath_txq *txq;
3169 struct ieee80211_frame *wh;
3170 u_int subtype, flags, ctsduration;
3172 const HAL_RATE_TABLE *rt;
3173 HAL_BOOL shortPreamble;
3174 struct ath_node *an;
3178 wh = mtod(m0, struct ieee80211_frame *);
3179 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
3180 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3181 hdrlen = ieee80211_anyhdrsize(wh);
3183 * Packet length must not include any
3184 * pad bytes; deduct them here.
3186 pktlen = m0->m_pkthdr.len - (hdrlen & 3);
3189 const struct ieee80211_cipher *cip;
3190 struct ieee80211_key *k;
3193 * Construct the 802.11 header+trailer for an encrypted
3194 * frame. The only reason this can fail is because of an
3195 * unknown or unsupported cipher/key type.
3197 k = ieee80211_crypto_encap(ic, ni, m0);
3200 * This can happen when the key is yanked after the
3201 * frame was queued. Just discard the frame; the
3202 * 802.11 layer counts failures and provides
3203 * debugging/diagnostics.
3209 * Adjust the packet + header lengths for the crypto
3210 * additions and calculate the h/w key index. When
3211 * a s/w mic is done the frame will have had any mic
3212 * added to it prior to entry so skb->len above will
3213 * account for it. Otherwise we need to add it to the
3217 hdrlen += cip->ic_header;
3218 pktlen += cip->ic_header + cip->ic_trailer;
3219 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0)
3220 pktlen += cip->ic_miclen;
3221 keyix = k->wk_keyix;
3223 /* packet header may have moved, reset our local pointer */
3224 wh = mtod(m0, struct ieee80211_frame *);
3225 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) {
3227 * Use station key cache slot, if assigned.
3229 keyix = ni->ni_ucastkey.wk_keyix;
3230 if (keyix == IEEE80211_KEYIX_NONE)
3231 keyix = HAL_TXKEYIX_INVALID;
3233 keyix = HAL_TXKEYIX_INVALID;
3235 pktlen += IEEE80211_CRC_LEN;
3238 * Load the DMA map so any coalescing is done. This
3239 * also calculates the number of descriptors we need.
3241 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
3242 bf->bf_segs, &bf->bf_nseg,
3244 if (error == EFBIG) {
3245 /* XXX packet requires too many descriptors */
3246 bf->bf_nseg = ATH_TXDESC+1;
3247 } else if (error != 0) {
3248 sc->sc_stats.ast_tx_busdma++;
3253 * Discard null packets and check for packets that
3254 * require too many TX descriptors. We try to convert
3255 * the latter to a cluster.
3257 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */
3258 sc->sc_stats.ast_tx_linear++;
3259 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC);
3262 sc->sc_stats.ast_tx_nombuf++;
3266 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0,
3267 bf->bf_segs, &bf->bf_nseg,
3270 sc->sc_stats.ast_tx_busdma++;
3274 KASSERT(bf->bf_nseg <= ATH_TXDESC,
3275 ("too many segments after defrag; nseg %u", bf->bf_nseg));
3276 } else if (bf->bf_nseg == 0) { /* null packet, discard */
3277 sc->sc_stats.ast_tx_nodata++;
3281 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen);
3282 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
3284 bf->bf_node = ni; /* NB: held reference */
3286 /* setup descriptors */
3288 rt = sc->sc_currates;
3289 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
3292 * NB: the 802.11 layer marks whether or not we should
3293 * use short preamble based on the current mode and
3294 * negotiated parameters.
3296 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3297 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) {
3298 shortPreamble = AH_TRUE;
3299 sc->sc_stats.ast_tx_shortpre++;
3301 shortPreamble = AH_FALSE;
3305 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */
3307 * Calculate Atheros packet type from IEEE80211 packet header,
3308 * setup for rate calculations, and select h/w transmit queue.
3310 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
3311 case IEEE80211_FC0_TYPE_MGT:
3312 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
3313 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON)
3314 atype = HAL_PKT_TYPE_BEACON;
3315 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
3316 atype = HAL_PKT_TYPE_PROBE_RESP;
3317 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
3318 atype = HAL_PKT_TYPE_ATIM;
3320 atype = HAL_PKT_TYPE_NORMAL; /* XXX */
3321 rix = 0; /* XXX lowest rate */
3322 try0 = ATH_TXMAXTRY;
3324 txrate = an->an_tx_mgtratesp;
3326 txrate = an->an_tx_mgtrate;
3327 /* NB: force all management frames to highest queue */
3328 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3329 /* NB: force all management frames to highest queue */
3333 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3335 case IEEE80211_FC0_TYPE_CTL:
3336 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */
3337 rix = 0; /* XXX lowest rate */
3338 try0 = ATH_TXMAXTRY;
3340 txrate = an->an_tx_mgtratesp;
3342 txrate = an->an_tx_mgtrate;
3343 /* NB: force all ctl frames to highest queue */
3344 if (ni->ni_flags & IEEE80211_NODE_QOS) {
3345 /* NB: force all ctl frames to highest queue */
3349 flags |= HAL_TXDESC_INTREQ; /* force interrupt */
3351 case IEEE80211_FC0_TYPE_DATA:
3352 atype = HAL_PKT_TYPE_NORMAL; /* default */
3354 * Data frames; consult the rate control module.
3356 ath_rate_findrate(sc, an, shortPreamble, pktlen,
3357 &rix, &try0, &txrate);
3358 sc->sc_txrate = txrate; /* for LED blinking */
3360 * Default all non-QoS traffic to the background queue.
3362 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) {
3363 pri = M_WME_GETAC(m0);
3364 if (cap->cap_wmeParams[pri].wmep_noackPolicy) {
3365 flags |= HAL_TXDESC_NOACK;
3366 sc->sc_stats.ast_tx_noack++;
3372 if_printf(ifp, "bogus frame type 0x%x (%s)\n",
3373 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__);
3378 txq = sc->sc_ac2q[pri];
3381 * When servicing one or more stations in power-save mode
3382 * multicast frames must be buffered until after the beacon.
3383 * We use the CAB queue for that.
3385 if (ismcast && ic->ic_ps_sta) {
3387 /* XXX? more bit in 802.11 frame header */
3391 * Calculate miscellaneous flags.
3394 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */
3395 sc->sc_stats.ast_tx_noack++;
3396 } else if (pktlen > ic->ic_rtsthreshold) {
3397 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */
3398 cix = rt->info[rix].controlRate;
3399 sc->sc_stats.ast_tx_rts++;
3403 * If 802.11g protection is enabled, determine whether
3404 * to use RTS/CTS or just CTS. Note that this is only
3405 * done for OFDM unicast frames.
3407 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
3408 rt->info[rix].phy == IEEE80211_T_OFDM &&
3409 (flags & HAL_TXDESC_NOACK) == 0) {
3410 /* XXX fragments must use CCK rates w/ protection */
3411 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS)
3412 flags |= HAL_TXDESC_RTSENA;
3413 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY)
3414 flags |= HAL_TXDESC_CTSENA;
3415 cix = rt->info[sc->sc_protrix].controlRate;
3416 sc->sc_stats.ast_tx_protect++;
3420 * Calculate duration. This logically belongs in the 802.11
3421 * layer but it lacks sufficient information to calculate it.
3423 if ((flags & HAL_TXDESC_NOACK) == 0 &&
3424 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) {
3427 * XXX not right with fragmentation.
3430 dur = rt->info[rix].spAckDuration;
3432 dur = rt->info[rix].lpAckDuration;
3433 *(u_int16_t *)wh->i_dur = htole16(dur);
3437 * Calculate RTS/CTS rate and duration if needed.
3440 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
3442 * CTS transmit rate is derived from the transmit rate
3443 * by looking in the h/w rate table. We must also factor
3444 * in whether or not a short preamble is to be used.
3446 /* NB: cix is set above where RTS/CTS is enabled */
3447 KASSERT(cix != 0xff, ("cix not setup"));
3448 ctsrate = rt->info[cix].rateCode;
3450 * Compute the transmit duration based on the frame
3451 * size and the size of an ACK frame. We call into the
3452 * HAL to do the computation since it depends on the
3453 * characteristics of the actual PHY being used.
3455 * NB: CTS is assumed the same size as an ACK so we can
3456 * use the precalculated ACK durations.
3458 if (shortPreamble) {
3459 ctsrate |= rt->info[cix].shortPreamble;
3460 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3461 ctsduration += rt->info[cix].spAckDuration;
3462 ctsduration += ath_hal_computetxtime(ah,
3463 rt, pktlen, rix, AH_TRUE);
3464 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3465 ctsduration += rt->info[cix].spAckDuration;
3467 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
3468 ctsduration += rt->info[cix].lpAckDuration;
3469 ctsduration += ath_hal_computetxtime(ah,
3470 rt, pktlen, rix, AH_FALSE);
3471 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
3472 ctsduration += rt->info[cix].lpAckDuration;
3475 * Must disable multi-rate retry when using RTS/CTS.
3477 try0 = ATH_TXMAXTRY;
3481 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT))
3482 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len,
3483 sc->sc_hwmap[txrate].ieeerate, -1);
3486 bpf_mtap(ic->ic_rawbpf, m0);
3487 if (sc->sc_drvbpf) {
3488 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags;
3490 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3491 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate;
3492 sc->sc_tx_th.wt_txpower = ni->ni_txpower;
3493 sc->sc_tx_th.wt_antenna = sc->sc_txantenna;
3495 bpf_mtap2(sc->sc_drvbpf,
3496 &sc->sc_tx_th, sc->sc_tx_th_len, m0);
3500 * Determine if a tx interrupt should be generated for
3501 * this descriptor. We take a tx interrupt to reap
3502 * descriptors when the h/w hits an EOL condition or
3503 * when the descriptor is specifically marked to generate
3504 * an interrupt. We periodically mark descriptors in this
3505 * way to insure timely replenishing of the supply needed
3506 * for sending frames. Defering interrupts reduces system
3507 * load and potentially allows more concurrent work to be
3508 * done but if done to aggressively can cause senders to
3511 * NB: use >= to deal with sc_txintrperiod changing
3512 * dynamically through sysctl.
3514 if (flags & HAL_TXDESC_INTREQ) {
3515 txq->axq_intrcnt = 0;
3516 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) {
3517 flags |= HAL_TXDESC_INTREQ;
3518 txq->axq_intrcnt = 0;
3522 * Formulate first tx descriptor with tx controls.
3524 /* XXX check return value? */
3525 ath_hal_setuptxdesc(ah, ds
3526 , pktlen /* packet length */
3527 , hdrlen /* header length */
3528 , atype /* Atheros packet type */
3529 , ni->ni_txpower /* txpower */
3530 , txrate, try0 /* series 0 rate/tries */
3531 , keyix /* key cache index */
3532 , sc->sc_txantenna /* antenna mode */
3534 , ctsrate /* rts/cts rate */
3535 , ctsduration /* rts/cts duration */
3538 * Setup the multi-rate retry state only when we're
3539 * going to use it. This assumes ath_hal_setuptxdesc
3540 * initializes the descriptors (so we don't have to)
3541 * when the hardware supports multi-rate retry and
3544 if (try0 != ATH_TXMAXTRY)
3545 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix);
3548 * Fillin the remainder of the descriptor info.
3551 for (i = 0; i < bf->bf_nseg; i++, ds++) {
3552 ds->ds_data = bf->bf_segs[i].ds_addr;
3553 if (i == bf->bf_nseg - 1)
3556 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1);
3557 ath_hal_filltxdesc(ah, ds
3558 , bf->bf_segs[i].ds_len /* segment length */
3559 , i == 0 /* first segment */
3560 , i == bf->bf_nseg - 1 /* last segment */
3561 , ds0 /* first descriptor */
3563 DPRINTF(sc, ATH_DEBUG_XMIT,
3564 "%s: %d: %08x %08x %08x %08x %08x %08x\n",
3565 __func__, i, ds->ds_link, ds->ds_data,
3566 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]);
3569 * Insert the frame on the outbound list and
3570 * pass it on to the hardware.
3573 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
3574 u_int32_t txopLimit = IEEE80211_TXOP_TO_US(
3575 cap->cap_wmeParams[pri].wmep_txopLimit);
3577 * When bursting, potentially extend the CTS duration
3578 * of a previously queued frame to cover this frame
3579 * and not exceed the txopLimit. If that can be done
3580 * then disable RTS/CTS on this frame since it's now
3581 * covered (burst extension). Otherwise we must terminate
3582 * the burst before this frame goes out so as not to
3583 * violate the WME parameters. All this is complicated
3584 * as we need to update the state of packets on the
3585 * (live) hardware queue. The logic is buried in the hal
3586 * because it's highly chip-specific.
3588 if (txopLimit != 0) {
3589 sc->sc_stats.ast_tx_ctsburst++;
3590 if (updateCTSForBursting(ah, ds0, txq) == 0) {
3592 * This frame was not covered by RTS/CTS from
3593 * the previous frame in the burst; update the
3594 * descriptor pointers so this frame is now
3595 * treated as the last frame for extending a
3598 txq->axq_lastdsWithCTS = ds0;
3599 /* set gating Desc to final desc */
3601 (struct ath_desc *)txq->axq_link;
3603 sc->sc_stats.ast_tx_ctsext++;
3606 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
3607 if (txq->axq_link == NULL) {
3608 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
3609 DPRINTF(sc, ATH_DEBUG_XMIT,
3610 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__,
3611 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc,
3614 *txq->axq_link = bf->bf_daddr;
3615 DPRINTF(sc, ATH_DEBUG_XMIT,
3616 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__,
3617 txq->axq_qnum, txq->axq_link,
3618 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth);
3620 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link;
3622 * The CAB queue is started from the SWBA handler since
3623 * frames only go out on DTIM and to avoid possible races.
3625 if (txq != sc->sc_cabq)
3626 ath_hal_txstart(ah, txq->axq_qnum);
3627 ATH_TXQ_UNLOCK(txq);
3630 #undef updateCTSForBursting
3635 * Process completed xmit descriptors from the specified queue.
3638 ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
3640 struct ath_hal *ah = sc->sc_ah;
3641 struct ieee80211com *ic = &sc->sc_ic;
3643 struct ath_desc *ds, *ds0;
3644 struct ieee80211_node *ni;
3645 struct ath_node *an;
3649 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n",
3650 __func__, txq->axq_qnum,
3651 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum),
3655 txq->axq_intrcnt = 0; /* reset periodic desc intr count */
3656 bf = STAILQ_FIRST(&txq->axq_q);
3658 txq->axq_link = NULL;
3659 ATH_TXQ_UNLOCK(txq);
3662 ds0 = &bf->bf_desc[0];
3663 ds = &bf->bf_desc[bf->bf_nseg - 1];
3664 status = ath_hal_txprocdesc(ah, ds);
3666 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
3667 ath_printtxbuf(bf, status == HAL_OK);
3669 if (status == HAL_EINPROGRESS) {
3670 ATH_TXQ_UNLOCK(txq);
3673 if (ds0 == txq->axq_lastdsWithCTS)
3674 txq->axq_lastdsWithCTS = NULL;
3675 if (ds == txq->axq_gatingds)
3676 txq->axq_gatingds = NULL;
3677 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3678 ATH_TXQ_UNLOCK(txq);
3683 if (ds->ds_txstat.ts_status == 0) {
3684 u_int8_t txant = ds->ds_txstat.ts_antenna;
3685 sc->sc_stats.ast_ant_tx[txant]++;
3686 sc->sc_ant_tx[txant]++;
3687 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
3688 sc->sc_stats.ast_tx_altrate++;
3689 sc->sc_stats.ast_tx_rssi =
3690 ds->ds_txstat.ts_rssi;
3691 ATH_RSSI_LPF(an->an_halstats.ns_avgtxrssi,
3692 ds->ds_txstat.ts_rssi);
3693 pri = M_WME_GETAC(bf->bf_m);
3694 if (pri >= WME_AC_VO)
3695 ic->ic_wme.wme_hipri_traffic++;
3696 ni->ni_inact = ni->ni_inact_reload;
3698 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
3699 sc->sc_stats.ast_tx_xretries++;
3700 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
3701 sc->sc_stats.ast_tx_fifoerr++;
3702 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
3703 sc->sc_stats.ast_tx_filtered++;
3705 sr = ds->ds_txstat.ts_shortretry;
3706 lr = ds->ds_txstat.ts_longretry;
3707 sc->sc_stats.ast_tx_shortretry += sr;
3708 sc->sc_stats.ast_tx_longretry += lr;
3710 * Hand the descriptor to the rate control algorithm.
3712 ath_rate_tx_complete(sc, an, ds, ds0);
3714 * Reclaim reference to node.
3716 * NB: the node may be reclaimed here if, for example
3717 * this is a DEAUTH message that was sent and the
3718 * node was timed out due to inactivity.
3720 ieee80211_free_node(ni);
3722 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
3723 BUS_DMASYNC_POSTWRITE);
3724 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3730 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
3731 ATH_TXBUF_UNLOCK(sc);
3736 * Deferred processing of transmit interrupt; special-cased
3737 * for a single hardware transmit queue (e.g. 5210 and 5211).
3740 ath_tx_proc_q0(void *arg, int npending)
3742 struct ath_softc *sc = arg;
3743 struct ifnet *ifp = sc->sc_ifp;
3745 ath_tx_processq(sc, &sc->sc_txq[0]);
3746 ath_tx_processq(sc, sc->sc_cabq);
3747 ifp->if_flags &= ~IFF_OACTIVE;
3748 sc->sc_tx_timer = 0;
3751 ath_led_event(sc, ATH_LED_TX);
3757 * Deferred processing of transmit interrupt; special-cased
3758 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support).
3761 ath_tx_proc_q0123(void *arg, int npending)
3763 struct ath_softc *sc = arg;
3764 struct ifnet *ifp = sc->sc_ifp;
3767 * Process each active queue.
3769 ath_tx_processq(sc, &sc->sc_txq[0]);
3770 ath_tx_processq(sc, &sc->sc_txq[1]);
3771 ath_tx_processq(sc, &sc->sc_txq[2]);
3772 ath_tx_processq(sc, &sc->sc_txq[3]);
3773 ath_tx_processq(sc, sc->sc_cabq);
3775 ifp->if_flags &= ~IFF_OACTIVE;
3776 sc->sc_tx_timer = 0;
3779 ath_led_event(sc, ATH_LED_TX);
3785 * Deferred processing of transmit interrupt.
3788 ath_tx_proc(void *arg, int npending)
3790 struct ath_softc *sc = arg;
3791 struct ifnet *ifp = sc->sc_ifp;
3795 * Process each active queue.
3797 /* XXX faster to read ISR_S0_S and ISR_S1_S to determine q's? */
3798 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3799 if (ATH_TXQ_SETUP(sc, i))
3800 ath_tx_processq(sc, &sc->sc_txq[i]);
3802 ifp->if_flags &= ~IFF_OACTIVE;
3803 sc->sc_tx_timer = 0;
3806 ath_led_event(sc, ATH_LED_TX);
3812 ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
3814 struct ath_hal *ah = sc->sc_ah;
3815 struct ieee80211_node *ni;
3819 * NB: this assumes output has been stopped and
3820 * we do not need to block ath_tx_tasklet
3824 bf = STAILQ_FIRST(&txq->axq_q);
3826 txq->axq_link = NULL;
3827 ATH_TXQ_UNLOCK(txq);
3830 ATH_TXQ_REMOVE_HEAD(txq, bf_list);
3831 ATH_TXQ_UNLOCK(txq);
3833 if (sc->sc_debug & ATH_DEBUG_RESET)
3835 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK);
3836 #endif /* AR_DEBUG */
3837 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
3844 * Reclaim node reference.
3846 ieee80211_free_node(ni);
3849 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list);
3850 ATH_TXBUF_UNLOCK(sc);
3855 ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
3857 struct ath_hal *ah = sc->sc_ah;
3859 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
3860 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n",
3861 __func__, txq->axq_qnum,
3862 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum),
3867 * Drain the transmit queues and reclaim resources.
3870 ath_draintxq(struct ath_softc *sc)
3872 struct ath_hal *ah = sc->sc_ah;
3873 struct ifnet *ifp = sc->sc_ifp;
3876 /* XXX return value */
3877 if (!sc->sc_invalid) {
3878 /* don't touch the hardware if marked invalid */
3879 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
3880 DPRINTF(sc, ATH_DEBUG_RESET,
3881 "%s: beacon queue %p\n", __func__,
3882 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq));
3883 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3884 if (ATH_TXQ_SETUP(sc, i))
3885 ath_tx_stopdma(sc, &sc->sc_txq[i]);
3887 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
3888 if (ATH_TXQ_SETUP(sc, i))
3889 ath_tx_draintxq(sc, &sc->sc_txq[i]);
3890 ifp->if_flags &= ~IFF_OACTIVE;
3891 sc->sc_tx_timer = 0;
3895 * Disable the receive h/w in preparation for a reset.
3898 ath_stoprecv(struct ath_softc *sc)
3900 #define PA2DESC(_sc, _pa) \
3901 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
3902 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
3903 struct ath_hal *ah = sc->sc_ah;
3905 ath_hal_stoppcurecv(ah); /* disable PCU */
3906 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
3907 ath_hal_stopdmarecv(ah); /* disable DMA engine */
3908 DELAY(3000); /* 3ms is long enough for 1 frame */
3910 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
3913 printf("%s: rx queue %p, link %p\n", __func__,
3914 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink);
3915 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
3916 struct ath_desc *ds = bf->bf_desc;
3917 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
3918 bf->bf_daddr, PA2DESC(sc, ds->ds_link));
3919 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
3920 ath_printrxbuf(bf, status == HAL_OK);
3924 sc->sc_rxlink = NULL; /* just in case */
3929 * Enable the receive h/w following a reset.
3932 ath_startrecv(struct ath_softc *sc)
3934 struct ath_hal *ah = sc->sc_ah;
3937 sc->sc_rxlink = NULL;
3938 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
3939 int error = ath_rxbuf_init(sc, bf);
3941 DPRINTF(sc, ATH_DEBUG_RECV,
3942 "%s: ath_rxbuf_init failed %d\n",
3948 bf = STAILQ_FIRST(&sc->sc_rxbuf);
3949 ath_hal_putrxbuf(ah, bf->bf_daddr);
3950 ath_hal_rxena(ah); /* enable recv descriptors */
3951 ath_mode_init(sc); /* set filters, etc. */
3952 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
3957 * Update internal state after a channel change.
3960 ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan)
3962 struct ieee80211com *ic = &sc->sc_ic;
3963 enum ieee80211_phymode mode;
3967 * Change channels and update the h/w rate map
3968 * if we're switching; e.g. 11a to 11b/g.
3970 mode = ieee80211_chan2mode(ic, chan);
3971 if (mode != sc->sc_curmode)
3972 ath_setcurmode(sc, mode);
3974 * Update BPF state. NB: ethereal et. al. don't handle
3975 * merged flags well so pick a unique mode for their use.
3977 if (IEEE80211_IS_CHAN_A(chan))
3978 flags = IEEE80211_CHAN_A;
3979 /* XXX 11g schizophrenia */
3980 else if (IEEE80211_IS_CHAN_G(chan) ||
3981 IEEE80211_IS_CHAN_PUREG(chan))
3982 flags = IEEE80211_CHAN_G;
3984 flags = IEEE80211_CHAN_B;
3985 if (IEEE80211_IS_CHAN_T(chan))
3986 flags |= IEEE80211_CHAN_TURBO;
3987 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
3988 htole16(chan->ic_freq);
3989 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
3994 * Set/change channels. If the channel is really being changed,
3995 * it's done by reseting the chip. To accomplish this we must
3996 * first cleanup any pending DMA, then restart stuff after a la
4000 ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
4002 struct ath_hal *ah = sc->sc_ah;
4003 struct ieee80211com *ic = &sc->sc_ic;
4007 * Convert to a HAL channel description with
4008 * the flags constrained to reflect the current
4011 hchan.channel = chan->ic_freq;
4012 hchan.channelFlags = ath_chan2flags(ic, chan);
4014 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n",
4016 ath_hal_mhz2ieee(sc->sc_curchan.channel,
4017 sc->sc_curchan.channelFlags),
4018 sc->sc_curchan.channel,
4019 ath_hal_mhz2ieee(hchan.channel, hchan.channelFlags), hchan.channel);
4020 if (hchan.channel != sc->sc_curchan.channel ||
4021 hchan.channelFlags != sc->sc_curchan.channelFlags) {
4025 * To switch channels clear any pending DMA operations;
4026 * wait long enough for the RX fifo to drain, reset the
4027 * hardware at the new frequency, and then re-enable
4028 * the relevant bits of the h/w.
4030 ath_hal_intrset(ah, 0); /* disable interrupts */
4031 ath_draintxq(sc); /* clear pending tx frames */
4032 ath_stoprecv(sc); /* turn off frame recv */
4033 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) {
4034 if_printf(ic->ic_ifp, "ath_chan_set: unable to reset "
4035 "channel %u (%u Mhz)\n",
4036 ieee80211_chan2ieee(ic, chan), chan->ic_freq);
4039 sc->sc_curchan = hchan;
4040 ath_update_txpow(sc); /* update tx power state */
4043 * Re-enable rx framework.
4045 if (ath_startrecv(sc) != 0) {
4046 if_printf(ic->ic_ifp,
4047 "ath_chan_set: unable to restart recv logic\n");
4052 * Change channels and update the h/w rate map
4053 * if we're switching; e.g. 11a to 11b/g.
4055 ic->ic_ibss_chan = chan;
4056 ath_chan_change(sc, chan);
4059 * Re-enable interrupts.
4061 ath_hal_intrset(ah, sc->sc_imask);
4067 ath_next_scan(void *arg)
4069 struct ath_softc *sc = arg;
4070 struct ieee80211com *ic = &sc->sc_ic;
4072 if (ic->ic_state == IEEE80211_S_SCAN)
4073 ieee80211_next_scan(ic);
4077 * Periodically recalibrate the PHY to account
4078 * for temperature/environment changes.
4081 ath_calibrate(void *arg)
4083 struct ath_softc *sc = arg;
4084 struct ath_hal *ah = sc->sc_ah;
4086 sc->sc_stats.ast_per_cal++;
4088 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: channel %u/%x\n",
4089 __func__, sc->sc_curchan.channel, sc->sc_curchan.channelFlags);
4091 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) {
4093 * Rfgain is out of bounds, reset the chip
4094 * to load new gain values.
4096 sc->sc_stats.ast_per_rfgain++;
4097 ath_reset(sc->sc_ifp);
4099 if (!ath_hal_calibrate(ah, &sc->sc_curchan)) {
4100 DPRINTF(sc, ATH_DEBUG_ANY,
4101 "%s: calibration of channel %u failed\n",
4102 __func__, sc->sc_curchan.channel);
4103 sc->sc_stats.ast_per_calfail++;
4105 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, ath_calibrate, sc);
4109 ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
4111 struct ifnet *ifp = ic->ic_ifp;
4112 struct ath_softc *sc = ifp->if_softc;
4113 struct ath_hal *ah = sc->sc_ah;
4114 struct ieee80211_node *ni;
4116 const u_int8_t *bssid;
4118 static const HAL_LED_STATE leds[] = {
4119 HAL_LED_INIT, /* IEEE80211_S_INIT */
4120 HAL_LED_SCAN, /* IEEE80211_S_SCAN */
4121 HAL_LED_AUTH, /* IEEE80211_S_AUTH */
4122 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */
4123 HAL_LED_RUN, /* IEEE80211_S_RUN */
4126 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__,
4127 ieee80211_state_name[ic->ic_state],
4128 ieee80211_state_name[nstate]);
4130 callout_stop(&sc->sc_scan_ch);
4131 callout_stop(&sc->sc_cal_ch);
4132 ath_hal_setledstate(ah, leds[nstate]); /* set LED */
4134 if (nstate == IEEE80211_S_INIT) {
4135 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4137 * NB: disable interrupts so we don't rx frames.
4139 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL);
4141 * Notify the rate control algorithm.
4143 ath_rate_newstate(sc, nstate);
4147 error = ath_chan_set(sc, ni->ni_chan);
4150 rfilt = ath_calcrxfilter(sc, nstate);
4151 if (nstate == IEEE80211_S_SCAN)
4152 bssid = ifp->if_broadcastaddr;
4154 bssid = ni->ni_bssid;
4155 ath_hal_setrxfilter(ah, rfilt);
4156 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n",
4157 __func__, rfilt, ether_sprintf(bssid));
4159 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA)
4160 ath_hal_setassocid(ah, bssid, ni->ni_associd);
4162 ath_hal_setassocid(ah, bssid, 0);
4163 if (ic->ic_flags & IEEE80211_F_PRIVACY) {
4164 for (i = 0; i < IEEE80211_WEP_NKID; i++)
4165 if (ath_hal_keyisvalid(ah, i))
4166 ath_hal_keysetmac(ah, i, bssid);
4170 * Notify the rate control algorithm so rates
4171 * are setup should ath_beacon_alloc be called.
4173 ath_rate_newstate(sc, nstate);
4175 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
4176 /* nothing to do */;
4177 } else if (nstate == IEEE80211_S_RUN) {
4178 DPRINTF(sc, ATH_DEBUG_STATE,
4179 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s "
4180 "capinfo=0x%04x chan=%d\n"
4184 , ether_sprintf(ni->ni_bssid)
4186 , ieee80211_chan2ieee(ic, ni->ni_chan));
4188 switch (ic->ic_opmode) {
4189 case IEEE80211_M_HOSTAP:
4190 case IEEE80211_M_IBSS:
4192 * Allocate and setup the beacon frame.
4194 * Stop any previous beacon DMA. This may be
4195 * necessary, for example, when an ibss merge
4196 * causes reconfiguration; there will be a state
4197 * transition from RUN->RUN that means we may
4198 * be called with beacon transmission active.
4200 ath_hal_stoptxdma(ah, sc->sc_bhalq);
4201 ath_beacon_free(sc);
4202 error = ath_beacon_alloc(sc, ni);
4206 case IEEE80211_M_STA:
4208 * Allocate a key cache slot to the station.
4210 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 &&
4212 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE)
4213 ath_setup_stationkey(ni);
4220 * Configure the beacon and sleep timers.
4222 ath_beacon_config(sc);
4225 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS));
4226 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS);
4230 * Invoke the parent method to complete the work.
4232 error = sc->sc_newstate(ic, nstate, arg);
4234 * Finally, start any timers.
4236 if (nstate == IEEE80211_S_RUN) {
4237 /* start periodic recalibration timer */
4238 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz,
4240 } else if (nstate == IEEE80211_S_SCAN) {
4241 /* start ap/neighbor scan timer */
4242 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000,
4250 * Allocate a key cache slot to the station so we can
4251 * setup a mapping from key index to node. The key cache
4252 * slot is needed for managing antenna state and for
4253 * compression when stations do not use crypto. We do
4254 * it uniliaterally here; if crypto is employed this slot
4255 * will be reassigned.
4258 ath_setup_stationkey(struct ieee80211_node *ni)
4260 struct ieee80211com *ic = ni->ni_ic;
4261 struct ath_softc *sc = ic->ic_ifp->if_softc;
4264 keyix = ath_key_alloc(ic, &ni->ni_ucastkey);
4265 if (keyix == IEEE80211_KEYIX_NONE) {
4267 * Key cache is full; we'll fall back to doing
4268 * the more expensive lookup in software. Note
4269 * this also means no h/w compression.
4271 /* XXX msg+statistic */
4273 ni->ni_ucastkey.wk_keyix = keyix;
4274 /* NB: this will create a pass-thru key entry */
4275 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss);
4280 * Setup driver-specific state for a newly associated node.
4281 * Note that we're called also on a re-associate, the isnew
4282 * param tells us if this is the first time or not.
4285 ath_newassoc(struct ieee80211com *ic, struct ieee80211_node *ni, int isnew)
4287 struct ath_softc *sc = ic->ic_ifp->if_softc;
4289 ath_rate_newassoc(sc, ATH_NODE(ni), isnew);
4291 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) {
4292 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE,
4293 ("new assoc with a unicast key already setup (keyix %u)",
4294 ni->ni_ucastkey.wk_keyix));
4295 ath_setup_stationkey(ni);
4300 ath_getchannels(struct ath_softc *sc, u_int cc,
4301 HAL_BOOL outdoor, HAL_BOOL xchanmode)
4303 struct ieee80211com *ic = &sc->sc_ic;
4304 struct ifnet *ifp = sc->sc_ifp;
4305 struct ath_hal *ah = sc->sc_ah;
4309 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL),
4311 if (chans == NULL) {
4312 if_printf(ifp, "unable to allocate channel table\n");
4315 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan,
4316 cc, HAL_MODE_ALL, outdoor, xchanmode)) {
4319 ath_hal_getregdomain(ah, &rd);
4320 if_printf(ifp, "unable to collect channel list from hal; "
4321 "regdomain likely %u country code %u\n", rd, cc);
4322 free(chans, M_TEMP);
4327 * Convert HAL channels to ieee80211 ones and insert
4328 * them in the table according to their channel number.
4330 for (i = 0; i < nchan; i++) {
4331 HAL_CHANNEL *c = &chans[i];
4332 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags);
4333 if (ix > IEEE80211_CHAN_MAX) {
4334 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n",
4335 ix, c->channel, c->channelFlags);
4338 /* NB: flags are known to be compatible */
4339 if (ic->ic_channels[ix].ic_freq == 0) {
4340 ic->ic_channels[ix].ic_freq = c->channel;
4341 ic->ic_channels[ix].ic_flags = c->channelFlags;
4343 /* channels overlap; e.g. 11g and 11b */
4344 ic->ic_channels[ix].ic_flags |= c->channelFlags;
4347 free(chans, M_TEMP);
4352 ath_led_done(void *arg)
4354 struct ath_softc *sc = arg;
4356 sc->sc_blinking = 0;
4360 * Turn the LED off: flip the pin and then set a timer so no
4361 * update will happen for the specified duration.
4364 ath_led_off(void *arg)
4366 struct ath_softc *sc = arg;
4368 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon);
4369 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc);
4373 * Blink the LED according to the specified on/off times.
4376 ath_led_blink(struct ath_softc *sc, int on, int off)
4378 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off);
4379 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon);
4380 sc->sc_blinking = 1;
4381 sc->sc_ledoff = off;
4382 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc);
4386 ath_led_event(struct ath_softc *sc, int event)
4389 sc->sc_ledevent = ticks; /* time of last event */
4390 if (sc->sc_blinking) /* don't interrupt active blink */
4394 ath_led_blink(sc, sc->sc_hwmap[0].ledon,
4395 sc->sc_hwmap[0].ledoff);
4398 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon,
4399 sc->sc_hwmap[sc->sc_txrate].ledoff);
4402 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon,
4403 sc->sc_hwmap[sc->sc_rxrate].ledoff);
4409 ath_update_txpow(struct ath_softc *sc)
4411 struct ieee80211com *ic = &sc->sc_ic;
4412 struct ath_hal *ah = sc->sc_ah;
4415 if (sc->sc_curtxpow != ic->ic_txpowlimit) {
4416 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit);
4417 /* read back in case value is clamped */
4418 ath_hal_gettxpowlimit(ah, &txpow);
4419 ic->ic_txpowlimit = sc->sc_curtxpow = txpow;
4422 * Fetch max tx power level for status requests.
4424 ath_hal_getmaxtxpow(sc->sc_ah, &txpow);
4425 ic->ic_bss->ni_txpower = txpow;
4429 ath_rate_setup(struct ath_softc *sc, u_int mode)
4431 struct ath_hal *ah = sc->sc_ah;
4432 struct ieee80211com *ic = &sc->sc_ic;
4433 const HAL_RATE_TABLE *rt;
4434 struct ieee80211_rateset *rs;
4438 case IEEE80211_MODE_11A:
4439 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A);
4441 case IEEE80211_MODE_11B:
4442 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B);
4444 case IEEE80211_MODE_11G:
4445 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G);
4447 case IEEE80211_MODE_TURBO_A:
4448 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO);
4450 case IEEE80211_MODE_TURBO_G:
4451 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_108G);
4454 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n",
4458 rt = sc->sc_rates[mode];
4461 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) {
4462 DPRINTF(sc, ATH_DEBUG_ANY,
4463 "%s: rate table too small (%u > %u)\n",
4464 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE);
4465 maxrates = IEEE80211_RATE_MAXSIZE;
4467 maxrates = rt->rateCount;
4468 rs = &ic->ic_sup_rates[mode];
4469 for (i = 0; i < maxrates; i++)
4470 rs->rs_rates[i] = rt->info[i].dot11Rate;
4471 rs->rs_nrates = maxrates;
4476 ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode)
4478 #define N(a) (sizeof(a)/sizeof(a[0]))
4479 /* NB: on/off times from the Atheros NDIS driver, w/ permission */
4480 static const struct {
4481 u_int rate; /* tx/rx 802.11 rate */
4482 u_int16_t timeOn; /* LED on time (ms) */
4483 u_int16_t timeOff; /* LED off time (ms) */
4500 const HAL_RATE_TABLE *rt;
4503 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
4504 rt = sc->sc_rates[mode];
4505 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode));
4506 for (i = 0; i < rt->rateCount; i++)
4507 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i;
4508 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap));
4509 for (i = 0; i < 32; i++) {
4510 u_int8_t ix = rt->rateCodeToIndex[i];
4512 sc->sc_hwmap[i].ledon = (500 * hz) / 1000;
4513 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000;
4516 sc->sc_hwmap[i].ieeerate =
4517 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL;
4518 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD;
4519 if (rt->info[ix].shortPreamble ||
4520 rt->info[ix].phy == IEEE80211_T_OFDM)
4521 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE;
4522 /* NB: receive frames include FCS */
4523 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags |
4524 IEEE80211_RADIOTAP_F_FCS;
4525 /* setup blink rate table to avoid per-packet lookup */
4526 for (j = 0; j < N(blinkrates)-1; j++)
4527 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate)
4529 /* NB: this uses the last entry if the rate isn't found */
4530 /* XXX beware of overlow */
4531 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000;
4532 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000;
4534 sc->sc_currates = rt;
4535 sc->sc_curmode = mode;
4537 * All protection frames are transmited at 2Mb/s for
4538 * 11g, otherwise at 1Mb/s.
4539 * XXX select protection rate index from rate table.
4541 sc->sc_protrix = (mode == IEEE80211_MODE_11G ? 1 : 0);
4542 /* NB: caller is responsible for reseting rate control state */
4548 ath_printrxbuf(struct ath_buf *bf, int done)
4550 struct ath_desc *ds;
4553 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
4554 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n",
4555 i, ds, (struct ath_desc *)bf->bf_daddr + i,
4556 ds->ds_link, ds->ds_data,
4557 ds->ds_ctl0, ds->ds_ctl1,
4558 ds->ds_hw[0], ds->ds_hw[1],
4559 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!');
4564 ath_printtxbuf(struct ath_buf *bf, int done)
4566 struct ath_desc *ds;
4569 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) {
4570 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n",
4571 i, ds, (struct ath_desc *)bf->bf_daddr + i,
4572 ds->ds_link, ds->ds_data,
4573 ds->ds_ctl0, ds->ds_ctl1,
4574 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3],
4575 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!');
4578 #endif /* AR_DEBUG */
4581 ath_watchdog(struct ifnet *ifp)
4583 struct ath_softc *sc = ifp->if_softc;
4584 struct ieee80211com *ic = &sc->sc_ic;
4587 if ((ifp->if_flags & IFF_RUNNING) == 0 || sc->sc_invalid)
4589 if (sc->sc_tx_timer) {
4590 if (--sc->sc_tx_timer == 0) {
4591 if_printf(ifp, "device timeout\n");
4594 sc->sc_stats.ast_watchdog++;
4598 ieee80211_watchdog(ic);
4602 * Diagnostic interface to the HAL. This is used by various
4603 * tools to do things like retrieve register contents for
4604 * debugging. The mechanism is intentionally opaque so that
4605 * it can change frequently w/o concern for compatiblity.
4608 ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad)
4610 struct ath_hal *ah = sc->sc_ah;
4611 u_int id = ad->ad_id & ATH_DIAG_ID;
4612 void *indata = NULL;
4613 void *outdata = NULL;
4614 u_int32_t insize = ad->ad_in_size;
4615 u_int32_t outsize = ad->ad_out_size;
4618 if (ad->ad_id & ATH_DIAG_IN) {
4622 indata = malloc(insize, M_TEMP, M_NOWAIT);
4623 if (indata == NULL) {
4627 error = copyin(ad->ad_in_data, indata, insize);
4631 if (ad->ad_id & ATH_DIAG_DYN) {
4633 * Allocate a buffer for the results (otherwise the HAL
4634 * returns a pointer to a buffer where we can read the
4635 * results). Note that we depend on the HAL leaving this
4636 * pointer for us to use below in reclaiming the buffer;
4637 * may want to be more defensive.
4639 outdata = malloc(outsize, M_TEMP, M_NOWAIT);
4640 if (outdata == NULL) {
4645 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) {
4646 if (outsize < ad->ad_out_size)
4647 ad->ad_out_size = outsize;
4648 if (outdata != NULL)
4649 error = copyout(outdata, ad->ad_out_data,
4655 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL)
4656 free(indata, M_TEMP);
4657 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL)
4658 free(outdata, M_TEMP);
4663 ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
4665 #define IS_RUNNING(ifp) \
4666 ((ifp->if_flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP))
4667 struct ath_softc *sc = ifp->if_softc;
4668 struct ieee80211com *ic = &sc->sc_ic;
4669 struct ifreq *ifr = (struct ifreq *)data;
4675 if (IS_RUNNING(ifp)) {
4677 * To avoid rescanning another access point,
4678 * do not call ath_init() here. Instead,
4679 * only reflect promisc mode settings.
4682 } else if (ifp->if_flags & IFF_UP) {
4684 * Beware of being called during attach/detach
4685 * to reset promiscuous mode. In that case we
4686 * will still be marked UP but not RUNNING.
4687 * However trying to re-init the interface
4688 * is the wrong thing to do as we've already
4689 * torn down much of our state. There's
4690 * probably a better way to deal with this.
4692 if (!sc->sc_invalid && ic->ic_bss != NULL)
4693 ath_init(sc); /* XXX lose error */
4695 ath_stop_locked(ifp);
4700 * The upper layer has already installed/removed
4701 * the multicast address(es), just recalculate the
4702 * multicast filter for the card.
4704 if (ifp->if_flags & IFF_RUNNING)
4708 /* NB: embed these numbers to get a consistent view */
4709 sc->sc_stats.ast_tx_packets = ifp->if_opackets;
4710 sc->sc_stats.ast_rx_packets = ifp->if_ipackets;
4711 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic);
4714 * NB: Drop the softc lock in case of a page fault;
4715 * we'll accept any potential inconsisentcy in the
4716 * statistics. The alternative is to copy the data
4717 * to a local structure.
4719 return copyout(&sc->sc_stats,
4720 ifr->ifr_data, sizeof (sc->sc_stats));
4722 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr);
4725 error = ieee80211_ioctl(ic, cmd, data);
4726 if (error == ENETRESET) {
4727 if (IS_RUNNING(ifp) &&
4728 ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
4729 ath_init(sc); /* XXX lose error */
4732 if (error == ERESTART)
4733 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0;
4742 ath_sysctl_slottime(SYSCTL_HANDLER_ARGS)
4744 struct ath_softc *sc = arg1;
4745 u_int slottime = ath_hal_getslottime(sc->sc_ah);
4748 error = sysctl_handle_int(oidp, &slottime, 0, req);
4749 if (error || !req->newptr)
4751 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0;
4755 ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS)
4757 struct ath_softc *sc = arg1;
4758 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah);
4761 error = sysctl_handle_int(oidp, &acktimeout, 0, req);
4762 if (error || !req->newptr)
4764 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0;
4768 ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS)
4770 struct ath_softc *sc = arg1;
4771 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah);
4774 error = sysctl_handle_int(oidp, &ctstimeout, 0, req);
4775 if (error || !req->newptr)
4777 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0;
4781 ath_sysctl_softled(SYSCTL_HANDLER_ARGS)
4783 struct ath_softc *sc = arg1;
4784 int softled = sc->sc_softled;
4787 error = sysctl_handle_int(oidp, &softled, 0, req);
4788 if (error || !req->newptr)
4790 softled = (softled != 0);
4791 if (softled != sc->sc_softled) {
4793 /* NB: handle any sc_ledpin change */
4794 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin);
4795 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin,
4798 sc->sc_softled = softled;
4804 ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS)
4806 struct ath_softc *sc = arg1;
4807 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah);
4810 error = sysctl_handle_int(oidp, &defantenna, 0, req);
4811 if (!error && req->newptr)
4812 ath_hal_setdefantenna(sc->sc_ah, defantenna);
4817 ath_sysctl_diversity(SYSCTL_HANDLER_ARGS)
4819 struct ath_softc *sc = arg1;
4820 u_int diversity = sc->sc_diversity;
4823 error = sysctl_handle_int(oidp, &diversity, 0, req);
4824 if (error || !req->newptr)
4826 sc->sc_diversity = diversity;
4827 return !ath_hal_setdiversity(sc->sc_ah, diversity) ? EINVAL : 0;
4831 ath_sysctl_diag(SYSCTL_HANDLER_ARGS)
4833 struct ath_softc *sc = arg1;
4837 if (!ath_hal_getdiag(sc->sc_ah, &diag))
4839 error = sysctl_handle_int(oidp, &diag, 0, req);
4840 if (error || !req->newptr)
4842 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0;
4846 ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS)
4848 struct ath_softc *sc = arg1;
4849 struct ifnet *ifp = sc->sc_ifp;
4853 ath_hal_gettpscale(sc->sc_ah, &scale);
4854 error = sysctl_handle_int(oidp, &scale, 0, req);
4855 if (error || !req->newptr)
4857 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : ath_reset(ifp);
4861 ath_sysctl_tpc(SYSCTL_HANDLER_ARGS)
4863 struct ath_softc *sc = arg1;
4864 u_int tpc = ath_hal_gettpc(sc->sc_ah);
4867 error = sysctl_handle_int(oidp, &tpc, 0, req);
4868 if (error || !req->newptr)
4870 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0;
4874 ath_sysctlattach(struct ath_softc *sc)
4876 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
4877 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
4879 ath_hal_getcountrycode(sc->sc_ah, &sc->sc_countrycode);
4880 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4881 "countrycode", CTLFLAG_RD, &sc->sc_countrycode, 0,
4882 "EEPROM country code");
4883 ath_hal_getregdomain(sc->sc_ah, &sc->sc_regdomain);
4884 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4885 "regdomain", CTLFLAG_RD, &sc->sc_regdomain, 0,
4886 "EEPROM regdomain code");
4887 sc->sc_debug = ath_debug;
4888 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4889 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
4890 "control debugging printfs");
4892 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4893 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4894 ath_sysctl_slottime, "I", "802.11 slot time (us)");
4895 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4896 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4897 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)");
4898 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4899 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4900 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)");
4901 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4902 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4903 ath_sysctl_softled, "I", "enable/disable software LED support");
4904 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4905 "ledpin", CTLFLAG_RW, &sc->sc_ledpin, 0,
4906 "GPIO pin connected to LED");
4907 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4908 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0,
4909 "setting to turn LED on");
4910 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4911 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0,
4912 "idle time for inactivity LED (ticks)");
4913 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4914 "txantenna", CTLFLAG_RW, &sc->sc_txantenna, 0,
4915 "tx antenna (0=auto)");
4916 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4917 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4918 ath_sysctl_rxantenna, "I", "default/rx antenna");
4919 if (sc->sc_hasdiversity)
4920 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4921 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4922 ath_sysctl_diversity, "I", "antenna diversity");
4923 sc->sc_txintrperiod = ATH_TXINTR_PERIOD;
4924 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4925 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0,
4926 "tx descriptor batching");
4927 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4928 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4929 ath_sysctl_diag, "I", "h/w diagnostic control");
4930 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4931 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4932 ath_sysctl_tpscale, "I", "tx power scaling");
4934 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
4935 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0,
4936 ath_sysctl_tpc, "I", "enable/disable per-packet TPC");
4940 ath_bpfattach(struct ath_softc *sc)
4942 struct ifnet *ifp = sc->sc_ifp;
4944 bpfattach2(ifp, DLT_IEEE802_11_RADIO,
4945 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
4948 * Initialize constant fields.
4949 * XXX make header lengths a multiple of 32-bits so subsequent
4950 * headers are properly aligned; this is a kludge to keep
4951 * certain applications happy.
4953 * NB: the channel is setup each time we transition to the
4954 * RUN state to avoid filling it in for each frame.
4956 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t));
4957 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
4958 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT);
4960 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t));
4961 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
4962 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT);
4966 * Announce various information on device/driver attach.
4969 ath_announce(struct ath_softc *sc)
4971 #define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B)
4972 struct ifnet *ifp = sc->sc_ifp;
4973 struct ath_hal *ah = sc->sc_ah;
4976 if_printf(ifp, "mac %d.%d phy %d.%d",
4977 ah->ah_macVersion, ah->ah_macRev,
4978 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf);
4980 * Print radio revision(s). We check the wireless modes
4981 * to avoid falsely printing revs for inoperable parts.
4982 * Dual-band radio revs are returned in the 5Ghz rev number.
4984 ath_hal_getcountrycode(ah, &cc);
4985 modes = ath_hal_getwirelessmodes(ah, cc);
4986 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) {
4987 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev)
4988 printf(" 5ghz radio %d.%d 2ghz radio %d.%d",
4989 ah->ah_analog5GhzRev >> 4,
4990 ah->ah_analog5GhzRev & 0xf,
4991 ah->ah_analog2GhzRev >> 4,
4992 ah->ah_analog2GhzRev & 0xf);
4994 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
4995 ah->ah_analog5GhzRev & 0xf);
4997 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4,
4998 ah->ah_analog5GhzRev & 0xf);
5002 for (i = 0; i <= WME_AC_VO; i++) {
5003 struct ath_txq *txq = sc->sc_ac2q[i];
5004 if_printf(ifp, "Use hw queue %u for %s traffic\n",
5005 txq->axq_qnum, ieee80211_wme_acnames[i]);
5007 if_printf(ifp, "Use hw queue %u for CAB traffic\n",
5008 sc->sc_cabq->axq_qnum);
5009 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq);
5011 #undef HAL_MODE_DUALBAND