2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
15 * redistribution must be conditioned upon including a substantially
16 * similar Disclaimer requirement for further binary redistribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGES.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 * Driver for the Atheros Wireless LAN controller.
38 * This software is derived from work of Atsushi Onoe; his contribution
39 * is greatly appreciated.
45 * This is needed for register operations which are performed
46 * by the driver - eg, calls to ath_hal_gettsf32().
48 * It's also required for any AH_DEBUG checks in here, eg the
49 * module dependencies.
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/sysctl.h>
58 #include <sys/malloc.h>
60 #include <sys/mutex.h>
61 #include <sys/kernel.h>
62 #include <sys/socket.h>
63 #include <sys/sockio.h>
64 #include <sys/errno.h>
65 #include <sys/callout.h>
67 #include <sys/endian.h>
68 #include <sys/kthread.h>
69 #include <sys/taskqueue.h>
71 #include <sys/module.h>
73 #include <sys/smp.h> /* for mp_ncpus */
75 #include <machine/bus.h>
78 #include <net/if_var.h>
79 #include <net/if_dl.h>
80 #include <net/if_media.h>
81 #include <net/if_types.h>
82 #include <net/if_arp.h>
83 #include <net/ethernet.h>
84 #include <net/if_llc.h>
86 #include <net80211/ieee80211_var.h>
87 #include <net80211/ieee80211_regdomain.h>
88 #ifdef IEEE80211_SUPPORT_SUPERG
89 #include <net80211/ieee80211_superg.h>
95 #include <netinet/in.h>
96 #include <netinet/if_ether.h>
99 #include <dev/ath/if_athvar.h>
101 #include <dev/ath/if_ath_debug.h>
102 #include <dev/ath/if_ath_misc.h>
103 #include <dev/ath/if_ath_tx.h>
104 #include <dev/ath/if_ath_beacon.h>
107 #include <dev/ath/ath_tx99/ath_tx99.h>
111 * Setup a h/w transmit queue for beacons.
114 ath_beaconq_setup(struct ath_softc *sc)
116 struct ath_hal *ah = sc->sc_ah;
119 memset(&qi, 0, sizeof(qi));
120 qi.tqi_aifs = HAL_TXQ_USEDEFAULT;
121 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT;
122 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT;
123 /* NB: for dynamic turbo, don't enable any other interrupts */
124 qi.tqi_qflags = HAL_TXQ_TXDESCINT_ENABLE;
126 qi.tqi_qflags |= HAL_TXQ_TXOKINT_ENABLE |
127 HAL_TXQ_TXERRINT_ENABLE;
129 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi);
133 * Setup the transmit queue parameters for the beacon queue.
136 ath_beaconq_config(struct ath_softc *sc)
138 #define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1)
139 struct ieee80211com *ic = &sc->sc_ic;
140 struct ath_hal *ah = sc->sc_ah;
143 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi);
144 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
145 ic->ic_opmode == IEEE80211_M_MBSS) {
147 * Always burst out beacon and CAB traffic.
149 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT;
150 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT;
151 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT;
153 struct chanAccParams chp;
154 struct wmeParams *wmep;
156 ieee80211_wme_ic_getparams(ic, &chp);
157 wmep = &chp.cap_wmeParams[WME_AC_BE];
160 * Adhoc mode; important thing is to use 2x cwmin.
162 qi.tqi_aifs = wmep->wmep_aifsn;
163 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin);
164 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax);
167 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) {
168 device_printf(sc->sc_dev, "unable to update parameters for "
169 "beacon hardware queue!\n");
172 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */
175 #undef ATH_EXPONENT_TO_VALUE
179 * Allocate and setup an initial beacon frame.
182 ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni)
184 struct ieee80211vap *vap = ni->ni_vap;
185 struct ath_vap *avp = ATH_VAP(vap);
191 DPRINTF(sc, ATH_DEBUG_NODE, "%s: bf_m=%p, bf_node=%p\n",
192 __func__, bf->bf_m, bf->bf_node);
193 if (bf->bf_m != NULL) {
194 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
198 if (bf->bf_node != NULL) {
199 ieee80211_free_node(bf->bf_node);
204 * NB: the beacon data buffer must be 32-bit aligned;
205 * we assume the mbuf routines will return us something
206 * with this alignment (perhaps should assert).
208 m = ieee80211_beacon_alloc(ni);
210 device_printf(sc->sc_dev, "%s: cannot get mbuf\n", __func__);
211 sc->sc_stats.ast_be_nombuf++;
214 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
215 bf->bf_segs, &bf->bf_nseg,
218 device_printf(sc->sc_dev,
219 "%s: cannot map mbuf, bus_dmamap_load_mbuf_sg returns %d\n",
226 * Calculate a TSF adjustment factor required for staggered
227 * beacons. Note that we assume the format of the beacon
228 * frame leaves the tstamp field immediately following the
231 if (sc->sc_stagbeacons && avp->av_bslot > 0) {
233 struct ieee80211_frame *wh;
236 * The beacon interval is in TU's; the TSF is in usecs.
237 * We figure out how many TU's to add to align the timestamp
238 * then convert to TSF units and handle byte swapping before
239 * inserting it in the frame. The hardware will then add this
240 * each time a beacon frame is sent. Note that we align vap's
241 * 1..N and leave vap 0 untouched. This means vap 0 has a
242 * timestamp in one beacon interval while the others get a
243 * timstamp aligned to the next interval.
245 tsfadjust = ni->ni_intval *
246 (ATH_BCBUF - avp->av_bslot) / ATH_BCBUF;
247 tsfadjust = htole64(tsfadjust << 10); /* TU -> TSF */
249 DPRINTF(sc, ATH_DEBUG_BEACON,
250 "%s: %s beacons bslot %d intval %u tsfadjust %llu\n",
251 __func__, sc->sc_stagbeacons ? "stagger" : "burst",
252 avp->av_bslot, ni->ni_intval,
253 (long long unsigned) le64toh(tsfadjust));
255 wh = mtod(m, struct ieee80211_frame *);
256 memcpy(&wh[1], &tsfadjust, sizeof(tsfadjust));
259 bf->bf_node = ieee80211_ref_node(ni);
265 * Setup the beacon frame for transmit.
268 ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf)
270 #define USE_SHPREAMBLE(_ic) \
271 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\
272 == IEEE80211_F_SHPREAMBLE)
273 struct ieee80211_node *ni = bf->bf_node;
274 struct ieee80211com *ic = ni->ni_ic;
275 struct mbuf *m = bf->bf_m;
276 struct ath_hal *ah = sc->sc_ah;
279 const HAL_RATE_TABLE *rt;
281 HAL_DMA_ADDR bufAddrList[4];
282 uint32_t segLenList[4];
283 HAL_11N_RATE_SERIES rc[4];
285 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: m %p len %u\n",
286 __func__, m, m->m_len);
288 /* setup descriptors */
293 flags = HAL_TXDESC_NOACK;
294 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) {
295 /* self-linked descriptor */
296 ath_hal_settxdesclink(sc->sc_ah, ds, bf->bf_daddr);
297 flags |= HAL_TXDESC_VEOL;
299 * Let hardware handle antenna switching.
301 antenna = sc->sc_txantenna;
303 ath_hal_settxdesclink(sc->sc_ah, ds, 0);
305 * Switch antenna every 4 beacons.
306 * XXX assumes two antenna
308 if (sc->sc_txantenna != 0)
309 antenna = sc->sc_txantenna;
310 else if (sc->sc_stagbeacons && sc->sc_nbcnvaps != 0)
311 antenna = ((sc->sc_stats.ast_be_xmit / sc->sc_nbcnvaps) & 4 ? 2 : 1);
313 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1);
316 KASSERT(bf->bf_nseg == 1,
317 ("multi-segment beacon frame; nseg %u", bf->bf_nseg));
320 * Calculate rate code.
321 * XXX everything at min xmit rate
324 rt = sc->sc_currates;
325 rate = rt->info[rix].rateCode;
326 if (USE_SHPREAMBLE(ic))
327 rate |= rt->info[rix].shortPreamble;
328 ath_hal_setuptxdesc(ah, ds
329 , m->m_len + IEEE80211_CRC_LEN /* frame length */
330 , sizeof(struct ieee80211_frame)/* header length */
331 , HAL_PKT_TYPE_BEACON /* Atheros packet type */
332 , ieee80211_get_node_txpower(ni) /* txpower XXX */
333 , rate, 1 /* series 0 rate/tries */
334 , HAL_TXKEYIX_INVALID /* no encryption */
335 , antenna /* antenna mode */
336 , flags /* no ack, veol for beacons */
337 , 0 /* rts/cts rate */
338 , 0 /* rts/cts duration */
342 * The EDMA HAL currently assumes that _all_ rate control
343 * settings are done in ath_hal_set11nratescenario(), rather
344 * than in ath_hal_setuptxdesc().
347 memset(&rc, 0, sizeof(rc));
349 rc[0].ChSel = sc->sc_txchainmask;
351 rc[0].Rate = rt->info[rix].rateCode;
352 rc[0].RateIndex = rix;
353 rc[0].tx_power_cap = 0x3f;
355 ath_hal_computetxtime(ah, rt, roundup(m->m_len, 4),
357 ath_hal_set11nratescenario(ah, ds, 0, 0, rc, 4, flags);
360 /* NB: beacon's BufLen must be a multiple of 4 bytes */
361 segLenList[0] = roundup(m->m_len, 4);
362 segLenList[1] = segLenList[2] = segLenList[3] = 0;
363 bufAddrList[0] = bf->bf_segs[0].ds_addr;
364 bufAddrList[1] = bufAddrList[2] = bufAddrList[3] = 0;
365 ath_hal_filltxdesc(ah, ds
368 , 0 /* XXX desc id */
369 , sc->sc_bhalq /* hardware TXQ */
370 , AH_TRUE /* first segment */
371 , AH_TRUE /* last segment */
372 , ds /* first descriptor */
377 #undef USE_SHPREAMBLE
381 ath_beacon_update(struct ieee80211vap *vap, int item)
383 struct ieee80211_beacon_offsets *bo = &vap->iv_bcn_off;
385 setbit(bo->bo_flags, item);
389 * Handle a beacon miss.
392 ath_beacon_miss(struct ath_softc *sc)
394 HAL_SURVEY_SAMPLE hs;
398 bzero(&hs, sizeof(hs));
400 ret = ath_hal_get_mib_cycle_counts(sc->sc_ah, &hs);
402 if (ath_hal_gethangstate(sc->sc_ah, 0xffff, &hangs) && hangs != 0) {
403 DPRINTF(sc, ATH_DEBUG_BEACON,
410 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_MISSED_BEACON))
411 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_MISSED_BEACON, 0, NULL);
414 DPRINTF(sc, ATH_DEBUG_BEACON,
415 "%s: valid=%d, txbusy=%u, rxbusy=%u, chanbusy=%u, "
416 "extchanbusy=%u, cyclecount=%u\n",
427 * Transmit a beacon frame at SWBA. Dynamic updates to the
428 * frame contents are done as needed and the slot time is
429 * also adjusted based on current state.
432 ath_beacon_proc(void *arg, int pending)
434 struct ath_softc *sc = arg;
435 struct ath_hal *ah = sc->sc_ah;
436 struct ieee80211vap *vap;
441 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n",
444 * Check if the previous beacon has gone out. If
445 * not don't try to post another, skip this period
446 * and wait for the next. Missed beacons indicate
447 * a problem and should not occur. If we miss too
448 * many consecutive beacons reset the device.
450 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) {
452 sc->sc_stats.ast_be_missed++;
454 DPRINTF(sc, ATH_DEBUG_BEACON,
455 "%s: missed %u consecutive beacons\n",
456 __func__, sc->sc_bmisscount);
457 if (sc->sc_bmisscount >= ath_bstuck_threshold)
458 taskqueue_enqueue(sc->sc_tq, &sc->sc_bstucktask);
461 if (sc->sc_bmisscount != 0) {
462 DPRINTF(sc, ATH_DEBUG_BEACON,
463 "%s: resume beacon xmit after %u misses\n",
464 __func__, sc->sc_bmisscount);
465 sc->sc_bmisscount = 0;
467 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_RESUME_BEACON))
468 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_RESUME_BEACON, 0, NULL);
472 if (sc->sc_stagbeacons) { /* staggered beacons */
473 struct ieee80211com *ic = &sc->sc_ic;
476 tsftu = ath_hal_gettsf32(ah) >> 10;
478 slot = ((tsftu % ic->ic_lintval) * ATH_BCBUF) / ic->ic_lintval;
479 vap = sc->sc_bslot[(slot+1) % ATH_BCBUF];
481 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
482 bf = ath_beacon_generate(sc, vap);
484 bfaddr = bf->bf_daddr;
486 } else { /* burst'd beacons */
487 uint32_t *bflink = &bfaddr;
489 for (slot = 0; slot < ATH_BCBUF; slot++) {
490 vap = sc->sc_bslot[slot];
491 if (vap != NULL && vap->iv_state >= IEEE80211_S_RUN) {
492 bf = ath_beacon_generate(sc, vap);
494 * XXX TODO: this should use settxdesclinkptr()
495 * otherwise it won't work for EDMA chipsets!
498 /* XXX should do this using the ds */
499 *bflink = bf->bf_daddr;
500 ath_hal_gettxdesclinkptr(sc->sc_ah,
501 bf->bf_desc, &bflink);
506 * XXX TODO: this should use settxdesclinkptr()
507 * otherwise it won't work for EDMA chipsets!
509 *bflink = 0; /* terminate list */
513 * Handle slot time change when a non-ERP station joins/leaves
514 * an 11g network. The 802.11 layer notifies us via callback,
515 * we mark updateslot, then wait one beacon before effecting
516 * the change. This gives associated stations at least one
517 * beacon interval to note the state change.
520 if (sc->sc_updateslot == UPDATE) {
521 sc->sc_updateslot = COMMIT; /* commit next beacon */
522 sc->sc_slotupdate = slot;
523 } else if (sc->sc_updateslot == COMMIT && sc->sc_slotupdate == slot)
524 ath_setslottime(sc); /* commit change to h/w */
527 * Check recent per-antenna transmit statistics and flip
528 * the default antenna if noticeably more frames went out
529 * on the non-default antenna.
530 * XXX assumes 2 anntenae
532 if (!sc->sc_diversity && (!sc->sc_stagbeacons || slot == 0)) {
533 otherant = sc->sc_defant & 1 ? 2 : 1;
534 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2)
535 ath_setdefantenna(sc, otherant);
536 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0;
539 /* Program the CABQ with the contents of the CABQ txq and start it */
540 ATH_TXQ_LOCK(sc->sc_cabq);
541 ath_beacon_cabq_start(sc);
542 ATH_TXQ_UNLOCK(sc->sc_cabq);
544 /* Program the new beacon frame if we have one for this interval */
547 * Stop any current dma and put the new frame on the queue.
548 * This should never fail since we check above that no frames
549 * are still pending on the queue.
551 if (! sc->sc_isedma) {
552 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) {
553 DPRINTF(sc, ATH_DEBUG_ANY,
554 "%s: beacon queue %u did not stop?\n",
555 __func__, sc->sc_bhalq);
558 /* NB: cabq traffic should already be queued and primed */
560 ath_hal_puttxbuf(ah, sc->sc_bhalq, bfaddr);
561 ath_hal_txstart(ah, sc->sc_bhalq);
563 sc->sc_stats.ast_be_xmit++;
568 ath_beacon_cabq_start_edma(struct ath_softc *sc)
570 struct ath_buf *bf, *bf_last;
571 struct ath_txq *cabq = sc->sc_cabq;
577 ATH_TXQ_LOCK_ASSERT(cabq);
579 if (TAILQ_EMPTY(&cabq->axq_q))
581 bf = TAILQ_FIRST(&cabq->axq_q);
582 bf_last = TAILQ_LAST(&cabq->axq_q, axq_q_s);
585 * This is a dirty, dirty hack to push the contents of
586 * the cabq staging queue into the FIFO.
588 * This ideally should live in the EDMA code file
589 * and only push things into the CABQ if there's a FIFO
592 * We can't treat this like a normal TX queue because
593 * in the case of multi-VAP traffic, we may have to flush
594 * the CABQ each new (staggered) beacon that goes out.
595 * But for non-staggered beacons, we could in theory
596 * handle multicast traffic for all VAPs in one FIFO
597 * push. Just keep all of this in mind if you're wondering
598 * how to correctly/better handle multi-VAP CABQ traffic
603 * Is the CABQ FIFO free? If not, complain loudly and
604 * don't queue anything. Maybe we'll flush the CABQ
605 * traffic, maybe we won't. But that'll happen next
608 if (cabq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) {
609 device_printf(sc->sc_dev,
610 "%s: Q%d: CAB FIFO queue=%d?\n",
613 cabq->axq_fifo_depth);
618 * Ok, so here's the gymnastics reqiured to make this
623 * Tag the first/last buffer appropriately.
625 bf->bf_flags |= ATH_BUF_FIFOPTR;
626 bf_last->bf_flags |= ATH_BUF_FIFOEND;
630 TAILQ_FOREACH(bfi, &cabq->axq_q, bf_list) {
631 ath_printtxbuf(sc, bf, cabq->axq_qnum, i, 0);
637 * We now need to push this set of frames onto the tail
638 * of the FIFO queue. We don't adjust the aggregate
639 * count, only the queue depth counter(s).
640 * We also need to blank the link pointer now.
642 TAILQ_CONCAT(&cabq->fifo.axq_q, &cabq->axq_q, bf_list);
643 cabq->axq_link = NULL;
644 cabq->fifo.axq_depth += cabq->axq_depth;
647 /* Bump FIFO queue */
648 cabq->axq_fifo_depth++;
650 /* Push the first entry into the hardware */
651 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr);
652 cabq->axq_flags |= ATH_TXQ_PUTRUNNING;
654 /* NB: gated by beacon so safe to start here */
655 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum);
660 ath_beacon_cabq_start_legacy(struct ath_softc *sc)
663 struct ath_txq *cabq = sc->sc_cabq;
665 ATH_TXQ_LOCK_ASSERT(cabq);
666 if (TAILQ_EMPTY(&cabq->axq_q))
668 bf = TAILQ_FIRST(&cabq->axq_q);
670 /* Push the first entry into the hardware */
671 ath_hal_puttxbuf(sc->sc_ah, cabq->axq_qnum, bf->bf_daddr);
672 cabq->axq_flags |= ATH_TXQ_PUTRUNNING;
674 /* NB: gated by beacon so safe to start here */
675 ath_hal_txstart(sc->sc_ah, cabq->axq_qnum);
679 * Start CABQ transmission - this assumes that all frames are prepped
680 * and ready in the CABQ.
683 ath_beacon_cabq_start(struct ath_softc *sc)
685 struct ath_txq *cabq = sc->sc_cabq;
687 ATH_TXQ_LOCK_ASSERT(cabq);
689 if (TAILQ_EMPTY(&cabq->axq_q))
693 ath_beacon_cabq_start_edma(sc);
695 ath_beacon_cabq_start_legacy(sc);
699 ath_beacon_generate(struct ath_softc *sc, struct ieee80211vap *vap)
701 struct ath_vap *avp = ATH_VAP(vap);
702 struct ath_txq *cabq = sc->sc_cabq;
707 KASSERT(vap->iv_state >= IEEE80211_S_RUN,
708 ("not running, state %d", vap->iv_state));
709 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
712 * Update dynamic beacon contents. If this returns
713 * non-zero then we need to remap the memory because
714 * the beacon frame changed size (probably because
715 * of the TIM bitmap).
719 /* XXX lock mcastq? */
720 nmcastq = avp->av_mcastq.axq_depth;
722 if (ieee80211_beacon_update(bf->bf_node, m, nmcastq)) {
723 /* XXX too conservative? */
724 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
725 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
726 bf->bf_segs, &bf->bf_nseg,
729 if_printf(vap->iv_ifp,
730 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
735 if ((vap->iv_bcn_off.bo_tim[4] & 1) && cabq->axq_depth) {
736 DPRINTF(sc, ATH_DEBUG_BEACON,
737 "%s: cabq did not drain, mcastq %u cabq %u\n",
738 __func__, nmcastq, cabq->axq_depth);
739 sc->sc_stats.ast_cabq_busy++;
740 if (sc->sc_nvaps > 1 && sc->sc_stagbeacons) {
742 * CABQ traffic from a previous vap is still pending.
743 * We must drain the q before this beacon frame goes
744 * out as otherwise this vap's stations will get cab
745 * frames from a different vap.
746 * XXX could be slow causing us to miss DBA
749 * XXX TODO: this doesn't stop CABQ DMA - it assumes
750 * that since we're about to transmit a beacon, we've
751 * already stopped transmitting on the CABQ. But this
752 * doesn't at all mean that the CABQ DMA QCU will
753 * accept a new TXDP! So what, should we do a DMA
754 * stop? What if it fails?
756 * More thought is required here.
759 * XXX can we even stop TX DMA here? Check what the
760 * reference driver does for cabq for beacons, given
761 * that stopping TX requires RX is paused.
763 ath_tx_draintxq(sc, cabq);
766 ath_beacon_setup(sc, bf);
767 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
770 * XXX TODO: tie into net80211 for quiet time IE update and program
771 * local AP timer if we require it. The process of updating the
772 * beacon will also update the IE with the relevant counters.
776 * Enable the CAB queue before the beacon queue to
777 * insure cab frames are triggered by this beacon.
779 if (vap->iv_bcn_off.bo_tim[4] & 1) {
780 /* NB: only at DTIM */
781 ATH_TXQ_LOCK(&avp->av_mcastq);
783 struct ath_buf *bfm, *bfc_last;
786 * Move frames from the s/w mcast q to the h/w cab q.
788 * XXX TODO: if we chain together multiple VAPs
789 * worth of CABQ traffic, should we keep the
790 * MORE data bit set on the last frame of each
791 * intermediary VAP (ie, only clear the MORE
792 * bit of the last frame on the last vap?)
794 bfm = TAILQ_FIRST(&avp->av_mcastq.axq_q);
798 * If there's already a frame on the CABQ, we
799 * need to link to the end of the last frame.
800 * We can't use axq_link here because
801 * EDMA descriptors require some recalculation
802 * (checksum) to occur.
804 bfc_last = ATH_TXQ_LAST(cabq, axq_q_s);
805 if (bfc_last != NULL) {
806 ath_hal_settxdesclink(sc->sc_ah,
810 ath_txqmove(cabq, &avp->av_mcastq);
811 ATH_TXQ_UNLOCK(cabq);
813 * XXX not entirely accurate, in case a mcast
814 * queue frame arrived before we grabbed the TX
817 sc->sc_stats.ast_cabq_xmit += nmcastq;
819 ATH_TXQ_UNLOCK(&avp->av_mcastq);
825 ath_beacon_start_adhoc(struct ath_softc *sc, struct ieee80211vap *vap)
827 struct ath_vap *avp = ATH_VAP(vap);
828 struct ath_hal *ah = sc->sc_ah;
833 KASSERT(avp->av_bcbuf != NULL, ("no beacon buffer"));
836 * Update dynamic beacon contents. If this returns
837 * non-zero then we need to remap the memory because
838 * the beacon frame changed size (probably because
839 * of the TIM bitmap).
843 if (ieee80211_beacon_update(bf->bf_node, m, 0)) {
844 /* XXX too conservative? */
845 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
846 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m,
847 bf->bf_segs, &bf->bf_nseg,
850 if_printf(vap->iv_ifp,
851 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n",
856 ath_beacon_setup(sc, bf);
857 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE);
859 /* NB: caller is known to have already stopped tx dma */
860 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr);
861 ath_hal_txstart(ah, sc->sc_bhalq);
865 * Reclaim beacon resources and return buffer to the pool.
868 ath_beacon_return(struct ath_softc *sc, struct ath_buf *bf)
871 DPRINTF(sc, ATH_DEBUG_NODE, "%s: free bf=%p, bf_m=%p, bf_node=%p\n",
872 __func__, bf, bf->bf_m, bf->bf_node);
873 if (bf->bf_m != NULL) {
874 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
878 if (bf->bf_node != NULL) {
879 ieee80211_free_node(bf->bf_node);
882 TAILQ_INSERT_TAIL(&sc->sc_bbuf, bf, bf_list);
886 * Reclaim beacon resources.
889 ath_beacon_free(struct ath_softc *sc)
893 TAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) {
894 DPRINTF(sc, ATH_DEBUG_NODE,
895 "%s: free bf=%p, bf_m=%p, bf_node=%p\n",
896 __func__, bf, bf->bf_m, bf->bf_node);
897 if (bf->bf_m != NULL) {
898 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
902 if (bf->bf_node != NULL) {
903 ieee80211_free_node(bf->bf_node);
910 * Configure the beacon and sleep timers.
912 * When operating as an AP this resets the TSF and sets
913 * up the hardware to notify us when we need to issue beacons.
915 * When operating in station mode this sets up the beacon
916 * timers according to the timestamp of the last received
917 * beacon and the current TSF, configures PCF and DTIM
918 * handling, programs the sleep registers so the hardware
919 * will wakeup in time to receive beacons, and configures
920 * the beacon miss handling so we'll receive a BMISS
921 * interrupt when we stop seeing beacons from the AP
922 * we've associated with.
925 ath_beacon_config(struct ath_softc *sc, struct ieee80211vap *vap)
927 #define TSF_TO_TU(_h,_l) \
928 ((((u_int32_t)(_h)) << 22) | (((u_int32_t)(_l)) >> 10))
930 struct ath_hal *ah = sc->sc_ah;
932 struct ieee80211com *ic = &sc->sc_ic;
933 struct ieee80211_node *ni;
934 u_int32_t nexttbtt, intval, tsftu;
935 u_int32_t nexttbtt_u8, intval_u8;
936 u_int64_t tsf, tsf_beacon;
939 vap = TAILQ_FIRST(&ic->ic_vaps); /* XXX */
941 * Just ensure that we aren't being called when the last
945 device_printf(sc->sc_dev, "%s: called with no VAPs\n",
950 /* Now that we have a vap, we can do this bit */
953 ni = ieee80211_ref_node(vap->iv_bss);
956 ath_power_set_power_state(sc, HAL_PM_AWAKE);
959 /* Always clear the quiet IE timers; let the next update program them */
960 ath_hal_set_quiet(ah, 0, 0, 0, HAL_QUIET_DISABLE);
961 memset(&avp->quiet_ie, 0, sizeof(avp->quiet_ie));
963 /* extract tstamp from last beacon and convert to TU */
964 nexttbtt = TSF_TO_TU(le32dec(ni->ni_tstamp.data + 4),
965 le32dec(ni->ni_tstamp.data));
967 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32;
968 tsf_beacon |= le32dec(ni->ni_tstamp.data);
970 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
971 ic->ic_opmode == IEEE80211_M_MBSS) {
973 * For multi-bss ap/mesh support beacons are either staggered
974 * evenly over N slots or burst together. For the former
975 * arrange for the SWBA to be delivered for each slot.
976 * Slots that are not occupied will generate nothing.
978 /* NB: the beacon interval is kept internally in TU's */
979 intval = ni->ni_intval & HAL_BEACON_PERIOD;
980 if (sc->sc_stagbeacons)
983 /* NB: the beacon interval is kept internally in TU's */
984 intval = ni->ni_intval & HAL_BEACON_PERIOD;
988 * Note: rounding up to the next intval can cause problems with
989 * bad APs when we're in powersave mode.
991 * In STA mode with powersave enabled, beacons are only received
992 * whenever the beacon timer fires to wake up the hardware.
993 * Now, if this is rounded up to the next intval, it assumes
994 * that the AP has started transmitting beacons at TSF values that
995 * are multiples of intval, versus say being 25 TU off.
997 * The specification (802.11-2012 10.1.3.2 - Beacon Generation in
998 * Infrastructure Networks) requires APs be beaconing at a
999 * mutiple of intval. So, if bintval=100, then we shouldn't
1000 * get beacons at intervals other than around multiples of 100.
1002 if (nexttbtt == 0) /* e.g. for ap mode */
1005 nexttbtt = roundup(nexttbtt, intval);
1007 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n",
1008 __func__, nexttbtt, intval, ni->ni_intval);
1009 if (ic->ic_opmode == IEEE80211_M_STA && !sc->sc_swbmiss) {
1010 HAL_BEACON_STATE bs;
1011 int dtimperiod, dtimcount;
1012 int cfpperiod, cfpcount;
1015 * Setup dtim and cfp parameters according to
1016 * last beacon we received (which may be none).
1018 dtimperiod = ni->ni_dtim_period;
1019 if (dtimperiod <= 0) /* NB: 0 if not known */
1021 dtimcount = ni->ni_dtim_count;
1022 if (dtimcount >= dtimperiod) /* NB: sanity check */
1023 dtimcount = 0; /* XXX? */
1024 cfpperiod = 1; /* NB: no PCF support yet */
1027 * Pull nexttbtt forward to reflect the current
1028 * TSF and calculate dtim+cfp state for the result.
1030 tsf = ath_hal_gettsf64(ah);
1031 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
1033 DPRINTF(sc, ATH_DEBUG_BEACON,
1034 "%s: beacon tsf=%llu, hw tsf=%llu, nexttbtt=%u, tsftu=%u\n",
1036 (unsigned long long) tsf_beacon,
1037 (unsigned long long) tsf,
1040 DPRINTF(sc, ATH_DEBUG_BEACON,
1041 "%s: beacon tsf=%llu, hw tsf=%llu, tsf delta=%lld\n",
1043 (unsigned long long) tsf_beacon,
1044 (unsigned long long) tsf,
1046 (long long) tsf_beacon);
1048 DPRINTF(sc, ATH_DEBUG_BEACON,
1049 "%s: nexttbtt=%llu, beacon tsf delta=%lld\n",
1051 (unsigned long long) nexttbtt,
1052 (long long) ((long long) nexttbtt * 1024LL) - (long long) tsf_beacon);
1056 if (nexttbtt > tsftu) {
1057 uint32_t countdiff, oldtbtt, remainder;
1060 remainder = (nexttbtt - tsftu) % intval;
1061 nexttbtt = tsftu + remainder;
1063 countdiff = (oldtbtt - nexttbtt) / intval % dtimperiod;
1064 if (dtimcount > countdiff) {
1065 dtimcount -= countdiff;
1067 dtimcount += dtimperiod - countdiff;
1069 } else { //nexttbtt <= tsftu
1070 uint32_t countdiff, oldtbtt, remainder;
1073 remainder = (tsftu - nexttbtt) % intval;
1074 nexttbtt = tsftu - remainder + intval;
1075 countdiff = (nexttbtt - oldtbtt) / intval % dtimperiod;
1076 if (dtimcount > countdiff) {
1077 dtimcount -= countdiff;
1079 dtimcount += dtimperiod - countdiff;
1083 DPRINTF(sc, ATH_DEBUG_BEACON,
1084 "%s: adj nexttbtt=%llu, rx tsf delta=%lld\n",
1086 (unsigned long long) nexttbtt,
1087 (long long) ((long long)nexttbtt * 1024LL) - (long long)tsf);
1089 memset(&bs, 0, sizeof(bs));
1090 bs.bs_intval = intval;
1091 bs.bs_nexttbtt = nexttbtt;
1092 bs.bs_dtimperiod = dtimperiod*intval;
1093 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval;
1094 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod;
1095 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod;
1096 bs.bs_cfpmaxduration = 0;
1099 * The 802.11 layer records the offset to the DTIM
1100 * bitmap while receiving beacons; use it here to
1101 * enable h/w detection of our AID being marked in
1102 * the bitmap vector (to indicate frames for us are
1103 * pending at the AP).
1104 * XXX do DTIM handling in s/w to WAR old h/w bugs
1105 * XXX enable based on h/w rev for newer chips
1107 bs.bs_timoffset = ni->ni_timoff;
1110 * Calculate the number of consecutive beacons to miss
1111 * before taking a BMISS interrupt.
1112 * Note that we clamp the result to at most 10 beacons.
1114 bs.bs_bmissthreshold = vap->iv_bmissthreshold;
1115 if (bs.bs_bmissthreshold > 10)
1116 bs.bs_bmissthreshold = 10;
1117 else if (bs.bs_bmissthreshold <= 0)
1118 bs.bs_bmissthreshold = 1;
1121 * Calculate sleep duration. The configuration is
1122 * given in ms. We insure a multiple of the beacon
1123 * period is used. Also, if the sleep duration is
1124 * greater than the DTIM period then it makes senses
1125 * to make it a multiple of that.
1127 * XXX fixed at 100ms
1129 bs.bs_sleepduration =
1130 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval);
1131 if (bs.bs_sleepduration > bs.bs_dtimperiod)
1132 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod);
1134 DPRINTF(sc, ATH_DEBUG_BEACON,
1135 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u "
1136 "nextdtim %u bmiss %u sleep %u cfp:period %u "
1137 "maxdur %u next %u timoffset %u\n"
1145 , bs.bs_bmissthreshold
1146 , bs.bs_sleepduration
1148 , bs.bs_cfpmaxduration
1152 ath_hal_intrset(ah, 0);
1153 ath_hal_beacontimers(ah, &bs);
1154 sc->sc_imask |= HAL_INT_BMISS;
1155 ath_hal_intrset(ah, sc->sc_imask);
1157 ath_hal_intrset(ah, 0);
1158 if (nexttbtt == intval)
1159 intval |= HAL_BEACON_RESET_TSF;
1160 if (ic->ic_opmode == IEEE80211_M_IBSS) {
1162 * In IBSS mode enable the beacon timers but only
1163 * enable SWBA interrupts if we need to manually
1164 * prepare beacon frames. Otherwise we use a
1165 * self-linked tx descriptor and let the hardware
1168 intval |= HAL_BEACON_ENA;
1169 if (!sc->sc_hasveol)
1170 sc->sc_imask |= HAL_INT_SWBA;
1171 if ((intval & HAL_BEACON_RESET_TSF) == 0) {
1173 * Pull nexttbtt forward to reflect
1176 tsf = ath_hal_gettsf64(ah);
1177 tsftu = TSF_TO_TU(tsf>>32, tsf) + FUDGE;
1180 } while (nexttbtt < tsftu);
1182 ath_beaconq_config(sc);
1183 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
1184 ic->ic_opmode == IEEE80211_M_MBSS) {
1186 * In AP/mesh mode we enable the beacon timers
1187 * and SWBA interrupts to prepare beacon frames.
1189 intval |= HAL_BEACON_ENA;
1190 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */
1191 ath_beaconq_config(sc);
1195 * Now dirty things because for now, the EDMA HAL has
1196 * nexttbtt and intval is TU/8.
1198 if (sc->sc_isedma) {
1199 nexttbtt_u8 = (nexttbtt << 3);
1200 intval_u8 = (intval << 3);
1201 if (intval & HAL_BEACON_ENA)
1202 intval_u8 |= HAL_BEACON_ENA;
1203 if (intval & HAL_BEACON_RESET_TSF)
1204 intval_u8 |= HAL_BEACON_RESET_TSF;
1205 ath_hal_beaconinit(ah, nexttbtt_u8, intval_u8);
1207 ath_hal_beaconinit(ah, nexttbtt, intval);
1208 sc->sc_bmisscount = 0;
1209 ath_hal_intrset(ah, sc->sc_imask);
1211 * When using a self-linked beacon descriptor in
1212 * ibss mode load it once here.
1214 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol)
1215 ath_beacon_start_adhoc(sc, vap);
1217 ieee80211_free_node(ni);
1220 ath_power_restore_power_state(sc);