2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for the Atheros Wireless LAN controller.
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
56 #include <sys/malloc.h>
58 #include <sys/mutex.h>
59 #include <sys/kernel.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/errno.h>
63 #include <sys/callout.h>
65 #include <sys/endian.h>
66 #include <sys/kthread.h>
67 #include <sys/taskqueue.h>
69 #include <sys/module.h>
71 #include <sys/smp.h> /* for mp_ncpus */
73 #include <machine/bus.h>
76 #include <net/if_var.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/if_types.h>
80 #include <net/if_arp.h>
81 #include <net/ethernet.h>
82 #include <net/if_llc.h>
84 #include <net80211/ieee80211_var.h>
85 #include <net80211/ieee80211_regdomain.h>
86 #ifdef IEEE80211_SUPPORT_SUPERG
87 #include <net80211/ieee80211_superg.h>
89 #ifdef IEEE80211_SUPPORT_TDMA
90 #include <net80211/ieee80211_tdma.h>
96 #include <netinet/in.h>
97 #include <netinet/if_ether.h>
100 #include <dev/ath/if_athvar.h>
101 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
102 #include <dev/ath/ath_hal/ah_diagcodes.h>
104 #include <dev/ath/if_ath_debug.h>
105 #include <dev/ath/if_ath_misc.h>
106 #include <dev/ath/if_ath_tsf.h>
107 #include <dev/ath/if_ath_tx.h>
108 #include <dev/ath/if_ath_sysctl.h>
109 #include <dev/ath/if_ath_led.h>
110 #include <dev/ath/if_ath_keycache.h>
111 #include <dev/ath/if_ath_rx.h>
112 #include <dev/ath/if_ath_beacon.h>
113 #include <dev/ath/if_athdfs.h>
114 #include <dev/ath/if_ath_descdma.h>
117 #include <dev/ath/ath_tx99/ath_tx99.h>
121 #include <dev/ath/if_ath_alq.h>
124 #include <dev/ath/if_ath_lna_div.h>
127 * Calculate the receive filter according to the
128 * operating mode and state:
130 * o always accept unicast, broadcast, and multicast traffic
131 * o accept PHY error frames when hardware doesn't have MIB support
132 * to count and we need them for ANI (sta mode only until recently)
133 * and we are not scanning (ANI is disabled)
134 * NB: older hal's add rx filter bits out of sight and we need to
135 * blindly preserve them
136 * o probe request frames are accepted only when operating in
137 * hostap, adhoc, mesh, or monitor modes
138 * o enable promiscuous mode
139 * - when in monitor mode
140 * - if interface marked PROMISC (assumes bridge setting is filtered)
142 * - when operating in station mode for collecting rssi data when
143 * the station is otherwise quiet, or
144 * - when operating in adhoc mode so the 802.11 layer creates
145 * node table entries for peers,
147 * - when doing s/w beacon miss (e.g. for ap+sta)
148 * - when operating in ap mode in 11g to detect overlapping bss that
150 * - when operating in mesh mode to detect neighbors
151 * o accept control frames:
152 * - when in monitor mode
153 * XXX HT protection for 11n
156 ath_calcrxfilter(struct ath_softc *sc)
158 struct ieee80211com *ic = &sc->sc_ic;
161 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
162 if (!sc->sc_needmib && !sc->sc_scanning)
163 rfilt |= HAL_RX_FILTER_PHYERR;
164 if (ic->ic_opmode != IEEE80211_M_STA)
165 rfilt |= HAL_RX_FILTER_PROBEREQ;
166 /* XXX ic->ic_monvaps != 0? */
167 if (ic->ic_opmode == IEEE80211_M_MONITOR || ic->ic_promisc > 0)
168 rfilt |= HAL_RX_FILTER_PROM;
171 * Only listen to all beacons if we're scanning.
173 * Otherwise we only really need to hear beacons from
176 * IBSS? software beacon miss? Just receive all beacons.
177 * We need to hear beacons/probe requests from everyone so
180 if (ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) {
181 rfilt |= HAL_RX_FILTER_BEACON;
182 } else if (ic->ic_opmode == IEEE80211_M_STA) {
183 if (sc->sc_do_mybeacon && ! sc->sc_scanning) {
184 rfilt |= HAL_RX_FILTER_MYBEACON;
185 } else { /* scanning, non-mybeacon chips */
186 rfilt |= HAL_RX_FILTER_BEACON;
191 * NB: We don't recalculate the rx filter when
192 * ic_protmode changes; otherwise we could do
193 * this only when ic_protmode != NONE.
195 if (ic->ic_opmode == IEEE80211_M_HOSTAP &&
196 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
197 rfilt |= HAL_RX_FILTER_BEACON;
200 * Enable hardware PS-POLL RX only for hostap mode;
201 * STA mode sends PS-POLL frames but never
204 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL,
205 0, NULL) == HAL_OK &&
206 ic->ic_opmode == IEEE80211_M_HOSTAP)
207 rfilt |= HAL_RX_FILTER_PSPOLL;
209 if (sc->sc_nmeshvaps) {
210 rfilt |= HAL_RX_FILTER_BEACON;
211 if (sc->sc_hasbmatch)
212 rfilt |= HAL_RX_FILTER_BSSID;
214 rfilt |= HAL_RX_FILTER_PROM;
216 if (ic->ic_opmode == IEEE80211_M_MONITOR)
217 rfilt |= HAL_RX_FILTER_CONTROL;
220 * Enable RX of compressed BAR frames only when doing
221 * 802.11n. Required for A-MPDU.
223 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan))
224 rfilt |= HAL_RX_FILTER_COMPBAR;
227 * Enable radar PHY errors if requested by the
231 rfilt |= HAL_RX_FILTER_PHYRADAR;
234 * Enable spectral PHY errors if requested by the
237 if (sc->sc_dospectral)
238 rfilt |= HAL_RX_FILTER_PHYRADAR;
240 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s\n",
241 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode]);
246 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
248 struct ath_hal *ah = sc->sc_ah;
253 /* XXX TODO: ATH_RX_LOCK_ASSERT(sc); */
258 * NB: by assigning a page to the rx dma buffer we
259 * implicitly satisfy the Atheros requirement that
260 * this buffer be cache-line-aligned and sized to be
261 * multiple of the cache line size. Not doing this
262 * causes weird stuff to happen (for the 5210 at least).
264 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
266 DPRINTF(sc, ATH_DEBUG_ANY,
267 "%s: no mbuf/cluster\n", __func__);
268 sc->sc_stats.ast_rx_nombuf++;
271 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
273 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
275 bf->bf_segs, &bf->bf_nseg,
278 DPRINTF(sc, ATH_DEBUG_ANY,
279 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
281 sc->sc_stats.ast_rx_busdma++;
285 KASSERT(bf->bf_nseg == 1,
286 ("multi-segment packet; nseg %u", bf->bf_nseg));
289 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
292 * Setup descriptors. For receive we always terminate
293 * the descriptor list with a self-linked entry so we'll
294 * not get overrun under high load (as can happen with a
295 * 5212 when ANI processing enables PHY error frames).
297 * To insure the last descriptor is self-linked we create
298 * each descriptor as self-linked and add it to the end. As
299 * each additional descriptor is added the previous self-linked
300 * entry is ``fixed'' naturally. This should be safe even
301 * if DMA is happening. When processing RX interrupts we
302 * never remove/process the last, self-linked, entry on the
303 * descriptor list. This insures the hardware always has
304 * someplace to write a new frame.
307 * 11N: we can no longer afford to self link the last descriptor.
308 * MAC acknowledges BA status as long as it copies frames to host
309 * buffer (or rx fifo). This can incorrectly acknowledge packets
310 * to a sender if last desc is self-linked.
314 ds->ds_link = bf->bf_daddr; /* link to self */
316 ds->ds_link = 0; /* terminate the list */
317 ds->ds_data = bf->bf_segs[0].ds_addr;
318 ath_hal_setuprxdesc(ah, ds
319 , m->m_len /* buffer size */
323 if (sc->sc_rxlink != NULL)
324 *sc->sc_rxlink = bf->bf_daddr;
325 sc->sc_rxlink = &ds->ds_link;
330 * Intercept management frames to collect beacon rssi data
331 * and to do ibss merges.
334 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
335 int subtype, const struct ieee80211_rx_stats *rxs, int rssi, int nf)
337 struct ieee80211vap *vap = ni->ni_vap;
338 struct ath_softc *sc = vap->iv_ic->ic_softc;
339 uint64_t tsf_beacon_old, tsf_beacon;
342 int32_t tsf_delta_bmiss;
343 int32_t tsf_remainder;
344 uint64_t tsf_beacon_target;
347 tsf_beacon_old = ((uint64_t) LE_READ_4(ni->ni_tstamp.data + 4)) << 32;
348 tsf_beacon_old |= LE_READ_4(ni->ni_tstamp.data);
350 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10)
352 if (ni->ni_intval > 0) {
353 tsf_intval = TU_TO_TSF(ni->ni_intval);
358 * Call up first so subsequent work can use information
359 * potentially stored in the node (e.g. for ibss merge).
361 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rxs, rssi, nf);
363 case IEEE80211_FC0_SUBTYPE_BEACON:
364 /* update rssi statistics for use by the hal */
365 /* XXX unlocked check against vap->iv_bss? */
366 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
368 tsf_beacon = ((uint64_t) LE_READ_4(ni->ni_tstamp.data + 4)) << 32;
369 tsf_beacon |= LE_READ_4(ni->ni_tstamp.data);
371 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah);
374 * Let's calculate the delta and remainder, so we can see
375 * if the beacon timer from the AP is varying by more than
376 * a few TU. (Which would be a huge, huge problem.)
378 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old;
380 tsf_delta_bmiss = tsf_delta / tsf_intval;
383 * If our delta is greater than half the beacon interval,
384 * let's round the bmiss value up to the next beacon
385 * interval. Ie, we're running really, really early
386 * on the next beacon.
388 if (tsf_delta % tsf_intval > (tsf_intval / 2))
391 tsf_beacon_target = tsf_beacon_old +
392 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval);
395 * The remainder using '%' is between 0 .. intval-1.
396 * If we're actually running too fast, then the remainder
397 * will be some large number just under intval-1.
398 * So we need to look at whether we're running
399 * before or after the target beacon interval
400 * and if we are, modify how we do the remainder
403 if (tsf_beacon < tsf_beacon_target) {
405 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval));
407 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval;
410 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: old_tsf=%llu, new_tsf=%llu, target_tsf=%llu, delta=%lld, bmiss=%d, remainder=%d\n",
412 (unsigned long long) tsf_beacon_old,
413 (unsigned long long) tsf_beacon,
414 (unsigned long long) tsf_beacon_target,
415 (long long) tsf_delta,
419 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: tsf=%llu, nexttbtt=%llu, delta=%d\n",
421 (unsigned long long) tsf_beacon,
422 (unsigned long long) nexttbtt,
423 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval);
425 if (sc->sc_syncbeacon &&
427 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) {
428 DPRINTF(sc, ATH_DEBUG_BEACON,
429 "%s: syncbeacon=1; syncing\n",
432 * Resync beacon timers using the tsf of the beacon
433 * frame we just received.
435 ath_beacon_config(sc, vap);
436 sc->sc_syncbeacon = 0;
440 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
441 if (vap->iv_opmode == IEEE80211_M_IBSS &&
442 vap->iv_state == IEEE80211_S_RUN) {
443 uint32_t rstamp = sc->sc_lastrs->rs_tstamp;
444 uint64_t tsf = ath_extend_tsf(sc, rstamp,
445 ath_hal_gettsf64(sc->sc_ah));
447 * Handle ibss merge as needed; check the tsf on the
448 * frame before attempting the merge. The 802.11 spec
449 * says the station should change it's bssid to match
450 * the oldest station with the same ssid, where oldest
451 * is determined by the tsf. Note that hardware
452 * reconfiguration happens through callback to
453 * ath_newstate as the state machine will go from
454 * RUN -> RUN when this happens.
456 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
457 DPRINTF(sc, ATH_DEBUG_STATE,
458 "ibss merge, rstamp %u tsf %ju "
459 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
460 (uintmax_t)ni->ni_tstamp.tsf);
461 (void) ieee80211_ibss_merge(ni);
468 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
470 ath_rx_tap_vendor(struct ath_softc *sc, struct mbuf *m,
471 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
474 /* Fill in the extension bitmap */
475 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER);
477 /* Fill in the vendor header */
478 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f;
479 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03;
480 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00;
482 /* XXX what should this be? */
483 sc->sc_rx_th.wr_vh.vh_sub_ns = 0;
484 sc->sc_rx_th.wr_vh.vh_skip_len =
485 htole16(sizeof(struct ath_radiotap_vendor_hdr));
487 /* General version info */
488 sc->sc_rx_th.wr_v.vh_version = 1;
490 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask;
493 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0];
494 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1];
495 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2];
496 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0];
497 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1];
498 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2];
501 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0;
502 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1;
503 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2;
504 /* These are only populated from the AR9300 or later */
505 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3;
506 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4;
509 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX;
512 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate;
515 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags;
518 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR;
520 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR;
523 if (rs->rs_status & HAL_RXERR_PHY) {
524 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr;
525 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR;
527 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff;
529 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status;
530 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi;
532 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
535 ath_rx_tap(struct ath_softc *sc, struct mbuf *m,
536 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
538 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20)
539 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U)
540 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D)
541 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D)
542 const HAL_RATE_TABLE *rt;
545 rt = sc->sc_currates;
546 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
547 rix = rt->rateCodeToIndex[rs->rs_rate];
548 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
549 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
550 #ifdef AH_SUPPORT_AR5416
551 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT;
552 if (rs->rs_status & HAL_RXERR_PHY) {
554 * PHY error - make sure the channel flags
555 * reflect the actual channel configuration,
556 * not the received frame.
558 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan))
559 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
560 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan))
561 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
562 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan))
563 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
564 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */
565 struct ieee80211com *ic = &sc->sc_ic;
567 if ((rs->rs_flags & HAL_RX_2040) == 0)
568 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
569 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan))
570 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
572 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
573 if ((rs->rs_flags & HAL_RX_GI) == 0)
574 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
578 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf));
579 if (rs->rs_status & HAL_RXERR_CRC)
580 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
581 /* XXX propagate other error flags from descriptor */
582 sc->sc_rx_th.wr_antnoise = nf;
583 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi;
584 sc->sc_rx_th.wr_antenna = rs->rs_antenna;
592 ath_handle_micerror(struct ieee80211com *ic,
593 struct ieee80211_frame *wh, int keyix)
595 struct ieee80211_node *ni;
597 /* XXX recheck MIC to deal w/ chips that lie */
598 /* XXX discard MIC errors on !data frames */
599 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh);
601 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix);
602 ieee80211_free_node(ni);
607 * Process a single packet.
609 * The mbuf must already be synced, unmapped and removed from bf->bf_m
612 * The mbuf must be consumed by this routine - either passed up the
613 * net80211 stack, put on the holding queue, or freed.
616 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status,
617 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf,
622 struct ieee80211com *ic = &sc->sc_ic;
623 struct ieee80211_node *ni;
625 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
628 * Calculate the correct 64 bit TSF given
629 * the TSF64 register value and rs_tstamp.
631 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf);
633 /* These aren't specifically errors */
634 #ifdef AH_SUPPORT_AR5416
635 if (rs->rs_flags & HAL_RX_GI)
636 sc->sc_stats.ast_rx_halfgi++;
637 if (rs->rs_flags & HAL_RX_2040)
638 sc->sc_stats.ast_rx_2040++;
639 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE)
640 sc->sc_stats.ast_rx_pre_crc_err++;
641 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST)
642 sc->sc_stats.ast_rx_post_crc_err++;
643 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY)
644 sc->sc_stats.ast_rx_decrypt_busy_err++;
645 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN)
646 sc->sc_stats.ast_rx_hi_rx_chain++;
647 if (rs->rs_flags & HAL_RX_STBC)
648 sc->sc_stats.ast_rx_stbc++;
649 #endif /* AH_SUPPORT_AR5416 */
651 if (rs->rs_status != 0) {
652 if (rs->rs_status & HAL_RXERR_CRC)
653 sc->sc_stats.ast_rx_crcerr++;
654 if (rs->rs_status & HAL_RXERR_FIFO)
655 sc->sc_stats.ast_rx_fifoerr++;
656 if (rs->rs_status & HAL_RXERR_PHY) {
657 sc->sc_stats.ast_rx_phyerr++;
658 /* Process DFS radar events */
659 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) ||
660 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) {
661 /* Now pass it to the radar processing code */
662 ath_dfs_process_phy_err(sc, m, rstamp, rs);
665 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */
666 if (rs->rs_phyerr < 64)
667 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++;
668 goto rx_error; /* NB: don't count in ierrors */
670 if (rs->rs_status & HAL_RXERR_DECRYPT) {
672 * Decrypt error. If the error occurred
673 * because there was no hardware key, then
674 * let the frame through so the upper layers
675 * can process it. This is necessary for 5210
676 * parts which have no way to setup a ``clear''
679 * XXX do key cache faulting
681 if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
683 sc->sc_stats.ast_rx_badcrypt++;
686 * Similar as above - if the failure was a keymiss
687 * just punt it up to the upper layers for now.
689 if (rs->rs_status & HAL_RXERR_KEYMISS) {
690 sc->sc_stats.ast_rx_keymiss++;
693 if (rs->rs_status & HAL_RXERR_MIC) {
694 sc->sc_stats.ast_rx_badmic++;
696 * Do minimal work required to hand off
697 * the 802.11 header for notification.
699 /* XXX frag's and qos frames */
700 len = rs->rs_datalen;
701 if (len >= sizeof (struct ieee80211_frame)) {
702 ath_handle_micerror(ic,
703 mtod(m, struct ieee80211_frame *),
705 rs->rs_keyix-32 : rs->rs_keyix);
708 counter_u64_add(ic->ic_ierrors, 1);
711 * Cleanup any pending partial frame.
713 if (re->m_rxpending != NULL) {
714 m_freem(re->m_rxpending);
715 re->m_rxpending = NULL;
718 * When a tap is present pass error frames
719 * that have been requested. By default we
720 * pass decrypt+mic errors but others may be
721 * interesting (e.g. crc).
723 if (ieee80211_radiotap_active(ic) &&
724 (rs->rs_status & sc->sc_monpass)) {
725 /* NB: bpf needs the mbuf length setup */
726 len = rs->rs_datalen;
727 m->m_pkthdr.len = m->m_len = len;
728 ath_rx_tap(sc, m, rs, rstamp, nf);
729 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
730 ath_rx_tap_vendor(sc, m, rs, rstamp, nf);
731 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
732 ieee80211_radiotap_rx_all(ic, m);
734 /* XXX pass MIC errors up for s/w reclaculation */
735 m_freem(m); m = NULL;
739 len = rs->rs_datalen;
744 * Frame spans multiple descriptors; save
745 * it for the next completed descriptor, it
746 * will be used to construct a jumbogram.
748 if (re->m_rxpending != NULL) {
749 /* NB: max frame size is currently 2 clusters */
750 sc->sc_stats.ast_rx_toobig++;
751 m_freem(re->m_rxpending);
753 m->m_pkthdr.len = len;
757 } else if (re->m_rxpending != NULL) {
759 * This is the second part of a jumbogram,
760 * chain it to the first mbuf, adjust the
761 * frame length, and clear the rxpending state.
763 re->m_rxpending->m_next = m;
764 re->m_rxpending->m_pkthdr.len += len;
766 re->m_rxpending = NULL;
769 * Normal single-descriptor receive; setup packet length.
771 m->m_pkthdr.len = len;
775 * Validate rs->rs_antenna.
777 * Some users w/ AR9285 NICs have reported crashes
778 * here because rs_antenna field is bogusly large.
779 * Let's enforce the maximum antenna limit of 8
780 * (and it shouldn't be hard coded, but that's a
781 * separate problem) and if there's an issue, print
782 * out an error and adjust rs_antenna to something
785 * This code should be removed once the actual
786 * root cause of the issue has been identified.
787 * For example, it may be that the rs_antenna
788 * field is only valid for the lsat frame of
789 * an aggregate and it just happens that it is
790 * "mostly" right. (This is a general statement -
791 * the majority of the statistics are only valid
792 * for the last frame in an aggregate.
794 if (rs->rs_antenna > 7) {
795 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n",
796 __func__, rs->rs_antenna);
798 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
799 #endif /* ATH_DEBUG */
800 rs->rs_antenna = 0; /* XXX better than nothing */
804 * If this is an AR9285/AR9485, then the receive and LNA
805 * configuration is stored in RSSI[2] / EXTRSSI[2].
806 * We can extract this out to build a much better
807 * receive antenna profile.
809 * Yes, this just blurts over the above RX antenna field
810 * for now. It's fine, the AR9285 doesn't really use
813 * Later on we should store away the fine grained LNA
814 * information and keep separate counters just for
815 * that. It'll help when debugging the AR9285/AR9485
816 * combined diversity code.
818 if (sc->sc_rx_lnamixer) {
821 /* Bits 0:1 - the LNA configuration used */
823 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED)
824 >> HAL_RX_LNA_CFG_USED_S);
826 /* Bit 2 - the external RX antenna switch */
827 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG)
828 rs->rs_antenna |= 0x4;
831 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
834 * Populate the rx status block. When there are bpf
835 * listeners we do the additional work to provide
836 * complete status. Otherwise we fill in only the
837 * material required by ieee80211_input. Note that
838 * noise setting is filled in above.
840 if (ieee80211_radiotap_active(ic)) {
841 ath_rx_tap(sc, m, rs, rstamp, nf);
842 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
843 ath_rx_tap_vendor(sc, m, rs, rstamp, nf);
844 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
848 * From this point on we assume the frame is at least
849 * as large as ieee80211_frame_min; verify that.
851 if (len < IEEE80211_MIN_LEN) {
852 if (!ieee80211_radiotap_active(ic)) {
853 DPRINTF(sc, ATH_DEBUG_RECV,
854 "%s: short packet %d\n", __func__, len);
855 sc->sc_stats.ast_rx_tooshort++;
857 /* NB: in particular this captures ack's */
858 ieee80211_radiotap_rx_all(ic, m);
860 m_freem(m); m = NULL;
864 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
865 const HAL_RATE_TABLE *rt = sc->sc_currates;
866 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate];
868 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len,
869 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi);
872 m_adj(m, -IEEE80211_CRC_LEN);
875 * Locate the node for sender, track state, and then
876 * pass the (referenced) node up to the 802.11 layer
879 ni = ieee80211_find_rxnode_withkey(ic,
880 mtod(m, const struct ieee80211_frame_min *),
881 rs->rs_keyix == HAL_RXKEYIX_INVALID ?
882 IEEE80211_KEYIX_NONE : rs->rs_keyix);
885 #ifdef AH_SUPPORT_AR5416
887 sc->sc_stats.ast_rx_agg++;
888 #endif /* AH_SUPPORT_AR5416 */
892 * Only punt packets for ampdu reorder processing for
893 * 11n nodes; net80211 enforces that M_AMPDU is only
896 if (ni->ni_flags & IEEE80211_NODE_HT)
897 m->m_flags |= M_AMPDU;
900 * Sending station is known, dispatch directly.
902 type = ieee80211_input(ni, m, rs->rs_rssi, nf);
903 ieee80211_free_node(ni);
906 * Arrange to update the last rx timestamp only for
907 * frames from our ap when operating in station mode.
908 * This assumes the rx key is always setup when
911 if (ic->ic_opmode == IEEE80211_M_STA &&
912 rs->rs_keyix != HAL_RXKEYIX_INVALID)
915 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf);
920 * At this point we have passed the frame up the stack; thus
921 * the mbuf is no longer ours.
925 * Track rx rssi and do any rx antenna management.
927 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
928 if (sc->sc_diversity) {
930 * When using fast diversity, change the default rx
931 * antenna if diversity chooses the other antenna 3
934 if (sc->sc_defant != rs->rs_antenna) {
935 if (++sc->sc_rxotherant >= 3)
936 ath_setdefantenna(sc, rs->rs_antenna);
938 sc->sc_rxotherant = 0;
941 /* Handle slow diversity if enabled */
942 if (sc->sc_dolnadiv) {
943 ath_lna_rx_comb_scan(sc, rs, ticks, hz);
946 if (sc->sc_softled) {
948 * Blink for any data frame. Otherwise do a
949 * heartbeat-style blink when idle. The latter
950 * is mainly for station mode where we depend on
951 * periodic beacon frames to trigger the poll event.
953 if (type == IEEE80211_FC0_TYPE_DATA) {
954 const HAL_RATE_TABLE *rt = sc->sc_currates;
956 rt->rateCodeToIndex[rs->rs_rate]);
957 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
958 ath_led_event(sc, 0);
962 * Debugging - complain if we didn't NULL the mbuf pointer
966 device_printf(sc->sc_dev,
967 "%s: mbuf %p should've been freed!\n",
974 #define ATH_RX_MAX 128
977 * XXX TODO: break out the "get buffers" from "call ath_rx_pkt()" like
978 * the EDMA code does.
980 * XXX TODO: then, do all of the RX list management stuff inside
981 * ATH_RX_LOCK() so we don't end up potentially racing. The EDMA
982 * code is doing it right.
985 ath_rx_proc(struct ath_softc *sc, int resched)
987 #define PA2DESC(_sc, _pa) \
988 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
989 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
991 struct ath_hal *ah = sc->sc_ah;
992 #ifdef IEEE80211_SUPPORT_SUPERG
993 struct ieee80211com *ic = &sc->sc_ic;
996 struct ath_rx_status *rs;
1006 /* XXX we must not hold the ATH_LOCK here */
1007 ATH_UNLOCK_ASSERT(sc);
1008 ATH_PCU_UNLOCK_ASSERT(sc);
1011 sc->sc_rxproc_cnt++;
1012 kickpcu = sc->sc_kickpcu;
1016 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1019 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__);
1021 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
1022 sc->sc_stats.ast_rx_noise = nf;
1023 tsf = ath_hal_gettsf64(ah);
1026 * Don't process too many packets at a time; give the
1027 * TX thread time to also run - otherwise the TX
1028 * latency can jump by quite a bit, causing throughput
1031 if (!kickpcu && npkts >= ATH_RX_MAX)
1034 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1035 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */
1036 device_printf(sc->sc_dev, "%s: no buffer!\n", __func__);
1038 } else if (bf == NULL) {
1041 * this can happen for non-self-linked RX chains
1043 sc->sc_stats.ast_rx_hitqueueend++;
1047 if (m == NULL) { /* NB: shouldn't happen */
1049 * If mbuf allocation failed previously there
1050 * will be no mbuf; try again to re-populate it.
1052 /* XXX make debug msg */
1053 device_printf(sc->sc_dev, "%s: no mbuf!\n", __func__);
1054 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
1058 if (ds->ds_link == bf->bf_daddr) {
1059 /* NB: never process the self-linked entry at the end */
1060 sc->sc_stats.ast_rx_hitqueueend++;
1063 /* XXX sync descriptor memory */
1065 * Must provide the virtual address of the current
1066 * descriptor, the physical address, and the virtual
1067 * address of the next descriptor in the h/w chain.
1068 * This allows the HAL to look ahead to see if the
1069 * hardware is done with a descriptor by checking the
1070 * done bit in the following descriptor and the address
1071 * of the current descriptor the DMA engine is working
1072 * on. All this is necessary because of our use of
1073 * a self-linked list to avoid rx overruns.
1075 rs = &bf->bf_status.ds_rxstat;
1076 status = ath_hal_rxprocdesc(ah, ds,
1077 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
1079 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
1080 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
1083 #ifdef ATH_DEBUG_ALQ
1084 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS))
1085 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS,
1086 sc->sc_rx_statuslen, (char *) ds);
1087 #endif /* ATH_DEBUG_ALQ */
1089 if (status == HAL_EINPROGRESS)
1092 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
1096 * Process a single frame.
1098 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD);
1099 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
1101 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m))
1105 * If there's a holding buffer, insert that onto
1106 * the RX list; the hardware is now definitely not pointing
1110 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf != NULL) {
1111 TAILQ_INSERT_TAIL(&sc->sc_rxbuf,
1112 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf,
1114 ret = ath_rxbuf_init(sc,
1115 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf);
1118 * Next, throw our buffer into the holding entry. The hardware
1119 * may use the descriptor to read the link pointer before
1120 * DMAing the next descriptor in to write out a packet.
1122 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = bf;
1125 /* rx signal state monitoring */
1126 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
1128 sc->sc_lastrx = tsf;
1130 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood);
1131 /* Queue DFS tasklet if needed */
1132 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan))
1133 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
1136 * Now that all the RX frames were handled that
1137 * need to be handled, kick the PCU if there's
1138 * been an RXEOL condition.
1140 if (resched && kickpcu) {
1142 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu");
1143 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n",
1147 * Go through the process of fully tearing down
1148 * the RX buffers and reinitialising them.
1150 * There's a hardware bug that causes the RX FIFO
1151 * to get confused under certain conditions and
1152 * constantly write over the same frame, leading
1153 * the RX driver code here to get heavily confused.
1156 * XXX Has RX DMA stopped enough here to just call
1158 * XXX Do we need to use the holding buffer to restart
1159 * RX DMA by appending entries to the final
1160 * descriptor? Quite likely.
1166 * Disabled for now - it'd be nice to be able to do
1167 * this in order to limit the amount of CPU time spent
1168 * reinitialising the RX side (and thus minimise RX
1169 * drops) however there's a hardware issue that
1170 * causes things to get too far out of whack.
1173 * XXX can we hold the PCU lock here?
1174 * Are there any net80211 buffer calls involved?
1176 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1177 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
1178 ath_hal_rxena(ah); /* enable recv descriptors */
1179 ath_mode_init(sc); /* set filters, etc. */
1180 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
1183 ath_hal_intrset(ah, sc->sc_imask);
1188 #ifdef IEEE80211_SUPPORT_SUPERG
1190 ieee80211_ff_age_all(ic, 100);
1194 * Put the hardware to sleep again if we're done with it.
1197 ath_power_restore_power_state(sc);
1201 * If we hit the maximum number of frames in this round,
1202 * reschedule for another immediate pass. This gives
1203 * the TX and TX completion routines time to run, which
1204 * will reduce latency.
1206 if (npkts >= ATH_RX_MAX)
1207 sc->sc_rx.recv_sched(sc, resched);
1210 sc->sc_rxproc_cnt--;
1217 * Only run the RX proc if it's not already running.
1218 * Since this may get run as part of the reset/flush path,
1219 * the task can't clash with an existing, running tasklet.
1222 ath_legacy_rx_tasklet(void *arg, int npending)
1224 struct ath_softc *sc = arg;
1226 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending);
1227 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
1229 if (sc->sc_inreset_cnt > 0) {
1230 device_printf(sc->sc_dev,
1231 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
1241 ath_legacy_flushrecv(struct ath_softc *sc)
1248 ath_legacy_flush_rxpending(struct ath_softc *sc)
1251 /* XXX ATH_RX_LOCK_ASSERT(sc); */
1253 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) {
1254 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
1255 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
1257 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) {
1258 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
1259 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
1264 ath_legacy_flush_rxholdbf(struct ath_softc *sc)
1268 /* XXX ATH_RX_LOCK_ASSERT(sc); */
1270 * If there are RX holding buffers, free them here and return
1273 * XXX should just verify that bf->bf_m is NULL, as it must
1276 bf = sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf;
1278 if (bf->bf_m != NULL)
1281 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
1282 (void) ath_rxbuf_init(sc, bf);
1284 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = NULL;
1286 bf = sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf;
1288 if (bf->bf_m != NULL)
1291 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
1292 (void) ath_rxbuf_init(sc, bf);
1294 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf = NULL;
1300 * Disable the receive h/w in preparation for a reset.
1303 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay)
1305 #define PA2DESC(_sc, _pa) \
1306 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
1307 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
1308 struct ath_hal *ah = sc->sc_ah;
1312 ath_hal_stoppcurecv(ah); /* disable PCU */
1313 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
1314 ath_hal_stopdmarecv(ah); /* disable DMA engine */
1316 * TODO: see if this particular DELAY() is required; it may be
1317 * masking some missing FIFO flush or DMA sync.
1322 DELAY(3000); /* 3ms is long enough for 1 frame */
1324 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
1328 device_printf(sc->sc_dev,
1329 "%s: rx queue %p, link %p\n",
1331 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP),
1334 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1335 struct ath_desc *ds = bf->bf_desc;
1336 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
1337 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
1338 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
1339 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
1340 ath_printrxbuf(sc, bf, ix, status == HAL_OK);
1346 (void) ath_legacy_flush_rxpending(sc);
1347 (void) ath_legacy_flush_rxholdbf(sc);
1349 sc->sc_rxlink = NULL; /* just in case */
1356 * XXX TODO: something was calling startrecv without calling
1357 * stoprecv. Let's figure out what/why. It was showing up
1358 * as a mbuf leak (rxpending) and ath_buf leak (holdbf.)
1362 * Enable the receive h/w following a reset.
1365 ath_legacy_startrecv(struct ath_softc *sc)
1367 struct ath_hal *ah = sc->sc_ah;
1373 * XXX should verify these are already all NULL!
1375 sc->sc_rxlink = NULL;
1376 (void) ath_legacy_flush_rxpending(sc);
1377 (void) ath_legacy_flush_rxholdbf(sc);
1380 * Re-chain all of the buffers in the RX buffer list.
1382 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1383 int error = ath_rxbuf_init(sc, bf);
1385 DPRINTF(sc, ATH_DEBUG_RECV,
1386 "%s: ath_rxbuf_init failed %d\n",
1392 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1393 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
1394 ath_hal_rxena(ah); /* enable recv descriptors */
1395 ath_mode_init(sc); /* set filters, etc. */
1396 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
1403 ath_legacy_dma_rxsetup(struct ath_softc *sc)
1407 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
1408 "rx", sizeof(struct ath_desc), ath_rxbuf, 1);
1416 ath_legacy_dma_rxteardown(struct ath_softc *sc)
1419 if (sc->sc_rxdma.dd_desc_len != 0)
1420 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
1425 ath_legacy_recv_sched(struct ath_softc *sc, int dosched)
1428 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1432 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q,
1436 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1440 ath_recv_setup_legacy(struct ath_softc *sc)
1443 /* Sensible legacy defaults */
1445 * XXX this should be changed to properly support the
1446 * exact RX descriptor size for each HAL.
1448 sc->sc_rx_statuslen = sizeof(struct ath_desc);
1450 sc->sc_rx.recv_start = ath_legacy_startrecv;
1451 sc->sc_rx.recv_stop = ath_legacy_stoprecv;
1452 sc->sc_rx.recv_flush = ath_legacy_flushrecv;
1453 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet;
1454 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init;
1456 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup;
1457 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown;
1458 sc->sc_rx.recv_sched = ath_legacy_recv_sched;
1459 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue;