2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for the Atheros Wireless LAN controller.
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
56 #include <sys/malloc.h>
58 #include <sys/mutex.h>
59 #include <sys/kernel.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/errno.h>
63 #include <sys/callout.h>
65 #include <sys/endian.h>
66 #include <sys/kthread.h>
67 #include <sys/taskqueue.h>
69 #include <sys/module.h>
71 #include <sys/smp.h> /* for mp_ncpus */
73 #include <machine/bus.h>
76 #include <net/if_var.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/if_types.h>
80 #include <net/if_arp.h>
81 #include <net/ethernet.h>
82 #include <net/if_llc.h>
84 #include <net80211/ieee80211_var.h>
85 #include <net80211/ieee80211_regdomain.h>
86 #ifdef IEEE80211_SUPPORT_SUPERG
87 #include <net80211/ieee80211_superg.h>
89 #ifdef IEEE80211_SUPPORT_TDMA
90 #include <net80211/ieee80211_tdma.h>
96 #include <netinet/in.h>
97 #include <netinet/if_ether.h>
100 #include <dev/ath/if_athvar.h>
101 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
102 #include <dev/ath/ath_hal/ah_diagcodes.h>
104 #include <dev/ath/if_ath_debug.h>
105 #include <dev/ath/if_ath_misc.h>
106 #include <dev/ath/if_ath_tsf.h>
107 #include <dev/ath/if_ath_tx.h>
108 #include <dev/ath/if_ath_sysctl.h>
109 #include <dev/ath/if_ath_led.h>
110 #include <dev/ath/if_ath_keycache.h>
111 #include <dev/ath/if_ath_rx.h>
112 #include <dev/ath/if_ath_beacon.h>
113 #include <dev/ath/if_athdfs.h>
114 #include <dev/ath/if_ath_descdma.h>
117 #include <dev/ath/ath_tx99/ath_tx99.h>
121 #include <dev/ath/if_ath_alq.h>
124 #include <dev/ath/if_ath_lna_div.h>
127 * Calculate the receive filter according to the
128 * operating mode and state:
130 * o always accept unicast, broadcast, and multicast traffic
131 * o accept PHY error frames when hardware doesn't have MIB support
132 * to count and we need them for ANI (sta mode only until recently)
133 * and we are not scanning (ANI is disabled)
134 * NB: older hal's add rx filter bits out of sight and we need to
135 * blindly preserve them
136 * o probe request frames are accepted only when operating in
137 * hostap, adhoc, mesh, or monitor modes
138 * o enable promiscuous mode
139 * - when in monitor mode
140 * - if interface marked PROMISC (assumes bridge setting is filtered)
142 * - when operating in station mode for collecting rssi data when
143 * the station is otherwise quiet, or
144 * - when operating in adhoc mode so the 802.11 layer creates
145 * node table entries for peers,
147 * - when doing s/w beacon miss (e.g. for ap+sta)
148 * - when operating in ap mode in 11g to detect overlapping bss that
150 * - when operating in mesh mode to detect neighbors
151 * o accept control frames:
152 * - when in monitor mode
153 * XXX HT protection for 11n
156 ath_calcrxfilter(struct ath_softc *sc)
158 struct ieee80211com *ic = &sc->sc_ic;
161 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST;
162 if (!sc->sc_needmib && !sc->sc_scanning)
163 rfilt |= HAL_RX_FILTER_PHYERR;
164 if (ic->ic_opmode != IEEE80211_M_STA)
165 rfilt |= HAL_RX_FILTER_PROBEREQ;
166 /* XXX ic->ic_monvaps != 0? */
167 if (ic->ic_opmode == IEEE80211_M_MONITOR || ic->ic_promisc > 0)
168 rfilt |= HAL_RX_FILTER_PROM;
171 * Only listen to all beacons if we're scanning.
173 * Otherwise we only really need to hear beacons from
176 * IBSS? software beacon miss? Just receive all beacons.
177 * We need to hear beacons/probe requests from everyone so
180 if (ic->ic_opmode == IEEE80211_M_IBSS || sc->sc_swbmiss) {
181 rfilt |= HAL_RX_FILTER_BEACON;
182 } else if (ic->ic_opmode == IEEE80211_M_STA) {
183 if (sc->sc_do_mybeacon && ! sc->sc_scanning) {
184 rfilt |= HAL_RX_FILTER_MYBEACON;
185 } else { /* scanning, non-mybeacon chips */
186 rfilt |= HAL_RX_FILTER_BEACON;
191 * NB: We don't recalculate the rx filter when
192 * ic_protmode changes; otherwise we could do
193 * this only when ic_protmode != NONE.
195 if (ic->ic_opmode == IEEE80211_M_HOSTAP &&
196 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
197 rfilt |= HAL_RX_FILTER_BEACON;
200 * Enable hardware PS-POLL RX only for hostap mode;
201 * STA mode sends PS-POLL frames but never
204 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL,
205 0, NULL) == HAL_OK &&
206 ic->ic_opmode == IEEE80211_M_HOSTAP)
207 rfilt |= HAL_RX_FILTER_PSPOLL;
209 if (sc->sc_nmeshvaps) {
210 rfilt |= HAL_RX_FILTER_BEACON;
211 if (sc->sc_hasbmatch)
212 rfilt |= HAL_RX_FILTER_BSSID;
214 rfilt |= HAL_RX_FILTER_PROM;
216 if (ic->ic_opmode == IEEE80211_M_MONITOR)
217 rfilt |= HAL_RX_FILTER_CONTROL;
220 * Enable RX of compressed BAR frames only when doing
221 * 802.11n. Required for A-MPDU.
223 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan))
224 rfilt |= HAL_RX_FILTER_COMPBAR;
227 * Enable radar PHY errors if requested by the
231 rfilt |= HAL_RX_FILTER_PHYRADAR;
234 * Enable spectral PHY errors if requested by the
237 if (sc->sc_dospectral)
238 rfilt |= HAL_RX_FILTER_PHYRADAR;
240 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s\n",
241 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode]);
246 ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
248 struct ath_hal *ah = sc->sc_ah;
253 /* XXX TODO: ATH_RX_LOCK_ASSERT(sc); */
258 * NB: by assigning a page to the rx dma buffer we
259 * implicitly satisfy the Atheros requirement that
260 * this buffer be cache-line-aligned and sized to be
261 * multiple of the cache line size. Not doing this
262 * causes weird stuff to happen (for the 5210 at least).
264 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
266 DPRINTF(sc, ATH_DEBUG_ANY,
267 "%s: no mbuf/cluster\n", __func__);
268 sc->sc_stats.ast_rx_nombuf++;
271 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
273 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
275 bf->bf_segs, &bf->bf_nseg,
278 DPRINTF(sc, ATH_DEBUG_ANY,
279 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n",
281 sc->sc_stats.ast_rx_busdma++;
285 KASSERT(bf->bf_nseg == 1,
286 ("multi-segment packet; nseg %u", bf->bf_nseg));
289 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD);
292 * Setup descriptors. For receive we always terminate
293 * the descriptor list with a self-linked entry so we'll
294 * not get overrun under high load (as can happen with a
295 * 5212 when ANI processing enables PHY error frames).
297 * To insure the last descriptor is self-linked we create
298 * each descriptor as self-linked and add it to the end. As
299 * each additional descriptor is added the previous self-linked
300 * entry is ``fixed'' naturally. This should be safe even
301 * if DMA is happening. When processing RX interrupts we
302 * never remove/process the last, self-linked, entry on the
303 * descriptor list. This insures the hardware always has
304 * someplace to write a new frame.
307 * 11N: we can no longer afford to self link the last descriptor.
308 * MAC acknowledges BA status as long as it copies frames to host
309 * buffer (or rx fifo). This can incorrectly acknowledge packets
310 * to a sender if last desc is self-linked.
314 ds->ds_link = bf->bf_daddr; /* link to self */
316 ds->ds_link = 0; /* terminate the list */
317 ds->ds_data = bf->bf_segs[0].ds_addr;
318 ath_hal_setuprxdesc(ah, ds
319 , m->m_len /* buffer size */
323 if (sc->sc_rxlink != NULL)
324 *sc->sc_rxlink = bf->bf_daddr;
325 sc->sc_rxlink = &ds->ds_link;
330 * Intercept management frames to collect beacon rssi data
331 * and to do ibss merges.
334 ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m,
335 int subtype, const struct ieee80211_rx_stats *rxs, int rssi, int nf)
337 struct ieee80211vap *vap = ni->ni_vap;
338 struct ath_softc *sc = vap->iv_ic->ic_softc;
339 uint64_t tsf_beacon_old, tsf_beacon;
342 int32_t tsf_delta_bmiss;
343 int32_t tsf_remainder;
344 uint64_t tsf_beacon_target;
347 tsf_beacon_old = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32;
348 tsf_beacon_old |= le32dec(ni->ni_tstamp.data);
350 #define TU_TO_TSF(_tu) (((u_int64_t)(_tu)) << 10)
352 if (ni->ni_intval > 0) {
353 tsf_intval = TU_TO_TSF(ni->ni_intval);
358 * Call up first so subsequent work can use information
359 * potentially stored in the node (e.g. for ibss merge).
361 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rxs, rssi, nf);
363 case IEEE80211_FC0_SUBTYPE_BEACON:
366 * Only do the following processing if it's for
369 * In scan and IBSS mode we receive all beacons,
370 * which means we need to filter out stuff
371 * that isn't for us or we'll end up constantly
372 * trying to sync / merge to BSSes that aren't
375 if (IEEE80211_ADDR_EQ(ni->ni_bssid, vap->iv_bss->ni_bssid)) {
376 /* update rssi statistics for use by the hal */
377 /* XXX unlocked check against vap->iv_bss? */
378 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi);
381 tsf_beacon = ((uint64_t) le32dec(ni->ni_tstamp.data + 4)) << 32;
382 tsf_beacon |= le32dec(ni->ni_tstamp.data);
384 nexttbtt = ath_hal_getnexttbtt(sc->sc_ah);
387 * Let's calculate the delta and remainder, so we can see
388 * if the beacon timer from the AP is varying by more than
389 * a few TU. (Which would be a huge, huge problem.)
391 tsf_delta = (long long) tsf_beacon - (long long) tsf_beacon_old;
393 tsf_delta_bmiss = tsf_delta / tsf_intval;
396 * If our delta is greater than half the beacon interval,
397 * let's round the bmiss value up to the next beacon
398 * interval. Ie, we're running really, really early
399 * on the next beacon.
401 if (tsf_delta % tsf_intval > (tsf_intval / 2))
404 tsf_beacon_target = tsf_beacon_old +
405 (((unsigned long long) tsf_delta_bmiss) * (long long) tsf_intval);
408 * The remainder using '%' is between 0 .. intval-1.
409 * If we're actually running too fast, then the remainder
410 * will be some large number just under intval-1.
411 * So we need to look at whether we're running
412 * before or after the target beacon interval
413 * and if we are, modify how we do the remainder
416 if (tsf_beacon < tsf_beacon_target) {
418 -(tsf_intval - ((tsf_beacon - tsf_beacon_old) % tsf_intval));
420 tsf_remainder = (tsf_beacon - tsf_beacon_old) % tsf_intval;
423 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: old_tsf=%llu (%u), new_tsf=%llu (%u), target_tsf=%llu (%u), delta=%lld, bmiss=%d, remainder=%d\n",
425 (unsigned long long) tsf_beacon_old,
426 (unsigned int) (tsf_beacon_old >> 10),
427 (unsigned long long) tsf_beacon,
428 (unsigned int ) (tsf_beacon >> 10),
429 (unsigned long long) tsf_beacon_target,
430 (unsigned int) (tsf_beacon_target >> 10),
431 (long long) tsf_delta,
435 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: tsf=%llu (%u), nexttbtt=%llu (%u), delta=%d\n",
437 (unsigned long long) tsf_beacon,
438 (unsigned int) (tsf_beacon >> 10),
439 (unsigned long long) nexttbtt,
440 (unsigned int) (nexttbtt >> 10),
441 (int32_t) tsf_beacon - (int32_t) nexttbtt + tsf_intval);
443 /* We only do syncbeacon on STA VAPs; not on IBSS */
444 if (vap->iv_opmode == IEEE80211_M_STA &&
447 (vap->iv_state == IEEE80211_S_RUN || vap->iv_state == IEEE80211_S_SLEEP)) {
448 DPRINTF(sc, ATH_DEBUG_BEACON,
449 "%s: syncbeacon=1; syncing\n",
452 * Resync beacon timers using the tsf of the beacon
453 * frame we just received.
455 ath_beacon_config(sc, vap);
456 sc->sc_syncbeacon = 0;
461 case IEEE80211_FC0_SUBTYPE_PROBE_RESP:
462 if (vap->iv_opmode == IEEE80211_M_IBSS &&
463 vap->iv_state == IEEE80211_S_RUN &&
464 ieee80211_ibss_merge_check(ni)) {
465 uint32_t rstamp = sc->sc_lastrs->rs_tstamp;
466 uint64_t tsf = ath_extend_tsf(sc, rstamp,
467 ath_hal_gettsf64(sc->sc_ah));
469 * Handle ibss merge as needed; check the tsf on the
470 * frame before attempting the merge. The 802.11 spec
471 * says the station should change it's bssid to match
472 * the oldest station with the same ssid, where oldest
473 * is determined by the tsf. Note that hardware
474 * reconfiguration happens through callback to
475 * ath_newstate as the state machine will go from
476 * RUN -> RUN when this happens.
478 if (le64toh(ni->ni_tstamp.tsf) >= tsf) {
479 DPRINTF(sc, ATH_DEBUG_STATE,
480 "ibss merge, rstamp %u tsf %ju "
481 "tstamp %ju\n", rstamp, (uintmax_t)tsf,
482 (uintmax_t)ni->ni_tstamp.tsf);
483 (void) ieee80211_ibss_merge(ni);
490 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
492 ath_rx_tap_vendor(struct ath_softc *sc, struct mbuf *m,
493 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
496 /* Fill in the extension bitmap */
497 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER);
499 /* Fill in the vendor header */
500 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f;
501 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03;
502 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00;
504 /* XXX what should this be? */
505 sc->sc_rx_th.wr_vh.vh_sub_ns = 0;
506 sc->sc_rx_th.wr_vh.vh_skip_len =
507 htole16(sizeof(struct ath_radiotap_vendor_hdr));
509 /* General version info */
510 sc->sc_rx_th.wr_v.vh_version = 1;
512 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask;
515 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0];
516 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1];
517 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2];
518 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0];
519 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1];
520 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2];
523 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0;
524 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1;
525 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2;
526 /* These are only populated from the AR9300 or later */
527 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3;
528 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4;
531 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX;
534 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate;
537 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags;
540 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR;
542 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR;
545 if (rs->rs_status & HAL_RXERR_PHY) {
546 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr;
547 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR;
549 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff;
551 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status;
552 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi;
554 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
557 ath_rx_tap(struct ath_softc *sc, struct mbuf *m,
558 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf)
560 #define CHAN_HT20 htole32(IEEE80211_CHAN_HT20)
561 #define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U)
562 #define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D)
563 #define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D)
564 const HAL_RATE_TABLE *rt;
567 rt = sc->sc_currates;
568 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode));
569 rix = rt->rateCodeToIndex[rs->rs_rate];
570 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate;
571 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags;
572 #ifdef AH_SUPPORT_AR5416
573 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT;
574 if (rs->rs_status & HAL_RXERR_PHY) {
576 * PHY error - make sure the channel flags
577 * reflect the actual channel configuration,
578 * not the received frame.
580 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan))
581 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
582 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan))
583 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
584 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan))
585 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
586 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */
587 struct ieee80211com *ic = &sc->sc_ic;
589 if ((rs->rs_flags & HAL_RX_2040) == 0)
590 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20;
591 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan))
592 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U;
594 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D;
595 if ((rs->rs_flags & HAL_RX_GI) == 0)
596 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI;
600 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf));
601 if (rs->rs_status & HAL_RXERR_CRC)
602 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS;
603 /* XXX propagate other error flags from descriptor */
604 sc->sc_rx_th.wr_antnoise = nf;
605 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi;
606 sc->sc_rx_th.wr_antenna = rs->rs_antenna;
614 ath_handle_micerror(struct ieee80211com *ic,
615 struct ieee80211_frame *wh, int keyix)
617 struct ieee80211_node *ni;
619 /* XXX recheck MIC to deal w/ chips that lie */
620 /* XXX discard MIC errors on !data frames */
621 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh);
623 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix);
624 ieee80211_free_node(ni);
629 * Process a single packet.
631 * The mbuf must already be synced, unmapped and removed from bf->bf_m
634 * The mbuf must be consumed by this routine - either passed up the
635 * net80211 stack, put on the holding queue, or freed.
638 ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status,
639 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf,
643 /* XXX TODO: make this an mbuf tag? */
644 struct ieee80211_rx_stats rxs;
646 struct ieee80211com *ic = &sc->sc_ic;
647 struct ieee80211_node *ni;
649 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
652 * Calculate the correct 64 bit TSF given
653 * the TSF64 register value and rs_tstamp.
655 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf);
657 /* These aren't specifically errors */
658 #ifdef AH_SUPPORT_AR5416
659 if (rs->rs_flags & HAL_RX_GI)
660 sc->sc_stats.ast_rx_halfgi++;
661 if (rs->rs_flags & HAL_RX_2040)
662 sc->sc_stats.ast_rx_2040++;
663 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE)
664 sc->sc_stats.ast_rx_pre_crc_err++;
665 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST)
666 sc->sc_stats.ast_rx_post_crc_err++;
667 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY)
668 sc->sc_stats.ast_rx_decrypt_busy_err++;
669 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN)
670 sc->sc_stats.ast_rx_hi_rx_chain++;
671 if (rs->rs_flags & HAL_RX_STBC)
672 sc->sc_stats.ast_rx_stbc++;
673 #endif /* AH_SUPPORT_AR5416 */
675 if (rs->rs_status != 0) {
676 if (rs->rs_status & HAL_RXERR_CRC)
677 sc->sc_stats.ast_rx_crcerr++;
678 if (rs->rs_status & HAL_RXERR_FIFO)
679 sc->sc_stats.ast_rx_fifoerr++;
680 if (rs->rs_status & HAL_RXERR_PHY) {
681 sc->sc_stats.ast_rx_phyerr++;
682 /* Process DFS radar events */
683 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) ||
684 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) {
685 /* Now pass it to the radar processing code */
686 ath_dfs_process_phy_err(sc, m, rstamp, rs);
689 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */
690 if (rs->rs_phyerr < 64)
691 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++;
692 goto rx_error; /* NB: don't count in ierrors */
694 if (rs->rs_status & HAL_RXERR_DECRYPT) {
696 * Decrypt error. If the error occurred
697 * because there was no hardware key, then
698 * let the frame through so the upper layers
699 * can process it. This is necessary for 5210
700 * parts which have no way to setup a ``clear''
703 * XXX do key cache faulting
705 if (rs->rs_keyix == HAL_RXKEYIX_INVALID)
707 sc->sc_stats.ast_rx_badcrypt++;
710 * Similar as above - if the failure was a keymiss
711 * just punt it up to the upper layers for now.
713 if (rs->rs_status & HAL_RXERR_KEYMISS) {
714 sc->sc_stats.ast_rx_keymiss++;
717 if (rs->rs_status & HAL_RXERR_MIC) {
718 sc->sc_stats.ast_rx_badmic++;
720 * Do minimal work required to hand off
721 * the 802.11 header for notification.
723 /* XXX frag's and qos frames */
724 len = rs->rs_datalen;
725 if (len >= sizeof (struct ieee80211_frame)) {
726 ath_handle_micerror(ic,
727 mtod(m, struct ieee80211_frame *),
729 rs->rs_keyix-32 : rs->rs_keyix);
732 counter_u64_add(ic->ic_ierrors, 1);
735 * Cleanup any pending partial frame.
737 if (re->m_rxpending != NULL) {
738 m_freem(re->m_rxpending);
739 re->m_rxpending = NULL;
742 * When a tap is present pass error frames
743 * that have been requested. By default we
744 * pass decrypt+mic errors but others may be
745 * interesting (e.g. crc).
747 if (ieee80211_radiotap_active(ic) &&
748 (rs->rs_status & sc->sc_monpass)) {
749 /* NB: bpf needs the mbuf length setup */
750 len = rs->rs_datalen;
751 m->m_pkthdr.len = m->m_len = len;
752 ath_rx_tap(sc, m, rs, rstamp, nf);
753 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
754 ath_rx_tap_vendor(sc, m, rs, rstamp, nf);
755 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
756 ieee80211_radiotap_rx_all(ic, m);
758 /* XXX pass MIC errors up for s/w reclaculation */
759 m_freem(m); m = NULL;
763 len = rs->rs_datalen;
768 * Frame spans multiple descriptors; save
769 * it for the next completed descriptor, it
770 * will be used to construct a jumbogram.
772 if (re->m_rxpending != NULL) {
773 /* NB: max frame size is currently 2 clusters */
774 sc->sc_stats.ast_rx_toobig++;
775 m_freem(re->m_rxpending);
777 m->m_pkthdr.len = len;
781 } else if (re->m_rxpending != NULL) {
783 * This is the second part of a jumbogram,
784 * chain it to the first mbuf, adjust the
785 * frame length, and clear the rxpending state.
787 re->m_rxpending->m_next = m;
788 re->m_rxpending->m_pkthdr.len += len;
790 re->m_rxpending = NULL;
793 * Normal single-descriptor receive; setup packet length.
795 m->m_pkthdr.len = len;
799 * Validate rs->rs_antenna.
801 * Some users w/ AR9285 NICs have reported crashes
802 * here because rs_antenna field is bogusly large.
803 * Let's enforce the maximum antenna limit of 8
804 * (and it shouldn't be hard coded, but that's a
805 * separate problem) and if there's an issue, print
806 * out an error and adjust rs_antenna to something
809 * This code should be removed once the actual
810 * root cause of the issue has been identified.
811 * For example, it may be that the rs_antenna
812 * field is only valid for the last frame of
813 * an aggregate and it just happens that it is
814 * "mostly" right. (This is a general statement -
815 * the majority of the statistics are only valid
816 * for the last frame in an aggregate.
818 if (rs->rs_antenna > 7) {
819 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n",
820 __func__, rs->rs_antenna);
822 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
823 #endif /* ATH_DEBUG */
824 rs->rs_antenna = 0; /* XXX better than nothing */
828 * If this is an AR9285/AR9485, then the receive and LNA
829 * configuration is stored in RSSI[2] / EXTRSSI[2].
830 * We can extract this out to build a much better
831 * receive antenna profile.
833 * Yes, this just blurts over the above RX antenna field
834 * for now. It's fine, the AR9285 doesn't really use
837 * Later on we should store away the fine grained LNA
838 * information and keep separate counters just for
839 * that. It'll help when debugging the AR9285/AR9485
840 * combined diversity code.
842 if (sc->sc_rx_lnamixer) {
845 /* Bits 0:1 - the LNA configuration used */
847 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED)
848 >> HAL_RX_LNA_CFG_USED_S);
850 /* Bit 2 - the external RX antenna switch */
851 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG)
852 rs->rs_antenna |= 0x4;
855 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++;
858 * Populate the rx status block. When there are bpf
859 * listeners we do the additional work to provide
860 * complete status. Otherwise we fill in only the
861 * material required by ieee80211_input. Note that
862 * noise setting is filled in above.
864 if (ieee80211_radiotap_active(ic)) {
865 ath_rx_tap(sc, m, rs, rstamp, nf);
866 #ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT
867 ath_rx_tap_vendor(sc, m, rs, rstamp, nf);
868 #endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */
872 * From this point on we assume the frame is at least
873 * as large as ieee80211_frame_min; verify that.
875 if (len < IEEE80211_MIN_LEN) {
876 if (!ieee80211_radiotap_active(ic)) {
877 DPRINTF(sc, ATH_DEBUG_RECV,
878 "%s: short packet %d\n", __func__, len);
879 sc->sc_stats.ast_rx_tooshort++;
881 /* NB: in particular this captures ack's */
882 ieee80211_radiotap_rx_all(ic, m);
884 m_freem(m); m = NULL;
888 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) {
889 const HAL_RATE_TABLE *rt = sc->sc_currates;
890 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate];
892 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len,
893 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi);
896 m_adj(m, -IEEE80211_CRC_LEN);
899 * Locate the node for sender, track state, and then
900 * pass the (referenced) node up to the 802.11 layer
903 ni = ieee80211_find_rxnode_withkey(ic,
904 mtod(m, const struct ieee80211_frame_min *),
905 rs->rs_keyix == HAL_RXKEYIX_INVALID ?
906 IEEE80211_KEYIX_NONE : rs->rs_keyix);
909 #ifdef AH_SUPPORT_AR5416
911 sc->sc_stats.ast_rx_agg++;
912 #endif /* AH_SUPPORT_AR5416 */
916 * Populate the per-chain RSSI values where appropriate.
918 bzero(&rxs, sizeof(rxs));
919 rxs.r_flags |= IEEE80211_R_NF | IEEE80211_R_RSSI |
920 IEEE80211_R_C_CHAIN |
924 IEEE80211_R_TSF_START; /* XXX TODO: validate */
925 rxs.c_rssi = rs->rs_rssi;
927 rxs.c_chain = 3; /* XXX TODO: check */
928 rxs.c_rx_tsf = rstamp;
930 for (i = 0; i < 3; i++) {
931 rxs.c_rssi_ctl[i] = rs->rs_rssi_ctl[i];
932 rxs.c_rssi_ext[i] = rs->rs_rssi_ext[i];
934 * XXX note: we currently don't track
935 * per-chain noisefloor.
937 rxs.c_nf_ctl[i] = nf;
938 rxs.c_nf_ext[i] = nf;
943 * Only punt packets for ampdu reorder processing for
944 * 11n nodes; net80211 enforces that M_AMPDU is only
947 if (ni->ni_flags & IEEE80211_NODE_HT)
948 m->m_flags |= M_AMPDU;
951 * Sending station is known, dispatch directly.
953 (void) ieee80211_add_rx_params(m, &rxs);
954 type = ieee80211_input_mimo(ni, m);
955 ieee80211_free_node(ni);
958 * Arrange to update the last rx timestamp only for
959 * frames from our ap when operating in station mode.
960 * This assumes the rx key is always setup when
963 if (ic->ic_opmode == IEEE80211_M_STA &&
964 rs->rs_keyix != HAL_RXKEYIX_INVALID)
967 (void) ieee80211_add_rx_params(m, &rxs);
968 type = ieee80211_input_mimo_all(ic, m);
973 * At this point we have passed the frame up the stack; thus
974 * the mbuf is no longer ours.
978 * Track rx rssi and do any rx antenna management.
980 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi);
981 if (sc->sc_diversity) {
983 * When using fast diversity, change the default rx
984 * antenna if diversity chooses the other antenna 3
987 if (sc->sc_defant != rs->rs_antenna) {
988 if (++sc->sc_rxotherant >= 3)
989 ath_setdefantenna(sc, rs->rs_antenna);
991 sc->sc_rxotherant = 0;
994 /* Handle slow diversity if enabled */
995 if (sc->sc_dolnadiv) {
996 ath_lna_rx_comb_scan(sc, rs, ticks, hz);
999 if (sc->sc_softled) {
1001 * Blink for any data frame. Otherwise do a
1002 * heartbeat-style blink when idle. The latter
1003 * is mainly for station mode where we depend on
1004 * periodic beacon frames to trigger the poll event.
1006 if (type == IEEE80211_FC0_TYPE_DATA) {
1007 const HAL_RATE_TABLE *rt = sc->sc_currates;
1009 rt->rateCodeToIndex[rs->rs_rate]);
1010 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle)
1011 ath_led_event(sc, 0);
1015 * Debugging - complain if we didn't NULL the mbuf pointer
1019 device_printf(sc->sc_dev,
1020 "%s: mbuf %p should've been freed!\n",
1027 #define ATH_RX_MAX 128
1030 * XXX TODO: break out the "get buffers" from "call ath_rx_pkt()" like
1031 * the EDMA code does.
1033 * XXX TODO: then, do all of the RX list management stuff inside
1034 * ATH_RX_LOCK() so we don't end up potentially racing. The EDMA
1035 * code is doing it right.
1038 ath_rx_proc(struct ath_softc *sc, int resched)
1040 #define PA2DESC(_sc, _pa) \
1041 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
1042 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
1044 struct ath_hal *ah = sc->sc_ah;
1045 #ifdef IEEE80211_SUPPORT_SUPERG
1046 struct ieee80211com *ic = &sc->sc_ic;
1048 struct ath_desc *ds;
1049 struct ath_rx_status *rs;
1059 /* XXX we must not hold the ATH_LOCK here */
1060 ATH_UNLOCK_ASSERT(sc);
1061 ATH_PCU_UNLOCK_ASSERT(sc);
1064 sc->sc_rxproc_cnt++;
1065 kickpcu = sc->sc_kickpcu;
1069 ath_power_set_power_state(sc, HAL_PM_AWAKE);
1072 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__);
1074 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
1075 sc->sc_stats.ast_rx_noise = nf;
1076 tsf = ath_hal_gettsf64(ah);
1079 * Don't process too many packets at a time; give the
1080 * TX thread time to also run - otherwise the TX
1081 * latency can jump by quite a bit, causing throughput
1084 if (!kickpcu && npkts >= ATH_RX_MAX)
1087 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1088 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */
1089 device_printf(sc->sc_dev, "%s: no buffer!\n", __func__);
1091 } else if (bf == NULL) {
1094 * this can happen for non-self-linked RX chains
1096 sc->sc_stats.ast_rx_hitqueueend++;
1100 if (m == NULL) { /* NB: shouldn't happen */
1102 * If mbuf allocation failed previously there
1103 * will be no mbuf; try again to re-populate it.
1105 /* XXX make debug msg */
1106 device_printf(sc->sc_dev, "%s: no mbuf!\n", __func__);
1107 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
1111 if (ds->ds_link == bf->bf_daddr) {
1112 /* NB: never process the self-linked entry at the end */
1113 sc->sc_stats.ast_rx_hitqueueend++;
1116 /* XXX sync descriptor memory */
1118 * Must provide the virtual address of the current
1119 * descriptor, the physical address, and the virtual
1120 * address of the next descriptor in the h/w chain.
1121 * This allows the HAL to look ahead to see if the
1122 * hardware is done with a descriptor by checking the
1123 * done bit in the following descriptor and the address
1124 * of the current descriptor the DMA engine is working
1125 * on. All this is necessary because of our use of
1126 * a self-linked list to avoid rx overruns.
1128 rs = &bf->bf_status.ds_rxstat;
1129 status = ath_hal_rxprocdesc(ah, ds,
1130 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
1132 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
1133 ath_printrxbuf(sc, bf, 0, status == HAL_OK);
1136 #ifdef ATH_DEBUG_ALQ
1137 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS))
1138 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS,
1139 sc->sc_rx_statuslen, (char *) ds);
1140 #endif /* ATH_DEBUG_ALQ */
1142 if (status == HAL_EINPROGRESS)
1145 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
1149 * Process a single frame.
1151 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD);
1152 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
1154 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m))
1158 * If there's a holding buffer, insert that onto
1159 * the RX list; the hardware is now definitely not pointing
1163 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf != NULL) {
1164 TAILQ_INSERT_TAIL(&sc->sc_rxbuf,
1165 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf,
1167 ret = ath_rxbuf_init(sc,
1168 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf);
1171 * Next, throw our buffer into the holding entry. The hardware
1172 * may use the descriptor to read the link pointer before
1173 * DMAing the next descriptor in to write out a packet.
1175 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = bf;
1178 /* rx signal state monitoring */
1179 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
1181 sc->sc_lastrx = tsf;
1183 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood);
1184 /* Queue DFS tasklet if needed */
1185 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan))
1186 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
1189 * Now that all the RX frames were handled that
1190 * need to be handled, kick the PCU if there's
1191 * been an RXEOL condition.
1193 if (resched && kickpcu) {
1195 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu");
1196 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n",
1200 * Go through the process of fully tearing down
1201 * the RX buffers and reinitialising them.
1203 * There's a hardware bug that causes the RX FIFO
1204 * to get confused under certain conditions and
1205 * constantly write over the same frame, leading
1206 * the RX driver code here to get heavily confused.
1209 * XXX Has RX DMA stopped enough here to just call
1211 * XXX Do we need to use the holding buffer to restart
1212 * RX DMA by appending entries to the final
1213 * descriptor? Quite likely.
1219 * Disabled for now - it'd be nice to be able to do
1220 * this in order to limit the amount of CPU time spent
1221 * reinitialising the RX side (and thus minimise RX
1222 * drops) however there's a hardware issue that
1223 * causes things to get too far out of whack.
1226 * XXX can we hold the PCU lock here?
1227 * Are there any net80211 buffer calls involved?
1229 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1230 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
1231 ath_hal_rxena(ah); /* enable recv descriptors */
1232 ath_mode_init(sc); /* set filters, etc. */
1233 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
1236 ath_hal_intrset(ah, sc->sc_imask);
1241 #ifdef IEEE80211_SUPPORT_SUPERG
1243 ieee80211_ff_age_all(ic, 100);
1247 * Put the hardware to sleep again if we're done with it.
1250 ath_power_restore_power_state(sc);
1254 * If we hit the maximum number of frames in this round,
1255 * reschedule for another immediate pass. This gives
1256 * the TX and TX completion routines time to run, which
1257 * will reduce latency.
1259 if (npkts >= ATH_RX_MAX)
1260 sc->sc_rx.recv_sched(sc, resched);
1263 sc->sc_rxproc_cnt--;
1270 * Only run the RX proc if it's not already running.
1271 * Since this may get run as part of the reset/flush path,
1272 * the task can't clash with an existing, running tasklet.
1275 ath_legacy_rx_tasklet(void *arg, int npending)
1277 struct ath_softc *sc = arg;
1279 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending);
1280 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending);
1282 if (sc->sc_inreset_cnt > 0) {
1283 device_printf(sc->sc_dev,
1284 "%s: sc_inreset_cnt > 0; skipping\n", __func__);
1294 ath_legacy_flushrecv(struct ath_softc *sc)
1301 ath_legacy_flush_rxpending(struct ath_softc *sc)
1304 /* XXX ATH_RX_LOCK_ASSERT(sc); */
1306 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) {
1307 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
1308 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
1310 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) {
1311 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
1312 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
1317 ath_legacy_flush_rxholdbf(struct ath_softc *sc)
1321 /* XXX ATH_RX_LOCK_ASSERT(sc); */
1323 * If there are RX holding buffers, free them here and return
1326 * XXX should just verify that bf->bf_m is NULL, as it must
1329 bf = sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf;
1331 if (bf->bf_m != NULL)
1334 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
1335 (void) ath_rxbuf_init(sc, bf);
1337 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_holdbf = NULL;
1339 bf = sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf;
1341 if (bf->bf_m != NULL)
1344 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
1345 (void) ath_rxbuf_init(sc, bf);
1347 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_holdbf = NULL;
1353 * Disable the receive h/w in preparation for a reset.
1356 ath_legacy_stoprecv(struct ath_softc *sc, int dodelay)
1358 #define PA2DESC(_sc, _pa) \
1359 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
1360 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
1361 struct ath_hal *ah = sc->sc_ah;
1365 ath_hal_stoppcurecv(ah); /* disable PCU */
1366 ath_hal_setrxfilter(ah, 0); /* clear recv filter */
1367 ath_hal_stopdmarecv(ah); /* disable DMA engine */
1369 * TODO: see if this particular DELAY() is required; it may be
1370 * masking some missing FIFO flush or DMA sync.
1375 DELAY(3000); /* 3ms is long enough for 1 frame */
1377 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) {
1381 device_printf(sc->sc_dev,
1382 "%s: rx queue %p, link %p\n",
1384 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP),
1387 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1388 struct ath_desc *ds = bf->bf_desc;
1389 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat;
1390 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds,
1391 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs);
1392 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL))
1393 ath_printrxbuf(sc, bf, ix, status == HAL_OK);
1399 (void) ath_legacy_flush_rxpending(sc);
1400 (void) ath_legacy_flush_rxholdbf(sc);
1402 sc->sc_rxlink = NULL; /* just in case */
1409 * XXX TODO: something was calling startrecv without calling
1410 * stoprecv. Let's figure out what/why. It was showing up
1411 * as a mbuf leak (rxpending) and ath_buf leak (holdbf.)
1415 * Enable the receive h/w following a reset.
1418 ath_legacy_startrecv(struct ath_softc *sc)
1420 struct ath_hal *ah = sc->sc_ah;
1426 * XXX should verify these are already all NULL!
1428 sc->sc_rxlink = NULL;
1429 (void) ath_legacy_flush_rxpending(sc);
1430 (void) ath_legacy_flush_rxholdbf(sc);
1433 * Re-chain all of the buffers in the RX buffer list.
1435 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) {
1436 int error = ath_rxbuf_init(sc, bf);
1438 DPRINTF(sc, ATH_DEBUG_RECV,
1439 "%s: ath_rxbuf_init failed %d\n",
1445 bf = TAILQ_FIRST(&sc->sc_rxbuf);
1446 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP);
1447 ath_hal_rxena(ah); /* enable recv descriptors */
1448 ath_mode_init(sc); /* set filters, etc. */
1449 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */
1456 ath_legacy_dma_rxsetup(struct ath_softc *sc)
1460 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
1461 "rx", sizeof(struct ath_desc), ath_rxbuf, 1);
1469 ath_legacy_dma_rxteardown(struct ath_softc *sc)
1472 if (sc->sc_rxdma.dd_desc_len != 0)
1473 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
1478 ath_legacy_recv_sched(struct ath_softc *sc, int dosched)
1481 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1485 ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q,
1489 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
1493 ath_recv_setup_legacy(struct ath_softc *sc)
1496 /* Sensible legacy defaults */
1498 * XXX this should be changed to properly support the
1499 * exact RX descriptor size for each HAL.
1501 sc->sc_rx_statuslen = sizeof(struct ath_desc);
1503 sc->sc_rx.recv_start = ath_legacy_startrecv;
1504 sc->sc_rx.recv_stop = ath_legacy_stoprecv;
1505 sc->sc_rx.recv_flush = ath_legacy_flushrecv;
1506 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet;
1507 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init;
1509 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup;
1510 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown;
1511 sc->sc_rx.recv_sched = ath_legacy_recv_sched;
1512 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue;