2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for the Atheros Wireless LAN controller.
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
56 #include <sys/malloc.h>
58 #include <sys/mutex.h>
59 #include <sys/kernel.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/errno.h>
63 #include <sys/callout.h>
65 #include <sys/endian.h>
66 #include <sys/kthread.h>
67 #include <sys/taskqueue.h>
69 #include <sys/module.h>
71 #include <sys/smp.h> /* for mp_ncpus */
73 #include <machine/bus.h>
76 #include <net/if_var.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/if_types.h>
80 #include <net/if_arp.h>
81 #include <net/ethernet.h>
82 #include <net/if_llc.h>
84 #include <net80211/ieee80211_var.h>
85 #include <net80211/ieee80211_regdomain.h>
86 #ifdef IEEE80211_SUPPORT_SUPERG
87 #include <net80211/ieee80211_superg.h>
89 #ifdef IEEE80211_SUPPORT_TDMA
90 #include <net80211/ieee80211_tdma.h>
96 #include <netinet/in.h>
97 #include <netinet/if_ether.h>
100 #include <dev/ath/if_athvar.h>
101 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
102 #include <dev/ath/ath_hal/ah_diagcodes.h>
104 #include <dev/ath/if_ath_debug.h>
105 #include <dev/ath/if_ath_misc.h>
106 #include <dev/ath/if_ath_tsf.h>
107 #include <dev/ath/if_ath_tx.h>
108 #include <dev/ath/if_ath_sysctl.h>
109 #include <dev/ath/if_ath_led.h>
110 #include <dev/ath/if_ath_keycache.h>
111 #include <dev/ath/if_ath_rx.h>
112 #include <dev/ath/if_ath_beacon.h>
113 #include <dev/ath/if_athdfs.h>
116 #include <dev/ath/ath_tx99/ath_tx99.h>
119 #include <dev/ath/if_ath_rx_edma.h>
122 #include <dev/ath/if_ath_alq.h>
126 * some general macros
128 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
129 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
131 MALLOC_DECLARE(M_ATHDEV);
136 * + Make sure the FIFO is correctly flushed and reinitialised
138 * + Verify multi-descriptor frames work!
139 * + There's a "memory use after free" which needs to be tracked down
140 * and fixed ASAP. I've seen this in the legacy path too, so it
141 * may be a generic RX path issue.
145 * XXX shuffle the function orders so these pre-declarations aren't
148 static int ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype,
150 static int ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype);
151 static void ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf);
152 static void ath_edma_recv_proc_queue(struct ath_softc *sc,
153 HAL_RX_QUEUE qtype, int dosched);
154 static int ath_edma_recv_proc_deferred_queue(struct ath_softc *sc,
155 HAL_RX_QUEUE qtype, int dosched);
158 ath_edma_stoprecv(struct ath_softc *sc, int dodelay)
160 struct ath_hal *ah = sc->sc_ah;
164 ath_hal_stoppcurecv(ah);
165 ath_hal_setrxfilter(ah, 0);
170 if (ath_hal_stopdmarecv(ah) == AH_TRUE)
171 sc->sc_rx_stopped = 1;
174 * Give the various bus FIFOs (not EDMA descriptor FIFO)
175 * time to finish flushing out data.
179 /* Flush RX pending for each queue */
180 /* XXX should generic-ify this */
181 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending) {
182 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
183 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
186 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending) {
187 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
188 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
194 * Re-initialise the FIFO given the current buffer contents.
195 * Specifically, walk from head -> tail, pushing the FIFO contents
196 * back into the FIFO.
199 ath_edma_reinit_fifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
201 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
205 ATH_RX_LOCK_ASSERT(sc);
208 for (j = 0; j < re->m_fifo_depth; j++) {
210 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
211 "%s: Q%d: pos=%i, addr=0x%jx\n",
215 (uintmax_t)bf->bf_daddr);
216 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
217 INCR(i, re->m_fifolen);
220 /* Ensure this worked out right */
221 if (i != re->m_fifo_tail) {
222 device_printf(sc->sc_dev, "%s: i (%d) != tail! (%d)\n",
233 ath_edma_startrecv(struct ath_softc *sc)
235 struct ath_hal *ah = sc->sc_ah;
240 * Sanity check - are we being called whilst RX
241 * isn't stopped? If so, we may end up pushing
242 * too many entries into the RX FIFO and
250 * In theory the hardware has been initialised, right?
252 if (sc->sc_rx_resetted == 1) {
253 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
254 "%s: Re-initing HP FIFO\n", __func__);
255 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_HP);
256 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
257 "%s: Re-initing LP FIFO\n", __func__);
258 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_LP);
259 sc->sc_rx_resetted = 0;
261 device_printf(sc->sc_dev,
262 "%s: called without resetting chip?\n",
266 /* Add up to m_fifolen entries in each queue */
268 * These must occur after the above write so the FIFO buffers
269 * are pushed/tracked in the same order as the hardware will
272 * XXX TODO: is this really necessary? We should've stopped
273 * the hardware already and reinitialised it, so it's a no-op.
275 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_HP,
276 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_fifolen);
278 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_LP,
279 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_fifolen);
282 ath_hal_startpcurecv(ah);
285 * We're now doing RX DMA!
287 sc->sc_rx_stopped = 0;
295 ath_edma_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
300 ath_power_set_power_state(sc, HAL_PM_AWAKE);
303 ath_edma_recv_proc_queue(sc, qtype, dosched);
306 ath_power_restore_power_state(sc);
309 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
313 ath_edma_recv_sched(struct ath_softc *sc, int dosched)
317 ath_power_set_power_state(sc, HAL_PM_AWAKE);
320 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, dosched);
321 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, dosched);
324 ath_power_restore_power_state(sc);
327 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
331 ath_edma_recv_flush(struct ath_softc *sc)
334 DPRINTF(sc, ATH_DEBUG_RECV, "%s: called\n", __func__);
341 ath_power_set_power_state(sc, HAL_PM_AWAKE);
345 * Flush any active frames from FIFO -> deferred list
347 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 0);
348 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 0);
351 * Process what's in the deferred queue
354 * XXX: If we read the tsf/channoise here and then pass it in,
355 * we could restore the power state before processing
356 * the deferred queue.
358 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_HP, 0);
359 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_LP, 0);
362 ath_power_restore_power_state(sc);
371 * Process frames from the current queue into the deferred queue.
374 ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
377 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
378 struct ath_rx_status *rs;
382 struct ath_hal *ah = sc->sc_ah;
387 tsf = ath_hal_gettsf64(ah);
388 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
389 sc->sc_stats.ast_rx_noise = nf;
394 if (sc->sc_rx_resetted == 1) {
396 * XXX We shouldn't ever be scheduled if
397 * receive has been stopped - so complain
400 device_printf(sc->sc_dev,
401 "%s: sc_rx_resetted=1! Bad!\n",
409 bf = re->m_fifo[re->m_fifo_head];
410 /* This shouldn't occur! */
412 device_printf(sc->sc_dev, "%s: Q%d: NULL bf?\n",
421 * Sync descriptor memory - this also syncs the buffer for us.
422 * EDMA descriptors are in cached memory.
424 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
425 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
426 rs = &bf->bf_status.ds_rxstat;
427 bf->bf_rxstatus = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr,
430 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
431 ath_printrxbuf(sc, bf, 0, bf->bf_rxstatus == HAL_OK);
432 #endif /* ATH_DEBUG */
434 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS))
435 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS,
436 sc->sc_rx_statuslen, (char *) ds);
437 #endif /* ATH_DEBUG */
438 if (bf->bf_rxstatus == HAL_EINPROGRESS)
442 * Completed descriptor.
444 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
445 "%s: Q%d: completed!\n", __func__, qtype);
449 * We've been synced already, so unmap.
451 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
454 * Remove the FIFO entry and place it on the completion
457 re->m_fifo[re->m_fifo_head] = NULL;
458 TAILQ_INSERT_TAIL(&sc->sc_rx_rxlist[qtype], bf, bf_list);
460 /* Bump the descriptor FIFO stats */
461 INCR(re->m_fifo_head, re->m_fifolen);
463 /* XXX check it doesn't fall below 0 */
464 } while (re->m_fifo_depth > 0);
466 /* Append some more fresh frames to the FIFO */
468 ath_edma_rxfifo_alloc(sc, qtype, re->m_fifolen);
472 /* rx signal state monitoring */
473 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
475 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1,
476 "ath edma rx proc: npkts=%d\n",
483 * Flush the deferred queue.
485 * This destructively flushes the deferred queue - it doesn't
486 * call the wireless stack on each mbuf.
489 ath_edma_flush_deferred_queue(struct ath_softc *sc)
493 ATH_RX_LOCK_ASSERT(sc);
495 /* Free in one set, inside the lock */
496 while (! TAILQ_EMPTY(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP])) {
497 bf = TAILQ_FIRST(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP]);
498 TAILQ_REMOVE(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP], bf, bf_list);
499 /* Free the buffer/mbuf */
500 ath_edma_rxbuf_free(sc, bf);
502 while (! TAILQ_EMPTY(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP])) {
503 bf = TAILQ_FIRST(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP]);
504 TAILQ_REMOVE(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP], bf, bf_list);
505 /* Free the buffer/mbuf */
506 ath_edma_rxbuf_free(sc, bf);
511 ath_edma_recv_proc_deferred_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
516 struct ath_buf *bf, *next;
517 struct ath_rx_status *rs;
524 nf = ath_hal_getchannoise(sc->sc_ah, sc->sc_curchan);
526 * XXX TODO: the NF/TSF should be stamped on the bufs themselves,
527 * otherwise we may end up adding in the wrong values if this
528 * is delayed too far..
530 tsf = ath_hal_gettsf64(sc->sc_ah);
532 /* Copy the list over */
534 TAILQ_CONCAT(&rxlist, &sc->sc_rx_rxlist[qtype], bf_list);
537 /* Handle the completed descriptors */
539 * XXX is this SAFE call needed? The ath_buf entries
540 * aren't modified by ath_rx_pkt, right?
542 TAILQ_FOREACH_SAFE(bf, &rxlist, bf_list, next) {
544 * Skip the RX descriptor status - start at the data offset
546 m_adj(bf->bf_m, sc->sc_rx_statuslen);
548 /* Handle the frame */
550 rs = &bf->bf_status.ds_rxstat;
553 if (ath_rx_pkt(sc, rs, bf->bf_rxstatus, tsf, nf, qtype, bf, m))
561 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1,
562 "ath edma rx deferred proc: ngood=%d\n",
565 /* Free in one set, inside the lock */
567 while (! TAILQ_EMPTY(&rxlist)) {
568 bf = TAILQ_FIRST(&rxlist);
569 TAILQ_REMOVE(&rxlist, bf, bf_list);
570 /* Free the buffer/mbuf */
571 ath_edma_rxbuf_free(sc, bf);
579 ath_edma_recv_tasklet(void *arg, int npending)
581 struct ath_softc *sc = (struct ath_softc *) arg;
582 #ifdef IEEE80211_SUPPORT_SUPERG
583 struct ieee80211com *ic = &sc->sc_ic;
586 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: called; npending=%d\n",
591 if (sc->sc_inreset_cnt > 0) {
592 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; skipping\n",
601 ath_power_set_power_state(sc, HAL_PM_AWAKE);
604 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 1);
605 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 1);
607 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_HP, 1);
608 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_LP, 1);
611 * XXX: If we read the tsf/channoise here and then pass it in,
612 * we could restore the power state before processing
613 * the deferred queue.
616 ath_power_restore_power_state(sc);
619 #ifdef IEEE80211_SUPPORT_SUPERG
620 ieee80211_ff_age_all(ic, 100);
622 if (ath_dfs_tasklet_needed(sc, sc->sc_curchan))
623 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
631 * Allocate an RX mbuf for the given ath_buf and initialise
634 * + Allocate a 4KB mbuf;
635 * + Setup the DMA map for the given buffer;
639 ath_edma_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
646 ATH_RX_LOCK_ASSERT(sc);
648 m = m_getm(NULL, sc->sc_edma_bufsize, M_NOWAIT, MT_DATA);
650 return (ENOBUFS); /* XXX ?*/
652 /* XXX warn/enforce alignment */
654 len = m->m_ext.ext_size;
656 device_printf(sc->sc_dev, "%s: called: m=%p, size=%d, mtod=%p\n",
663 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
666 * Populate ath_buf fields.
668 bf->bf_desc = mtod(m, struct ath_desc *);
669 bf->bf_lastds = bf->bf_desc; /* XXX only really for TX? */
673 * Zero the descriptor and ensure it makes it out to the
674 * bounce buffer if one is required.
676 * XXX PREWRITE will copy the whole buffer; we only needed it
677 * to sync the first 32 DWORDS. Oh well.
679 memset(bf->bf_desc, '\0', sc->sc_rx_statuslen);
682 * Create DMA mapping.
684 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
685 bf->bf_dmamap, m, bf->bf_segs, &bf->bf_nseg, BUS_DMA_NOWAIT);
688 device_printf(sc->sc_dev, "%s: failed; error=%d\n",
696 * Set daddr to the physical mapping page.
698 bf->bf_daddr = bf->bf_segs[0].ds_addr;
701 * Prepare for the upcoming read.
703 * We need to both sync some data into the buffer (the zero'ed
704 * descriptor payload) and also prepare for the read that's going
707 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
708 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
715 * Allocate a RX buffer.
717 static struct ath_buf *
718 ath_edma_rxbuf_alloc(struct ath_softc *sc)
723 ATH_RX_LOCK_ASSERT(sc);
725 /* Allocate buffer */
726 bf = TAILQ_FIRST(&sc->sc_rxbuf);
727 /* XXX shouldn't happen upon startup? */
729 device_printf(sc->sc_dev, "%s: nothing on rxbuf?!\n",
734 /* Remove it from the free list */
735 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
737 /* Assign RX mbuf to it */
738 error = ath_edma_rxbuf_init(sc, bf);
740 device_printf(sc->sc_dev,
741 "%s: bf=%p, rxbuf alloc failed! error=%d\n",
745 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
753 ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf)
756 ATH_RX_LOCK_ASSERT(sc);
759 * Only unload the frame if we haven't consumed
760 * the mbuf via ath_rx_pkt().
763 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
769 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
773 * Allocate up to 'n' entries and push them onto the hardware FIFO.
775 * Return how many entries were successfully pushed onto the
779 ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype, int nbufs)
781 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
785 ATH_RX_LOCK_ASSERT(sc);
788 * Allocate buffers until the FIFO is full or nbufs is reached.
790 for (i = 0; i < nbufs && re->m_fifo_depth < re->m_fifolen; i++) {
791 /* Ensure the FIFO is already blank, complain loudly! */
792 if (re->m_fifo[re->m_fifo_tail] != NULL) {
793 device_printf(sc->sc_dev,
794 "%s: Q%d: fifo[%d] != NULL (%p)\n",
798 re->m_fifo[re->m_fifo_tail]);
801 ath_edma_rxbuf_free(sc, re->m_fifo[re->m_fifo_tail]);
803 /* XXX check it's not < 0 */
804 re->m_fifo[re->m_fifo_tail] = NULL;
807 bf = ath_edma_rxbuf_alloc(sc);
808 /* XXX should ensure the FIFO is not NULL? */
810 device_printf(sc->sc_dev,
811 "%s: Q%d: alloc failed: i=%d, nbufs=%d?\n",
819 re->m_fifo[re->m_fifo_tail] = bf;
821 /* Write to the RX FIFO */
822 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
823 "%s: Q%d: putrxbuf=%p (0x%jx)\n",
827 (uintmax_t) bf->bf_daddr);
828 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
831 INCR(re->m_fifo_tail, re->m_fifolen);
835 * Return how many were allocated.
837 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: nbufs=%d, nalloced=%d\n",
846 ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype)
848 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
851 ATH_RX_LOCK_ASSERT(sc);
853 for (i = 0; i < re->m_fifolen; i++) {
854 if (re->m_fifo[i] != NULL) {
856 struct ath_buf *bf = re->m_fifo[i];
858 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
859 ath_printrxbuf(sc, bf, 0, HAL_OK);
861 ath_edma_rxbuf_free(sc, re->m_fifo[i]);
862 re->m_fifo[i] = NULL;
867 if (re->m_rxpending != NULL) {
868 m_freem(re->m_rxpending);
869 re->m_rxpending = NULL;
871 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
877 * Setup the initial RX FIFO structure.
880 ath_edma_setup_rxfifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
882 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
884 ATH_RX_LOCK_ASSERT(sc);
886 if (! ath_hal_getrxfifodepth(sc->sc_ah, qtype, &re->m_fifolen)) {
887 device_printf(sc->sc_dev, "%s: qtype=%d, failed\n",
894 device_printf(sc->sc_dev,
895 "%s: type=%d, FIFO depth = %d entries\n",
900 /* Allocate ath_buf FIFO array, pre-zero'ed */
901 re->m_fifo = malloc(sizeof(struct ath_buf *) * re->m_fifolen,
904 if (re->m_fifo == NULL) {
905 device_printf(sc->sc_dev, "%s: malloc failed\n",
911 * Set initial "empty" state.
913 re->m_rxpending = NULL;
914 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
920 ath_edma_rxfifo_free(struct ath_softc *sc, HAL_RX_QUEUE qtype)
922 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
924 device_printf(sc->sc_dev, "%s: called; qtype=%d\n",
928 free(re->m_fifo, M_ATHDEV);
934 ath_edma_dma_rxsetup(struct ath_softc *sc)
939 * Create RX DMA tag and buffers.
941 error = ath_descdma_setup_rx_edma(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
942 "rx", ath_rxbuf, sc->sc_rx_statuslen);
947 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_HP);
948 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_LP);
955 ath_edma_dma_rxteardown(struct ath_softc *sc)
959 ath_edma_flush_deferred_queue(sc);
960 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_HP);
961 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_HP);
963 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_LP);
964 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_LP);
967 /* Free RX ath_buf */
968 /* Free RX DMA tag */
969 if (sc->sc_rxdma.dd_desc_len != 0)
970 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
976 ath_recv_setup_edma(struct ath_softc *sc)
979 /* Set buffer size to 4k */
980 sc->sc_edma_bufsize = 4096;
982 /* Fetch EDMA field and buffer sizes */
983 (void) ath_hal_getrxstatuslen(sc->sc_ah, &sc->sc_rx_statuslen);
985 /* Configure the hardware with the RX buffer size */
986 (void) ath_hal_setrxbufsize(sc->sc_ah, sc->sc_edma_bufsize -
987 sc->sc_rx_statuslen);
990 device_printf(sc->sc_dev, "RX status length: %d\n",
991 sc->sc_rx_statuslen);
992 device_printf(sc->sc_dev, "RX buffer size: %d\n",
993 sc->sc_edma_bufsize);
996 sc->sc_rx.recv_stop = ath_edma_stoprecv;
997 sc->sc_rx.recv_start = ath_edma_startrecv;
998 sc->sc_rx.recv_flush = ath_edma_recv_flush;
999 sc->sc_rx.recv_tasklet = ath_edma_recv_tasklet;
1000 sc->sc_rx.recv_rxbuf_init = ath_edma_rxbuf_init;
1002 sc->sc_rx.recv_setup = ath_edma_dma_rxsetup;
1003 sc->sc_rx.recv_teardown = ath_edma_dma_rxteardown;
1005 sc->sc_rx.recv_sched = ath_edma_recv_sched;
1006 sc->sc_rx.recv_sched_queue = ath_edma_recv_sched_queue;