2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for the Atheros Wireless LAN controller.
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
56 #include <sys/malloc.h>
58 #include <sys/mutex.h>
59 #include <sys/kernel.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/errno.h>
63 #include <sys/callout.h>
65 #include <sys/endian.h>
66 #include <sys/kthread.h>
67 #include <sys/taskqueue.h>
69 #include <sys/module.h>
71 #include <sys/smp.h> /* for mp_ncpus */
73 #include <machine/bus.h>
76 #include <net/if_dl.h>
77 #include <net/if_media.h>
78 #include <net/if_types.h>
79 #include <net/if_arp.h>
80 #include <net/ethernet.h>
81 #include <net/if_llc.h>
83 #include <net80211/ieee80211_var.h>
84 #include <net80211/ieee80211_regdomain.h>
85 #ifdef IEEE80211_SUPPORT_SUPERG
86 #include <net80211/ieee80211_superg.h>
88 #ifdef IEEE80211_SUPPORT_TDMA
89 #include <net80211/ieee80211_tdma.h>
95 #include <netinet/in.h>
96 #include <netinet/if_ether.h>
99 #include <dev/ath/if_athvar.h>
100 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
101 #include <dev/ath/ath_hal/ah_diagcodes.h>
103 #include <dev/ath/if_ath_debug.h>
104 #include <dev/ath/if_ath_misc.h>
105 #include <dev/ath/if_ath_tsf.h>
106 #include <dev/ath/if_ath_tx.h>
107 #include <dev/ath/if_ath_sysctl.h>
108 #include <dev/ath/if_ath_led.h>
109 #include <dev/ath/if_ath_keycache.h>
110 #include <dev/ath/if_ath_rx.h>
111 #include <dev/ath/if_ath_beacon.h>
112 #include <dev/ath/if_athdfs.h>
115 #include <dev/ath/ath_tx99/ath_tx99.h>
118 #include <dev/ath/if_ath_rx_edma.h>
121 #include <dev/ath/if_ath_alq.h>
125 * some general macros
127 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
128 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
130 MALLOC_DECLARE(M_ATHDEV);
135 * + Add an RX lock, just to ensure we don't have things clash;
136 * + Make sure the FIFO is correctly flushed and reinitialised
138 * + Handle the "kickpcu" state where the FIFO overflows.
139 * + Implement a "flush" routine, which doesn't push any
140 * new frames into the FIFO.
141 * + Verify multi-descriptor frames work!
142 * + There's a "memory use after free" which needs to be tracked down
143 * and fixed ASAP. I've seen this in the legacy path too, so it
144 * may be a generic RX path issue.
148 * XXX shuffle the function orders so these pre-declarations aren't
151 static int ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype,
153 static int ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype);
154 static void ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf);
155 static int ath_edma_recv_proc_queue(struct ath_softc *sc,
156 HAL_RX_QUEUE qtype, int dosched);
159 ath_edma_stoprecv(struct ath_softc *sc, int dodelay)
161 struct ath_hal *ah = sc->sc_ah;
164 ath_hal_stoppcurecv(ah);
165 ath_hal_setrxfilter(ah, 0);
166 ath_hal_stopdmarecv(ah);
170 /* Flush RX pending for each queue */
171 /* XXX should generic-ify this */
172 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending) {
173 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
174 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
177 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending) {
178 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
179 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
185 * Re-initialise the FIFO given the current buffer contents.
186 * Specifically, walk from head -> tail, pushing the FIFO contents
187 * back into the FIFO.
190 ath_edma_reinit_fifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
192 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
196 ATH_RX_LOCK_ASSERT(sc);
199 for (j = 0; j < re->m_fifo_depth; j++) {
201 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
202 "%s: Q%d: pos=%i, addr=0x%jx\n",
206 (uintmax_t)bf->bf_daddr);
207 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
208 INCR(i, re->m_fifolen);
211 /* Ensure this worked out right */
212 if (i != re->m_fifo_tail) {
213 device_printf(sc->sc_dev, "%s: i (%d) != tail! (%d)\n",
223 * XXX TODO: this needs to reallocate the FIFO entries when a reset
224 * occurs, in case the FIFO is filled up and no new descriptors get
225 * thrown into the FIFO.
228 ath_edma_startrecv(struct ath_softc *sc)
230 struct ath_hal *ah = sc->sc_ah;
238 * Entries should only be written out if the
241 * XXX This isn't correct. I should be looking
242 * at the value of AR_RXDP_SIZE (0x0070) to determine
243 * how many entries are in here.
245 * A warm reset will clear the registers but not the FIFO.
247 * And I believe this is actually the address of the last
248 * handled buffer rather than the current FIFO pointer.
249 * So if no frames have been (yet) seen, we'll reinit the
252 * I'll chase that up at some point.
254 if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_HP) == 0) {
255 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
256 "%s: Re-initing HP FIFO\n", __func__);
257 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_HP);
259 if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_LP) == 0) {
260 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
261 "%s: Re-initing LP FIFO\n", __func__);
262 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_LP);
265 /* Add up to m_fifolen entries in each queue */
267 * These must occur after the above write so the FIFO buffers
268 * are pushed/tracked in the same order as the hardware will
271 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_HP,
272 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_fifolen);
274 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_LP,
275 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_fifolen);
278 ath_hal_startpcurecv(ah);
286 ath_edma_recv_flush(struct ath_softc *sc)
289 DPRINTF(sc, ATH_DEBUG_RECV, "%s: called\n", __func__);
295 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 0);
296 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 0);
304 * Process frames from the current queue.
308 * + Add a "dosched" flag, so we don't reschedule any FIFO frames
309 * to the hardware or re-kick the PCU after 'kickpcu' is set.
311 * + Perhaps split "check FIFO contents" and "handle frames", so
312 * we can run the "check FIFO contents" in ath_intr(), but
313 * "handle frames" in the RX tasklet.
316 ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
319 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
320 struct ath_rx_status *rs;
324 struct ath_hal *ah = sc->sc_ah;
327 int ngood = 0, npkts = 0;
329 struct ath_buf *next;
333 tsf = ath_hal_gettsf64(ah);
334 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
335 sc->sc_stats.ast_rx_noise = nf;
340 bf = re->m_fifo[re->m_fifo_head];
341 /* This shouldn't occur! */
343 device_printf(sc->sc_dev, "%s: Q%d: NULL bf?\n",
352 * Sync descriptor memory - this also syncs the buffer for us.
354 * EDMA descriptors are in cached memory.
356 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
357 BUS_DMASYNC_POSTREAD);
358 rs = &bf->bf_status.ds_rxstat;
359 bf->bf_rxstatus = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr,
362 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
363 ath_printrxbuf(sc, bf, 0, bf->bf_rxstatus == HAL_OK);
364 #endif /* ATH_DEBUG */
366 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS))
367 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS,
368 sc->sc_rx_statuslen, (char *) ds);
369 #endif /* ATH_DEBUG */
370 if (bf->bf_rxstatus == HAL_EINPROGRESS)
374 * Completed descriptor.
376 * In the future we'll call ath_rx_pkt(), but it first
377 * has to be taught about EDMA RX queues (so it can
378 * access sc_rxpending correctly.)
380 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
381 "%s: Q%d: completed!\n", __func__, qtype);
385 * Remove the FIFO entry and place it on the completion
388 re->m_fifo[re->m_fifo_head] = NULL;
389 TAILQ_INSERT_TAIL(&rxlist, bf, bf_list);
391 /* Bump the descriptor FIFO stats */
392 INCR(re->m_fifo_head, re->m_fifolen);
394 /* XXX check it doesn't fall below 0 */
395 } while (re->m_fifo_depth > 0);
397 /* Append some more fresh frames to the FIFO */
399 ath_edma_rxfifo_alloc(sc, qtype, re->m_fifolen);
403 /* Handle the completed descriptors */
404 TAILQ_FOREACH_SAFE(bf, &rxlist, bf_list, next) {
406 * Skip the RX descriptor status - start at the data offset
408 m_adj(bf->bf_m, sc->sc_rx_statuslen);
410 /* Handle the frame */
412 * Note: this may or may not free bf->bf_m and sync/unmap
415 rs = &bf->bf_status.ds_rxstat;
416 if (ath_rx_pkt(sc, rs, bf->bf_rxstatus, tsf, nf, qtype, bf))
420 /* Free in one set, inside the lock */
422 TAILQ_FOREACH_SAFE(bf, &rxlist, bf_list, next) {
423 /* Free the buffer/mbuf */
424 ath_edma_rxbuf_free(sc, bf);
428 /* rx signal state monitoring */
429 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
433 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 2,
434 "ath edma rx proc: npkts=%d, ngood=%d",
437 /* Handle resched and kickpcu appropriately */
439 if (dosched && sc->sc_kickpcu) {
440 ATH_KTR(sc, ATH_KTR_ERROR, 0,
441 "ath_edma_recv_proc_queue(): kickpcu");
442 device_printf(sc->sc_dev,
443 "%s: handled npkts %d ngood %d\n",
444 __func__, npkts, ngood);
447 * XXX TODO: what should occur here? Just re-poke and
448 * re-enable the RX FIFO?
458 ath_edma_recv_tasklet(void *arg, int npending)
460 struct ath_softc *sc = (struct ath_softc *) arg;
461 struct ifnet *ifp = sc->sc_ifp;
462 #ifdef IEEE80211_SUPPORT_SUPERG
463 struct ieee80211com *ic = ifp->if_l2com;
466 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: called; npending=%d\n",
471 if (sc->sc_inreset_cnt > 0) {
472 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; skipping\n",
480 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 1);
481 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 1);
483 /* XXX inside IF_LOCK ? */
484 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
485 #ifdef IEEE80211_SUPPORT_SUPERG
486 ieee80211_ff_age_all(ic, 100);
488 if (! IFQ_IS_EMPTY(&ifp->if_snd))
491 if (ath_dfs_tasklet_needed(sc, sc->sc_curchan))
492 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
500 * Allocate an RX mbuf for the given ath_buf and initialise
503 * + Allocate a 4KB mbuf;
504 * + Setup the DMA map for the given buffer;
505 * + Keep a pointer to the start of the mbuf - that's where the
507 * + Take a pointer to the start of the RX buffer, set the
508 * mbuf "start" to be there;
512 ath_edma_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
519 ATH_RX_LOCK_ASSERT(sc);
521 m = m_getm(NULL, sc->sc_edma_bufsize, M_NOWAIT, MT_DATA);
523 return (ENOBUFS); /* XXX ?*/
525 /* XXX warn/enforce alignment */
527 len = m->m_ext.ext_size;
529 device_printf(sc->sc_dev, "%s: called: m=%p, size=%d, mtod=%p\n",
536 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
539 * Create DMA mapping.
541 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
542 bf->bf_dmamap, m, bf->bf_segs, &bf->bf_nseg, BUS_DMA_NOWAIT);
544 device_printf(sc->sc_dev, "%s: failed; error=%d\n",
552 * Populate ath_buf fields.
555 bf->bf_desc = mtod(m, struct ath_desc *);
556 bf->bf_daddr = bf->bf_segs[0].ds_addr;
557 bf->bf_lastds = bf->bf_desc; /* XXX only really for TX? */
560 /* Zero the descriptor */
561 memset(bf->bf_desc, '\0', sc->sc_rx_statuslen);
565 * Adjust mbuf header and length/size to compensate for the
568 m_adj(m, sc->sc_rx_statuslen);
576 static struct ath_buf *
577 ath_edma_rxbuf_alloc(struct ath_softc *sc)
582 ATH_RX_LOCK_ASSERT(sc);
584 /* Allocate buffer */
585 bf = TAILQ_FIRST(&sc->sc_rxbuf);
586 /* XXX shouldn't happen upon startup? */
590 /* Remove it from the free list */
591 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
593 /* Assign RX mbuf to it */
594 error = ath_edma_rxbuf_init(sc, bf);
596 device_printf(sc->sc_dev,
597 "%s: bf=%p, rxbuf alloc failed! error=%d\n",
601 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
609 ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf)
612 ATH_RX_LOCK_ASSERT(sc);
614 /* We're doing this multiple times? */
615 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
623 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
627 * Allocate up to 'n' entries and push them onto the hardware FIFO.
629 * Return how many entries were successfully pushed onto the
633 ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype, int nbufs)
635 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
639 ATH_RX_LOCK_ASSERT(sc);
642 * Allocate buffers until the FIFO is full or nbufs is reached.
644 for (i = 0; i < nbufs && re->m_fifo_depth < re->m_fifolen; i++) {
645 /* Ensure the FIFO is already blank, complain loudly! */
646 if (re->m_fifo[re->m_fifo_tail] != NULL) {
647 device_printf(sc->sc_dev,
648 "%s: Q%d: fifo[%d] != NULL (%p)\n",
652 re->m_fifo[re->m_fifo_tail]);
655 ath_edma_rxbuf_free(sc, re->m_fifo[re->m_fifo_tail]);
657 /* XXX check it's not < 0 */
658 re->m_fifo[re->m_fifo_tail] = NULL;
661 bf = ath_edma_rxbuf_alloc(sc);
662 /* XXX should ensure the FIFO is not NULL? */
664 device_printf(sc->sc_dev, "%s: Q%d: alloc failed?\n",
670 re->m_fifo[re->m_fifo_tail] = bf;
673 * Flush the descriptor contents before it's handed to the
676 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
677 BUS_DMASYNC_PREREAD);
679 /* Write to the RX FIFO */
680 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: putrxbuf=%p\n",
684 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
687 INCR(re->m_fifo_tail, re->m_fifolen);
691 * Return how many were allocated.
693 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: nbufs=%d, nalloced=%d\n",
702 ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype)
704 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
707 ATH_RX_LOCK_ASSERT(sc);
709 for (i = 0; i < re->m_fifolen; i++) {
710 if (re->m_fifo[i] != NULL) {
712 struct ath_buf *bf = re->m_fifo[i];
714 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
715 ath_printrxbuf(sc, bf, 0, HAL_OK);
717 ath_edma_rxbuf_free(sc, re->m_fifo[i]);
718 re->m_fifo[i] = NULL;
723 if (re->m_rxpending != NULL) {
724 m_freem(re->m_rxpending);
725 re->m_rxpending = NULL;
727 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
733 * Setup the initial RX FIFO structure.
736 ath_edma_setup_rxfifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
738 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
740 ATH_RX_LOCK_ASSERT(sc);
742 if (! ath_hal_getrxfifodepth(sc->sc_ah, qtype, &re->m_fifolen)) {
743 device_printf(sc->sc_dev, "%s: qtype=%d, failed\n",
748 device_printf(sc->sc_dev, "%s: type=%d, FIFO depth = %d entries\n",
753 /* Allocate ath_buf FIFO array, pre-zero'ed */
754 re->m_fifo = malloc(sizeof(struct ath_buf *) * re->m_fifolen,
757 if (re->m_fifo == NULL) {
758 device_printf(sc->sc_dev, "%s: malloc failed\n",
764 * Set initial "empty" state.
766 re->m_rxpending = NULL;
767 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
773 ath_edma_rxfifo_free(struct ath_softc *sc, HAL_RX_QUEUE qtype)
775 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
777 device_printf(sc->sc_dev, "%s: called; qtype=%d\n",
781 free(re->m_fifo, M_ATHDEV);
787 ath_edma_dma_rxsetup(struct ath_softc *sc)
792 * Create RX DMA tag and buffers.
794 error = ath_descdma_setup_rx_edma(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
795 "rx", ath_rxbuf, sc->sc_rx_statuslen);
800 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_HP);
801 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_LP);
808 ath_edma_dma_rxteardown(struct ath_softc *sc)
812 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_HP);
813 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_HP);
815 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_LP);
816 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_LP);
819 /* Free RX ath_buf */
820 /* Free RX DMA tag */
821 if (sc->sc_rxdma.dd_desc_len != 0)
822 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
828 ath_recv_setup_edma(struct ath_softc *sc)
831 /* Set buffer size to 4k */
832 sc->sc_edma_bufsize = 4096;
834 /* Fetch EDMA field and buffer sizes */
835 (void) ath_hal_getrxstatuslen(sc->sc_ah, &sc->sc_rx_statuslen);
837 /* Configure the hardware with the RX buffer size */
838 (void) ath_hal_setrxbufsize(sc->sc_ah, sc->sc_edma_bufsize -
839 sc->sc_rx_statuslen);
841 device_printf(sc->sc_dev, "RX status length: %d\n",
842 sc->sc_rx_statuslen);
843 device_printf(sc->sc_dev, "RX buffer size: %d\n",
844 sc->sc_edma_bufsize);
846 sc->sc_rx.recv_stop = ath_edma_stoprecv;
847 sc->sc_rx.recv_start = ath_edma_startrecv;
848 sc->sc_rx.recv_flush = ath_edma_recv_flush;
849 sc->sc_rx.recv_tasklet = ath_edma_recv_tasklet;
850 sc->sc_rx.recv_rxbuf_init = ath_edma_rxbuf_init;
852 sc->sc_rx.recv_setup = ath_edma_dma_rxsetup;
853 sc->sc_rx.recv_teardown = ath_edma_dma_rxteardown;