2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for the Atheros Wireless LAN controller.
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
56 #include <sys/malloc.h>
58 #include <sys/mutex.h>
59 #include <sys/kernel.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/errno.h>
63 #include <sys/callout.h>
65 #include <sys/endian.h>
66 #include <sys/kthread.h>
67 #include <sys/taskqueue.h>
69 #include <sys/module.h>
71 #include <sys/smp.h> /* for mp_ncpus */
73 #include <machine/bus.h>
76 #include <net/if_dl.h>
77 #include <net/if_media.h>
78 #include <net/if_types.h>
79 #include <net/if_arp.h>
80 #include <net/ethernet.h>
81 #include <net/if_llc.h>
83 #include <net80211/ieee80211_var.h>
84 #include <net80211/ieee80211_regdomain.h>
85 #ifdef IEEE80211_SUPPORT_SUPERG
86 #include <net80211/ieee80211_superg.h>
88 #ifdef IEEE80211_SUPPORT_TDMA
89 #include <net80211/ieee80211_tdma.h>
95 #include <netinet/in.h>
96 #include <netinet/if_ether.h>
99 #include <dev/ath/if_athvar.h>
100 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
101 #include <dev/ath/ath_hal/ah_diagcodes.h>
103 #include <dev/ath/if_ath_debug.h>
104 #include <dev/ath/if_ath_misc.h>
105 #include <dev/ath/if_ath_tsf.h>
106 #include <dev/ath/if_ath_tx.h>
107 #include <dev/ath/if_ath_sysctl.h>
108 #include <dev/ath/if_ath_led.h>
109 #include <dev/ath/if_ath_keycache.h>
110 #include <dev/ath/if_ath_rx.h>
111 #include <dev/ath/if_ath_beacon.h>
112 #include <dev/ath/if_athdfs.h>
115 #include <dev/ath/ath_tx99/ath_tx99.h>
118 #include <dev/ath/if_ath_rx_edma.h>
121 #include <dev/ath/if_ath_alq.h>
125 * some general macros
127 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
128 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
130 MALLOC_DECLARE(M_ATHDEV);
135 * + Make sure the FIFO is correctly flushed and reinitialised
137 * + Verify multi-descriptor frames work!
138 * + There's a "memory use after free" which needs to be tracked down
139 * and fixed ASAP. I've seen this in the legacy path too, so it
140 * may be a generic RX path issue.
144 * XXX shuffle the function orders so these pre-declarations aren't
147 static int ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype,
149 static int ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype);
150 static void ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf);
151 static void ath_edma_recv_proc_queue(struct ath_softc *sc,
152 HAL_RX_QUEUE qtype, int dosched);
153 static int ath_edma_recv_proc_deferred_queue(struct ath_softc *sc,
154 HAL_RX_QUEUE qtype, int dosched);
157 ath_edma_stoprecv(struct ath_softc *sc, int dodelay)
159 struct ath_hal *ah = sc->sc_ah;
162 ath_hal_stoppcurecv(ah);
163 ath_hal_setrxfilter(ah, 0);
164 ath_hal_stopdmarecv(ah);
168 /* Flush RX pending for each queue */
169 /* XXX should generic-ify this */
170 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending) {
171 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
172 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
175 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending) {
176 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
177 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
183 * Re-initialise the FIFO given the current buffer contents.
184 * Specifically, walk from head -> tail, pushing the FIFO contents
185 * back into the FIFO.
188 ath_edma_reinit_fifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
190 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
194 ATH_RX_LOCK_ASSERT(sc);
197 for (j = 0; j < re->m_fifo_depth; j++) {
199 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
200 "%s: Q%d: pos=%i, addr=0x%jx\n",
204 (uintmax_t)bf->bf_daddr);
205 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
206 INCR(i, re->m_fifolen);
209 /* Ensure this worked out right */
210 if (i != re->m_fifo_tail) {
211 device_printf(sc->sc_dev, "%s: i (%d) != tail! (%d)\n",
221 * XXX TODO: this needs to reallocate the FIFO entries when a reset
222 * occurs, in case the FIFO is filled up and no new descriptors get
223 * thrown into the FIFO.
226 ath_edma_startrecv(struct ath_softc *sc)
228 struct ath_hal *ah = sc->sc_ah;
236 * Entries should only be written out if the
239 * XXX This isn't correct. I should be looking
240 * at the value of AR_RXDP_SIZE (0x0070) to determine
241 * how many entries are in here.
243 * A warm reset will clear the registers but not the FIFO.
245 * And I believe this is actually the address of the last
246 * handled buffer rather than the current FIFO pointer.
247 * So if no frames have been (yet) seen, we'll reinit the
250 * I'll chase that up at some point.
252 if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_HP) == 0) {
253 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
254 "%s: Re-initing HP FIFO\n", __func__);
255 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_HP);
257 if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_LP) == 0) {
258 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
259 "%s: Re-initing LP FIFO\n", __func__);
260 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_LP);
263 /* Add up to m_fifolen entries in each queue */
265 * These must occur after the above write so the FIFO buffers
266 * are pushed/tracked in the same order as the hardware will
269 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_HP,
270 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_fifolen);
272 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_LP,
273 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_fifolen);
276 ath_hal_startpcurecv(ah);
284 ath_edma_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
288 ath_edma_recv_proc_queue(sc, qtype, dosched);
289 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
293 ath_edma_recv_sched(struct ath_softc *sc, int dosched)
296 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, dosched);
297 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, dosched);
298 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
302 ath_edma_recv_flush(struct ath_softc *sc)
305 DPRINTF(sc, ATH_DEBUG_RECV, "%s: called\n", __func__);
312 * Flush any active frames from FIFO -> deferred list
314 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 0);
315 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 0);
318 * Process what's in the deferred queue
320 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_HP, 0);
321 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_LP, 0);
329 * Process frames from the current queue into the deferred queue.
332 ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
335 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
336 struct ath_rx_status *rs;
340 struct ath_hal *ah = sc->sc_ah;
345 tsf = ath_hal_gettsf64(ah);
346 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
347 sc->sc_stats.ast_rx_noise = nf;
352 bf = re->m_fifo[re->m_fifo_head];
353 /* This shouldn't occur! */
355 device_printf(sc->sc_dev, "%s: Q%d: NULL bf?\n",
364 * Sync descriptor memory - this also syncs the buffer for us.
366 * EDMA descriptors are in cached memory.
368 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
369 BUS_DMASYNC_POSTREAD);
370 rs = &bf->bf_status.ds_rxstat;
371 bf->bf_rxstatus = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr,
374 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
375 ath_printrxbuf(sc, bf, 0, bf->bf_rxstatus == HAL_OK);
376 #endif /* ATH_DEBUG */
378 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS))
379 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS,
380 sc->sc_rx_statuslen, (char *) ds);
381 #endif /* ATH_DEBUG */
382 if (bf->bf_rxstatus == HAL_EINPROGRESS)
386 * Completed descriptor.
388 * In the future we'll call ath_rx_pkt(), but it first
389 * has to be taught about EDMA RX queues (so it can
390 * access sc_rxpending correctly.)
392 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
393 "%s: Q%d: completed!\n", __func__, qtype);
397 * Remove the FIFO entry and place it on the completion
400 re->m_fifo[re->m_fifo_head] = NULL;
401 TAILQ_INSERT_TAIL(&sc->sc_rx_rxlist, bf, bf_list);
403 /* Bump the descriptor FIFO stats */
404 INCR(re->m_fifo_head, re->m_fifolen);
406 /* XXX check it doesn't fall below 0 */
407 } while (re->m_fifo_depth > 0);
409 /* Append some more fresh frames to the FIFO */
411 ath_edma_rxfifo_alloc(sc, qtype, re->m_fifolen);
415 /* rx signal state monitoring */
416 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
418 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1,
419 "ath edma rx proc: npkts=%d\n",
422 /* Handle resched and kickpcu appropriately */
424 if (dosched && sc->sc_kickpcu) {
425 ATH_KTR(sc, ATH_KTR_ERROR, 0,
426 "ath_edma_recv_proc_queue(): kickpcu");
427 device_printf(sc->sc_dev,
428 "%s: handled npkts %d\n",
432 * XXX TODO: what should occur here? Just re-poke and
433 * re-enable the RX FIFO?
443 * Flush the deferred queue.
445 * This destructively flushes the deferred queue - it doesn't
446 * call the wireless stack on each mbuf.
449 ath_edma_flush_deferred_queue(struct ath_softc *sc)
451 struct ath_buf *bf, *next;
453 ATH_RX_LOCK_ASSERT(sc);
454 /* Free in one set, inside the lock */
455 TAILQ_FOREACH_SAFE(bf, &sc->sc_rx_rxlist, bf_list, next) {
456 /* Free the buffer/mbuf */
457 ath_edma_rxbuf_free(sc, bf);
462 ath_edma_recv_proc_deferred_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
467 struct ath_buf *bf, *next;
468 struct ath_rx_status *rs;
474 nf = ath_hal_getchannoise(sc->sc_ah, sc->sc_curchan);
476 * XXX TODO: the NF/TSF should be stamped on the bufs themselves,
477 * otherwise we may end up adding in the wrong values if this
478 * is delayed too far..
480 tsf = ath_hal_gettsf64(sc->sc_ah);
482 /* Copy the list over */
484 TAILQ_CONCAT(&rxlist, &sc->sc_rx_rxlist, bf_list);
487 /* Handle the completed descriptors */
488 TAILQ_FOREACH_SAFE(bf, &rxlist, bf_list, next) {
490 * Skip the RX descriptor status - start at the data offset
492 m_adj(bf->bf_m, sc->sc_rx_statuslen);
494 /* Handle the frame */
496 * Note: this may or may not free bf->bf_m and sync/unmap
499 rs = &bf->bf_status.ds_rxstat;
500 if (ath_rx_pkt(sc, rs, bf->bf_rxstatus, tsf, nf, qtype, bf))
508 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1,
509 "ath edma rx deferred proc: ngood=%d\n",
512 /* Free in one set, inside the lock */
514 TAILQ_FOREACH_SAFE(bf, &rxlist, bf_list, next) {
515 /* Free the buffer/mbuf */
516 ath_edma_rxbuf_free(sc, bf);
524 ath_edma_recv_tasklet(void *arg, int npending)
526 struct ath_softc *sc = (struct ath_softc *) arg;
527 struct ifnet *ifp = sc->sc_ifp;
528 #ifdef IEEE80211_SUPPORT_SUPERG
529 struct ieee80211com *ic = ifp->if_l2com;
532 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: called; npending=%d\n",
537 if (sc->sc_inreset_cnt > 0) {
538 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; skipping\n",
546 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 1);
547 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 1);
549 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_HP, 1);
550 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_LP, 1);
552 /* XXX inside IF_LOCK ? */
553 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
554 #ifdef IEEE80211_SUPPORT_SUPERG
555 ieee80211_ff_age_all(ic, 100);
557 if (! IFQ_IS_EMPTY(&ifp->if_snd))
560 if (ath_dfs_tasklet_needed(sc, sc->sc_curchan))
561 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
569 * Allocate an RX mbuf for the given ath_buf and initialise
572 * + Allocate a 4KB mbuf;
573 * + Setup the DMA map for the given buffer;
574 * + Keep a pointer to the start of the mbuf - that's where the
576 * + Take a pointer to the start of the RX buffer, set the
577 * mbuf "start" to be there;
581 ath_edma_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
588 ATH_RX_LOCK_ASSERT(sc);
590 m = m_getm(NULL, sc->sc_edma_bufsize, M_NOWAIT, MT_DATA);
592 return (ENOBUFS); /* XXX ?*/
594 /* XXX warn/enforce alignment */
596 len = m->m_ext.ext_size;
598 device_printf(sc->sc_dev, "%s: called: m=%p, size=%d, mtod=%p\n",
605 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
608 * Create DMA mapping.
610 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
611 bf->bf_dmamap, m, bf->bf_segs, &bf->bf_nseg, BUS_DMA_NOWAIT);
613 device_printf(sc->sc_dev, "%s: failed; error=%d\n",
621 * Populate ath_buf fields.
624 bf->bf_desc = mtod(m, struct ath_desc *);
625 bf->bf_daddr = bf->bf_segs[0].ds_addr;
626 bf->bf_lastds = bf->bf_desc; /* XXX only really for TX? */
629 /* Zero the descriptor */
630 memset(bf->bf_desc, '\0', sc->sc_rx_statuslen);
634 * Adjust mbuf header and length/size to compensate for the
637 m_adj(m, sc->sc_rx_statuslen);
645 static struct ath_buf *
646 ath_edma_rxbuf_alloc(struct ath_softc *sc)
651 ATH_RX_LOCK_ASSERT(sc);
653 /* Allocate buffer */
654 bf = TAILQ_FIRST(&sc->sc_rxbuf);
655 /* XXX shouldn't happen upon startup? */
659 /* Remove it from the free list */
660 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
662 /* Assign RX mbuf to it */
663 error = ath_edma_rxbuf_init(sc, bf);
665 device_printf(sc->sc_dev,
666 "%s: bf=%p, rxbuf alloc failed! error=%d\n",
670 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
678 ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf)
681 ATH_RX_LOCK_ASSERT(sc);
683 /* We're doing this multiple times? */
684 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
692 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
696 * Allocate up to 'n' entries and push them onto the hardware FIFO.
698 * Return how many entries were successfully pushed onto the
702 ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype, int nbufs)
704 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
708 ATH_RX_LOCK_ASSERT(sc);
711 * Allocate buffers until the FIFO is full or nbufs is reached.
713 for (i = 0; i < nbufs && re->m_fifo_depth < re->m_fifolen; i++) {
714 /* Ensure the FIFO is already blank, complain loudly! */
715 if (re->m_fifo[re->m_fifo_tail] != NULL) {
716 device_printf(sc->sc_dev,
717 "%s: Q%d: fifo[%d] != NULL (%p)\n",
721 re->m_fifo[re->m_fifo_tail]);
724 ath_edma_rxbuf_free(sc, re->m_fifo[re->m_fifo_tail]);
726 /* XXX check it's not < 0 */
727 re->m_fifo[re->m_fifo_tail] = NULL;
730 bf = ath_edma_rxbuf_alloc(sc);
731 /* XXX should ensure the FIFO is not NULL? */
733 device_printf(sc->sc_dev,
734 "%s: Q%d: alloc failed: i=%d, nbufs=%d?\n",
742 re->m_fifo[re->m_fifo_tail] = bf;
745 * Flush the descriptor contents before it's handed to the
748 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
749 BUS_DMASYNC_PREREAD);
751 /* Write to the RX FIFO */
752 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: putrxbuf=%p\n",
756 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
759 INCR(re->m_fifo_tail, re->m_fifolen);
763 * Return how many were allocated.
765 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: nbufs=%d, nalloced=%d\n",
774 ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype)
776 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
779 ATH_RX_LOCK_ASSERT(sc);
781 for (i = 0; i < re->m_fifolen; i++) {
782 if (re->m_fifo[i] != NULL) {
784 struct ath_buf *bf = re->m_fifo[i];
786 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
787 ath_printrxbuf(sc, bf, 0, HAL_OK);
789 ath_edma_rxbuf_free(sc, re->m_fifo[i]);
790 re->m_fifo[i] = NULL;
795 if (re->m_rxpending != NULL) {
796 m_freem(re->m_rxpending);
797 re->m_rxpending = NULL;
799 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
805 * Setup the initial RX FIFO structure.
808 ath_edma_setup_rxfifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
810 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
812 ATH_RX_LOCK_ASSERT(sc);
814 if (! ath_hal_getrxfifodepth(sc->sc_ah, qtype, &re->m_fifolen)) {
815 device_printf(sc->sc_dev, "%s: qtype=%d, failed\n",
820 device_printf(sc->sc_dev, "%s: type=%d, FIFO depth = %d entries\n",
825 /* Allocate ath_buf FIFO array, pre-zero'ed */
826 re->m_fifo = malloc(sizeof(struct ath_buf *) * re->m_fifolen,
829 if (re->m_fifo == NULL) {
830 device_printf(sc->sc_dev, "%s: malloc failed\n",
836 * Set initial "empty" state.
838 re->m_rxpending = NULL;
839 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
845 ath_edma_rxfifo_free(struct ath_softc *sc, HAL_RX_QUEUE qtype)
847 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
849 device_printf(sc->sc_dev, "%s: called; qtype=%d\n",
853 free(re->m_fifo, M_ATHDEV);
859 ath_edma_dma_rxsetup(struct ath_softc *sc)
864 * Create RX DMA tag and buffers.
866 error = ath_descdma_setup_rx_edma(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
867 "rx", ath_rxbuf, sc->sc_rx_statuslen);
872 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_HP);
873 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_LP);
880 ath_edma_dma_rxteardown(struct ath_softc *sc)
884 ath_edma_flush_deferred_queue(sc);
885 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_HP);
886 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_HP);
888 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_LP);
889 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_LP);
892 /* Free RX ath_buf */
893 /* Free RX DMA tag */
894 if (sc->sc_rxdma.dd_desc_len != 0)
895 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
901 ath_recv_setup_edma(struct ath_softc *sc)
904 /* Set buffer size to 4k */
905 sc->sc_edma_bufsize = 4096;
907 /* Fetch EDMA field and buffer sizes */
908 (void) ath_hal_getrxstatuslen(sc->sc_ah, &sc->sc_rx_statuslen);
910 /* Configure the hardware with the RX buffer size */
911 (void) ath_hal_setrxbufsize(sc->sc_ah, sc->sc_edma_bufsize -
912 sc->sc_rx_statuslen);
914 device_printf(sc->sc_dev, "RX status length: %d\n",
915 sc->sc_rx_statuslen);
916 device_printf(sc->sc_dev, "RX buffer size: %d\n",
917 sc->sc_edma_bufsize);
919 sc->sc_rx.recv_stop = ath_edma_stoprecv;
920 sc->sc_rx.recv_start = ath_edma_startrecv;
921 sc->sc_rx.recv_flush = ath_edma_recv_flush;
922 sc->sc_rx.recv_tasklet = ath_edma_recv_tasklet;
923 sc->sc_rx.recv_rxbuf_init = ath_edma_rxbuf_init;
925 sc->sc_rx.recv_setup = ath_edma_dma_rxsetup;
926 sc->sc_rx.recv_teardown = ath_edma_dma_rxteardown;
928 sc->sc_rx.recv_sched = ath_edma_recv_sched;
929 sc->sc_rx.recv_sched_queue = ath_edma_recv_sched_queue;