2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for the Atheros Wireless LAN controller.
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
56 #include <sys/malloc.h>
58 #include <sys/mutex.h>
59 #include <sys/kernel.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/errno.h>
63 #include <sys/callout.h>
65 #include <sys/endian.h>
66 #include <sys/kthread.h>
67 #include <sys/taskqueue.h>
69 #include <sys/module.h>
71 #include <sys/smp.h> /* for mp_ncpus */
73 #include <machine/bus.h>
76 #include <net/if_var.h>
77 #include <net/if_dl.h>
78 #include <net/if_media.h>
79 #include <net/if_types.h>
80 #include <net/if_arp.h>
81 #include <net/ethernet.h>
82 #include <net/if_llc.h>
84 #include <net80211/ieee80211_var.h>
85 #include <net80211/ieee80211_regdomain.h>
86 #ifdef IEEE80211_SUPPORT_SUPERG
87 #include <net80211/ieee80211_superg.h>
89 #ifdef IEEE80211_SUPPORT_TDMA
90 #include <net80211/ieee80211_tdma.h>
96 #include <netinet/in.h>
97 #include <netinet/if_ether.h>
100 #include <dev/ath/if_athvar.h>
101 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
102 #include <dev/ath/ath_hal/ah_diagcodes.h>
104 #include <dev/ath/if_ath_debug.h>
105 #include <dev/ath/if_ath_misc.h>
106 #include <dev/ath/if_ath_tsf.h>
107 #include <dev/ath/if_ath_tx.h>
108 #include <dev/ath/if_ath_sysctl.h>
109 #include <dev/ath/if_ath_led.h>
110 #include <dev/ath/if_ath_keycache.h>
111 #include <dev/ath/if_ath_rx.h>
112 #include <dev/ath/if_ath_beacon.h>
113 #include <dev/ath/if_athdfs.h>
116 #include <dev/ath/ath_tx99/ath_tx99.h>
119 #include <dev/ath/if_ath_rx_edma.h>
122 #include <dev/ath/if_ath_alq.h>
126 * some general macros
128 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
129 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
131 MALLOC_DECLARE(M_ATHDEV);
136 * + Make sure the FIFO is correctly flushed and reinitialised
138 * + Verify multi-descriptor frames work!
139 * + There's a "memory use after free" which needs to be tracked down
140 * and fixed ASAP. I've seen this in the legacy path too, so it
141 * may be a generic RX path issue.
145 * XXX shuffle the function orders so these pre-declarations aren't
148 static int ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype,
150 static int ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype);
151 static void ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf);
152 static void ath_edma_recv_proc_queue(struct ath_softc *sc,
153 HAL_RX_QUEUE qtype, int dosched);
154 static int ath_edma_recv_proc_deferred_queue(struct ath_softc *sc,
155 HAL_RX_QUEUE qtype, int dosched);
158 ath_edma_stoprecv(struct ath_softc *sc, int dodelay)
160 struct ath_hal *ah = sc->sc_ah;
163 ath_hal_stoppcurecv(ah);
164 ath_hal_setrxfilter(ah, 0);
165 ath_hal_stopdmarecv(ah);
169 /* Flush RX pending for each queue */
170 /* XXX should generic-ify this */
171 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending) {
172 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
173 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
176 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending) {
177 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
178 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
184 * Re-initialise the FIFO given the current buffer contents.
185 * Specifically, walk from head -> tail, pushing the FIFO contents
186 * back into the FIFO.
189 ath_edma_reinit_fifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
191 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
195 ATH_RX_LOCK_ASSERT(sc);
198 for (j = 0; j < re->m_fifo_depth; j++) {
200 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
201 "%s: Q%d: pos=%i, addr=0x%jx\n",
205 (uintmax_t)bf->bf_daddr);
206 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
207 INCR(i, re->m_fifolen);
210 /* Ensure this worked out right */
211 if (i != re->m_fifo_tail) {
212 device_printf(sc->sc_dev, "%s: i (%d) != tail! (%d)\n",
222 * XXX TODO: this needs to reallocate the FIFO entries when a reset
223 * occurs, in case the FIFO is filled up and no new descriptors get
224 * thrown into the FIFO.
227 ath_edma_startrecv(struct ath_softc *sc)
229 struct ath_hal *ah = sc->sc_ah;
237 * Entries should only be written out if the
240 * XXX This isn't correct. I should be looking
241 * at the value of AR_RXDP_SIZE (0x0070) to determine
242 * how many entries are in here.
244 * A warm reset will clear the registers but not the FIFO.
246 * And I believe this is actually the address of the last
247 * handled buffer rather than the current FIFO pointer.
248 * So if no frames have been (yet) seen, we'll reinit the
251 * I'll chase that up at some point.
253 if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_HP) == 0) {
254 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
255 "%s: Re-initing HP FIFO\n", __func__);
256 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_HP);
258 if (ath_hal_getrxbuf(sc->sc_ah, HAL_RX_QUEUE_LP) == 0) {
259 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
260 "%s: Re-initing LP FIFO\n", __func__);
261 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_LP);
264 /* Add up to m_fifolen entries in each queue */
266 * These must occur after the above write so the FIFO buffers
267 * are pushed/tracked in the same order as the hardware will
270 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_HP,
271 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_fifolen);
273 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_LP,
274 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_fifolen);
277 ath_hal_startpcurecv(ah);
285 ath_edma_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
289 ath_edma_recv_proc_queue(sc, qtype, dosched);
290 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
294 ath_edma_recv_sched(struct ath_softc *sc, int dosched)
297 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, dosched);
298 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, dosched);
299 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
303 ath_edma_recv_flush(struct ath_softc *sc)
306 DPRINTF(sc, ATH_DEBUG_RECV, "%s: called\n", __func__);
313 * Flush any active frames from FIFO -> deferred list
315 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 0);
316 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 0);
319 * Process what's in the deferred queue
321 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_HP, 0);
322 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_LP, 0);
330 * Process frames from the current queue into the deferred queue.
333 ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
336 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
337 struct ath_rx_status *rs;
341 struct ath_hal *ah = sc->sc_ah;
346 tsf = ath_hal_gettsf64(ah);
347 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
348 sc->sc_stats.ast_rx_noise = nf;
353 bf = re->m_fifo[re->m_fifo_head];
354 /* This shouldn't occur! */
356 device_printf(sc->sc_dev, "%s: Q%d: NULL bf?\n",
365 * Sync descriptor memory - this also syncs the buffer for us.
366 * EDMA descriptors are in cached memory.
368 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
369 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
370 rs = &bf->bf_status.ds_rxstat;
371 bf->bf_rxstatus = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr,
374 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
375 ath_printrxbuf(sc, bf, 0, bf->bf_rxstatus == HAL_OK);
376 #endif /* ATH_DEBUG */
378 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS))
379 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS,
380 sc->sc_rx_statuslen, (char *) ds);
381 #endif /* ATH_DEBUG */
382 if (bf->bf_rxstatus == HAL_EINPROGRESS)
386 * Completed descriptor.
388 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
389 "%s: Q%d: completed!\n", __func__, qtype);
393 * We've been synced already, so unmap.
395 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
398 * Remove the FIFO entry and place it on the completion
401 re->m_fifo[re->m_fifo_head] = NULL;
402 TAILQ_INSERT_TAIL(&sc->sc_rx_rxlist[qtype], bf, bf_list);
404 /* Bump the descriptor FIFO stats */
405 INCR(re->m_fifo_head, re->m_fifolen);
407 /* XXX check it doesn't fall below 0 */
408 } while (re->m_fifo_depth > 0);
410 /* Append some more fresh frames to the FIFO */
412 ath_edma_rxfifo_alloc(sc, qtype, re->m_fifolen);
416 /* rx signal state monitoring */
417 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
419 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1,
420 "ath edma rx proc: npkts=%d\n",
423 /* Handle resched and kickpcu appropriately */
425 if (dosched && sc->sc_kickpcu) {
426 ATH_KTR(sc, ATH_KTR_ERROR, 0,
427 "ath_edma_recv_proc_queue(): kickpcu");
429 device_printf(sc->sc_dev,
430 "%s: handled npkts %d\n",
434 * XXX TODO: what should occur here? Just re-poke and
435 * re-enable the RX FIFO?
445 * Flush the deferred queue.
447 * This destructively flushes the deferred queue - it doesn't
448 * call the wireless stack on each mbuf.
451 ath_edma_flush_deferred_queue(struct ath_softc *sc)
455 ATH_RX_LOCK_ASSERT(sc);
457 /* Free in one set, inside the lock */
458 while (! TAILQ_EMPTY(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP])) {
459 bf = TAILQ_FIRST(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP]);
460 TAILQ_REMOVE(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP], bf, bf_list);
461 /* Free the buffer/mbuf */
462 ath_edma_rxbuf_free(sc, bf);
464 while (! TAILQ_EMPTY(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP])) {
465 bf = TAILQ_FIRST(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP]);
466 TAILQ_REMOVE(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP], bf, bf_list);
467 /* Free the buffer/mbuf */
468 ath_edma_rxbuf_free(sc, bf);
473 ath_edma_recv_proc_deferred_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
478 struct ath_buf *bf, *next;
479 struct ath_rx_status *rs;
486 nf = ath_hal_getchannoise(sc->sc_ah, sc->sc_curchan);
488 * XXX TODO: the NF/TSF should be stamped on the bufs themselves,
489 * otherwise we may end up adding in the wrong values if this
490 * is delayed too far..
492 tsf = ath_hal_gettsf64(sc->sc_ah);
494 /* Copy the list over */
496 TAILQ_CONCAT(&rxlist, &sc->sc_rx_rxlist[qtype], bf_list);
499 /* Handle the completed descriptors */
501 * XXX is this SAFE call needed? The ath_buf entries
502 * aren't modified by ath_rx_pkt, right?
504 TAILQ_FOREACH_SAFE(bf, &rxlist, bf_list, next) {
506 * Skip the RX descriptor status - start at the data offset
508 m_adj(bf->bf_m, sc->sc_rx_statuslen);
510 /* Handle the frame */
512 rs = &bf->bf_status.ds_rxstat;
515 if (ath_rx_pkt(sc, rs, bf->bf_rxstatus, tsf, nf, qtype, bf, m))
523 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1,
524 "ath edma rx deferred proc: ngood=%d\n",
527 /* Free in one set, inside the lock */
529 while (! TAILQ_EMPTY(&rxlist)) {
530 bf = TAILQ_FIRST(&rxlist);
531 TAILQ_REMOVE(&rxlist, bf, bf_list);
532 /* Free the buffer/mbuf */
533 ath_edma_rxbuf_free(sc, bf);
541 ath_edma_recv_tasklet(void *arg, int npending)
543 struct ath_softc *sc = (struct ath_softc *) arg;
544 struct ifnet *ifp = sc->sc_ifp;
545 #ifdef IEEE80211_SUPPORT_SUPERG
546 struct ieee80211com *ic = ifp->if_l2com;
549 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: called; npending=%d\n",
554 if (sc->sc_inreset_cnt > 0) {
555 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; skipping\n",
563 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 1);
564 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 1);
566 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_HP, 1);
567 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_LP, 1);
569 /* XXX inside IF_LOCK ? */
570 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) {
571 #ifdef IEEE80211_SUPPORT_SUPERG
572 ieee80211_ff_age_all(ic, 100);
574 if (! IFQ_IS_EMPTY(&ifp->if_snd))
577 if (ath_dfs_tasklet_needed(sc, sc->sc_curchan))
578 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
586 * Allocate an RX mbuf for the given ath_buf and initialise
589 * + Allocate a 4KB mbuf;
590 * + Setup the DMA map for the given buffer;
594 ath_edma_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
601 ATH_RX_LOCK_ASSERT(sc);
603 m = m_getm(NULL, sc->sc_edma_bufsize, M_NOWAIT, MT_DATA);
605 return (ENOBUFS); /* XXX ?*/
607 /* XXX warn/enforce alignment */
609 len = m->m_ext.ext_size;
611 device_printf(sc->sc_dev, "%s: called: m=%p, size=%d, mtod=%p\n",
618 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
621 * Populate ath_buf fields.
623 bf->bf_desc = mtod(m, struct ath_desc *);
624 bf->bf_lastds = bf->bf_desc; /* XXX only really for TX? */
628 * Zero the descriptor and ensure it makes it out to the
629 * bounce buffer if one is required.
631 * XXX PREWRITE will copy the whole buffer; we only needed it
632 * to sync the first 32 DWORDS. Oh well.
634 memset(bf->bf_desc, '\0', sc->sc_rx_statuslen);
637 * Create DMA mapping.
639 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
640 bf->bf_dmamap, m, bf->bf_segs, &bf->bf_nseg, BUS_DMA_NOWAIT);
643 device_printf(sc->sc_dev, "%s: failed; error=%d\n",
651 * Set daddr to the physical mapping page.
653 bf->bf_daddr = bf->bf_segs[0].ds_addr;
656 * Prepare for the upcoming read.
658 * We need to both sync some data into the buffer (the zero'ed
659 * descriptor payload) and also prepare for the read that's going
662 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
663 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
670 * Allocate a RX buffer.
672 static struct ath_buf *
673 ath_edma_rxbuf_alloc(struct ath_softc *sc)
678 ATH_RX_LOCK_ASSERT(sc);
680 /* Allocate buffer */
681 bf = TAILQ_FIRST(&sc->sc_rxbuf);
682 /* XXX shouldn't happen upon startup? */
684 device_printf(sc->sc_dev, "%s: nothing on rxbuf?!\n",
689 /* Remove it from the free list */
690 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
692 /* Assign RX mbuf to it */
693 error = ath_edma_rxbuf_init(sc, bf);
695 device_printf(sc->sc_dev,
696 "%s: bf=%p, rxbuf alloc failed! error=%d\n",
700 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
708 ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf)
711 ATH_RX_LOCK_ASSERT(sc);
714 * Only unload the frame if we haven't consumed
715 * the mbuf via ath_rx_pkt().
718 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
724 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
728 * Allocate up to 'n' entries and push them onto the hardware FIFO.
730 * Return how many entries were successfully pushed onto the
734 ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype, int nbufs)
736 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
740 ATH_RX_LOCK_ASSERT(sc);
743 * Allocate buffers until the FIFO is full or nbufs is reached.
745 for (i = 0; i < nbufs && re->m_fifo_depth < re->m_fifolen; i++) {
746 /* Ensure the FIFO is already blank, complain loudly! */
747 if (re->m_fifo[re->m_fifo_tail] != NULL) {
748 device_printf(sc->sc_dev,
749 "%s: Q%d: fifo[%d] != NULL (%p)\n",
753 re->m_fifo[re->m_fifo_tail]);
756 ath_edma_rxbuf_free(sc, re->m_fifo[re->m_fifo_tail]);
758 /* XXX check it's not < 0 */
759 re->m_fifo[re->m_fifo_tail] = NULL;
762 bf = ath_edma_rxbuf_alloc(sc);
763 /* XXX should ensure the FIFO is not NULL? */
765 device_printf(sc->sc_dev,
766 "%s: Q%d: alloc failed: i=%d, nbufs=%d?\n",
774 re->m_fifo[re->m_fifo_tail] = bf;
776 /* Write to the RX FIFO */
777 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
778 "%s: Q%d: putrxbuf=%p (0x%jx)\n",
782 (uintmax_t) bf->bf_daddr);
783 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
786 INCR(re->m_fifo_tail, re->m_fifolen);
790 * Return how many were allocated.
792 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: nbufs=%d, nalloced=%d\n",
801 ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype)
803 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
806 ATH_RX_LOCK_ASSERT(sc);
808 for (i = 0; i < re->m_fifolen; i++) {
809 if (re->m_fifo[i] != NULL) {
811 struct ath_buf *bf = re->m_fifo[i];
813 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
814 ath_printrxbuf(sc, bf, 0, HAL_OK);
816 ath_edma_rxbuf_free(sc, re->m_fifo[i]);
817 re->m_fifo[i] = NULL;
822 if (re->m_rxpending != NULL) {
823 m_freem(re->m_rxpending);
824 re->m_rxpending = NULL;
826 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
832 * Setup the initial RX FIFO structure.
835 ath_edma_setup_rxfifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
837 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
839 ATH_RX_LOCK_ASSERT(sc);
841 if (! ath_hal_getrxfifodepth(sc->sc_ah, qtype, &re->m_fifolen)) {
842 device_printf(sc->sc_dev, "%s: qtype=%d, failed\n",
847 device_printf(sc->sc_dev, "%s: type=%d, FIFO depth = %d entries\n",
852 /* Allocate ath_buf FIFO array, pre-zero'ed */
853 re->m_fifo = malloc(sizeof(struct ath_buf *) * re->m_fifolen,
856 if (re->m_fifo == NULL) {
857 device_printf(sc->sc_dev, "%s: malloc failed\n",
863 * Set initial "empty" state.
865 re->m_rxpending = NULL;
866 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
872 ath_edma_rxfifo_free(struct ath_softc *sc, HAL_RX_QUEUE qtype)
874 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
876 device_printf(sc->sc_dev, "%s: called; qtype=%d\n",
880 free(re->m_fifo, M_ATHDEV);
886 ath_edma_dma_rxsetup(struct ath_softc *sc)
891 * Create RX DMA tag and buffers.
893 error = ath_descdma_setup_rx_edma(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
894 "rx", ath_rxbuf, sc->sc_rx_statuslen);
899 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_HP);
900 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_LP);
907 ath_edma_dma_rxteardown(struct ath_softc *sc)
911 ath_edma_flush_deferred_queue(sc);
912 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_HP);
913 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_HP);
915 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_LP);
916 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_LP);
919 /* Free RX ath_buf */
920 /* Free RX DMA tag */
921 if (sc->sc_rxdma.dd_desc_len != 0)
922 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
928 ath_recv_setup_edma(struct ath_softc *sc)
931 /* Set buffer size to 4k */
932 sc->sc_edma_bufsize = 4096;
934 /* Fetch EDMA field and buffer sizes */
935 (void) ath_hal_getrxstatuslen(sc->sc_ah, &sc->sc_rx_statuslen);
937 /* Configure the hardware with the RX buffer size */
938 (void) ath_hal_setrxbufsize(sc->sc_ah, sc->sc_edma_bufsize -
939 sc->sc_rx_statuslen);
941 device_printf(sc->sc_dev, "RX status length: %d\n",
942 sc->sc_rx_statuslen);
943 device_printf(sc->sc_dev, "RX buffer size: %d\n",
944 sc->sc_edma_bufsize);
946 sc->sc_rx.recv_stop = ath_edma_stoprecv;
947 sc->sc_rx.recv_start = ath_edma_startrecv;
948 sc->sc_rx.recv_flush = ath_edma_recv_flush;
949 sc->sc_rx.recv_tasklet = ath_edma_recv_tasklet;
950 sc->sc_rx.recv_rxbuf_init = ath_edma_rxbuf_init;
952 sc->sc_rx.recv_setup = ath_edma_dma_rxsetup;
953 sc->sc_rx.recv_teardown = ath_edma_dma_rxteardown;
955 sc->sc_rx.recv_sched = ath_edma_recv_sched;
956 sc->sc_rx.recv_sched_queue = ath_edma_recv_sched_queue;