2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
15 * redistribution must be conditioned upon including a substantially
16 * similar Disclaimer requirement for further binary redistribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
29 * THE POSSIBILITY OF SUCH DAMAGES.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 * Driver for the Atheros Wireless LAN controller.
38 * This software is derived from work of Atsushi Onoe; his contribution
39 * is greatly appreciated.
45 * This is needed for register operations which are performed
46 * by the driver - eg, calls to ath_hal_gettsf32().
48 * It's also required for any AH_DEBUG checks in here, eg the
49 * module dependencies.
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/sysctl.h>
58 #include <sys/malloc.h>
60 #include <sys/mutex.h>
61 #include <sys/kernel.h>
62 #include <sys/socket.h>
63 #include <sys/sockio.h>
64 #include <sys/errno.h>
65 #include <sys/callout.h>
67 #include <sys/endian.h>
68 #include <sys/kthread.h>
69 #include <sys/taskqueue.h>
71 #include <sys/module.h>
73 #include <sys/smp.h> /* for mp_ncpus */
75 #include <machine/bus.h>
78 #include <net/if_var.h>
79 #include <net/if_dl.h>
80 #include <net/if_media.h>
81 #include <net/if_types.h>
82 #include <net/if_arp.h>
83 #include <net/ethernet.h>
84 #include <net/if_llc.h>
86 #include <net80211/ieee80211_var.h>
87 #include <net80211/ieee80211_regdomain.h>
88 #ifdef IEEE80211_SUPPORT_SUPERG
89 #include <net80211/ieee80211_superg.h>
91 #ifdef IEEE80211_SUPPORT_TDMA
92 #include <net80211/ieee80211_tdma.h>
98 #include <netinet/in.h>
99 #include <netinet/if_ether.h>
102 #include <dev/ath/if_athvar.h>
103 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
104 #include <dev/ath/ath_hal/ah_diagcodes.h>
106 #include <dev/ath/if_ath_debug.h>
107 #include <dev/ath/if_ath_misc.h>
108 #include <dev/ath/if_ath_tsf.h>
109 #include <dev/ath/if_ath_tx.h>
110 #include <dev/ath/if_ath_sysctl.h>
111 #include <dev/ath/if_ath_led.h>
112 #include <dev/ath/if_ath_keycache.h>
113 #include <dev/ath/if_ath_rx.h>
114 #include <dev/ath/if_ath_beacon.h>
115 #include <dev/ath/if_athdfs.h>
116 #include <dev/ath/if_ath_descdma.h>
119 #include <dev/ath/ath_tx99/ath_tx99.h>
122 #include <dev/ath/if_ath_rx_edma.h>
125 #include <dev/ath/if_ath_alq.h>
129 * some general macros
131 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
132 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
134 MALLOC_DECLARE(M_ATHDEV);
139 * + Make sure the FIFO is correctly flushed and reinitialised
141 * + Verify multi-descriptor frames work!
142 * + There's a "memory use after free" which needs to be tracked down
143 * and fixed ASAP. I've seen this in the legacy path too, so it
144 * may be a generic RX path issue.
148 * XXX shuffle the function orders so these pre-declarations aren't
151 static int ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype,
153 static int ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype);
154 static void ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf);
155 static void ath_edma_recv_proc_queue(struct ath_softc *sc,
156 HAL_RX_QUEUE qtype, int dosched);
157 static int ath_edma_recv_proc_deferred_queue(struct ath_softc *sc,
158 HAL_RX_QUEUE qtype, int dosched);
161 ath_edma_stoprecv(struct ath_softc *sc, int dodelay)
163 struct ath_hal *ah = sc->sc_ah;
167 ath_hal_stoppcurecv(ah);
168 ath_hal_setrxfilter(ah, 0);
173 if (ath_hal_stopdmarecv(ah) == AH_TRUE)
174 sc->sc_rx_stopped = 1;
177 * Give the various bus FIFOs (not EDMA descriptor FIFO)
178 * time to finish flushing out data.
182 /* Flush RX pending for each queue */
183 /* XXX should generic-ify this */
184 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending) {
185 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
186 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
189 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending) {
190 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
191 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
197 * Re-initialise the FIFO given the current buffer contents.
198 * Specifically, walk from head -> tail, pushing the FIFO contents
199 * back into the FIFO.
202 ath_edma_reinit_fifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
204 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
208 ATH_RX_LOCK_ASSERT(sc);
211 for (j = 0; j < re->m_fifo_depth; j++) {
213 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
214 "%s: Q%d: pos=%i, addr=0x%jx\n",
218 (uintmax_t)bf->bf_daddr);
219 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
220 INCR(i, re->m_fifolen);
223 /* Ensure this worked out right */
224 if (i != re->m_fifo_tail) {
225 device_printf(sc->sc_dev, "%s: i (%d) != tail! (%d)\n",
236 ath_edma_startrecv(struct ath_softc *sc)
238 struct ath_hal *ah = sc->sc_ah;
243 * Sanity check - are we being called whilst RX
244 * isn't stopped? If so, we may end up pushing
245 * too many entries into the RX FIFO and
253 * In theory the hardware has been initialised, right?
255 if (sc->sc_rx_resetted == 1) {
256 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
257 "%s: Re-initing HP FIFO\n", __func__);
258 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_HP);
259 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
260 "%s: Re-initing LP FIFO\n", __func__);
261 ath_edma_reinit_fifo(sc, HAL_RX_QUEUE_LP);
262 sc->sc_rx_resetted = 0;
264 device_printf(sc->sc_dev,
265 "%s: called without resetting chip?\n",
269 /* Add up to m_fifolen entries in each queue */
271 * These must occur after the above write so the FIFO buffers
272 * are pushed/tracked in the same order as the hardware will
275 * XXX TODO: is this really necessary? We should've stopped
276 * the hardware already and reinitialised it, so it's a no-op.
278 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_HP,
279 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_fifolen);
281 ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_LP,
282 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_fifolen);
285 ath_hal_startpcurecv(ah);
288 * We're now doing RX DMA!
290 sc->sc_rx_stopped = 0;
298 ath_edma_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
303 ath_power_set_power_state(sc, HAL_PM_AWAKE);
306 ath_edma_recv_proc_queue(sc, qtype, dosched);
309 ath_power_restore_power_state(sc);
312 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
316 ath_edma_recv_sched(struct ath_softc *sc, int dosched)
320 ath_power_set_power_state(sc, HAL_PM_AWAKE);
323 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, dosched);
324 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, dosched);
327 ath_power_restore_power_state(sc);
330 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask);
334 ath_edma_recv_flush(struct ath_softc *sc)
337 DPRINTF(sc, ATH_DEBUG_RECV, "%s: called\n", __func__);
344 ath_power_set_power_state(sc, HAL_PM_AWAKE);
348 * Flush any active frames from FIFO -> deferred list
350 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 0);
351 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 0);
354 * Process what's in the deferred queue
357 * XXX: If we read the tsf/channoise here and then pass it in,
358 * we could restore the power state before processing
359 * the deferred queue.
361 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_HP, 0);
362 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_LP, 0);
365 ath_power_restore_power_state(sc);
374 * Process frames from the current queue into the deferred queue.
377 ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
380 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
381 struct ath_rx_status *rs;
385 struct ath_hal *ah = sc->sc_ah;
390 tsf = ath_hal_gettsf64(ah);
391 nf = ath_hal_getchannoise(ah, sc->sc_curchan);
392 sc->sc_stats.ast_rx_noise = nf;
397 if (sc->sc_rx_resetted == 1) {
399 * XXX We shouldn't ever be scheduled if
400 * receive has been stopped - so complain
403 device_printf(sc->sc_dev,
404 "%s: sc_rx_resetted=1! Bad!\n",
412 bf = re->m_fifo[re->m_fifo_head];
413 /* This shouldn't occur! */
415 device_printf(sc->sc_dev, "%s: Q%d: NULL bf?\n",
424 * Sync descriptor memory - this also syncs the buffer for us.
425 * EDMA descriptors are in cached memory.
427 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
428 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
429 rs = &bf->bf_status.ds_rxstat;
430 bf->bf_rxstatus = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr,
432 if (bf->bf_rxstatus == HAL_EINPROGRESS)
435 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
436 ath_printrxbuf(sc, bf, 0, bf->bf_rxstatus == HAL_OK);
437 #endif /* ATH_DEBUG */
439 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS))
440 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS,
441 sc->sc_rx_statuslen, (char *) ds);
442 #endif /* ATH_DEBUG */
445 * Completed descriptor.
447 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
448 "%s: Q%d: completed!\n", __func__, qtype);
452 * We've been synced already, so unmap.
454 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
457 * Remove the FIFO entry and place it on the completion
460 re->m_fifo[re->m_fifo_head] = NULL;
461 TAILQ_INSERT_TAIL(&sc->sc_rx_rxlist[qtype], bf, bf_list);
463 /* Bump the descriptor FIFO stats */
464 INCR(re->m_fifo_head, re->m_fifolen);
466 /* XXX check it doesn't fall below 0 */
467 } while (re->m_fifo_depth > 0);
469 /* Append some more fresh frames to the FIFO */
471 ath_edma_rxfifo_alloc(sc, qtype, re->m_fifolen);
475 /* rx signal state monitoring */
476 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan);
478 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1,
479 "ath edma rx proc: npkts=%d\n",
486 * Flush the deferred queue.
488 * This destructively flushes the deferred queue - it doesn't
489 * call the wireless stack on each mbuf.
492 ath_edma_flush_deferred_queue(struct ath_softc *sc)
496 ATH_RX_LOCK_ASSERT(sc);
498 /* Free in one set, inside the lock */
499 while (! TAILQ_EMPTY(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP])) {
500 bf = TAILQ_FIRST(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP]);
501 TAILQ_REMOVE(&sc->sc_rx_rxlist[HAL_RX_QUEUE_LP], bf, bf_list);
502 /* Free the buffer/mbuf */
503 ath_edma_rxbuf_free(sc, bf);
505 while (! TAILQ_EMPTY(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP])) {
506 bf = TAILQ_FIRST(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP]);
507 TAILQ_REMOVE(&sc->sc_rx_rxlist[HAL_RX_QUEUE_HP], bf, bf_list);
508 /* Free the buffer/mbuf */
509 ath_edma_rxbuf_free(sc, bf);
514 ath_edma_recv_proc_deferred_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype,
519 struct ath_buf *bf, *next;
520 struct ath_rx_status *rs;
527 nf = ath_hal_getchannoise(sc->sc_ah, sc->sc_curchan);
529 * XXX TODO: the NF/TSF should be stamped on the bufs themselves,
530 * otherwise we may end up adding in the wrong values if this
531 * is delayed too far..
533 tsf = ath_hal_gettsf64(sc->sc_ah);
535 /* Copy the list over */
537 TAILQ_CONCAT(&rxlist, &sc->sc_rx_rxlist[qtype], bf_list);
540 /* Handle the completed descriptors */
542 * XXX is this SAFE call needed? The ath_buf entries
543 * aren't modified by ath_rx_pkt, right?
545 TAILQ_FOREACH_SAFE(bf, &rxlist, bf_list, next) {
547 * Skip the RX descriptor status - start at the data offset
549 m_adj(bf->bf_m, sc->sc_rx_statuslen);
551 /* Handle the frame */
553 rs = &bf->bf_status.ds_rxstat;
556 if (ath_rx_pkt(sc, rs, bf->bf_rxstatus, tsf, nf, qtype, bf, m))
564 ATH_KTR(sc, ATH_KTR_INTERRUPTS, 1,
565 "ath edma rx deferred proc: ngood=%d\n",
568 /* Free in one set, inside the lock */
570 while (! TAILQ_EMPTY(&rxlist)) {
571 bf = TAILQ_FIRST(&rxlist);
572 TAILQ_REMOVE(&rxlist, bf, bf_list);
573 /* Free the buffer/mbuf */
574 ath_edma_rxbuf_free(sc, bf);
582 ath_edma_recv_tasklet(void *arg, int npending)
584 struct ath_softc *sc = (struct ath_softc *) arg;
585 #ifdef IEEE80211_SUPPORT_SUPERG
586 struct ieee80211com *ic = &sc->sc_ic;
589 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: called; npending=%d\n",
594 if (sc->sc_inreset_cnt > 0) {
595 device_printf(sc->sc_dev, "%s: sc_inreset_cnt > 0; skipping\n",
604 ath_power_set_power_state(sc, HAL_PM_AWAKE);
607 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP, 1);
608 ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP, 1);
610 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_HP, 1);
611 ath_edma_recv_proc_deferred_queue(sc, HAL_RX_QUEUE_LP, 1);
614 * XXX: If we read the tsf/channoise here and then pass it in,
615 * we could restore the power state before processing
616 * the deferred queue.
619 ath_power_restore_power_state(sc);
622 #ifdef IEEE80211_SUPPORT_SUPERG
623 ieee80211_ff_age_all(ic, 100);
625 if (ath_dfs_tasklet_needed(sc, sc->sc_curchan))
626 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask);
634 * Allocate an RX mbuf for the given ath_buf and initialise
637 * + Allocate a 4KB mbuf;
638 * + Setup the DMA map for the given buffer;
642 ath_edma_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
649 ATH_RX_LOCK_ASSERT(sc);
651 m = m_getm(NULL, sc->sc_edma_bufsize, M_NOWAIT, MT_DATA);
653 return (ENOBUFS); /* XXX ?*/
655 /* XXX warn/enforce alignment */
657 len = m->m_ext.ext_size;
659 device_printf(sc->sc_dev, "%s: called: m=%p, size=%d, mtod=%p\n",
666 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
669 * Populate ath_buf fields.
671 bf->bf_desc = mtod(m, struct ath_desc *);
672 bf->bf_lastds = bf->bf_desc; /* XXX only really for TX? */
676 * Zero the descriptor and ensure it makes it out to the
677 * bounce buffer if one is required.
679 * XXX PREWRITE will copy the whole buffer; we only needed it
680 * to sync the first 32 DWORDS. Oh well.
682 memset(bf->bf_desc, '\0', sc->sc_rx_statuslen);
685 * Create DMA mapping.
687 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
688 bf->bf_dmamap, m, bf->bf_segs, &bf->bf_nseg, BUS_DMA_NOWAIT);
691 device_printf(sc->sc_dev, "%s: failed; error=%d\n",
699 * Set daddr to the physical mapping page.
701 bf->bf_daddr = bf->bf_segs[0].ds_addr;
704 * Prepare for the upcoming read.
706 * We need to both sync some data into the buffer (the zero'ed
707 * descriptor payload) and also prepare for the read that's going
710 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
718 * Allocate a RX buffer.
720 static struct ath_buf *
721 ath_edma_rxbuf_alloc(struct ath_softc *sc)
726 ATH_RX_LOCK_ASSERT(sc);
728 /* Allocate buffer */
729 bf = TAILQ_FIRST(&sc->sc_rxbuf);
730 /* XXX shouldn't happen upon startup? */
732 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: nothing on rxbuf?!\n",
737 /* Remove it from the free list */
738 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
740 /* Assign RX mbuf to it */
741 error = ath_edma_rxbuf_init(sc, bf);
743 device_printf(sc->sc_dev,
744 "%s: bf=%p, rxbuf alloc failed! error=%d\n",
748 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
756 ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf)
759 ATH_RX_LOCK_ASSERT(sc);
762 * Only unload the frame if we haven't consumed
763 * the mbuf via ath_rx_pkt().
766 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
772 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
776 * Allocate up to 'n' entries and push them onto the hardware FIFO.
778 * Return how many entries were successfully pushed onto the
782 ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype, int nbufs)
784 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
788 ATH_RX_LOCK_ASSERT(sc);
791 * Allocate buffers until the FIFO is full or nbufs is reached.
793 for (i = 0; i < nbufs && re->m_fifo_depth < re->m_fifolen; i++) {
794 /* Ensure the FIFO is already blank, complain loudly! */
795 if (re->m_fifo[re->m_fifo_tail] != NULL) {
796 device_printf(sc->sc_dev,
797 "%s: Q%d: fifo[%d] != NULL (%p)\n",
801 re->m_fifo[re->m_fifo_tail]);
804 ath_edma_rxbuf_free(sc, re->m_fifo[re->m_fifo_tail]);
806 /* XXX check it's not < 0 */
807 re->m_fifo[re->m_fifo_tail] = NULL;
810 bf = ath_edma_rxbuf_alloc(sc);
811 /* XXX should ensure the FIFO is not NULL? */
813 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
814 "%s: Q%d: alloc failed: i=%d, nbufs=%d?\n",
822 re->m_fifo[re->m_fifo_tail] = bf;
824 /* Write to the RX FIFO */
825 DPRINTF(sc, ATH_DEBUG_EDMA_RX,
826 "%s: Q%d: putrxbuf=%p (0x%jx)\n",
830 (uintmax_t) bf->bf_daddr);
831 ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
834 INCR(re->m_fifo_tail, re->m_fifolen);
838 * Return how many were allocated.
840 DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: nbufs=%d, nalloced=%d\n",
849 ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype)
851 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
854 ATH_RX_LOCK_ASSERT(sc);
856 for (i = 0; i < re->m_fifolen; i++) {
857 if (re->m_fifo[i] != NULL) {
859 struct ath_buf *bf = re->m_fifo[i];
861 if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
862 ath_printrxbuf(sc, bf, 0, HAL_OK);
864 ath_edma_rxbuf_free(sc, re->m_fifo[i]);
865 re->m_fifo[i] = NULL;
870 if (re->m_rxpending != NULL) {
871 m_freem(re->m_rxpending);
872 re->m_rxpending = NULL;
874 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
880 * Setup the initial RX FIFO structure.
883 ath_edma_setup_rxfifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
885 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
887 ATH_RX_LOCK_ASSERT(sc);
889 if (! ath_hal_getrxfifodepth(sc->sc_ah, qtype, &re->m_fifolen)) {
890 device_printf(sc->sc_dev, "%s: qtype=%d, failed\n",
897 device_printf(sc->sc_dev,
898 "%s: type=%d, FIFO depth = %d entries\n",
903 /* Allocate ath_buf FIFO array, pre-zero'ed */
904 re->m_fifo = malloc(sizeof(struct ath_buf *) * re->m_fifolen,
907 if (re->m_fifo == NULL) {
908 device_printf(sc->sc_dev, "%s: malloc failed\n",
914 * Set initial "empty" state.
916 re->m_rxpending = NULL;
917 re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
923 ath_edma_rxfifo_free(struct ath_softc *sc, HAL_RX_QUEUE qtype)
925 struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
927 device_printf(sc->sc_dev, "%s: called; qtype=%d\n",
931 free(re->m_fifo, M_ATHDEV);
937 ath_edma_dma_rxsetup(struct ath_softc *sc)
942 * Create RX DMA tag and buffers.
944 error = ath_descdma_setup_rx_edma(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
945 "rx", ath_rxbuf, sc->sc_rx_statuslen);
950 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_HP);
951 (void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_LP);
958 ath_edma_dma_rxteardown(struct ath_softc *sc)
962 ath_edma_flush_deferred_queue(sc);
963 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_HP);
964 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_HP);
966 ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_LP);
967 ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_LP);
970 /* Free RX ath_buf */
971 /* Free RX DMA tag */
972 if (sc->sc_rxdma.dd_desc_len != 0)
973 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
979 ath_recv_setup_edma(struct ath_softc *sc)
982 /* Set buffer size to 4k */
983 sc->sc_edma_bufsize = 4096;
985 /* Fetch EDMA field and buffer sizes */
986 (void) ath_hal_getrxstatuslen(sc->sc_ah, &sc->sc_rx_statuslen);
988 /* Configure the hardware with the RX buffer size */
989 (void) ath_hal_setrxbufsize(sc->sc_ah, sc->sc_edma_bufsize -
990 sc->sc_rx_statuslen);
993 device_printf(sc->sc_dev, "RX status length: %d\n",
994 sc->sc_rx_statuslen);
995 device_printf(sc->sc_dev, "RX buffer size: %d\n",
996 sc->sc_edma_bufsize);
999 sc->sc_rx.recv_stop = ath_edma_stoprecv;
1000 sc->sc_rx.recv_start = ath_edma_startrecv;
1001 sc->sc_rx.recv_flush = ath_edma_recv_flush;
1002 sc->sc_rx.recv_tasklet = ath_edma_recv_tasklet;
1003 sc->sc_rx.recv_rxbuf_init = ath_edma_rxbuf_init;
1005 sc->sc_rx.recv_setup = ath_edma_dma_rxsetup;
1006 sc->sc_rx.recv_teardown = ath_edma_dma_rxteardown;
1008 sc->sc_rx.recv_sched = ath_edma_recv_sched;
1009 sc->sc_rx.recv_sched_queue = ath_edma_recv_sched_queue;