2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for the Atheros Wireless LAN controller.
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
56 #include <sys/malloc.h>
58 #include <sys/mutex.h>
59 #include <sys/kernel.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/errno.h>
63 #include <sys/callout.h>
65 #include <sys/endian.h>
66 #include <sys/kthread.h>
67 #include <sys/taskqueue.h>
69 #include <sys/module.h>
71 #include <sys/smp.h> /* for mp_ncpus */
73 #include <machine/bus.h>
76 #include <net/if_dl.h>
77 #include <net/if_media.h>
78 #include <net/if_types.h>
79 #include <net/if_arp.h>
80 #include <net/ethernet.h>
81 #include <net/if_llc.h>
83 #include <net80211/ieee80211_var.h>
84 #include <net80211/ieee80211_regdomain.h>
85 #ifdef IEEE80211_SUPPORT_SUPERG
86 #include <net80211/ieee80211_superg.h>
88 #ifdef IEEE80211_SUPPORT_TDMA
89 #include <net80211/ieee80211_tdma.h>
95 #include <netinet/in.h>
96 #include <netinet/if_ether.h>
99 #include <dev/ath/if_athvar.h>
100 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
101 #include <dev/ath/ath_hal/ah_diagcodes.h>
103 #include <dev/ath/if_ath_debug.h>
104 #include <dev/ath/if_ath_misc.h>
105 #include <dev/ath/if_ath_tsf.h>
106 #include <dev/ath/if_ath_tx.h>
107 #include <dev/ath/if_ath_sysctl.h>
108 #include <dev/ath/if_ath_led.h>
109 #include <dev/ath/if_ath_keycache.h>
110 #include <dev/ath/if_ath_rx.h>
111 #include <dev/ath/if_ath_beacon.h>
112 #include <dev/ath/if_athdfs.h>
115 #include <dev/ath/ath_tx99/ath_tx99.h>
118 #include <dev/ath/if_ath_tx_edma.h>
121 #include <dev/ath/if_ath_alq.h>
125 * some general macros
127 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
128 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
131 * XXX doesn't belong here, and should be tunable
133 #define ATH_TXSTATUS_RING_SIZE 512
135 MALLOC_DECLARE(M_ATHDEV);
137 static void ath_edma_tx_processq(struct ath_softc *sc, int dosched);
140 ath_edma_tx_fifo_fill(struct ath_softc *sc, struct ath_txq *txq)
145 ATH_TX_LOCK_ASSERT(sc);
147 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called\n", __func__);
149 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) {
150 if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH)
152 ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr);
154 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
155 ath_printtxbuf(sc, bf, txq->axq_qnum, i, 0);
156 #endif/* ATH_DEBUG */
158 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
159 ath_tx_alq_post(sc, bf);
160 #endif /* ATH_DEBUG_ALQ */
161 txq->axq_fifo_depth++;
165 ath_hal_txstart(sc->sc_ah, txq->axq_qnum);
169 * Re-initialise the DMA FIFO with the current contents of
172 * This should only be called as part of the chip reset path, as it
173 * assumes the FIFO is currently empty.
176 ath_edma_dma_restart(struct ath_softc *sc, struct ath_txq *txq)
179 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called: txq=%p, qnum=%d\n",
184 ATH_TX_LOCK_ASSERT(sc);
185 ath_edma_tx_fifo_fill(sc, txq);
190 * Hand off this frame to a hardware queue.
192 * Things are a bit hairy in the EDMA world. The TX FIFO is only
193 * 8 entries deep, so we need to keep track of exactly what we've
194 * pushed into the FIFO and what's just sitting in the TX queue,
197 * So this is split into two halves - frames get appended to the
198 * TXQ; then a scheduler is called to push some frames into the
202 ath_edma_xmit_handoff_hw(struct ath_softc *sc, struct ath_txq *txq,
205 struct ath_hal *ah = sc->sc_ah;
207 ATH_TX_LOCK_ASSERT(sc);
209 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
210 ("%s: busy status 0x%x", __func__, bf->bf_flags));
213 * XXX TODO: write a hard-coded check to ensure that
214 * the queue id in the TX descriptor matches txq->axq_qnum.
217 /* Update aggr stats */
218 if (bf->bf_state.bfs_aggr)
219 txq->axq_aggr_depth++;
221 /* Push and update frame stats */
222 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
224 /* Only schedule to the FIFO if there's space */
225 if (txq->axq_fifo_depth < HAL_TXFIFO_DEPTH) {
227 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
228 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 0);
229 #endif /* ATH_DEBUG */
231 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
232 ath_tx_alq_post(sc, bf);
233 #endif /* ATH_DEBUG_ALQ */
234 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
235 txq->axq_fifo_depth++;
236 ath_hal_txstart(ah, txq->axq_qnum);
241 * Hand off this frame to a multicast software queue.
243 * The EDMA TX CABQ will get a list of chained frames, chained
244 * together using the next pointer. The single head of that
245 * particular queue is pushed to the hardware CABQ.
248 ath_edma_xmit_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq,
252 ATH_TX_LOCK_ASSERT(sc);
253 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
254 ("%s: busy status 0x%x", __func__, bf->bf_flags));
257 * XXX this is mostly duplicated in ath_tx_handoff_mcast().
259 if (ATH_TXQ_FIRST(txq) != NULL) {
260 struct ath_buf *bf_last = ATH_TXQ_LAST(txq, axq_q_s);
261 struct ieee80211_frame *wh;
263 /* mark previous frame */
264 wh = mtod(bf_last->bf_m, struct ieee80211_frame *);
265 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
267 /* sync descriptor to memory */
268 bus_dmamap_sync(sc->sc_dmat, bf_last->bf_dmamap,
269 BUS_DMASYNC_PREWRITE);
273 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
274 ath_tx_alq_post(sc, bf);
275 #endif /* ATH_DEBUG_ALQ */
277 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
278 ath_hal_gettxdesclinkptr(sc->sc_ah, bf->bf_lastds, &txq->axq_link);
282 * Handoff this frame to the hardware.
284 * For the multicast queue, this will treat it as a software queue
285 * and append it to the list, after updating the MORE_DATA flag
286 * in the previous frame. The cabq processing code will ensure
287 * that the queue contents gets transferred over.
289 * For the hardware queues, this will queue a frame to the queue
290 * like before, then populate the FIFO from that. Since the
291 * EDMA hardware has 8 FIFO slots per TXQ, this ensures that
292 * frames such as management frames don't get prematurely dropped.
294 * This does imply that a similar flush-hwq-to-fifoq method will
295 * need to be called from the processq function, before the
296 * per-node software scheduler is called.
299 ath_edma_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq,
303 ATH_TX_LOCK_ASSERT(sc);
305 DPRINTF(sc, ATH_DEBUG_XMIT_DESC,
306 "%s: called; bf=%p, txq=%p, qnum=%d\n",
312 if (txq->axq_qnum == ATH_TXQ_SWQ)
313 ath_edma_xmit_handoff_mcast(sc, txq, bf);
315 ath_edma_xmit_handoff_hw(sc, txq, bf);
319 * XXX For now this is a placeholder; free the buffer
320 * and inform the stack that the TX failed.
322 ath_tx_default_comp(sc, bf, 1);
327 ath_edma_setup_txfifo(struct ath_softc *sc, int qnum)
329 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum];
331 te->m_fifo = malloc(sizeof(struct ath_buf *) * HAL_TXFIFO_DEPTH,
334 if (te->m_fifo == NULL) {
335 device_printf(sc->sc_dev, "%s: malloc failed\n",
341 * Set initial "empty" state.
343 te->m_fifo_head = te->m_fifo_tail = te->m_fifo_depth = 0;
349 ath_edma_free_txfifo(struct ath_softc *sc, int qnum)
351 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum];
353 /* XXX TODO: actually deref the ath_buf entries? */
354 free(te->m_fifo, M_ATHDEV);
359 ath_edma_dma_txsetup(struct ath_softc *sc)
364 error = ath_descdma_alloc_desc(sc, &sc->sc_txsdma,
365 NULL, "txcomp", sc->sc_tx_statuslen, ATH_TXSTATUS_RING_SIZE);
369 ath_hal_setuptxstatusring(sc->sc_ah,
370 (void *) sc->sc_txsdma.dd_desc,
371 sc->sc_txsdma.dd_desc_paddr,
372 ATH_TXSTATUS_RING_SIZE);
374 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
375 ath_edma_setup_txfifo(sc, i);
382 ath_edma_dma_txteardown(struct ath_softc *sc)
386 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
387 ath_edma_free_txfifo(sc, i);
390 ath_descdma_cleanup(sc, &sc->sc_txsdma, NULL);
395 * Drain all TXQs, potentially after completing the existing completed
399 ath_edma_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
401 struct ifnet *ifp = sc->sc_ifp;
404 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
406 (void) ath_stoptxdma(sc);
409 * If reset type is noloss, the TX FIFO needs to be serviced
410 * and those frames need to be handled.
412 * Otherwise, just toss everything in each TX queue.
414 if (reset_type == ATH_RESET_NOLOSS) {
415 ath_edma_tx_processq(sc, 0);
417 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
418 if (ATH_TXQ_SETUP(sc, i))
419 ath_tx_draintxq(sc, &sc->sc_txq[i]);
423 /* XXX dump out the TX completion FIFO contents */
425 /* XXX dump out the frames */
427 IF_LOCK(&ifp->if_snd);
428 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
429 IF_UNLOCK(&ifp->if_snd);
434 * TX completion tasklet.
438 ath_edma_tx_proc(void *arg, int npending)
440 struct ath_softc *sc = (struct ath_softc *) arg;
442 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called, npending=%d\n",
444 ath_edma_tx_processq(sc, 1);
448 * Process the TX status queue.
451 ath_edma_tx_processq(struct ath_softc *sc, int dosched)
453 struct ath_hal *ah = sc->sc_ah;
455 struct ath_tx_status ts;
458 struct ieee80211_node *ni;
464 uint32_t txstatus[32];
467 for (idx = 0; ; idx++) {
468 bzero(&ts, sizeof(ts));
470 ATH_TXSTATUS_LOCK(sc);
472 ath_hal_gettxrawtxdesc(ah, txstatus);
474 status = ath_hal_txprocdesc(ah, NULL, (void *) &ts);
475 ATH_TXSTATUS_UNLOCK(sc);
478 if (sc->sc_debug & ATH_DEBUG_TX_PROC)
479 ath_printtxstatbuf(sc, NULL, txstatus, ts.ts_queue_id,
480 idx, (status == HAL_OK));
483 if (status == HAL_EINPROGRESS)
487 * If there is an error with this descriptor, continue
490 * XXX TBD: log some statistics?
492 if (status == HAL_EIO) {
493 device_printf(sc->sc_dev, "%s: invalid TX status?\n",
499 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS))
500 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS,
503 #endif /* ATH_DEBUG_ALQ */
506 * At this point we have a valid status descriptor.
507 * The QID and descriptor ID (which currently isn't set)
508 * is part of the status.
510 * We then assume that the descriptor in question is the
511 * -head- of the given QID. Eventually we should verify
512 * this by using the descriptor ID.
516 * The beacon queue is not currently a "real" queue.
517 * Frames aren't pushed onto it and the lock isn't setup.
518 * So skip it for now; the beacon handling code will
519 * free and alloc more beacon buffers as appropriate.
521 if (ts.ts_queue_id == sc->sc_bhalq)
524 txq = &sc->sc_txq[ts.ts_queue_id];
527 bf = TAILQ_FIRST(&txq->axq_q);
529 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: qcuid=%d, bf=%p\n",
533 /* XXX TODO: actually output debugging info about this */
536 /* XXX assert the buffer/descriptor matches the status descid */
537 if (ts.ts_desc_id != bf->bf_descid) {
538 device_printf(sc->sc_dev,
539 "%s: mismatched descid (qid=%d, tsdescid=%d, "
548 /* This removes the buffer and decrements the queue depth */
549 ATH_TXQ_REMOVE(txq, bf, bf_list);
550 if (bf->bf_state.bfs_aggr)
551 txq->axq_aggr_depth--;
552 txq->axq_fifo_depth --;
553 /* XXX assert FIFO depth >= 0 */
557 * First we need to make sure ts_rate is valid.
559 * Pre-EDMA chips pass the whole TX descriptor to
560 * the proctxdesc function which will then fill out
561 * ts_rate based on the ts_finaltsi (final TX index)
562 * in the TX descriptor. However the TX completion
563 * FIFO doesn't have this information. So here we
564 * do a separate HAL call to populate that information.
566 * The same problem exists with ts_longretry.
567 * The FreeBSD HAL corrects ts_longretry in the HAL layer;
568 * the AR9380 HAL currently doesn't. So until the HAL
569 * is imported and this can be added, we correct for it
573 /* XXX faked for now. Ew. */
574 if (ts.ts_finaltsi < 4) {
576 bf->bf_state.bfs_rc[ts.ts_finaltsi].ratecode;
577 switch (ts.ts_finaltsi) {
578 case 3: ts.ts_longretry +=
579 bf->bf_state.bfs_rc[2].tries;
580 case 2: ts.ts_longretry +=
581 bf->bf_state.bfs_rc[1].tries;
582 case 1: ts.ts_longretry +=
583 bf->bf_state.bfs_rc[0].tries;
586 device_printf(sc->sc_dev, "%s: finaltsi=%d\n",
589 ts.ts_rate = bf->bf_state.bfs_rc[0].ratecode;
593 * XXX This is terrible.
595 * Right now, some code uses the TX status that is
596 * passed in here, but the completion handlers in the
597 * software TX path also use bf_status.ds_txstat.
598 * Ew. That should all go away.
600 * XXX It's also possible the rate control completion
601 * routine is called twice.
603 memcpy(&bf->bf_status, &ts, sizeof(ts));
608 /* XXX duplicate from ath_tx_processq */
609 if (ni != NULL && ts.ts_status == 0 &&
610 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) {
612 sc->sc_stats.ast_tx_rssi = ts.ts_rssi;
613 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
617 /* Handle frame completion and rate control update */
618 ath_tx_process_buf_completion(sc, txq, &ts, bf);
620 /* bf is invalid at this point */
623 * Now that there's space in the FIFO, let's push some
624 * more frames into it.
626 * Unfortunately for now, the txq has FIFO and non-FIFO
627 * frames in the same linked list, so there's no way
628 * to quickly/easily populate frames without walking
629 * the queue and skipping 'axq_fifo_depth' frames.
631 * So for now, let's only repopulate the FIFO once it
632 * is empty. It's sucky for performance but it's enough
633 * to begin validating that things are somewhat
637 if (dosched && txq->axq_fifo_depth == 0) {
638 ath_edma_tx_fifo_fill(sc, txq);
646 IF_LOCK(&sc->sc_ifp->if_snd);
647 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
648 IF_UNLOCK(&sc->sc_ifp->if_snd);
651 /* Kick software scheduler */
653 * XXX It's inefficient to do this if the FIFO queue is full,
654 * but there's no easy way right now to only populate
655 * the txq task for _one_ TXQ. This should be fixed.
662 ath_edma_attach_comp_func(struct ath_softc *sc)
665 TASK_INIT(&sc->sc_txtask, 0, ath_edma_tx_proc, sc);
669 ath_xmit_setup_edma(struct ath_softc *sc)
672 /* Fetch EDMA field and buffer sizes */
673 (void) ath_hal_gettxdesclen(sc->sc_ah, &sc->sc_tx_desclen);
674 (void) ath_hal_gettxstatuslen(sc->sc_ah, &sc->sc_tx_statuslen);
675 (void) ath_hal_getntxmaps(sc->sc_ah, &sc->sc_tx_nmaps);
677 device_printf(sc->sc_dev, "TX descriptor length: %d\n",
679 device_printf(sc->sc_dev, "TX status length: %d\n",
680 sc->sc_tx_statuslen);
681 device_printf(sc->sc_dev, "TX buffers per descriptor: %d\n",
684 sc->sc_tx.xmit_setup = ath_edma_dma_txsetup;
685 sc->sc_tx.xmit_teardown = ath_edma_dma_txteardown;
686 sc->sc_tx.xmit_attach_comp_func = ath_edma_attach_comp_func;
688 sc->sc_tx.xmit_dma_restart = ath_edma_dma_restart;
689 sc->sc_tx.xmit_handoff = ath_edma_xmit_handoff;
690 sc->sc_tx.xmit_drain = ath_edma_tx_drain;