2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
33 * Defintions for the Atheros Wireless LAN controller driver.
35 #ifndef _DEV_ATH_ATHVAR_H
36 #define _DEV_ATH_ATHVAR_H
38 #include <contrib/dev/ath/ah.h>
39 #include <contrib/dev/ath/ah_desc.h>
40 #include <net80211/ieee80211_radiotap.h>
41 #include <dev/ath/if_athioctl.h>
42 #include <dev/ath/if_athrate.h>
44 #define ATH_TIMEOUT 1000
47 #define ATH_RXBUF 40 /* number of RX buffers */
50 #define ATH_TXBUF 200 /* number of TX buffers */
52 #define ATH_BCBUF 4 /* number of beacon buffers */
54 #define ATH_TXDESC 10 /* number of descriptors per buffer */
55 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */
56 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */
57 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */
59 #define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */
60 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */
61 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */
64 * The key cache is used for h/w cipher state and also for
65 * tracking station state such as the current tx antenna.
66 * We also setup a mapping table between key cache slot indices
67 * and station state to short-circuit node lookups on rx.
68 * Different parts have different size key caches. We handle
69 * up to ATH_KEYMAX entries (could dynamically allocate state).
71 #define ATH_KEYMAX 128 /* max key cache size we handle */
72 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */
74 #define ATH_FF_TXQMIN 2 /* min txq depth for staging */
75 #define ATH_FF_TXQMAX 50 /* maximum # of queued frames allowed */
76 #define ATH_FF_STAGEMAX 5 /* max waiting period for staged frame*/
82 /* driver-specific node state */
84 struct ieee80211_node an_node; /* base class */
85 const struct ieee80211_txparam *an_tp;
86 u_int8_t an_mgmtrix; /* min h/w rate index */
87 u_int8_t an_mcastrix; /* mcast h/w rate index */
88 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */
89 /* variable-length rate control state follows */
91 #define ATH_NODE(ni) ((struct ath_node *)(ni))
92 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni))
94 #define ATH_RSSI_LPF_LEN 10
95 #define ATH_RSSI_DUMMY_MARKER 0x127
96 #define ATH_EP_MUL(x, mul) ((x) * (mul))
97 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
98 #define ATH_LPF_RSSI(x, y, len) \
99 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
100 #define ATH_RSSI_LPF(x, y) do { \
102 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
106 STAILQ_ENTRY(ath_buf) bf_list;
107 TAILQ_ENTRY(ath_buf) bf_stagelist; /* stage queue list */
108 u_int32_t bf_age; /* age when placed on stageq */
110 int bf_flags; /* tx descriptor flags */
111 struct ath_desc *bf_desc; /* virtual addr of desc */
112 struct ath_desc_status bf_status; /* tx/rx status */
113 bus_addr_t bf_daddr; /* physical addr of desc */
114 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */
115 struct mbuf *bf_m; /* mbuf for buf */
116 struct ieee80211_node *bf_node; /* pointer to the node */
117 bus_size_t bf_mapsize;
118 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */
119 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER];
121 typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
124 * DMA state for tx/rx descriptors.
128 struct ath_desc *dd_desc; /* descriptors */
129 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
130 bus_size_t dd_desc_len; /* size of dd_desc */
131 bus_dma_segment_t dd_dseg;
132 bus_dma_tag_t dd_dmat; /* bus DMA tag */
133 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
134 struct ath_buf *dd_bufptr; /* associated buffers */
138 * Data transmit queue state. One of these exists for each
139 * hardware transmit queue. Packets sent to us from above
140 * are assigned to queues based on their priority. Not all
141 * devices support a complete set of hardware transmit queues.
142 * For those devices the array sc_ac2q will map multiple
143 * priorities to fewer hardware queues (typically all to one
147 u_int axq_qnum; /* hardware q number */
148 #define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */
149 u_int axq_depth; /* queue depth (stat only) */
150 u_int axq_intrcnt; /* interrupt count */
151 u_int32_t *axq_link; /* link ptr in last TX desc */
152 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */
153 struct mtx axq_lock; /* lock on q and link */
154 char axq_name[12]; /* e.g. "ath0_txq4" */
156 * Fast-frame state. The staging queue holds awaiting
157 * a fast-frame pairing. Buffers on this queue are
158 * assigned an ``age'' and flushed when they wait too long.
160 TAILQ_HEAD(axq_headtype, ath_buf) axq_stageq;
161 u_int32_t axq_curage; /* queue age */
164 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \
165 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \
166 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \
167 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \
169 #define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock)
170 #define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock)
171 #define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock)
172 #define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED)
174 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
175 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
176 (_tq)->axq_depth++; \
177 (_tq)->axq_curage++; \
179 #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
180 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
181 (_tq)->axq_depth--; \
183 /* NB: this does not do the "head empty check" that STAILQ_LAST does */
184 #define ATH_TXQ_LAST(_tq) \
185 ((struct ath_buf *)(void *) \
186 ((char *)((_tq)->axq_q.stqh_last) - __offsetof(struct ath_buf, bf_list)))
189 struct ieee80211vap av_vap; /* base class */
190 int av_bslot; /* beacon slot index */
191 struct ath_buf *av_bcbuf; /* beacon buffer */
192 struct ieee80211_beacon_offsets av_boff;/* dynamic update state */
193 struct ath_txq av_mcastq; /* buffered mcast s/w queue */
195 void (*av_recv_mgmt)(struct ieee80211_node *,
196 struct mbuf *, int, int, int, u_int32_t);
197 int (*av_newstate)(struct ieee80211vap *,
198 enum ieee80211_state, int);
199 void (*av_bmiss)(struct ieee80211vap *);
201 #define ATH_VAP(vap) ((struct ath_vap *)(vap))
207 struct ifnet *sc_ifp; /* interface common */
208 struct ath_stats sc_stats; /* interface statistics */
210 int sc_nvaps; /* # vaps */
211 int sc_nstavaps; /* # station vaps */
212 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN];
213 u_int8_t sc_nbssid0; /* # vap's using base mac */
214 uint32_t sc_bssidmask; /* bssid mask */
216 void (*sc_node_free)(struct ieee80211_node *);
218 HAL_BUS_TAG sc_st; /* bus space tag */
219 HAL_BUS_HANDLE sc_sh; /* bus space handle */
220 bus_dma_tag_t sc_dmat; /* bus DMA tag */
221 struct mtx sc_mtx; /* master lock (recursive) */
222 struct taskqueue *sc_tq; /* private task queue */
223 struct ath_hal *sc_ah; /* Atheros HAL */
224 struct ath_ratectrl *sc_rc; /* tx rate control support */
225 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */
226 void (*sc_setdefantenna)(struct ath_softc *, u_int);
227 unsigned int sc_invalid : 1,/* disable hardware accesses */
228 sc_mrretry : 1,/* multi-rate retry support */
229 sc_softled : 1,/* enable LED gpio status */
230 sc_splitmic : 1,/* split TKIP MIC keys */
231 sc_needmib : 1,/* enable MIB stats intr */
232 sc_diversity: 1,/* enable rx diversity */
233 sc_hasveol : 1,/* tx VEOL support */
234 sc_ledstate : 1,/* LED on/off state */
235 sc_blinking : 1,/* LED blink operation active */
236 sc_mcastkey : 1,/* mcast key cache search */
237 sc_scanning : 1,/* scanning active */
238 sc_syncbeacon:1,/* sync/resync beacon timers */
239 sc_hasclrkey: 1,/* CLR key supported */
240 sc_xchanmode: 1,/* extended channel mode */
241 sc_outdoor : 1,/* outdoor operation */
242 sc_dturbo : 1,/* dynamic turbo in use */
243 sc_hasbmask : 1,/* bssid mask support */
244 sc_hastsfadd: 1,/* tsf adjust support */
245 sc_beacons : 1,/* beacons running */
246 sc_swbmiss : 1,/* sta mode using sw bmiss */
247 sc_stagbeacons:1,/* use staggered beacons */
248 sc_wmetkipmic:1;/* can do WME+TKIP MIC */
250 #define IEEE80211_MODE_HALF (IEEE80211_MODE_MAX+0)
251 #define IEEE80211_MODE_QUARTER (IEEE80211_MODE_MAX+1)
252 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX+2];
253 const HAL_RATE_TABLE *sc_currates; /* current rate table */
254 enum ieee80211_phymode sc_curmode; /* current phy mode */
255 HAL_OPMODE sc_opmode; /* current operating mode */
256 u_int16_t sc_curtxpow; /* current tx power limit */
257 u_int16_t sc_curaid; /* current association id */
258 HAL_CHANNEL sc_curchan; /* current h/w channel */
259 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN];
260 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
262 u_int8_t ieeerate; /* IEEE rate */
263 u_int8_t rxflags; /* radiotap rx flags */
264 u_int8_t txflags; /* radiotap tx flags */
265 u_int16_t ledon; /* softled on time */
266 u_int16_t ledoff; /* softled off time */
267 } sc_hwmap[32]; /* h/w rate ix mappings */
268 u_int8_t sc_protrix; /* protection rate index */
269 u_int8_t sc_lastdatarix; /* last data frame rate index */
270 u_int sc_mcastrate; /* ieee rate for mcastrateix */
271 u_int sc_fftxqmin; /* min frames before staging */
272 u_int sc_fftxqmax; /* max frames before drop */
273 u_int sc_txantenna; /* tx antenna (fixed or auto) */
274 HAL_INT sc_imask; /* interrupt mask copy */
275 u_int sc_keymax; /* size of key cache */
276 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */
278 u_int sc_ledpin; /* GPIO pin for driving LED */
279 u_int sc_ledon; /* pin setting for LED on */
280 u_int sc_ledidle; /* idle polling interval */
281 int sc_ledevent; /* time of last LED event */
282 u_int8_t sc_rxrate; /* current rx rate for LED */
283 u_int8_t sc_txrate; /* current tx rate for LED */
284 u_int16_t sc_ledoff; /* off time for current blink */
285 struct callout sc_ledtimer; /* led off timer */
287 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */
288 u_int sc_rfsilentpol; /* pin setting for rfkill on */
290 struct ath_tx_radiotap_header sc_tx_th;
292 struct ath_rx_radiotap_header sc_rx_th;
294 u_int sc_monpass; /* frames to pass in mon.mode */
296 struct ath_descdma sc_rxdma; /* RX descriptors */
297 ath_bufhead sc_rxbuf; /* receive buffer */
298 struct mbuf *sc_rxpending; /* pending receive data */
299 u_int32_t *sc_rxlink; /* link ptr in last RX desc */
300 struct task sc_rxtask; /* rx int processing */
301 struct task sc_rxorntask; /* rxorn int processing */
302 u_int8_t sc_defant; /* current default antenna */
303 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
304 u_int64_t sc_lastrx; /* tsf at last rx'd frame */
306 struct ath_descdma sc_txdma; /* TX descriptors */
307 ath_bufhead sc_txbuf; /* transmit buffer */
308 struct mtx sc_txbuflock; /* txbuf lock */
309 char sc_txname[12]; /* e.g. "ath0_buf" */
310 u_int sc_txqsetup; /* h/w queues setup */
311 u_int sc_txintrperiod;/* tx interrupt batching */
312 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
313 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
314 struct task sc_txtask; /* tx int processing */
316 struct ath_descdma sc_bdma; /* beacon descriptors */
317 ath_bufhead sc_bbuf; /* beacon buffers */
318 u_int sc_bhalq; /* HAL q for outgoing beacons */
319 u_int sc_bmisscount; /* missed beacon transmits */
320 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
321 struct ath_txq *sc_cabq; /* tx q for cab frames */
322 struct task sc_bmisstask; /* bmiss int processing */
323 struct task sc_bstucktask; /* stuck beacon processing */
325 OK, /* no change needed */
326 UPDATE, /* update pending */
327 COMMIT /* beacon sent, commit change */
328 } sc_updateslot; /* slot time update fsm */
329 int sc_slotupdate; /* slot to advance fsm */
330 struct ieee80211vap *sc_bslot[ATH_BCBUF];
331 int sc_nbcnvaps; /* # vaps with beacons */
333 struct callout sc_cal_ch; /* callout handle for cals */
334 int sc_calinterval; /* current polling interval */
335 int sc_caltries; /* cals at current interval */
336 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */
339 #define ATH_LOCK_INIT(_sc) \
340 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
341 NULL, MTX_DEF | MTX_RECURSE)
342 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
343 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
344 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
345 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
347 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
349 #define ATH_TXBUF_LOCK_INIT(_sc) do { \
350 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \
351 device_get_nameunit((_sc)->sc_dev)); \
352 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \
354 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock)
355 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock)
356 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock)
357 #define ATH_TXBUF_LOCK_ASSERT(_sc) \
358 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
360 int ath_attach(u_int16_t, struct ath_softc *);
361 int ath_detach(struct ath_softc *);
362 void ath_resume(struct ath_softc *);
363 void ath_suspend(struct ath_softc *);
364 void ath_shutdown(struct ath_softc *);
365 void ath_intr(void *);
368 * HAL definitions to comply with local coding convention.
370 #define ath_hal_detach(_ah) \
371 ((*(_ah)->ah_detach)((_ah)))
372 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
373 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
374 #define ath_hal_getratetable(_ah, _mode) \
375 ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
376 #define ath_hal_getmac(_ah, _mac) \
377 ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
378 #define ath_hal_setmac(_ah, _mac) \
379 ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
380 #define ath_hal_getbssidmask(_ah, _mask) \
381 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask)))
382 #define ath_hal_setbssidmask(_ah, _mask) \
383 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask)))
384 #define ath_hal_intrset(_ah, _mask) \
385 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
386 #define ath_hal_intrget(_ah) \
387 ((*(_ah)->ah_getInterrupts)((_ah)))
388 #define ath_hal_intrpend(_ah) \
389 ((*(_ah)->ah_isInterruptPending)((_ah)))
390 #define ath_hal_getisr(_ah, _pmask) \
391 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
392 #define ath_hal_updatetxtriglevel(_ah, _inc) \
393 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
394 #define ath_hal_setpower(_ah, _mode) \
395 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
396 #define ath_hal_keycachesize(_ah) \
397 ((*(_ah)->ah_getKeyCacheSize)((_ah)))
398 #define ath_hal_keyreset(_ah, _ix) \
399 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
400 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \
401 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
402 #define ath_hal_keyisvalid(_ah, _ix) \
403 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
404 #define ath_hal_keysetmac(_ah, _ix, _mac) \
405 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
406 #define ath_hal_getrxfilter(_ah) \
407 ((*(_ah)->ah_getRxFilter)((_ah)))
408 #define ath_hal_setrxfilter(_ah, _filter) \
409 ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
410 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
411 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
412 #define ath_hal_waitforbeacon(_ah, _bf) \
413 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
414 #define ath_hal_putrxbuf(_ah, _bufaddr) \
415 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
416 #define ath_hal_gettsf32(_ah) \
417 ((*(_ah)->ah_getTsf32)((_ah)))
418 #define ath_hal_gettsf64(_ah) \
419 ((*(_ah)->ah_getTsf64)((_ah)))
420 #define ath_hal_resettsf(_ah) \
421 ((*(_ah)->ah_resetTsf)((_ah)))
422 #define ath_hal_rxena(_ah) \
423 ((*(_ah)->ah_enableReceive)((_ah)))
424 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
425 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
426 #define ath_hal_gettxbuf(_ah, _q) \
427 ((*(_ah)->ah_getTxDP)((_ah), (_q)))
428 #define ath_hal_numtxpending(_ah, _q) \
429 ((*(_ah)->ah_numTxPending)((_ah), (_q)))
430 #define ath_hal_getrxbuf(_ah) \
431 ((*(_ah)->ah_getRxDP)((_ah)))
432 #define ath_hal_txstart(_ah, _q) \
433 ((*(_ah)->ah_startTxDma)((_ah), (_q)))
434 #define ath_hal_setchannel(_ah, _chan) \
435 ((*(_ah)->ah_setChannel)((_ah), (_chan)))
436 #define ath_hal_calibrate(_ah, _chan, _iqcal) \
437 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
438 #define ath_hal_setledstate(_ah, _state) \
439 ((*(_ah)->ah_setLedState)((_ah), (_state)))
440 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
441 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
442 #define ath_hal_beaconreset(_ah) \
443 ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
444 #define ath_hal_beacontimers(_ah, _bs) \
445 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
446 #define ath_hal_setassocid(_ah, _bss, _associd) \
447 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
448 #define ath_hal_phydisable(_ah) \
449 ((*(_ah)->ah_phyDisable)((_ah)))
450 #define ath_hal_setopmode(_ah) \
451 ((*(_ah)->ah_setPCUConfig)((_ah)))
452 #define ath_hal_stoptxdma(_ah, _qnum) \
453 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
454 #define ath_hal_stoppcurecv(_ah) \
455 ((*(_ah)->ah_stopPcuReceive)((_ah)))
456 #define ath_hal_startpcurecv(_ah) \
457 ((*(_ah)->ah_startPcuReceive)((_ah)))
458 #define ath_hal_stopdmarecv(_ah) \
459 ((*(_ah)->ah_stopDmaReceive)((_ah)))
460 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
461 ((*(_ah)->ah_getDiagState)((_ah), (_id), \
462 (_indata), (_insize), (_outdata), (_outsize)))
463 #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \
464 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize)
465 #define ath_hal_setuptxqueue(_ah, _type, _irq) \
466 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
467 #define ath_hal_resettxqueue(_ah, _q) \
468 ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
469 #define ath_hal_releasetxqueue(_ah, _q) \
470 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
471 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \
472 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
473 #define ath_hal_settxqueueprops(_ah, _q, _qi) \
474 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
475 #define ath_hal_getrfgain(_ah) \
476 ((*(_ah)->ah_getRfGain)((_ah)))
477 #define ath_hal_getdefantenna(_ah) \
478 ((*(_ah)->ah_getDefAntenna)((_ah)))
479 #define ath_hal_setdefantenna(_ah, _ant) \
480 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
481 #define ath_hal_rxmonitor(_ah, _arg, _chan) \
482 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
483 #define ath_hal_mibevent(_ah, _stats) \
484 ((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
485 #define ath_hal_setslottime(_ah, _us) \
486 ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
487 #define ath_hal_getslottime(_ah) \
488 ((*(_ah)->ah_getSlotTime)((_ah)))
489 #define ath_hal_setacktimeout(_ah, _us) \
490 ((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
491 #define ath_hal_getacktimeout(_ah) \
492 ((*(_ah)->ah_getAckTimeout)((_ah)))
493 #define ath_hal_setctstimeout(_ah, _us) \
494 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
495 #define ath_hal_getctstimeout(_ah) \
496 ((*(_ah)->ah_getCTSTimeout)((_ah)))
497 #define ath_hal_getcapability(_ah, _cap, _param, _result) \
498 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
499 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
500 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
501 #define ath_hal_ciphersupported(_ah, _cipher) \
502 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
503 #define ath_hal_getregdomain(_ah, _prd) \
504 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
505 #define ath_hal_setregdomain(_ah, _rd) \
506 (*(uint16_t *)(((uint8_t *)(_ah)) + 520) = (_rd))
507 #define ath_hal_getcountrycode(_ah, _pcc) \
508 (*(_pcc) = (_ah)->ah_countryCode)
509 #define ath_hal_gettkipmic(_ah) \
510 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK)
511 #define ath_hal_settkipmic(_ah, _v) \
512 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL)
513 #define ath_hal_hastkipsplit(_ah) \
514 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
515 #define ath_hal_gettkipsplit(_ah) \
516 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
517 #define ath_hal_settkipsplit(_ah, _v) \
518 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
519 #define ath_hal_haswmetkipmic(_ah) \
520 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK)
521 #define ath_hal_hwphycounters(_ah) \
522 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
523 #define ath_hal_hasdiversity(_ah) \
524 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
525 #define ath_hal_getdiversity(_ah) \
526 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
527 #define ath_hal_setdiversity(_ah, _v) \
528 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
529 #define ath_hal_getantennaswitch(_ah) \
530 ((*(_ah)->ah_getAntennaSwitch)((_ah)))
531 #define ath_hal_setantennaswitch(_ah, _v) \
532 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v)))
533 #define ath_hal_getdiag(_ah, _pv) \
534 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
535 #define ath_hal_setdiag(_ah, _v) \
536 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
537 #define ath_hal_getnumtxqueues(_ah, _pv) \
538 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
539 #define ath_hal_hasveol(_ah) \
540 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
541 #define ath_hal_hastxpowlimit(_ah) \
542 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
543 #define ath_hal_settxpowlimit(_ah, _pow) \
544 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
545 #define ath_hal_gettxpowlimit(_ah, _ppow) \
546 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
547 #define ath_hal_getmaxtxpow(_ah, _ppow) \
548 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
549 #define ath_hal_gettpscale(_ah, _scale) \
550 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
551 #define ath_hal_settpscale(_ah, _v) \
552 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
553 #define ath_hal_hastpc(_ah) \
554 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
555 #define ath_hal_gettpc(_ah) \
556 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
557 #define ath_hal_settpc(_ah, _v) \
558 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
559 #define ath_hal_hasbursting(_ah) \
560 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
562 #define ath_hal_hasmcastkeysearch(_ah) \
563 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
564 #define ath_hal_getmcastkeysearch(_ah) \
565 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
567 #define ath_hal_getmcastkeysearch(_ah) 0
569 #define ath_hal_hasfastframes(_ah) \
570 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK)
571 #define ath_hal_hasbssidmask(_ah) \
572 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK)
573 #define ath_hal_hastsfadjust(_ah) \
574 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK)
575 #define ath_hal_gettsfadjust(_ah) \
576 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK)
577 #define ath_hal_settsfadjust(_ah, _onoff) \
578 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL)
579 #define ath_hal_hasrfsilent(_ah) \
580 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
581 #define ath_hal_getrfkill(_ah) \
582 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
583 #define ath_hal_setrfkill(_ah, _onoff) \
584 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
585 #define ath_hal_getrfsilent(_ah, _prfsilent) \
586 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
587 #define ath_hal_setrfsilent(_ah, _rfsilent) \
588 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
589 #define ath_hal_gettpack(_ah, _ptpack) \
590 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
591 #define ath_hal_settpack(_ah, _tpack) \
592 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
593 #define ath_hal_gettpcts(_ah, _ptpcts) \
594 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
595 #define ath_hal_settpcts(_ah, _tpcts) \
596 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
597 #define ath_hal_getchannoise(_ah, _c) \
598 ((*(_ah)->ah_getChanNoise)((_ah), (_c)))
599 #if HAL_ABI_VERSION < 0x05122200
600 #define HAL_TXQ_TXOKINT_ENABLE TXQ_FLAG_TXOKINT_ENABLE
601 #define HAL_TXQ_TXERRINT_ENABLE TXQ_FLAG_TXERRINT_ENABLE
602 #define HAL_TXQ_TXDESCINT_ENABLE TXQ_FLAG_TXDESCINT_ENABLE
603 #define HAL_TXQ_TXEOLINT_ENABLE TXQ_FLAG_TXEOLINT_ENABLE
604 #define HAL_TXQ_TXURNINT_ENABLE TXQ_FLAG_TXURNINT_ENABLE
606 #if HAL_ABI_VERSION < 0x06102501
607 #define ath_hal_ispublicsafetysku(ah) \
608 (((ah)->ah_regdomain == 0 && (ah)->ah_countryCode == 842) || \
609 (ah)->ah_regdomain == 0x12)
611 #if HAL_ABI_VERSION < 0x06122400
612 /* XXX yech, can't get to regdomain so just hack a compat shim */
613 #define ath_hal_isgsmsku(ah) \
614 ((ah)->ah_countryCode == 843)
616 #if HAL_ABI_VERSION < 0x07050400
617 /* compat shims so code compilers--it won't work though */
618 #define CHANNEL_HT20 0x10000
619 #define CHANNEL_HT40PLUS 0x20000
620 #define CHANNEL_HT40MINUS 0x40000
621 #define HAL_MODE_11NG_HT20 0x008000
622 #define HAL_MODE_11NA_HT20 0x010000
625 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
626 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
627 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \
628 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
629 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
630 _txr0, _txtr0, _keyix, _ant, _flags, \
631 _rtsrate, _rtsdura) \
632 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
633 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
634 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
635 #define ath_hal_setupxtxdesc(_ah, _ds, \
636 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
637 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
638 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
639 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
640 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
641 #define ath_hal_txprocdesc(_ah, _ds, _ts) \
642 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
643 #define ath_hal_gettxintrtxqs(_ah, _txqs) \
644 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
646 #define ath_hal_gpioCfgOutput(_ah, _gpio) \
647 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio)))
648 #define ath_hal_gpioset(_ah, _gpio, _b) \
649 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
650 #define ath_hal_gpioget(_ah, _gpio) \
651 ((*(_ah)->ah_gpioGet)((_ah), (_gpio)))
652 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \
653 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b)))
655 #define ath_hal_radar_wait(_ah, _chan) \
656 ((*(_ah)->ah_radarWait)((_ah), (_chan)))
658 #endif /* _DEV_ATH_ATHVAR_H */