2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
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8 * modification, are permitted provided that the following conditions
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35 * Defintions for the Atheros Wireless LAN controller driver.
37 #ifndef _DEV_ATH_ATHVAR_H
38 #define _DEV_ATH_ATHVAR_H
40 #include <machine/atomic.h>
42 #include <dev/ath/ath_hal/ah.h>
43 #include <dev/ath/ath_hal/ah_desc.h>
44 #include <net80211/ieee80211_radiotap.h>
45 #include <dev/ath/if_athioctl.h>
46 #include <dev/ath/if_athrate.h>
48 #include <dev/ath/if_ath_alq.h>
51 #define ATH_TIMEOUT 1000
54 * There is a separate TX ath_buf pool for management frames.
55 * This ensures that management frames such as probe responses
56 * and BAR frames can be transmitted during periods of high
59 #define ATH_MGMT_TXBUF 32
62 * 802.11n requires more TX and RX buffers to do AMPDU.
70 #define ATH_RXBUF 40 /* number of RX buffers */
73 #define ATH_TXBUF 200 /* number of TX buffers */
75 #define ATH_BCBUF 4 /* number of beacon buffers */
77 #define ATH_TXDESC 10 /* number of descriptors per buffer */
78 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */
79 #define ATH_TXMGTTRY 4 /* xmit attempts for mgt/ctl frames */
80 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */
82 #define ATH_BEACON_AIFS_DEFAULT 1 /* default aifs for ap beacon q */
83 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */
84 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */
87 * The following bits can be set during the PCI (and perhaps non-PCI
88 * later) device probe path.
90 * It controls some of the driver and HAL behaviour.
93 #define ATH_PCI_CUS198 0x0001
94 #define ATH_PCI_CUS230 0x0002
95 #define ATH_PCI_CUS217 0x0004
96 #define ATH_PCI_CUS252 0x0008
97 #define ATH_PCI_WOW 0x0010
98 #define ATH_PCI_BT_ANT_DIV 0x0020
99 #define ATH_PCI_D3_L1_WAR 0x0040
100 #define ATH_PCI_AR9565_1ANT 0x0080
101 #define ATH_PCI_AR9565_2ANT 0x0100
102 #define ATH_PCI_NO_PLL_PWRSAVE 0x0200
103 #define ATH_PCI_KILLER 0x0400
106 * The key cache is used for h/w cipher state and also for
107 * tracking station state such as the current tx antenna.
108 * We also setup a mapping table between key cache slot indices
109 * and station state to short-circuit node lookups on rx.
110 * Different parts have different size key caches. We handle
111 * up to ATH_KEYMAX entries (could dynamically allocate state).
113 #define ATH_KEYMAX 128 /* max key cache size we handle */
114 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */
120 #define ATH_TID_MAX_BUFS (2 * IEEE80211_AGGR_BAWMAX)
125 * Note that TID 16 (WME_NUM_TID+1) is for handling non-QoS frames.
128 TAILQ_HEAD(,ath_buf) tid_q; /* pending buffers */
129 struct ath_node *an; /* pointer to parent */
131 int ac; /* which AC gets this traffic */
132 int hwq_depth; /* how many buffers are on HW */
133 u_int axq_depth; /* SW queue depth */
136 TAILQ_HEAD(,ath_buf) tid_q; /* filtered queue */
137 u_int axq_depth; /* SW queue depth */
141 * Entry on the ath_txq; when there's traffic
144 TAILQ_ENTRY(ath_tid) axq_qelem;
146 int paused; /* >0 if the TID has been paused */
149 * These are flags - perhaps later collapse
150 * down to a single uint32_t ?
152 int addba_tx_pending; /* TX ADDBA pending */
153 int bar_wait; /* waiting for BAR */
154 int bar_tx; /* BAR TXed */
155 int isfiltered; /* is this node currently filtered */
158 * Is the TID being cleaned up after a transition
159 * from aggregation to non-aggregation?
160 * When this is set to 1, this TID will be paused
161 * and no further traffic will be queued until all
162 * the hardware packets pending for this TID have been
163 * TXed/completed; at which point (non-aggregation)
164 * traffic will resume being TXed.
166 int cleanup_inprogress;
168 * How many hardware-queued packets are
169 * waiting to be cleaned up.
170 * This is only valid if cleanup_inprogress is 1.
175 * The following implements a ring representing
176 * the frames in the current BAW.
177 * To avoid copying the array content each time
178 * the BAW is moved, the baw_head/baw_tail point
179 * to the current BAW begin/end; when the BAW is
180 * shifted the head/tail of the array are also
181 * appropriately shifted.
183 /* active tx buffers, beginning at current BAW */
184 struct ath_buf *tx_buf[ATH_TID_MAX_BUFS];
185 /* where the baw head is in the array */
187 /* where the BAW tail is in the array */
191 /* driver-specific node state */
193 struct ieee80211_node an_node; /* base class */
194 u_int8_t an_mgmtrix; /* min h/w rate index */
195 u_int8_t an_mcastrix; /* mcast h/w rate index */
196 uint32_t an_is_powersave; /* node is sleeping */
197 uint32_t an_stack_psq; /* net80211 psq isn't empty */
198 uint32_t an_tim_set; /* TIM has been set */
199 struct ath_buf *an_ff_buf[WME_NUM_AC]; /* ff staging area */
200 struct ath_tid an_tid[IEEE80211_TID_SIZE]; /* per-TID state */
201 char an_name[32]; /* eg "wlan0_a1" */
202 struct mtx an_mtx; /* protecting the rate control state */
203 uint32_t an_swq_depth; /* how many SWQ packets for this
205 int clrdmask; /* has clrdmask been set */
206 uint32_t an_leak_count; /* How many frames to leak during pause */
207 HAL_NODE_STATS an_node_stats; /* HAL node stats for this node */
208 /* variable-length rate control state follows */
210 #define ATH_NODE(ni) ((struct ath_node *)(ni))
211 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni))
213 #define ATH_RSSI_LPF_LEN 10
214 #define ATH_RSSI_DUMMY_MARKER 0x127
215 #define ATH_EP_MUL(x, mul) ((x) * (mul))
216 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
217 #define ATH_LPF_RSSI(x, y, len) \
218 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
219 #define ATH_RSSI_LPF(x, y) do { \
221 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
223 #define ATH_EP_RND(x,mul) \
224 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
225 #define ATH_RSSI(x) ATH_EP_RND(x, HAL_RSSI_EP_MULTIPLIER)
228 ATH_BUFTYPE_NORMAL = 0,
229 ATH_BUFTYPE_MGMT = 1,
233 TAILQ_ENTRY(ath_buf) bf_list;
234 struct ath_buf * bf_next; /* next buffer in the aggregate */
236 HAL_STATUS bf_rxstatus;
237 uint16_t bf_flags; /* status flags (below) */
238 uint16_t bf_descid; /* 16 bit descriptor ID */
239 struct ath_desc *bf_desc; /* virtual addr of desc */
240 struct ath_desc_status bf_status; /* tx/rx status */
241 bus_addr_t bf_daddr; /* physical addr of desc */
242 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */
243 struct mbuf *bf_m; /* mbuf for buf */
244 struct ieee80211_node *bf_node; /* pointer to the node */
245 struct ath_desc *bf_lastds; /* last descriptor for comp status */
246 struct ath_buf *bf_last; /* last buffer in aggregate, or self for non-aggregate */
247 bus_size_t bf_mapsize;
248 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */
249 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER];
250 uint32_t bf_nextfraglen; /* length of next fragment */
252 /* Completion function to call on TX complete (fail or not) */
254 * "fail" here is set to 1 if the queue entries were removed
255 * through a call to ath_tx_draintxq().
257 void(* bf_comp) (struct ath_softc *sc, struct ath_buf *bf, int fail);
259 /* This state is kept to support software retries and aggregation */
261 uint16_t bfs_seqno; /* sequence number of this packet */
262 uint16_t bfs_ndelim; /* number of delims for padding */
264 uint8_t bfs_retries; /* retry count */
265 uint8_t bfs_tid; /* packet TID (or TID_MAX for no QoS) */
266 uint8_t bfs_nframes; /* number of frames in aggregate */
267 uint8_t bfs_pri; /* packet AC priority */
268 uint8_t bfs_tx_queue; /* destination hardware TX queue */
270 u_int32_t bfs_aggr:1, /* part of aggregate? */
271 bfs_aggrburst:1, /* part of aggregate burst? */
272 bfs_isretried:1, /* retried frame? */
273 bfs_dobaw:1, /* actually check against BAW? */
274 bfs_addedbaw:1, /* has been added to the BAW */
275 bfs_shpream:1, /* use short preamble */
276 bfs_istxfrag:1, /* is fragmented */
277 bfs_ismrr:1, /* do multi-rate TX retry */
278 bfs_doprot:1, /* do RTS/CTS based protection */
279 bfs_doratelookup:1; /* do rate lookup before each TX */
282 * These fields are passed into the
283 * descriptor setup functions.
286 /* Make this an 8 bit value? */
287 HAL_PKT_TYPE bfs_atype; /* packet type */
289 uint32_t bfs_pktlen; /* length of this packet */
291 uint16_t bfs_hdrlen; /* length of this packet header */
292 uint16_t bfs_al; /* length of aggregate */
294 uint16_t bfs_txflags; /* HAL (tx) descriptor flags */
295 uint8_t bfs_txrate0; /* first TX rate */
296 uint8_t bfs_try0; /* first try count */
298 uint16_t bfs_txpower; /* tx power */
299 uint8_t bfs_ctsrate0; /* Non-zero - use this as ctsrate */
300 uint8_t bfs_ctsrate; /* CTS rate */
303 int32_t bfs_keyix; /* crypto key index */
304 int32_t bfs_txantenna; /* TX antenna config */
306 /* Make this an 8 bit value? */
307 enum ieee80211_protmode bfs_protmode;
310 uint32_t bfs_ctsduration; /* CTS duration (pre-11n NICs) */
311 struct ath_rc_series bfs_rc[ATH_RC_NUM]; /* non-11n TX series */
314 typedef TAILQ_HEAD(ath_bufhead_s, ath_buf) ath_bufhead;
316 #define ATH_BUF_MGMT 0x00000001 /* (tx) desc is a mgmt desc */
317 #define ATH_BUF_BUSY 0x00000002 /* (tx) desc owned by h/w */
318 #define ATH_BUF_FIFOEND 0x00000004
319 #define ATH_BUF_FIFOPTR 0x00000008
320 #define ATH_BUF_TOA_PROBE 0x00000010 /* ToD/ToA exchange probe */
322 #define ATH_BUF_FLAGS_CLONE (ATH_BUF_MGMT | ATH_BUF_TOA_PROBE)
325 * DMA state for tx/rx descriptors.
329 struct ath_desc *dd_desc; /* descriptors */
330 int dd_descsize; /* size of single descriptor */
331 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
332 bus_size_t dd_desc_len; /* size of dd_desc */
333 bus_dma_segment_t dd_dseg;
334 bus_dma_tag_t dd_dmat; /* bus DMA tag */
335 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
336 struct ath_buf *dd_bufptr; /* associated buffers */
340 * Data transmit queue state. One of these exists for each
341 * hardware transmit queue. Packets sent to us from above
342 * are assigned to queues based on their priority. Not all
343 * devices support a complete set of hardware transmit queues.
344 * For those devices the array sc_ac2q will map multiple
345 * priorities to fewer hardware queues (typically all to one
349 struct ath_softc *axq_softc; /* Needed for scheduling */
350 u_int axq_qnum; /* hardware q number */
351 #define ATH_TXQ_SWQ (HAL_NUM_TX_QUEUES+1) /* qnum for s/w only queue */
352 u_int axq_ac; /* WME AC */
354 //#define ATH_TXQ_PUTPENDING 0x0001 /* ath_hal_puttxbuf pending */
355 #define ATH_TXQ_PUTRUNNING 0x0002 /* ath_hal_puttxbuf has been called */
356 u_int axq_depth; /* queue depth (stat only) */
357 u_int axq_aggr_depth; /* how many aggregates are queued */
358 u_int axq_intrcnt; /* interrupt count */
359 u_int32_t *axq_link; /* link ptr in last TX desc */
360 TAILQ_HEAD(axq_q_s, ath_buf) axq_q; /* transmit queue */
361 struct mtx axq_lock; /* lock on q and link */
364 * This is the FIFO staging buffer when doing EDMA.
366 * For legacy chips, we just push the head pointer to
367 * the hardware and we ignore this list.
369 * For EDMA, the staging buffer is treated as normal;
370 * when it's time to push a list of frames to the hardware
371 * we move that list here and we stamp buffers with
372 * flags to identify the beginning/end of that particular
376 TAILQ_HEAD(axq_q_f_s, ath_buf) axq_q;
377 u_int axq_depth; /* how many frames (1 per legacy, 1 per A-MPDU list) are in the FIFO queue */
379 u_int axq_fifo_depth; /* how many FIFO slots are active */
382 * XXX the holdingbf field is protected by the TXBUF lock
383 * for now, NOT the TXQ lock.
385 * Architecturally, it would likely be better to move
386 * the holdingbf field to a separate array in ath_softc
387 * just to highlight that it's not protected by the normal
390 struct ath_buf *axq_holdingbf; /* holding TX buffer */
391 char axq_name[12]; /* e.g. "ath0_txq4" */
393 /* Per-TID traffic queue for software -> hardware TX */
395 * This is protected by the general TX path lock, not (for now)
398 TAILQ_HEAD(axq_t_s,ath_tid) axq_tidq;
401 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \
402 snprintf((_tq)->axq_name, sizeof((_tq)->axq_name), "%s_txq%u", \
403 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \
404 mtx_init(&(_tq)->axq_lock, (_tq)->axq_name, NULL, MTX_DEF); \
406 #define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock)
407 #define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock)
408 #define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock)
409 #define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED)
410 #define ATH_TXQ_UNLOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, \
414 #define ATH_NODE_LOCK(_an) mtx_lock(&(_an)->an_mtx)
415 #define ATH_NODE_UNLOCK(_an) mtx_unlock(&(_an)->an_mtx)
416 #define ATH_NODE_LOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, MA_OWNED)
417 #define ATH_NODE_UNLOCK_ASSERT(_an) mtx_assert(&(_an)->an_mtx, \
421 * These are for the hardware queue.
423 #define ATH_TXQ_INSERT_HEAD(_tq, _elm, _field) do { \
424 TAILQ_INSERT_HEAD(&(_tq)->axq_q, (_elm), _field); \
425 (_tq)->axq_depth++; \
427 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
428 TAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
429 (_tq)->axq_depth++; \
431 #define ATH_TXQ_REMOVE(_tq, _elm, _field) do { \
432 TAILQ_REMOVE(&(_tq)->axq_q, _elm, _field); \
433 (_tq)->axq_depth--; \
435 #define ATH_TXQ_FIRST(_tq) TAILQ_FIRST(&(_tq)->axq_q)
436 #define ATH_TXQ_LAST(_tq, _field) TAILQ_LAST(&(_tq)->axq_q, _field)
439 * These are for the TID software queue.
441 #define ATH_TID_INSERT_HEAD(_tq, _elm, _field) do { \
442 TAILQ_INSERT_HEAD(&(_tq)->tid_q, (_elm), _field); \
443 (_tq)->axq_depth++; \
444 (_tq)->an->an_swq_depth++; \
446 #define ATH_TID_INSERT_TAIL(_tq, _elm, _field) do { \
447 TAILQ_INSERT_TAIL(&(_tq)->tid_q, (_elm), _field); \
448 (_tq)->axq_depth++; \
449 (_tq)->an->an_swq_depth++; \
451 #define ATH_TID_REMOVE(_tq, _elm, _field) do { \
452 TAILQ_REMOVE(&(_tq)->tid_q, _elm, _field); \
453 (_tq)->axq_depth--; \
454 (_tq)->an->an_swq_depth--; \
456 #define ATH_TID_FIRST(_tq) TAILQ_FIRST(&(_tq)->tid_q)
457 #define ATH_TID_LAST(_tq, _field) TAILQ_LAST(&(_tq)->tid_q, _field)
460 * These are for the TID filtered frame queue
462 #define ATH_TID_FILT_INSERT_HEAD(_tq, _elm, _field) do { \
463 TAILQ_INSERT_HEAD(&(_tq)->filtq.tid_q, (_elm), _field); \
464 (_tq)->axq_depth++; \
465 (_tq)->an->an_swq_depth++; \
467 #define ATH_TID_FILT_INSERT_TAIL(_tq, _elm, _field) do { \
468 TAILQ_INSERT_TAIL(&(_tq)->filtq.tid_q, (_elm), _field); \
469 (_tq)->axq_depth++; \
470 (_tq)->an->an_swq_depth++; \
472 #define ATH_TID_FILT_REMOVE(_tq, _elm, _field) do { \
473 TAILQ_REMOVE(&(_tq)->filtq.tid_q, _elm, _field); \
474 (_tq)->axq_depth--; \
475 (_tq)->an->an_swq_depth--; \
477 #define ATH_TID_FILT_FIRST(_tq) TAILQ_FIRST(&(_tq)->filtq.tid_q)
478 #define ATH_TID_FILT_LAST(_tq, _field) TAILQ_LAST(&(_tq)->filtq.tid_q,_field)
481 struct ieee80211vap av_vap; /* base class */
482 int av_bslot; /* beacon slot index */
483 struct ath_buf *av_bcbuf; /* beacon buffer */
484 struct ath_txq av_mcastq; /* buffered mcast s/w queue */
486 void (*av_recv_mgmt)(struct ieee80211_node *,
488 const struct ieee80211_rx_stats *, int, int);
489 int (*av_newstate)(struct ieee80211vap *,
490 enum ieee80211_state, int);
491 void (*av_bmiss)(struct ieee80211vap *);
492 void (*av_node_ps)(struct ieee80211_node *, int);
493 int (*av_set_tim)(struct ieee80211_node *, int);
494 void (*av_recv_pspoll)(struct ieee80211_node *,
496 struct ieee80211_quiet_ie quiet_ie;
498 #define ATH_VAP(vap) ((struct ath_vap *)(vap))
504 * Whether to reset the TX/RX queue with or without
508 ATH_RESET_DEFAULT = 0,
509 ATH_RESET_NOLOSS = 1,
513 struct ath_rx_methods {
514 void (*recv_sched_queue)(struct ath_softc *sc,
515 HAL_RX_QUEUE q, int dosched);
516 void (*recv_sched)(struct ath_softc *sc, int dosched);
517 void (*recv_stop)(struct ath_softc *sc, int dodelay);
518 int (*recv_start)(struct ath_softc *sc);
519 void (*recv_flush)(struct ath_softc *sc);
520 void (*recv_tasklet)(void *arg, int npending);
521 int (*recv_rxbuf_init)(struct ath_softc *sc,
523 int (*recv_setup)(struct ath_softc *sc);
524 int (*recv_teardown)(struct ath_softc *sc);
528 * Represent the current state of the RX FIFO.
531 struct ath_buf **m_fifo;
536 struct mbuf *m_rxpending;
537 struct ath_buf *m_holdbf;
540 struct ath_tx_edma_fifo {
541 struct ath_buf **m_fifo;
548 struct ath_tx_methods {
549 int (*xmit_setup)(struct ath_softc *sc);
550 int (*xmit_teardown)(struct ath_softc *sc);
551 void (*xmit_attach_comp_func)(struct ath_softc *sc);
553 void (*xmit_dma_restart)(struct ath_softc *sc,
554 struct ath_txq *txq);
555 void (*xmit_handoff)(struct ath_softc *sc,
556 struct ath_txq *txq, struct ath_buf *bf);
557 void (*xmit_drain)(struct ath_softc *sc,
558 ATH_RESET_TYPE reset_type);
562 struct ieee80211com sc_ic;
563 struct ath_stats sc_stats; /* device statistics */
564 struct ath_tx_aggr_stats sc_aggr_stats;
565 struct ath_intr_stats sc_intr_stats;
567 uint64_t sc_ktrdebug;
568 int sc_nvaps; /* # vaps */
569 int sc_nstavaps; /* # station vaps */
570 int sc_nmeshvaps; /* # mbss vaps */
571 u_int8_t sc_hwbssidmask[IEEE80211_ADDR_LEN];
572 u_int8_t sc_nbssid0; /* # vap's using base mac */
573 uint32_t sc_bssidmask; /* bssid mask */
575 struct ath_rx_methods sc_rx;
576 struct ath_rx_edma sc_rxedma[HAL_NUM_RX_QUEUES]; /* HP/LP queues */
577 ath_bufhead sc_rx_rxlist[HAL_NUM_RX_QUEUES]; /* deferred RX completion */
578 struct ath_tx_methods sc_tx;
579 struct ath_tx_edma_fifo sc_txedma[HAL_NUM_TX_QUEUES];
582 * This is (currently) protected by the TX queue lock;
583 * it should migrate to a separate lock later
584 * so as to minimise contention.
586 ath_bufhead sc_txbuf_list;
591 int sc_tx_nmaps; /* Number of TX maps */
593 int sc_rx_stopped; /* XXX only for EDMA */
594 int sc_rx_resetted; /* XXX only for EDMA */
596 void (*sc_node_cleanup)(struct ieee80211_node *);
597 void (*sc_node_free)(struct ieee80211_node *);
599 HAL_BUS_TAG sc_st; /* bus space tag */
600 HAL_BUS_HANDLE sc_sh; /* bus space handle */
601 bus_dma_tag_t sc_dmat; /* bus DMA tag */
602 struct mtx sc_mtx; /* master lock (recursive) */
603 struct mtx sc_pcu_mtx; /* PCU access mutex */
604 char sc_pcu_mtx_name[32];
605 struct mtx sc_rx_mtx; /* RX access mutex */
606 char sc_rx_mtx_name[32];
607 struct mtx sc_tx_mtx; /* TX handling/comp mutex */
608 char sc_tx_mtx_name[32];
609 struct mtx sc_tx_ic_mtx; /* TX queue mutex */
610 char sc_tx_ic_mtx_name[32];
611 struct taskqueue *sc_tq; /* private task queue */
612 struct ath_hal *sc_ah; /* Atheros HAL */
613 struct ath_ratectrl *sc_rc; /* tx rate control support */
614 struct ath_tx99 *sc_tx99; /* tx99 adjunct state */
615 void (*sc_setdefantenna)(struct ath_softc *, u_int);
618 * First set of flags.
620 uint32_t sc_invalid : 1,/* disable hardware accesses */
621 sc_mrretry : 1,/* multi-rate retry support */
622 sc_mrrprot : 1,/* MRR + protection support */
623 sc_softled : 1,/* enable LED gpio status */
624 sc_hardled : 1,/* enable MAC LED status */
625 sc_splitmic : 1,/* split TKIP MIC keys */
626 sc_needmib : 1,/* enable MIB stats intr */
627 sc_diversity: 1,/* enable rx diversity */
628 sc_hasveol : 1,/* tx VEOL support */
629 sc_ledstate : 1,/* LED on/off state */
630 sc_blinking : 1,/* LED blink operation active */
631 sc_mcastkey : 1,/* mcast key cache search */
632 sc_scanning : 1,/* scanning active */
633 sc_syncbeacon:1,/* sync/resync beacon timers */
634 sc_hasclrkey: 1,/* CLR key supported */
635 sc_xchanmode: 1,/* extended channel mode */
636 sc_outdoor : 1,/* outdoor operation */
637 sc_dturbo : 1,/* dynamic turbo in use */
638 sc_hasbmask : 1,/* bssid mask support */
639 sc_hasbmatch: 1,/* bssid match disable support*/
640 sc_hastsfadd: 1,/* tsf adjust support */
641 sc_beacons : 1,/* beacons running */
642 sc_swbmiss : 1,/* sta mode using sw bmiss */
643 sc_stagbeacons:1,/* use staggered beacons */
644 sc_wmetkipmic:1,/* can do WME+TKIP MIC */
645 sc_resume_up: 1,/* on resume, start all vaps */
646 sc_tdma : 1,/* TDMA in use */
647 sc_setcca : 1,/* set/clr CCA with TDMA */
648 sc_resetcal : 1,/* reset cal state next trip */
649 sc_rxslink : 1,/* do self-linked final descriptor */
650 sc_rxtsf32 : 1,/* RX dec TSF is 32 bits */
651 sc_isedma : 1,/* supports EDMA */
652 sc_do_mybeacon : 1; /* supports mybeacon */
655 * Second set of flags.
657 u_int32_t sc_running : 1, /* initialized */
662 sc_hasenforcetxop : 1, /* support enforce TxOP */
663 sc_hasdivcomb : 1, /* RX diversity combining */
664 sc_rx_lnamixer : 1, /* RX using LNA mixing */
665 sc_btcoex_mci : 1; /* MCI bluetooth coex */
667 int sc_cabq_enable; /* Enable cabq transmission */
670 * Enterprise mode configuration for AR9380 and later chipsets.
674 uint32_t sc_eerd; /* regdomain from EEPROM */
675 uint32_t sc_eecc; /* country code from EEPROM */
677 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
678 const HAL_RATE_TABLE *sc_currates; /* current rate table */
679 enum ieee80211_phymode sc_curmode; /* current phy mode */
680 HAL_OPMODE sc_opmode; /* current operating mode */
681 u_int16_t sc_curtxpow; /* current tx power limit */
682 u_int16_t sc_curaid; /* current association id */
683 struct ieee80211_channel *sc_curchan; /* current installed channel */
684 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN];
685 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
687 u_int8_t ieeerate; /* IEEE rate */
688 u_int8_t rxflags; /* radiotap rx flags */
689 u_int8_t txflags; /* radiotap tx flags */
690 u_int16_t ledon; /* softled on time */
691 u_int16_t ledoff; /* softled off time */
692 } sc_hwmap[32]; /* h/w rate ix mappings */
693 u_int8_t sc_protrix; /* protection rate index */
694 u_int8_t sc_lastdatarix; /* last data frame rate index */
695 u_int sc_mcastrate; /* ieee rate for mcastrateix */
696 u_int sc_fftxqmin; /* min frames before staging */
697 u_int sc_fftxqmax; /* max frames before drop */
698 u_int sc_txantenna; /* tx antenna (fixed or auto) */
700 HAL_INT sc_imask; /* interrupt mask copy */
703 * These are modified in the interrupt handler as well as
704 * the task queues and other contexts. Thus these must be
705 * protected by a mutex, or they could clash.
707 * For now, access to these is behind the ATH_LOCK,
710 uint32_t sc_txq_active; /* bitmap of active TXQs */
711 uint32_t sc_kickpcu; /* whether to kick the PCU */
712 uint32_t sc_rxproc_cnt; /* In RX processing */
713 uint32_t sc_txproc_cnt; /* In TX processing */
714 uint32_t sc_txstart_cnt; /* In TX output (raw/start) */
715 uint32_t sc_inreset_cnt; /* In active reset/chanchange */
716 uint32_t sc_txrx_cnt; /* refcount on stop/start'ing TX */
717 uint32_t sc_intr_cnt; /* refcount on interrupt handling */
719 u_int sc_keymax; /* size of key cache */
720 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */
723 * Software based LED blinking
725 u_int sc_ledpin; /* GPIO pin for driving LED */
726 u_int sc_ledon; /* pin setting for LED on */
727 u_int sc_ledidle; /* idle polling interval */
728 int sc_ledevent; /* time of last LED event */
729 u_int8_t sc_txrix; /* current tx rate for LED */
730 u_int16_t sc_ledoff; /* off time for current blink */
731 struct callout sc_ledtimer; /* led off timer */
734 * Hardware based LED blinking
736 int sc_led_pwr_pin; /* MAC power LED GPIO pin */
737 int sc_led_net_pin; /* MAC network LED GPIO pin */
739 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */
740 u_int sc_rfsilentpol; /* pin setting for rfkill on */
742 struct ath_descdma sc_rxdma; /* RX descriptors */
743 ath_bufhead sc_rxbuf; /* receive buffer */
744 u_int32_t *sc_rxlink; /* link ptr in last RX desc */
745 struct task sc_rxtask; /* rx int processing */
746 u_int8_t sc_defant; /* current default antenna */
747 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
748 u_int64_t sc_lastrx; /* tsf at last rx'd frame */
749 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */
750 struct ath_rx_radiotap_header sc_rx_th;
752 u_int sc_monpass; /* frames to pass in mon.mode */
754 struct ath_descdma sc_txdma; /* TX descriptors */
755 uint16_t sc_txbuf_descid;
756 ath_bufhead sc_txbuf; /* transmit buffer */
757 int sc_txbuf_cnt; /* how many buffers avail */
758 struct ath_descdma sc_txdma_mgmt; /* mgmt TX descriptors */
759 ath_bufhead sc_txbuf_mgmt; /* mgmt transmit buffer */
760 struct ath_descdma sc_txsdma; /* EDMA TX status desc's */
761 struct mtx sc_txbuflock; /* txbuf lock */
762 char sc_txname[12]; /* e.g. "ath0_buf" */
763 u_int sc_txqsetup; /* h/w queues setup */
764 u_int sc_txintrperiod;/* tx interrupt batching */
765 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
766 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
767 struct task sc_txtask; /* tx int processing */
768 struct task sc_txqtask; /* tx proc processing */
770 struct ath_descdma sc_txcompdma; /* TX EDMA completion */
771 struct mtx sc_txcomplock; /* TX EDMA completion lock */
772 char sc_txcompname[12]; /* eg ath0_txcomp */
774 int sc_wd_timer; /* count down for wd timer */
775 struct callout sc_wd_ch; /* tx watchdog timer */
776 struct ath_tx_radiotap_header sc_tx_th;
779 struct ath_descdma sc_bdma; /* beacon descriptors */
780 ath_bufhead sc_bbuf; /* beacon buffers */
781 u_int sc_bhalq; /* HAL q for outgoing beacons */
782 u_int sc_bmisscount; /* missed beacon transmits */
783 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
784 struct ath_txq *sc_cabq; /* tx q for cab frames */
785 struct task sc_bmisstask; /* bmiss int processing */
786 struct task sc_bstucktask; /* stuck beacon processing */
787 struct task sc_resettask; /* interface reset task */
788 struct task sc_fataltask; /* fatal task */
790 OK, /* no change needed */
791 UPDATE, /* update pending */
792 COMMIT /* beacon sent, commit change */
793 } sc_updateslot; /* slot time update fsm */
794 int sc_slotupdate; /* slot to advance fsm */
795 struct ieee80211vap *sc_bslot[ATH_BCBUF];
796 int sc_nbcnvaps; /* # vaps with beacons */
798 struct callout sc_cal_ch; /* callout handle for cals */
799 int sc_lastlongcal; /* last long cal completed */
800 int sc_lastcalreset;/* last cal reset done */
801 int sc_lastani; /* last ANI poll */
802 int sc_lastshortcal; /* last short calibration */
803 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */
804 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */
805 u_int sc_tdmadbaprep; /* TDMA DBA prep time */
806 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */
807 u_int sc_tdmaswba; /* TDMA SWBA counter */
808 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */
809 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */
810 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */
811 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */
812 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */
813 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */
814 uint32_t sc_txchainmask; /* hardware TX chainmask */
815 uint32_t sc_rxchainmask; /* hardware RX chainmask */
816 uint32_t sc_cur_txchainmask; /* currently configured TX chainmask */
817 uint32_t sc_cur_rxchainmask; /* currently configured RX chainmask */
818 uint32_t sc_rts_aggr_limit; /* TX limit on RTS aggregates */
819 int sc_aggr_limit; /* TX limit on all aggregates */
820 int sc_delim_min_pad; /* Minimum delimiter count */
825 * To avoid queue starvation in congested conditions,
826 * these parameters tune the maximum number of frames
827 * queued to the data/mcastq before they're dropped.
829 * This is to prevent:
830 * + a single destination overwhelming everything, including
831 * management/multicast frames;
832 * + multicast frames overwhelming everything (when the
833 * air is sufficiently busy that cabq can't drain.)
834 * + A node in powersave shouldn't be allowed to exhaust
835 * all available mbufs;
838 * + data_minfree is the maximum number of free buffers
839 * overall to successfully allow a data frame.
841 * + mcastq_maxdepth is the maximum depth allowed of the cabq.
843 int sc_txq_node_maxdepth;
844 int sc_txq_data_minfree;
845 int sc_txq_mcastq_maxdepth;
846 int sc_txq_node_psq_maxdepth;
849 * Software queue twiddles
852 * when to begin limiting non-aggregate frames to the
853 * hardware queue, regardless of the TID.
855 * when to begin limiting A-MPDU frames to the
856 * hardware queue, regardless of the TID.
857 * tid_hwq_lo: how low the per-TID hwq count has to be before the
858 * TID will be scheduled again
859 * tid_hwq_hi: how many frames to queue to the HWQ before the TID
860 * stops being scheduled.
862 int sc_hwq_limit_nonaggr;
863 int sc_hwq_limit_aggr;
867 /* DFS related state */
868 void *sc_dfs; /* Used by an optional DFS module */
869 int sc_dodfs; /* Whether to enable DFS rx filter bits */
870 struct task sc_dfstask; /* DFS processing task */
872 /* Spectral related state */
876 /* LNA diversity related state */
882 struct if_ath_alq sc_alq;
885 /* TX AMPDU handling */
886 int (*sc_addba_request)(struct ieee80211_node *,
887 struct ieee80211_tx_ampdu *, int, int, int);
888 int (*sc_addba_response)(struct ieee80211_node *,
889 struct ieee80211_tx_ampdu *, int, int, int);
890 void (*sc_addba_stop)(struct ieee80211_node *,
891 struct ieee80211_tx_ampdu *);
892 void (*sc_addba_response_timeout)
893 (struct ieee80211_node *,
894 struct ieee80211_tx_ampdu *);
895 void (*sc_bar_response)(struct ieee80211_node *ni,
896 struct ieee80211_tx_ampdu *tap,
900 * Powersave state tracking.
902 * target/cur powerstate is the chip power state.
903 * target selfgen state is the self-generated frames
904 * state. The chip can be awake but transmitted frames
905 * can have the PWRMGT bit set to 1 so the destination
906 * thinks the node is asleep.
908 HAL_POWER_MODE sc_target_powerstate;
909 HAL_POWER_MODE sc_target_selfgen_state;
911 HAL_POWER_MODE sc_cur_powerstate;
913 int sc_powersave_refcnt;
915 /* ATH_PCI_* flags */
916 uint32_t sc_pci_devinfo;
920 struct ath_descdma buf;
922 /* gpm/sched buffer, saved pointers */
924 bus_addr_t sched_paddr;
926 bus_addr_t gpm_paddr;
928 uint32_t wlan_channels[4];
932 #define ATH_LOCK_INIT(_sc) \
933 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
934 NULL, MTX_DEF | MTX_RECURSE)
935 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
936 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
937 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
938 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
939 #define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
942 * The TX lock is non-reentrant and serialises the TX frame send
943 * and completion operations.
945 #define ATH_TX_LOCK_INIT(_sc) do {\
946 snprintf((_sc)->sc_tx_mtx_name, \
947 sizeof((_sc)->sc_tx_mtx_name), \
949 device_get_nameunit((_sc)->sc_dev)); \
950 mtx_init(&(_sc)->sc_tx_mtx, (_sc)->sc_tx_mtx_name, \
953 #define ATH_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_tx_mtx)
954 #define ATH_TX_LOCK(_sc) mtx_lock(&(_sc)->sc_tx_mtx)
955 #define ATH_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_tx_mtx)
956 #define ATH_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \
958 #define ATH_TX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_tx_mtx, \
960 #define ATH_TX_TRYLOCK(_sc) (mtx_owned(&(_sc)->sc_tx_mtx) != 0 && \
961 mtx_trylock(&(_sc)->sc_tx_mtx))
964 * The PCU lock is non-recursive and should be treated as a spinlock.
965 * Although currently the interrupt code is run in netisr context and
966 * doesn't require this, this may change in the future.
967 * Please keep this in mind when protecting certain code paths
970 * The PCU lock is used to serialise access to the PCU so things such
971 * as TX, RX, state change (eg channel change), channel reset and updates
972 * from interrupt context (eg kickpcu, txqactive bits) do not clash.
974 * Although the current single-thread taskqueue mechanism protects the
975 * majority of these situations by simply serialising them, there are
976 * a few others which occur at the same time. These include the TX path
977 * (which only acquires ATH_LOCK when recycling buffers to the free list),
978 * ath_set_channel, the channel scanning API and perhaps quite a bit more.
980 #define ATH_PCU_LOCK_INIT(_sc) do {\
981 snprintf((_sc)->sc_pcu_mtx_name, \
982 sizeof((_sc)->sc_pcu_mtx_name), \
984 device_get_nameunit((_sc)->sc_dev)); \
985 mtx_init(&(_sc)->sc_pcu_mtx, (_sc)->sc_pcu_mtx_name, \
988 #define ATH_PCU_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_pcu_mtx)
989 #define ATH_PCU_LOCK(_sc) mtx_lock(&(_sc)->sc_pcu_mtx)
990 #define ATH_PCU_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_pcu_mtx)
991 #define ATH_PCU_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \
993 #define ATH_PCU_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_pcu_mtx, \
997 * The RX lock is primarily a(nother) workaround to ensure that the
998 * RX FIFO/list isn't modified by various execution paths.
999 * Even though RX occurs in a single context (the ath taskqueue), the
1000 * RX path can be executed via various reset/channel change paths.
1002 #define ATH_RX_LOCK_INIT(_sc) do {\
1003 snprintf((_sc)->sc_rx_mtx_name, \
1004 sizeof((_sc)->sc_rx_mtx_name), \
1006 device_get_nameunit((_sc)->sc_dev)); \
1007 mtx_init(&(_sc)->sc_rx_mtx, (_sc)->sc_rx_mtx_name, \
1010 #define ATH_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rx_mtx)
1011 #define ATH_RX_LOCK(_sc) mtx_lock(&(_sc)->sc_rx_mtx)
1012 #define ATH_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rx_mtx)
1013 #define ATH_RX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \
1015 #define ATH_RX_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_rx_mtx, \
1018 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
1020 #define ATH_TXBUF_LOCK_INIT(_sc) do { \
1021 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \
1022 device_get_nameunit((_sc)->sc_dev)); \
1023 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \
1025 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock)
1026 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock)
1027 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock)
1028 #define ATH_TXBUF_LOCK_ASSERT(_sc) \
1029 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
1030 #define ATH_TXBUF_UNLOCK_ASSERT(_sc) \
1031 mtx_assert(&(_sc)->sc_txbuflock, MA_NOTOWNED)
1033 #define ATH_TXSTATUS_LOCK_INIT(_sc) do { \
1034 snprintf((_sc)->sc_txcompname, sizeof((_sc)->sc_txcompname), \
1036 device_get_nameunit((_sc)->sc_dev)); \
1037 mtx_init(&(_sc)->sc_txcomplock, (_sc)->sc_txcompname, NULL, \
1040 #define ATH_TXSTATUS_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txcomplock)
1041 #define ATH_TXSTATUS_LOCK(_sc) mtx_lock(&(_sc)->sc_txcomplock)
1042 #define ATH_TXSTATUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txcomplock)
1043 #define ATH_TXSTATUS_LOCK_ASSERT(_sc) \
1044 mtx_assert(&(_sc)->sc_txcomplock, MA_OWNED)
1046 int ath_attach(u_int16_t, struct ath_softc *);
1047 int ath_detach(struct ath_softc *);
1048 void ath_resume(struct ath_softc *);
1049 void ath_suspend(struct ath_softc *);
1050 void ath_shutdown(struct ath_softc *);
1051 void ath_intr(void *);
1054 * HAL definitions to comply with local coding convention.
1056 #define ath_hal_detach(_ah) \
1057 ((*(_ah)->ah_detach)((_ah)))
1058 #define ath_hal_reset(_ah, _opmode, _chan, _fullreset, _resettype, _pstatus) \
1059 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_fullreset), \
1060 (_resettype), (_pstatus)))
1061 #define ath_hal_macversion(_ah) \
1062 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev))
1063 #define ath_hal_getratetable(_ah, _mode) \
1064 ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
1065 #define ath_hal_getmac(_ah, _mac) \
1066 ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
1067 #define ath_hal_setmac(_ah, _mac) \
1068 ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
1069 #define ath_hal_getbssidmask(_ah, _mask) \
1070 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask)))
1071 #define ath_hal_setbssidmask(_ah, _mask) \
1072 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask)))
1073 #define ath_hal_intrset(_ah, _mask) \
1074 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
1075 #define ath_hal_intrget(_ah) \
1076 ((*(_ah)->ah_getInterrupts)((_ah)))
1077 #define ath_hal_intrpend(_ah) \
1078 ((*(_ah)->ah_isInterruptPending)((_ah)))
1079 #define ath_hal_getisr(_ah, _pmask) \
1080 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
1081 #define ath_hal_updatetxtriglevel(_ah, _inc) \
1082 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
1083 #define ath_hal_setpower(_ah, _mode) \
1084 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE))
1085 #define ath_hal_setselfgenpower(_ah, _mode) \
1086 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_FALSE))
1087 #define ath_hal_keycachesize(_ah) \
1088 ((*(_ah)->ah_getKeyCacheSize)((_ah)))
1089 #define ath_hal_keyreset(_ah, _ix) \
1090 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
1091 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \
1092 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
1093 #define ath_hal_keyisvalid(_ah, _ix) \
1094 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
1095 #define ath_hal_keysetmac(_ah, _ix, _mac) \
1096 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
1097 #define ath_hal_getrxfilter(_ah) \
1098 ((*(_ah)->ah_getRxFilter)((_ah)))
1099 #define ath_hal_setrxfilter(_ah, _filter) \
1100 ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
1101 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
1102 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
1103 #define ath_hal_waitforbeacon(_ah, _bf) \
1104 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
1105 #define ath_hal_putrxbuf(_ah, _bufaddr, _rxq) \
1106 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr), (_rxq)))
1107 /* NB: common across all chips */
1108 #define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */
1109 #define ath_hal_gettsf32(_ah) \
1110 OS_REG_READ(_ah, AR_TSF_L32)
1111 #define ath_hal_gettsf64(_ah) \
1112 ((*(_ah)->ah_getTsf64)((_ah)))
1113 #define ath_hal_settsf64(_ah, _val) \
1114 ((*(_ah)->ah_setTsf64)((_ah), (_val)))
1115 #define ath_hal_resettsf(_ah) \
1116 ((*(_ah)->ah_resetTsf)((_ah)))
1117 #define ath_hal_rxena(_ah) \
1118 ((*(_ah)->ah_enableReceive)((_ah)))
1119 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
1120 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
1121 #define ath_hal_gettxbuf(_ah, _q) \
1122 ((*(_ah)->ah_getTxDP)((_ah), (_q)))
1123 #define ath_hal_numtxpending(_ah, _q) \
1124 ((*(_ah)->ah_numTxPending)((_ah), (_q)))
1125 #define ath_hal_getrxbuf(_ah, _rxq) \
1126 ((*(_ah)->ah_getRxDP)((_ah), (_rxq)))
1127 #define ath_hal_txstart(_ah, _q) \
1128 ((*(_ah)->ah_startTxDma)((_ah), (_q)))
1129 #define ath_hal_setchannel(_ah, _chan) \
1130 ((*(_ah)->ah_setChannel)((_ah), (_chan)))
1131 #define ath_hal_calibrate(_ah, _chan, _iqcal) \
1132 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal)))
1133 #define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \
1134 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone)))
1135 #define ath_hal_calreset(_ah, _chan) \
1136 ((*(_ah)->ah_resetCalValid)((_ah), (_chan)))
1137 #define ath_hal_setledstate(_ah, _state) \
1138 ((*(_ah)->ah_setLedState)((_ah), (_state)))
1139 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
1140 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
1141 #define ath_hal_beaconreset(_ah) \
1142 ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
1143 #define ath_hal_beaconsettimers(_ah, _bt) \
1144 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt)))
1145 #define ath_hal_beacontimers(_ah, _bs) \
1146 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
1147 #define ath_hal_getnexttbtt(_ah) \
1148 ((*(_ah)->ah_getNextTBTT)((_ah)))
1149 #define ath_hal_setassocid(_ah, _bss, _associd) \
1150 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
1151 #define ath_hal_phydisable(_ah) \
1152 ((*(_ah)->ah_phyDisable)((_ah)))
1153 #define ath_hal_setopmode(_ah) \
1154 ((*(_ah)->ah_setPCUConfig)((_ah)))
1155 #define ath_hal_stoptxdma(_ah, _qnum) \
1156 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
1157 #define ath_hal_stoppcurecv(_ah) \
1158 ((*(_ah)->ah_stopPcuReceive)((_ah)))
1159 #define ath_hal_startpcurecv(_ah, _is_scanning) \
1160 ((*(_ah)->ah_startPcuReceive)((_ah), (_is_scanning)))
1161 #define ath_hal_stopdmarecv(_ah) \
1162 ((*(_ah)->ah_stopDmaReceive)((_ah)))
1163 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
1164 ((*(_ah)->ah_getDiagState)((_ah), (_id), \
1165 (_indata), (_insize), (_outdata), (_outsize)))
1166 #define ath_hal_getfatalstate(_ah, _outdata, _outsize) \
1167 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize)
1168 #define ath_hal_setuptxqueue(_ah, _type, _irq) \
1169 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
1170 #define ath_hal_resettxqueue(_ah, _q) \
1171 ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
1172 #define ath_hal_releasetxqueue(_ah, _q) \
1173 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
1174 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \
1175 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
1176 #define ath_hal_settxqueueprops(_ah, _q, _qi) \
1177 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
1178 /* NB: common across all chips */
1179 #define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */
1180 #define ath_hal_txqenabled(_ah, _qnum) \
1181 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum)))
1182 #define ath_hal_getrfgain(_ah) \
1183 ((*(_ah)->ah_getRfGain)((_ah)))
1184 #define ath_hal_getdefantenna(_ah) \
1185 ((*(_ah)->ah_getDefAntenna)((_ah)))
1186 #define ath_hal_setdefantenna(_ah, _ant) \
1187 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
1188 #define ath_hal_rxmonitor(_ah, _arg, _chan) \
1189 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan)))
1190 #define ath_hal_ani_poll(_ah, _chan) \
1191 ((*(_ah)->ah_aniPoll)((_ah), (_chan)))
1192 #define ath_hal_mibevent(_ah, _stats) \
1193 ((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
1194 #define ath_hal_setslottime(_ah, _us) \
1195 ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
1196 #define ath_hal_getslottime(_ah) \
1197 ((*(_ah)->ah_getSlotTime)((_ah)))
1198 #define ath_hal_setacktimeout(_ah, _us) \
1199 ((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
1200 #define ath_hal_getacktimeout(_ah) \
1201 ((*(_ah)->ah_getAckTimeout)((_ah)))
1202 #define ath_hal_setctstimeout(_ah, _us) \
1203 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
1204 #define ath_hal_getctstimeout(_ah) \
1205 ((*(_ah)->ah_getCTSTimeout)((_ah)))
1206 #define ath_hal_getcapability(_ah, _cap, _param, _result) \
1207 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
1208 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
1209 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
1210 #define ath_hal_ciphersupported(_ah, _cipher) \
1211 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
1212 #define ath_hal_getregdomain(_ah, _prd) \
1213 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK)
1214 #define ath_hal_setregdomain(_ah, _rd) \
1215 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL)
1216 #define ath_hal_getcountrycode(_ah, _pcc) \
1217 (*(_pcc) = (_ah)->ah_countryCode)
1218 #define ath_hal_gettkipmic(_ah) \
1219 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK)
1220 #define ath_hal_settkipmic(_ah, _v) \
1221 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL)
1222 #define ath_hal_hastkipsplit(_ah) \
1223 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
1224 #define ath_hal_gettkipsplit(_ah) \
1225 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK)
1226 #define ath_hal_settkipsplit(_ah, _v) \
1227 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL)
1228 #define ath_hal_haswmetkipmic(_ah) \
1229 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK)
1230 #define ath_hal_hwphycounters(_ah) \
1231 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
1232 #define ath_hal_hasdiversity(_ah) \
1233 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
1234 #define ath_hal_getdiversity(_ah) \
1235 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
1236 #define ath_hal_setdiversity(_ah, _v) \
1237 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
1238 #define ath_hal_getantennaswitch(_ah) \
1239 ((*(_ah)->ah_getAntennaSwitch)((_ah)))
1240 #define ath_hal_setantennaswitch(_ah, _v) \
1241 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v)))
1242 #define ath_hal_getdiag(_ah, _pv) \
1243 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
1244 #define ath_hal_setdiag(_ah, _v) \
1245 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
1246 #define ath_hal_getnumtxqueues(_ah, _pv) \
1247 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
1248 #define ath_hal_hasveol(_ah) \
1249 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
1250 #define ath_hal_hastxpowlimit(_ah) \
1251 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
1252 #define ath_hal_settxpowlimit(_ah, _pow) \
1253 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
1254 #define ath_hal_gettxpowlimit(_ah, _ppow) \
1255 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
1256 #define ath_hal_getmaxtxpow(_ah, _ppow) \
1257 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
1258 #define ath_hal_gettpscale(_ah, _scale) \
1259 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
1260 #define ath_hal_settpscale(_ah, _v) \
1261 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
1262 #define ath_hal_hastpc(_ah) \
1263 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
1264 #define ath_hal_gettpc(_ah) \
1265 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
1266 #define ath_hal_settpc(_ah, _v) \
1267 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
1268 #define ath_hal_hasbursting(_ah) \
1269 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
1270 #define ath_hal_setmcastkeysearch(_ah, _v) \
1271 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL)
1272 #define ath_hal_hasmcastkeysearch(_ah) \
1273 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
1274 #define ath_hal_getmcastkeysearch(_ah) \
1275 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
1276 #define ath_hal_hasfastframes(_ah) \
1277 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK)
1278 #define ath_hal_hasbssidmask(_ah) \
1279 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK)
1280 #define ath_hal_hasbssidmatch(_ah) \
1281 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK)
1282 #define ath_hal_hastsfadjust(_ah) \
1283 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK)
1284 #define ath_hal_gettsfadjust(_ah) \
1285 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK)
1286 #define ath_hal_settsfadjust(_ah, _onoff) \
1287 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL)
1288 #define ath_hal_hasrfsilent(_ah) \
1289 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK)
1290 #define ath_hal_getrfkill(_ah) \
1291 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK)
1292 #define ath_hal_setrfkill(_ah, _onoff) \
1293 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL)
1294 #define ath_hal_getrfsilent(_ah, _prfsilent) \
1295 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK)
1296 #define ath_hal_setrfsilent(_ah, _rfsilent) \
1297 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL)
1298 #define ath_hal_gettpack(_ah, _ptpack) \
1299 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK)
1300 #define ath_hal_settpack(_ah, _tpack) \
1301 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL)
1302 #define ath_hal_gettpcts(_ah, _ptpcts) \
1303 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK)
1304 #define ath_hal_settpcts(_ah, _tpcts) \
1305 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL)
1306 #define ath_hal_hasintmit(_ah) \
1307 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \
1308 HAL_CAP_INTMIT_PRESENT, NULL) == HAL_OK)
1309 #define ath_hal_getintmit(_ah) \
1310 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, \
1311 HAL_CAP_INTMIT_ENABLE, NULL) == HAL_OK)
1312 #define ath_hal_setintmit(_ah, _v) \
1313 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, \
1314 HAL_CAP_INTMIT_ENABLE, _v, NULL)
1315 #define ath_hal_hasmybeacon(_ah) \
1316 (ath_hal_getcapability(_ah, HAL_CAP_DO_MYBEACON, 1, NULL) == HAL_OK)
1318 #define ath_hal_hasenforcetxop(_ah) \
1319 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 0, NULL) == HAL_OK)
1320 #define ath_hal_getenforcetxop(_ah) \
1321 (ath_hal_getcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, NULL) == HAL_OK)
1322 #define ath_hal_setenforcetxop(_ah, _v) \
1323 ath_hal_setcapability(_ah, HAL_CAP_ENFORCE_TXOP, 1, _v, NULL)
1325 #define ath_hal_hasrxlnamixer(_ah) \
1326 (ath_hal_getcapability(_ah, HAL_CAP_RX_LNA_MIXING, 0, NULL) == HAL_OK)
1328 #define ath_hal_hasdivantcomb(_ah) \
1329 (ath_hal_getcapability(_ah, HAL_CAP_ANT_DIV_COMB, 0, NULL) == HAL_OK)
1330 #define ath_hal_hasldpc(_ah) \
1331 (ath_hal_getcapability(_ah, HAL_CAP_LDPC, 0, NULL) == HAL_OK)
1332 #define ath_hal_hasldpcwar(_ah) \
1333 (ath_hal_getcapability(_ah, HAL_CAP_LDPCWAR, 0, NULL) == HAL_OK)
1335 /* EDMA definitions */
1336 #define ath_hal_hasedma(_ah) \
1337 (ath_hal_getcapability(_ah, HAL_CAP_ENHANCED_DMA_SUPPORT, \
1339 #define ath_hal_getrxfifodepth(_ah, _qtype, _req) \
1340 (ath_hal_getcapability(_ah, HAL_CAP_RXFIFODEPTH, _qtype, _req) \
1342 #define ath_hal_getntxmaps(_ah, _req) \
1343 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXMAPS, 0, _req) \
1345 #define ath_hal_gettxdesclen(_ah, _req) \
1346 (ath_hal_getcapability(_ah, HAL_CAP_TXDESCLEN, 0, _req) \
1348 #define ath_hal_gettxstatuslen(_ah, _req) \
1349 (ath_hal_getcapability(_ah, HAL_CAP_TXSTATUSLEN, 0, _req) \
1351 #define ath_hal_getrxstatuslen(_ah, _req) \
1352 (ath_hal_getcapability(_ah, HAL_CAP_RXSTATUSLEN, 0, _req) \
1354 #define ath_hal_setrxbufsize(_ah, _req) \
1355 (ath_hal_setcapability(_ah, HAL_CAP_RXBUFSIZE, 0, _req, NULL) \
1358 #define ath_hal_getchannoise(_ah, _c) \
1359 ((*(_ah)->ah_getChanNoise)((_ah), (_c)))
1361 /* 802.11n HAL methods */
1362 #define ath_hal_getrxchainmask(_ah, _prxchainmask) \
1363 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask))
1364 #define ath_hal_gettxchainmask(_ah, _ptxchainmask) \
1365 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask))
1366 #define ath_hal_setrxchainmask(_ah, _rx) \
1367 (ath_hal_setcapability(_ah, HAL_CAP_RX_CHAINMASK, 1, _rx, NULL))
1368 #define ath_hal_settxchainmask(_ah, _tx) \
1369 (ath_hal_setcapability(_ah, HAL_CAP_TX_CHAINMASK, 1, _tx, NULL))
1370 #define ath_hal_split4ktrans(_ah) \
1371 (ath_hal_getcapability(_ah, HAL_CAP_SPLIT_4KB_TRANS, \
1373 #define ath_hal_self_linked_final_rxdesc(_ah) \
1374 (ath_hal_getcapability(_ah, HAL_CAP_RXDESC_SELFLINK, \
1376 #define ath_hal_gtxto_supported(_ah) \
1377 (ath_hal_getcapability(_ah, HAL_CAP_GTXTO, 0, NULL) == HAL_OK)
1378 #define ath_hal_get_rx_tsf_prec(_ah, _pr) \
1379 (ath_hal_getcapability((_ah), HAL_CAP_RXTSTAMP_PREC, 0, (_pr)) \
1381 #define ath_hal_get_tx_tsf_prec(_ah, _pr) \
1382 (ath_hal_getcapability((_ah), HAL_CAP_TXTSTAMP_PREC, 0, (_pr)) \
1384 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
1385 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
1386 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \
1387 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs)))
1388 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
1389 _txr0, _txtr0, _keyix, _ant, _flags, \
1390 _rtsrate, _rtsdura) \
1391 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
1392 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
1393 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0))
1394 #define ath_hal_setupxtxdesc(_ah, _ds, \
1395 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
1396 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
1397 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
1398 #define ath_hal_filltxdesc(_ah, _ds, _b, _l, _did, _qid, _first, _last, _ds0) \
1399 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_b), (_l), (_did), (_qid), \
1400 (_first), (_last), (_ds0)))
1401 #define ath_hal_txprocdesc(_ah, _ds, _ts) \
1402 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts)))
1403 #define ath_hal_gettxintrtxqs(_ah, _txqs) \
1404 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs)))
1405 #define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \
1406 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries)))
1407 #define ath_hal_settxdesclink(_ah, _ds, _link) \
1408 ((*(_ah)->ah_setTxDescLink)((_ah), (_ds), (_link)))
1409 #define ath_hal_gettxdesclink(_ah, _ds, _link) \
1410 ((*(_ah)->ah_getTxDescLink)((_ah), (_ds), (_link)))
1411 #define ath_hal_gettxdesclinkptr(_ah, _ds, _linkptr) \
1412 ((*(_ah)->ah_getTxDescLinkPtr)((_ah), (_ds), (_linkptr)))
1413 #define ath_hal_setuptxstatusring(_ah, _tsstart, _tspstart, _size) \
1414 ((*(_ah)->ah_setupTxStatusRing)((_ah), (_tsstart), (_tspstart), \
1416 #define ath_hal_gettxrawtxdesc(_ah, _txstatus) \
1417 ((*(_ah)->ah_getTxRawTxDesc)((_ah), (_txstatus)))
1419 #define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \
1420 _txr0, _txtr0, _antm, _rcr, _rcd) \
1421 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \
1422 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd)))
1423 #define ath_hal_chaintxdesc(_ah, _ds, _bl, _sl, _pktlen, _hdrlen, _type, \
1424 _keyix, _cipher, _delims, _first, _last, _lastaggr) \
1425 ((*(_ah)->ah_chainTxDesc)((_ah), (_ds), (_bl), (_sl), \
1426 (_pktlen), (_hdrlen), (_type), (_keyix), (_cipher), (_delims), \
1427 (_first), (_last), (_lastaggr)))
1428 #define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \
1429 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0)))
1431 #define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \
1432 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \
1433 (_series), (_ns), (_flags)))
1435 #define ath_hal_set11n_aggr_first(_ah, _ds, _len, _num) \
1436 ((*(_ah)->ah_set11nAggrFirst)((_ah), (_ds), (_len), (_num)))
1437 #define ath_hal_set11n_aggr_middle(_ah, _ds, _num) \
1438 ((*(_ah)->ah_set11nAggrMiddle)((_ah), (_ds), (_num)))
1439 #define ath_hal_set11n_aggr_last(_ah, _ds) \
1440 ((*(_ah)->ah_set11nAggrLast)((_ah), (_ds)))
1442 #define ath_hal_set11nburstduration(_ah, _ds, _dur) \
1443 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur)))
1444 #define ath_hal_clr11n_aggr(_ah, _ds) \
1445 ((*(_ah)->ah_clr11nAggr)((_ah), (_ds)))
1446 #define ath_hal_set11n_virtmorefrag(_ah, _ds, _v) \
1447 ((*(_ah)->ah_set11nVirtMoreFrag)((_ah), (_ds), (_v)))
1449 #define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \
1450 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type)))
1451 #define ath_hal_gpioset(_ah, _gpio, _b) \
1452 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
1453 #define ath_hal_gpioget(_ah, _gpio) \
1454 ((*(_ah)->ah_gpioGet)((_ah), (_gpio)))
1455 #define ath_hal_gpiosetintr(_ah, _gpio, _b) \
1456 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b)))
1459 * PCIe suspend/resume/poweron/poweroff related macros
1461 #define ath_hal_enablepcie(_ah, _restore, _poweroff) \
1462 ((*(_ah)->ah_configPCIE)((_ah), (_restore), (_poweroff)))
1463 #define ath_hal_disablepcie(_ah) \
1464 ((*(_ah)->ah_disablePCIE)((_ah)))
1467 * This is badly-named; you need to set the correct parameters
1468 * to begin to receive useful radar events; and even then
1469 * it doesn't "enable" DFS. See the ath_dfs/null/ module for
1472 #define ath_hal_enabledfs(_ah, _param) \
1473 ((*(_ah)->ah_enableDfs)((_ah), (_param)))
1474 #define ath_hal_getdfsthresh(_ah, _param) \
1475 ((*(_ah)->ah_getDfsThresh)((_ah), (_param)))
1476 #define ath_hal_getdfsdefaultthresh(_ah, _param) \
1477 ((*(_ah)->ah_getDfsDefaultThresh)((_ah), (_param)))
1478 #define ath_hal_procradarevent(_ah, _rxs, _fulltsf, _buf, _event) \
1479 ((*(_ah)->ah_procRadarEvent)((_ah), (_rxs), (_fulltsf), \
1481 #define ath_hal_is_fast_clock_enabled(_ah) \
1482 ((*(_ah)->ah_isFastClockEnabled)((_ah)))
1483 #define ath_hal_radar_wait(_ah, _chan) \
1484 ((*(_ah)->ah_radarWait)((_ah), (_chan)))
1485 #define ath_hal_get_mib_cycle_counts(_ah, _sample) \
1486 ((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample)))
1487 #define ath_hal_get_chan_ext_busy(_ah) \
1488 ((*(_ah)->ah_get11nExtBusy)((_ah)))
1489 #define ath_hal_setchainmasks(_ah, _txchainmask, _rxchainmask) \
1490 ((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask)))
1491 #define ath_hal_set_quiet(_ah, _p, _d, _o, _f) \
1492 ((*(_ah)->ah_setQuiet)((_ah), (_p), (_d), (_o), (_f)))
1494 #define ath_hal_spectral_supported(_ah) \
1495 (ath_hal_getcapability(_ah, HAL_CAP_SPECTRAL_SCAN, 0, NULL) == HAL_OK)
1496 #define ath_hal_spectral_get_config(_ah, _p) \
1497 ((*(_ah)->ah_spectralGetConfig)((_ah), (_p)))
1498 #define ath_hal_spectral_configure(_ah, _p) \
1499 ((*(_ah)->ah_spectralConfigure)((_ah), (_p)))
1500 #define ath_hal_spectral_start(_ah) \
1501 ((*(_ah)->ah_spectralStart)((_ah)))
1502 #define ath_hal_spectral_stop(_ah) \
1503 ((*(_ah)->ah_spectralStop)((_ah)))
1505 #define ath_hal_btcoex_supported(_ah) \
1506 (ath_hal_getcapability(_ah, HAL_CAP_BT_COEX, 0, NULL) == HAL_OK)
1507 #define ath_hal_btcoex_set_info(_ah, _info) \
1508 ((*(_ah)->ah_btCoexSetInfo)((_ah), (_info)))
1509 #define ath_hal_btcoex_set_config(_ah, _cfg) \
1510 ((*(_ah)->ah_btCoexSetConfig)((_ah), (_cfg)))
1511 #define ath_hal_btcoex_set_qcu_thresh(_ah, _qcuid) \
1512 ((*(_ah)->ah_btCoexSetQcuThresh)((_ah), (_qcuid)))
1513 #define ath_hal_btcoex_set_weights(_ah, _weight) \
1514 ((*(_ah)->ah_btCoexSetWeights)((_ah), (_weight)))
1515 #define ath_hal_btcoex_set_bmiss_thresh(_ah, _thr) \
1516 ((*(_ah)->ah_btCoexSetBmissThresh)((_ah), (_thr)))
1517 #define ath_hal_btcoex_set_parameter(_ah, _attrib, _val) \
1518 ((*(_ah)->ah_btCoexSetParameter)((_ah), (_attrib), (_val)))
1519 #define ath_hal_btcoex_enable(_ah) \
1520 ((*(_ah)->ah_btCoexEnable)((_ah)))
1521 #define ath_hal_btcoex_disable(_ah) \
1522 ((*(_ah)->ah_btCoexDisable)((_ah)))
1524 #define ath_hal_btcoex_mci_setup(_ah, _gp, _gb, _gl, _sp) \
1525 ((*(_ah)->ah_btMciSetup)((_ah), (_gp), (_gb), (_gl), (_sp)))
1526 #define ath_hal_btcoex_mci_send_message(_ah, _h, _f, _p, _l, _wd, _cbt) \
1527 ((*(_ah)->ah_btMciSendMessage)((_ah), (_h), (_f), (_p), (_l), (_wd), (_cbt)))
1528 #define ath_hal_btcoex_mci_get_interrupt(_ah, _mi, _mm) \
1529 ((*(_ah)->ah_btMciGetInterrupt)((_ah), (_mi), (_mm)))
1530 #define ath_hal_btcoex_mci_state(_ah, _st, _pd) \
1531 ((*(_ah)->ah_btMciState)((_ah), (_st), (_pd)))
1532 #define ath_hal_btcoex_mci_detach(_ah) \
1533 ((*(_ah)->ah_btMciDetach)((_ah)))
1535 #define ath_hal_div_comb_conf_get(_ah, _conf) \
1536 ((*(_ah)->ah_divLnaConfGet)((_ah), (_conf)))
1537 #define ath_hal_div_comb_conf_set(_ah, _conf) \
1538 ((*(_ah)->ah_divLnaConfSet)((_ah), (_conf)))
1540 #endif /* _DEV_ATH_ATHVAR_H */