2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
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9 * notice, this list of conditions and the following disclaimer,
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14 * similar Disclaimer requirement for further binary redistribution.
15 * 3. Neither the names of the above-listed copyright holders nor the names
16 * of any contributors may be used to endorse or promote products derived
17 * from this software without specific prior written permission.
19 * Alternatively, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") version 2 as published by the Free
21 * Software Foundation.
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34 * THE POSSIBILITY OF SUCH DAMAGES.
40 * Defintions for the Atheros Wireless LAN controller driver.
42 #ifndef _DEV_ATH_ATHVAR_H
43 #define _DEV_ATH_ATHVAR_H
45 #include <sys/taskqueue.h>
47 #include <contrib/dev/ath/ah.h>
48 #include <net80211/ieee80211_radiotap.h>
49 #include <dev/ath/if_athioctl.h>
50 #include <dev/ath/if_athrate.h>
52 #define ATH_TIMEOUT 1000
54 #define ATH_RXBUF 40 /* number of RX buffers */
55 #define ATH_TXBUF 100 /* number of TX buffers */
56 #define ATH_TXDESC 10 /* number of descriptors per buffer */
57 #define ATH_TXMAXTRY 11 /* max number of transmit attempts */
58 #define ATH_TXINTR_PERIOD 5 /* max number of batched tx descriptors */
60 #define ATH_BEACON_AIFS_DEFAULT 0 /* default aifs for ap beacon q */
61 #define ATH_BEACON_CWMIN_DEFAULT 0 /* default cwmin for ap beacon q */
62 #define ATH_BEACON_CWMAX_DEFAULT 0 /* default cwmax for ap beacon q */
65 * The key cache is used for h/w cipher state and also for
66 * tracking station state such as the current tx antenna.
67 * We also setup a mapping table between key cache slot indices
68 * and station state to short-circuit node lookups on rx.
69 * Different parts have different size key caches. We handle
70 * up to ATH_KEYMAX entries (could dynamically allocate state).
72 #define ATH_KEYMAX 128 /* max key cache size we handle */
73 #define ATH_KEYBYTES (ATH_KEYMAX/NBBY) /* storage space in bytes */
75 /* driver-specific node state */
77 struct ieee80211_node an_node; /* base class */
78 u_int8_t an_tx_mgtrate; /* h/w rate for management/ctl frames */
79 u_int8_t an_tx_mgtratesp;/* short preamble h/w rate for " " */
80 u_int32_t an_avgrssi; /* average rssi over all rx frames */
81 HAL_NODE_STATS an_halstats; /* rssi statistics used by hal */
82 /* variable-length rate control state follows */
84 #define ATH_NODE(ni) ((struct ath_node *)(ni))
85 #define ATH_NODE_CONST(ni) ((const struct ath_node *)(ni))
87 #define ATH_RSSI_LPF_LEN 10
88 #define ATH_RSSI_DUMMY_MARKER 0x127
89 #define ATH_EP_MUL(x, mul) ((x) * (mul))
90 #define ATH_RSSI_IN(x) (ATH_EP_MUL((x), HAL_RSSI_EP_MULTIPLIER))
91 #define ATH_LPF_RSSI(x, y, len) \
92 ((x != ATH_RSSI_DUMMY_MARKER) ? (((x) * ((len) - 1) + (y)) / (len)) : (y))
93 #define ATH_RSSI_LPF(x, y) do { \
95 x = ATH_LPF_RSSI((x), ATH_RSSI_IN((y)), ATH_RSSI_LPF_LEN); \
99 STAILQ_ENTRY(ath_buf) bf_list;
101 int bf_flags; /* tx descriptor flags */
102 struct ath_desc *bf_desc; /* virtual addr of desc */
103 bus_addr_t bf_daddr; /* physical addr of desc */
104 bus_dmamap_t bf_dmamap; /* DMA map for mbuf chain */
105 struct mbuf *bf_m; /* mbuf for buf */
106 struct ieee80211_node *bf_node; /* pointer to the node */
107 bus_size_t bf_mapsize;
108 #define ATH_MAX_SCATTER ATH_TXDESC /* max(tx,rx,beacon) desc's */
109 bus_dma_segment_t bf_segs[ATH_MAX_SCATTER];
111 typedef STAILQ_HEAD(, ath_buf) ath_bufhead;
114 * DMA state for tx/rx descriptors.
118 struct ath_desc *dd_desc; /* descriptors */
119 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */
120 bus_addr_t dd_desc_len; /* size of dd_desc */
121 bus_dma_segment_t dd_dseg;
122 bus_dma_tag_t dd_dmat; /* bus DMA tag */
123 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */
124 struct ath_buf *dd_bufptr; /* associated buffers */
128 * Data transmit queue state. One of these exists for each
129 * hardware transmit queue. Packets sent to us from above
130 * are assigned to queues based on their priority. Not all
131 * devices support a complete set of hardware transmit queues.
132 * For those devices the array sc_ac2q will map multiple
133 * priorities to fewer hardware queues (typically all to one
137 u_int axq_qnum; /* hardware q number */
138 u_int axq_depth; /* queue depth (stat only) */
139 u_int axq_intrcnt; /* interrupt count */
140 u_int32_t *axq_link; /* link ptr in last TX desc */
141 STAILQ_HEAD(, ath_buf) axq_q; /* transmit queue */
142 struct mtx axq_lock; /* lock on q and link */
144 * State for patching up CTS when bursting.
146 struct ath_buf *axq_linkbuf; /* va of last buffer */
147 struct ath_desc *axq_lastdsWithCTS;
148 /* first desc of last descriptor
151 struct ath_desc *axq_gatingds; /* final desc of the gating desc
152 * that determines whether
153 * lastdsWithCTS has been DMA'ed
158 #define ATH_TXQ_LOCK_INIT(_sc, _tq) \
159 mtx_init(&(_tq)->axq_lock, \
160 device_get_nameunit((_sc)->sc_dev), "xmit q", MTX_DEF)
161 #define ATH_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->axq_lock)
162 #define ATH_TXQ_LOCK(_tq) mtx_lock(&(_tq)->axq_lock)
163 #define ATH_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->axq_lock)
164 #define ATH_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->axq_lock, MA_OWNED)
166 #define ATH_TXQ_INSERT_TAIL(_tq, _elm, _field) do { \
167 STAILQ_INSERT_TAIL(&(_tq)->axq_q, (_elm), _field); \
168 (_tq)->axq_depth++; \
170 #define ATH_TXQ_REMOVE_HEAD(_tq, _field) do { \
171 STAILQ_REMOVE_HEAD(&(_tq)->axq_q, _field); \
172 (_tq)->axq_depth--; \
176 struct ifnet *sc_ifp; /* interface common */
177 struct ath_stats sc_stats; /* interface statistics */
178 struct ieee80211com sc_ic; /* IEEE 802.11 common */
182 void (*sc_recv_mgmt)(struct ieee80211com *,
184 struct ieee80211_node *,
185 int, int, u_int32_t);
186 int (*sc_newstate)(struct ieee80211com *,
187 enum ieee80211_state, int);
188 void (*sc_node_free)(struct ieee80211_node *);
190 bus_space_tag_t sc_st; /* bus space tag */
191 bus_space_handle_t sc_sh; /* bus space handle */
192 bus_dma_tag_t sc_dmat; /* bus DMA tag */
193 struct mtx sc_mtx; /* master lock (recursive) */
194 struct ath_hal *sc_ah; /* Atheros HAL */
195 struct ath_ratectrl *sc_rc; /* tx rate control support */
196 void (*sc_setdefantenna)(struct ath_softc *, u_int);
197 unsigned int sc_invalid : 1, /* disable hardware accesses */
198 sc_mrretry : 1, /* multi-rate retry support */
199 sc_softled : 1, /* enable LED gpio status */
200 sc_splitmic: 1, /* split TKIP MIC keys */
201 sc_needmib : 1, /* enable MIB stats intr */
202 sc_hasdiversity : 1,/* rx diversity available */
203 sc_diversity : 1,/* enable rx diversity */
204 sc_hasveol : 1, /* tx VEOL support */
205 sc_hastpc : 1, /* per-packet TPC support */
206 sc_ledstate: 1, /* LED on/off state */
207 sc_blinking: 1, /* LED blink operation active */
208 sc_mcastkey: 1, /* mcast key cache search */
209 sc_hasclrkey:1; /* CLR key supported */
211 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX];
212 const HAL_RATE_TABLE *sc_currates; /* current rate table */
213 enum ieee80211_phymode sc_curmode; /* current phy mode */
214 u_int16_t sc_curtxpow; /* current tx power limit */
215 HAL_CHANNEL sc_curchan; /* current h/w channel */
216 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */
218 u_int8_t ieeerate; /* IEEE rate */
219 u_int8_t rxflags; /* radiotap rx flags */
220 u_int8_t txflags; /* radiotap tx flags */
221 u_int16_t ledon; /* softled on time */
222 u_int16_t ledoff; /* softled off time */
223 } sc_hwmap[32]; /* h/w rate ix mappings */
224 u_int8_t sc_protrix; /* protection rate index */
225 u_int sc_txantenna; /* tx antenna (fixed or auto) */
226 HAL_INT sc_imask; /* interrupt mask copy */
227 u_int sc_keymax; /* size of key cache */
228 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */
229 struct ieee80211_node *sc_keyixmap[ATH_KEYMAX];/* key ix->node map */
231 u_int sc_ledpin; /* GPIO pin for driving LED */
232 u_int sc_ledon; /* pin setting for LED on */
233 u_int sc_ledidle; /* idle polling interval */
234 int sc_ledevent; /* time of last LED event */
235 u_int8_t sc_rxrate; /* current rx rate for LED */
236 u_int8_t sc_txrate; /* current tx rate for LED */
237 u_int16_t sc_ledoff; /* off time for current blink */
238 struct callout sc_ledtimer; /* led off timer */
240 struct bpf_if *sc_drvbpf;
242 struct ath_tx_radiotap_header th;
247 struct ath_rx_radiotap_header th;
252 struct task sc_fataltask; /* fatal int processing */
254 struct ath_descdma sc_rxdma; /* RX descriptos */
255 ath_bufhead sc_rxbuf; /* receive buffer */
256 u_int32_t *sc_rxlink; /* link ptr in last RX desc */
257 struct task sc_rxtask; /* rx int processing */
258 struct task sc_rxorntask; /* rxorn int processing */
259 u_int8_t sc_defant; /* current default antenna */
260 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/
262 struct ath_descdma sc_txdma; /* TX descriptors */
263 ath_bufhead sc_txbuf; /* transmit buffer */
264 struct mtx sc_txbuflock; /* txbuf lock */
265 int sc_tx_timer; /* transmit timeout */
266 u_int sc_txqsetup; /* h/w queues setup */
267 u_int sc_txintrperiod;/* tx interrupt batching */
268 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES];
269 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */
270 struct task sc_txtask; /* tx int processing */
272 struct ath_descdma sc_bdma; /* beacon descriptors */
273 ath_bufhead sc_bbuf; /* beacon buffers */
274 u_int sc_bhalq; /* HAL q for outgoing beacons */
275 u_int sc_bmisscount; /* missed beacon transmits */
276 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */
277 struct ath_txq *sc_cabq; /* tx q for cab frames */
278 struct ieee80211_beacon_offsets sc_boff;/* dynamic update state */
279 struct task sc_bmisstask; /* bmiss int processing */
280 struct task sc_bstucktask; /* stuck beacon processing */
282 OK, /* no change needed */
283 UPDATE, /* update pending */
284 COMMIT /* beacon sent, commit change */
285 } sc_updateslot; /* slot time update fsm */
287 struct callout sc_cal_ch; /* callout handle for cals */
288 struct callout sc_scan_ch; /* callout handle for scan */
290 #define sc_tx_th u_tx_rt.th
291 #define sc_rx_th u_rx_rt.th
293 #define ATH_LOCK_INIT(_sc) \
294 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
295 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE)
296 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
297 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
298 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
299 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
301 #define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i))
303 #define ATH_TXBUF_LOCK_INIT(_sc) \
304 mtx_init(&(_sc)->sc_txbuflock, \
305 device_get_nameunit((_sc)->sc_dev), "xmit buf q", MTX_DEF)
306 #define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock)
307 #define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock)
308 #define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock)
309 #define ATH_TXBUF_LOCK_ASSERT(_sc) \
310 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED)
312 int ath_attach(u_int16_t, struct ath_softc *);
313 int ath_detach(struct ath_softc *);
314 void ath_resume(struct ath_softc *);
315 void ath_suspend(struct ath_softc *);
316 void ath_shutdown(struct ath_softc *);
317 void ath_intr(void *);
320 * HAL definitions to comply with local coding convention.
322 #define ath_hal_detach(_ah) \
323 ((*(_ah)->ah_detach)((_ah)))
324 #define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \
325 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus)))
326 #define ath_hal_getratetable(_ah, _mode) \
327 ((*(_ah)->ah_getRateTable)((_ah), (_mode)))
328 #define ath_hal_getmac(_ah, _mac) \
329 ((*(_ah)->ah_getMacAddress)((_ah), (_mac)))
330 #define ath_hal_setmac(_ah, _mac) \
331 ((*(_ah)->ah_setMacAddress)((_ah), (_mac)))
332 #define ath_hal_intrset(_ah, _mask) \
333 ((*(_ah)->ah_setInterrupts)((_ah), (_mask)))
334 #define ath_hal_intrget(_ah) \
335 ((*(_ah)->ah_getInterrupts)((_ah)))
336 #define ath_hal_intrpend(_ah) \
337 ((*(_ah)->ah_isInterruptPending)((_ah)))
338 #define ath_hal_getisr(_ah, _pmask) \
339 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask)))
340 #define ath_hal_updatetxtriglevel(_ah, _inc) \
341 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc)))
342 #define ath_hal_setpower(_ah, _mode, _sleepduration) \
343 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE, (_sleepduration)))
344 #define ath_hal_keycachesize(_ah) \
345 ((*(_ah)->ah_getKeyCacheSize)((_ah)))
346 #define ath_hal_keyreset(_ah, _ix) \
347 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix)))
348 #define ath_hal_keyset(_ah, _ix, _pk, _mac) \
349 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE))
350 #define ath_hal_keyisvalid(_ah, _ix) \
351 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix))))
352 #define ath_hal_keysetmac(_ah, _ix, _mac) \
353 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac)))
354 #define ath_hal_getrxfilter(_ah) \
355 ((*(_ah)->ah_getRxFilter)((_ah)))
356 #define ath_hal_setrxfilter(_ah, _filter) \
357 ((*(_ah)->ah_setRxFilter)((_ah), (_filter)))
358 #define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \
359 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1)))
360 #define ath_hal_waitforbeacon(_ah, _bf) \
361 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr))
362 #define ath_hal_putrxbuf(_ah, _bufaddr) \
363 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr)))
364 #define ath_hal_gettsf32(_ah) \
365 ((*(_ah)->ah_getTsf32)((_ah)))
366 #define ath_hal_gettsf64(_ah) \
367 ((*(_ah)->ah_getTsf64)((_ah)))
368 #define ath_hal_resettsf(_ah) \
369 ((*(_ah)->ah_resetTsf)((_ah)))
370 #define ath_hal_rxena(_ah) \
371 ((*(_ah)->ah_enableReceive)((_ah)))
372 #define ath_hal_puttxbuf(_ah, _q, _bufaddr) \
373 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr)))
374 #define ath_hal_gettxbuf(_ah, _q) \
375 ((*(_ah)->ah_getTxDP)((_ah), (_q)))
376 #define ath_hal_numtxpending(_ah, _q) \
377 ((*(_ah)->ah_numTxPending)((_ah), (_q)))
378 #define ath_hal_getrxbuf(_ah) \
379 ((*(_ah)->ah_getRxDP)((_ah)))
380 #define ath_hal_txstart(_ah, _q) \
381 ((*(_ah)->ah_startTxDma)((_ah), (_q)))
382 #define ath_hal_setchannel(_ah, _chan) \
383 ((*(_ah)->ah_setChannel)((_ah), (_chan)))
384 #define ath_hal_calibrate(_ah, _chan) \
385 ((*(_ah)->ah_perCalibration)((_ah), (_chan)))
386 #define ath_hal_setledstate(_ah, _state) \
387 ((*(_ah)->ah_setLedState)((_ah), (_state)))
388 #define ath_hal_beaconinit(_ah, _nextb, _bperiod) \
389 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod)))
390 #define ath_hal_beaconreset(_ah) \
391 ((*(_ah)->ah_resetStationBeaconTimers)((_ah)))
392 #define ath_hal_beacontimers(_ah, _bs) \
393 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs)))
394 #define ath_hal_setassocid(_ah, _bss, _associd) \
395 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd)))
396 #define ath_hal_phydisable(_ah) \
397 ((*(_ah)->ah_phyDisable)((_ah)))
398 #define ath_hal_setopmode(_ah) \
399 ((*(_ah)->ah_setPCUConfig)((_ah)))
400 #define ath_hal_stoptxdma(_ah, _qnum) \
401 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum)))
402 #define ath_hal_stoppcurecv(_ah) \
403 ((*(_ah)->ah_stopPcuReceive)((_ah)))
404 #define ath_hal_startpcurecv(_ah) \
405 ((*(_ah)->ah_startPcuReceive)((_ah)))
406 #define ath_hal_stopdmarecv(_ah) \
407 ((*(_ah)->ah_stopDmaReceive)((_ah)))
408 #define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \
409 ((*(_ah)->ah_getDiagState)((_ah), (_id), \
410 (_indata), (_insize), (_outdata), (_outsize)))
411 #define ath_hal_setuptxqueue(_ah, _type, _irq) \
412 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq)))
413 #define ath_hal_resettxqueue(_ah, _q) \
414 ((*(_ah)->ah_resetTxQueue)((_ah), (_q)))
415 #define ath_hal_releasetxqueue(_ah, _q) \
416 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q)))
417 #define ath_hal_gettxqueueprops(_ah, _q, _qi) \
418 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi)))
419 #define ath_hal_settxqueueprops(_ah, _q, _qi) \
420 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi)))
421 #define ath_hal_getrfgain(_ah) \
422 ((*(_ah)->ah_getRfGain)((_ah)))
423 #define ath_hal_getdefantenna(_ah) \
424 ((*(_ah)->ah_getDefAntenna)((_ah)))
425 #define ath_hal_setdefantenna(_ah, _ant) \
426 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant)))
427 #define ath_hal_rxmonitor(_ah, _arg) \
428 ((*(_ah)->ah_rxMonitor)((_ah), (_arg)))
429 #define ath_hal_mibevent(_ah, _stats) \
430 ((*(_ah)->ah_procMibEvent)((_ah), (_stats)))
431 #define ath_hal_setslottime(_ah, _us) \
432 ((*(_ah)->ah_setSlotTime)((_ah), (_us)))
433 #define ath_hal_getslottime(_ah) \
434 ((*(_ah)->ah_getSlotTime)((_ah)))
435 #define ath_hal_setacktimeout(_ah, _us) \
436 ((*(_ah)->ah_setAckTimeout)((_ah), (_us)))
437 #define ath_hal_getacktimeout(_ah) \
438 ((*(_ah)->ah_getAckTimeout)((_ah)))
439 #define ath_hal_setctstimeout(_ah, _us) \
440 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us)))
441 #define ath_hal_getctstimeout(_ah) \
442 ((*(_ah)->ah_getCTSTimeout)((_ah)))
443 #define ath_hal_getcapability(_ah, _cap, _param, _result) \
444 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result)))
445 #define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \
446 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status)))
447 #define ath_hal_ciphersupported(_ah, _cipher) \
448 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK)
449 #define ath_hal_getregdomain(_ah, _prd) \
450 ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd))
451 #define ath_hal_getcountrycode(_ah, _pcc) \
452 (*(_pcc) = (_ah)->ah_countryCode)
453 #define ath_hal_tkipsplit(_ah) \
454 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK)
455 #define ath_hal_hwphycounters(_ah) \
456 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK)
457 #define ath_hal_hasdiversity(_ah) \
458 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK)
459 #define ath_hal_getdiversity(_ah) \
460 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK)
461 #define ath_hal_setdiversity(_ah, _v) \
462 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL)
463 #define ath_hal_getdiag(_ah, _pv) \
464 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK)
465 #define ath_hal_setdiag(_ah, _v) \
466 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL)
467 #define ath_hal_getnumtxqueues(_ah, _pv) \
468 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK)
469 #define ath_hal_hasveol(_ah) \
470 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK)
471 #define ath_hal_hastxpowlimit(_ah) \
472 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK)
473 #define ath_hal_settxpowlimit(_ah, _pow) \
474 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow)))
475 #define ath_hal_gettxpowlimit(_ah, _ppow) \
476 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK)
477 #define ath_hal_getmaxtxpow(_ah, _ppow) \
478 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK)
479 #define ath_hal_gettpscale(_ah, _scale) \
480 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK)
481 #define ath_hal_settpscale(_ah, _v) \
482 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL)
483 #define ath_hal_hastpc(_ah) \
484 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK)
485 #define ath_hal_gettpc(_ah) \
486 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK)
487 #define ath_hal_settpc(_ah, _v) \
488 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL)
489 #define ath_hal_hasbursting(_ah) \
490 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK)
492 #define ath_hal_hasmcastkeysearch(_ah) \
493 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK)
494 #define ath_hal_getmcastkeysearch(_ah) \
495 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK)
497 #define ath_hal_getmcastkeysearch(_ah) 0
500 #define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \
501 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq)))
502 #define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext) \
503 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext)))
504 #define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \
505 _txr0, _txtr0, _keyix, _ant, _flags, \
506 _rtsrate, _rtsdura) \
507 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \
508 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \
509 (_flags), (_rtsrate), (_rtsdura)))
510 #define ath_hal_setupxtxdesc(_ah, _ds, \
511 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \
512 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \
513 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3)))
514 #define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \
515 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0)))
516 #define ath_hal_txprocdesc(_ah, _ds) \
517 ((*(_ah)->ah_procTxDesc)((_ah), (_ds)))
518 #define ath_hal_updateCTSForBursting(_ah, _ds, _prevds, _prevdsWithCTS, \
519 _gatingds, _txOpLimit, _ctsDuration) \
520 ((*(_ah)->ah_updateCTSForBursting)((_ah), (_ds), (_prevds), \
521 (_prevdsWithCTS), (_gatingds), (_txOpLimit), (_ctsDuration)))
523 #define ath_hal_gpioCfgOutput(_ah, _gpio) \
524 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio)))
525 #define ath_hal_gpioset(_ah, _gpio, _b) \
526 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b)))
528 #endif /* _DEV_ATH_ATHVAR_H */