1 /* $NetBSD: am79c930reg.h,v 1.3 2000/03/22 11:22:22 onoe Exp $ */
5 * Copyright (c) 1999 The NetBSD Foundation, Inc.
8 * This code is derived from software contributed to The NetBSD Foundation
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41 * Device register definitions gleaned from from the AMD "Am79C930
42 * PCnet(tm)-Mobile Single Chip Wireless LAN Media Access Controller"
43 * data sheet, AMD Pub #20183, Rev B, amendment/0, issue date August 1997.
45 * As of 1999/10/23, this was available from AMD's web site in PDF
51 * The 79c930 contains a bus interface unit, a media access
52 * controller, and a tranceiver attachment interface.
53 * The MAC contains an 80188 CPU core.
54 * typical devices built around this chip typically add 32k or 64k of
57 * The 80188 runs firmware which handles most of the 802.11 gorp, and
58 * communicates with the host using shared data structures in this
59 * memory; the specifics of the shared memory layout are not covered
60 * in this source file; see <dev/ic/am80211fw.h> for details of that layer.
67 #define AM79C930_IO_BASE 0
68 #define AM79C930_IO_SIZE 16
69 #define AM79C930_IO_SIZE_BIG 40
70 #define AM79C930_IO_ALIGN 0x40 /* am79c930 decodes lower 6bits */
73 #define AM79C930_GCR 0 /* General Config Register */
75 #define AM79C930_GCR_SWRESET 0x80 /* software reset */
76 #define AM79C930_GCR_CORESET 0x40 /* core reset */
77 #define AM79C930_GCR_DISPWDN 0x20 /* disable powerdown */
78 #define AM79C930_GCR_ECWAIT 0x10 /* embedded controller wait */
79 #define AM79C930_GCR_ECINT 0x08 /* interrupt from embedded ctrlr */
80 #define AM79C930_GCR_INT2EC 0x04 /* interrupt to embedded ctrlr */
81 #define AM79C930_GCR_ENECINT 0x02 /* enable interrupts from e.c. */
82 #define AM79C930_GCR_DAM 0x01 /* direct access mode (read only) */
84 #define AM79C930_GCR_BITS "\020\1DAM\2ENECINT\3INT2EC\4ECINT\5ECWAIT\6DISPWDN\7CORESET\010SWRESET"
86 #define AM79C930_BSS 1 /* Bank Switching Select register */
88 #define AM79C930_BSS_ECATR 0x80 /* E.C. ALE test read */
89 #define AM79C930_BSS_FS 0x20 /* Flash Select */
90 #define AM79C930_BSS_MBS 0x18 /* Memory Bank Select */
91 #define AM79C930_BSS_EIOW 0x04 /* Expand I/O Window */
92 #define AM79C930_BSS_TBS 0x03 /* TAI Bank Select */
94 #define AM79C930_LMA_LO 2 /* Local Memory Address register (low byte) */
96 #define AM79C930_LMA_HI 3 /* Local Memory Address register (high byte) */
98 /* set this bit to turn off ISAPnP version */
99 #define AM79C930_LMA_HI_ISAPWRDWN 0x80
102 * mmm, inconsistancy in chip documentation:
103 * According to page 79--80, all four of the following are equivalent
104 * and address the single byte pointed at by BSS_{FS,MBS} | LMA_{HI,LO}
105 * According to tables on p63 and p67, they're the LSB through MSB
109 #define AM79C930_IODPA 4 /* I/O Data port A */
110 #define AM79C930_IODPB 5 /* I/O Data port B */
111 #define AM79C930_IODPC 6 /* I/O Data port C */
112 #define AM79C930_IODPD 7 /* I/O Data port D */
116 * Tranceiver Attachment Interface Registers (TIR space)
117 * (omitted for now, since host access to them is for diagnostic
125 #define AM79C930_MEM_SIZE 0x8000 /* 32k */
126 #define AM79C930_MEM_BASE 0x0 /* starting at 0 */