2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2020 Advanced Micro Devices, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * Contact Information :
28 * Rajesh Kumar <rajesh1.kumar@amd.com>
29 * Shreyank Amartya <Shreyank.Amartya@amd.com>
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/mutex.h>
42 #include <sys/socket.h>
43 #include <sys/sysctl.h>
46 #include <net/if_media.h>
48 #include <dev/mii/mii.h>
49 #include <dev/mii/miivar.h>
51 #include <dev/pci/pcireg.h>
52 #include <dev/pci/pcivar.h>
55 #include "xgbe-common.h"
57 #include "miibus_if.h"
60 #include "opt_inet6.h"
62 MALLOC_DEFINE(M_AXGBE, "axgbe", "axgbe data");
64 extern struct if_txrx axgbe_txrx;
66 /* Function prototypes */
67 static void *axgbe_register(device_t);
68 static int axgbe_if_attach_pre(if_ctx_t);
69 static int axgbe_if_attach_post(if_ctx_t);
70 static int axgbe_if_detach(if_ctx_t);
71 static void axgbe_if_stop(if_ctx_t);
72 static void axgbe_if_init(if_ctx_t);
74 /* Queue related routines */
75 static int axgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
76 static int axgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
77 static int axgbe_alloc_channels(if_ctx_t);
78 static void axgbe_if_queues_free(if_ctx_t);
79 static int axgbe_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
80 static int axgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
82 /* Interrupt related routines */
83 static void axgbe_if_disable_intr(if_ctx_t);
84 static void axgbe_if_enable_intr(if_ctx_t);
85 static int axgbe_if_msix_intr_assign(if_ctx_t, int);
86 static void xgbe_free_intr(struct xgbe_prv_data *, struct resource *, void *, int);
88 /* Init and Iflib routines */
89 static void axgbe_pci_init(struct xgbe_prv_data *);
90 static void axgbe_pci_stop(if_ctx_t);
91 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *, struct xgbe_channel *);
92 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *);
93 static int axgbe_if_mtu_set(if_ctx_t, uint32_t);
94 static void axgbe_if_update_admin_status(if_ctx_t);
95 static void axgbe_if_media_status(if_ctx_t, struct ifmediareq *);
96 static int axgbe_if_media_change(if_ctx_t);
97 static int axgbe_if_promisc_set(if_ctx_t, int);
98 static uint64_t axgbe_if_get_counter(if_ctx_t, ift_counter);
99 static void axgbe_if_vlan_register(if_ctx_t, uint16_t);
100 static void axgbe_if_vlan_unregister(if_ctx_t, uint16_t);
101 #if __FreeBSD_version >= 1300000
102 static bool axgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event);
104 static void axgbe_set_counts(if_ctx_t);
105 static void axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *);
107 /* MII interface registered functions */
108 static int axgbe_miibus_readreg(device_t, int, int);
109 static int axgbe_miibus_writereg(device_t, int, int, int);
110 static void axgbe_miibus_statchg(device_t);
113 static int axgbe_dev_isr(void *);
114 static void axgbe_ecc_isr(void *);
115 static void axgbe_i2c_isr(void *);
116 static void axgbe_an_isr(void *);
117 static int axgbe_msix_que(void *);
120 static void xgbe_service(void *, int);
121 static void xgbe_service_timer(void *);
122 static void xgbe_init_timers(struct xgbe_prv_data *);
123 static void xgbe_stop_timers(struct xgbe_prv_data *);
126 static void xgbe_dump_prop_registers(struct xgbe_prv_data *);
129 * Allocate only for MAC (BAR0) and PCS (BAR1) registers, and just point the
130 * MSI-X table bar (BAR5) to iflib. iflib will do the allocation for MSI-X
133 static struct resource_spec axgbe_pci_mac_spec[] = {
134 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* MAC regs */
135 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, /* PCS regs */
139 static pci_vendor_info_t axgbe_vendor_info_array[] =
141 PVID(0x1022, 0x1458, "AMD 10 Gigabit Ethernet Driver"),
142 PVID(0x1022, 0x1459, "AMD 10 Gigabit Ethernet Driver"),
146 static struct xgbe_version_data xgbe_v2a = {
147 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
148 .xpcs_access = XGBE_XPCS_ACCESS_V2,
150 .tx_max_fifo_size = 229376,
151 .rx_max_fifo_size = 229376,
152 .tx_tstamp_workaround = 1,
155 .irq_reissue_support = 1,
156 .tx_desc_prefetch = 5,
157 .rx_desc_prefetch = 5,
158 .an_cdr_workaround = 1,
161 static struct xgbe_version_data xgbe_v2b = {
162 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
163 .xpcs_access = XGBE_XPCS_ACCESS_V2,
165 .tx_max_fifo_size = 65536,
166 .rx_max_fifo_size = 65536,
167 .tx_tstamp_workaround = 1,
170 .irq_reissue_support = 1,
171 .tx_desc_prefetch = 5,
172 .rx_desc_prefetch = 5,
173 .an_cdr_workaround = 1,
176 /* Device Interface */
177 static device_method_t ax_methods[] = {
178 DEVMETHOD(device_register, axgbe_register),
179 DEVMETHOD(device_probe, iflib_device_probe),
180 DEVMETHOD(device_attach, iflib_device_attach),
181 DEVMETHOD(device_detach, iflib_device_detach),
184 DEVMETHOD(miibus_readreg, axgbe_miibus_readreg),
185 DEVMETHOD(miibus_writereg, axgbe_miibus_writereg),
186 DEVMETHOD(miibus_statchg, axgbe_miibus_statchg),
191 static driver_t ax_driver = {
192 "ax", ax_methods, sizeof(struct axgbe_if_softc),
195 devclass_t ax_devclass;
196 DRIVER_MODULE(axp, pci, ax_driver, ax_devclass, 0, 0);
197 DRIVER_MODULE(miibus, ax, miibus_driver, miibus_devclass, 0, 0);
198 IFLIB_PNP_INFO(pci, ax_driver, axgbe_vendor_info_array);
200 MODULE_DEPEND(ax, pci, 1, 1, 1);
201 MODULE_DEPEND(ax, ether, 1, 1, 1);
202 MODULE_DEPEND(ax, iflib, 1, 1, 1);
203 MODULE_DEPEND(ax, miibus, 1, 1, 1);
205 /* Iflib Interface */
206 static device_method_t axgbe_if_methods[] = {
207 DEVMETHOD(ifdi_attach_pre, axgbe_if_attach_pre),
208 DEVMETHOD(ifdi_attach_post, axgbe_if_attach_post),
209 DEVMETHOD(ifdi_detach, axgbe_if_detach),
210 DEVMETHOD(ifdi_init, axgbe_if_init),
211 DEVMETHOD(ifdi_stop, axgbe_if_stop),
212 DEVMETHOD(ifdi_msix_intr_assign, axgbe_if_msix_intr_assign),
213 DEVMETHOD(ifdi_intr_enable, axgbe_if_enable_intr),
214 DEVMETHOD(ifdi_intr_disable, axgbe_if_disable_intr),
215 DEVMETHOD(ifdi_tx_queue_intr_enable, axgbe_if_tx_queue_intr_enable),
216 DEVMETHOD(ifdi_rx_queue_intr_enable, axgbe_if_rx_queue_intr_enable),
217 DEVMETHOD(ifdi_tx_queues_alloc, axgbe_if_tx_queues_alloc),
218 DEVMETHOD(ifdi_rx_queues_alloc, axgbe_if_rx_queues_alloc),
219 DEVMETHOD(ifdi_queues_free, axgbe_if_queues_free),
220 DEVMETHOD(ifdi_update_admin_status, axgbe_if_update_admin_status),
221 DEVMETHOD(ifdi_mtu_set, axgbe_if_mtu_set),
222 DEVMETHOD(ifdi_media_status, axgbe_if_media_status),
223 DEVMETHOD(ifdi_media_change, axgbe_if_media_change),
224 DEVMETHOD(ifdi_promisc_set, axgbe_if_promisc_set),
225 DEVMETHOD(ifdi_get_counter, axgbe_if_get_counter),
226 DEVMETHOD(ifdi_vlan_register, axgbe_if_vlan_register),
227 DEVMETHOD(ifdi_vlan_unregister, axgbe_if_vlan_unregister),
228 #if __FreeBSD_version >= 1300000
229 DEVMETHOD(ifdi_needs_restart, axgbe_if_needs_restart),
234 static driver_t axgbe_if_driver = {
235 "axgbe_if", axgbe_if_methods, sizeof(struct axgbe_if_softc)
238 /* Iflib Shared Context */
239 static struct if_shared_ctx axgbe_sctx_init = {
240 .isc_magic = IFLIB_MAGIC,
241 .isc_driver = &axgbe_if_driver,
242 .isc_q_align = PAGE_SIZE,
243 .isc_tx_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
244 .isc_tx_maxsegsize = PAGE_SIZE,
245 .isc_tso_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
246 .isc_tso_maxsegsize = PAGE_SIZE,
247 .isc_rx_maxsize = MJUM9BYTES,
248 .isc_rx_maxsegsize = MJUM9BYTES,
249 .isc_rx_nsegments = 1,
250 .isc_admin_intrcnt = 4,
252 .isc_vendor_info = axgbe_vendor_info_array,
253 .isc_driver_version = XGBE_DRV_VERSION,
255 .isc_nrxd_min = {XGBE_RX_DESC_CNT_MIN, XGBE_RX_DESC_CNT_MIN},
256 .isc_nrxd_default = {XGBE_RX_DESC_CNT_DEFAULT, XGBE_RX_DESC_CNT_DEFAULT},
257 .isc_nrxd_max = {XGBE_RX_DESC_CNT_MAX, XGBE_RX_DESC_CNT_MAX},
258 .isc_ntxd_min = {XGBE_TX_DESC_CNT_MIN},
259 .isc_ntxd_default = {XGBE_TX_DESC_CNT_DEFAULT},
260 .isc_ntxd_max = {XGBE_TX_DESC_CNT_MAX},
265 .isc_flags = IFLIB_TSO_INIT_IP | IFLIB_NEED_SCRATCH |
266 IFLIB_NEED_ZERO_CSUM | IFLIB_NEED_ETHER_PAD,
270 axgbe_register(device_t dev)
272 return (&axgbe_sctx_init);
275 /* MII Interface Functions */
277 axgbe_miibus_readreg(device_t dev, int phy, int reg)
279 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
280 struct xgbe_prv_data *pdata = &sc->pdata;
283 axgbe_printf(3, "%s: phy %d reg %d\n", __func__, phy, reg);
285 val = xgbe_phy_mii_read(pdata, phy, reg);
287 axgbe_printf(2, "%s: val 0x%x\n", __func__, val);
288 return (val & 0xFFFF);
292 axgbe_miibus_writereg(device_t dev, int phy, int reg, int val)
294 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
295 struct xgbe_prv_data *pdata = &sc->pdata;
297 axgbe_printf(3, "%s: phy %d reg %d val 0x%x\n", __func__, phy, reg, val);
299 xgbe_phy_mii_write(pdata, phy, reg, val);
305 axgbe_miibus_statchg(device_t dev)
307 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
308 struct xgbe_prv_data *pdata = &sc->pdata;
309 struct mii_data *mii = device_get_softc(pdata->axgbe_miibus);
310 struct ifnet *ifp = pdata->netdev;
313 axgbe_printf(2, "%s: Link %d/%d\n", __func__, pdata->phy.link,
316 if (mii == NULL || ifp == NULL ||
317 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
320 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
321 (IFM_ACTIVE | IFM_AVALID)) {
323 switch (IFM_SUBTYPE(mii->mii_media_active)) {
340 bmsr = axgbe_miibus_readreg(pdata->dev, pdata->mdio_addr, MII_BMSR);
341 if (bmsr & BMSR_ANEG) {
343 axgbe_printf(2, "%s: Autoneg Done\n", __func__);
345 /* Raise AN Interrupt */
346 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK,
347 XGBE_AN_CL73_INT_MASK);
352 axgbe_if_attach_pre(if_ctx_t ctx)
354 struct axgbe_if_softc *sc;
355 struct xgbe_prv_data *pdata;
356 struct resource *mac_res[2];
357 if_softc_ctx_t scctx;
358 if_shared_ctx_t sctx;
360 unsigned int ma_lo, ma_hi;
363 sc = iflib_get_softc(ctx);
364 sc->pdata.dev = dev = iflib_get_dev(ctx);
365 sc->sctx = sctx = iflib_get_sctx(ctx);
366 sc->scctx = scctx = iflib_get_softc_ctx(ctx);
367 sc->media = iflib_get_media(ctx);
369 sc->link_status = LINK_STATE_DOWN;
371 pdata->netdev = iflib_get_ifp(ctx);
373 spin_lock_init(&pdata->xpcs_lock);
375 /* Initialize locks */
376 mtx_init(&pdata->rss_mutex, "xgbe rss mutex lock", NULL, MTX_DEF);
377 mtx_init(&pdata->mdio_mutex, "xgbe MDIO mutex lock", NULL, MTX_SPIN);
379 /* Allocate VLAN bitmap */
380 pdata->active_vlans = bit_alloc(VLAN_NVID, M_AXGBE, M_WAITOK|M_ZERO);
381 pdata->num_active_vlans = 0;
383 /* Get the version data */
384 DBGPR("%s: Device ID: 0x%x\n", __func__, pci_get_device(dev));
385 if (pci_get_device(dev) == 0x1458)
386 sc->pdata.vdata = &xgbe_v2a;
387 else if (pci_get_device(dev) == 0x1459)
388 sc->pdata.vdata = &xgbe_v2b;
391 if (bus_alloc_resources(dev, axgbe_pci_mac_spec, mac_res))
394 sc->pdata.xgmac_res = mac_res[0];
395 sc->pdata.xpcs_res = mac_res[1];
397 /* Set the PCS indirect addressing definition registers*/
398 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
399 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
401 /* Configure the PCS indirect addressing support */
402 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
403 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
404 pdata->xpcs_window <<= 6;
405 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
406 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
407 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
408 DBGPR("xpcs window def : %#010x\n",
409 pdata->xpcs_window_def_reg);
410 DBGPR("xpcs window sel : %#010x\n",
411 pdata->xpcs_window_sel_reg);
412 DBGPR("xpcs window : %#010x\n",
414 DBGPR("xpcs window size : %#010x\n",
415 pdata->xpcs_window_size);
416 DBGPR("xpcs window mask : %#010x\n",
417 pdata->xpcs_window_mask);
419 /* Enable all interrupts in the hardware */
420 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
422 /* Retrieve the MAC address */
423 ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
424 ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
425 pdata->mac_addr[0] = ma_lo & 0xff;
426 pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;
427 pdata->mac_addr[2] = (ma_lo >>16) & 0xff;
428 pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;
429 pdata->mac_addr[4] = ma_hi & 0xff;
430 pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;
431 if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID)) {
432 axgbe_error("Invalid mac address\n");
435 iflib_set_mac(ctx, pdata->mac_addr);
438 pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;
439 pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;
441 /* Set the DMA coherency values */
443 pdata->arcr = XGBE_DMA_PCI_ARCR;
444 pdata->awcr = XGBE_DMA_PCI_AWCR;
445 pdata->awarcr = XGBE_DMA_PCI_AWARCR;
447 /* Read the port property registers */
448 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);
449 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);
450 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);
451 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);
452 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);
453 DBGPR("port property 0 = %#010x\n", pdata->pp0);
454 DBGPR("port property 1 = %#010x\n", pdata->pp1);
455 DBGPR("port property 2 = %#010x\n", pdata->pp2);
456 DBGPR("port property 3 = %#010x\n", pdata->pp3);
457 DBGPR("port property 4 = %#010x\n", pdata->pp4);
459 /* Set the maximum channels and queues */
460 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
462 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
464 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
466 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
468 DBGPR("max tx/rx channel count = %u/%u\n",
469 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
470 DBGPR("max tx/rx hw queue count = %u/%u\n",
471 pdata->tx_max_q_count, pdata->rx_max_q_count);
473 axgbe_set_counts(ctx);
475 /* Set the maximum fifo amounts */
476 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
478 pdata->tx_max_fifo_size *= 16384;
479 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
480 pdata->vdata->tx_max_fifo_size);
481 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
483 pdata->rx_max_fifo_size *= 16384;
484 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
485 pdata->vdata->rx_max_fifo_size);
486 DBGPR("max tx/rx max fifo size = %u/%u\n",
487 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
489 /* Initialize IFLIB if_softc_ctx_t */
490 axgbe_init_iflib_softc_ctx(sc);
493 if (axgbe_alloc_channels(ctx)) {
494 axgbe_error("Unable to allocate channel memory\n");
498 TASK_INIT(&pdata->service_work, 0, xgbe_service, pdata);
500 /* create the workqueue */
501 pdata->dev_workqueue = taskqueue_create("axgbe", M_WAITOK,
502 taskqueue_thread_enqueue, &pdata->dev_workqueue);
503 taskqueue_start_threads(&pdata->dev_workqueue, 1, PI_NET,
507 xgbe_init_timers(pdata);
510 } /* axgbe_if_attach_pre */
513 xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
515 xgbe_init_function_ptrs_dev(&pdata->hw_if);
516 xgbe_init_function_ptrs_phy(&pdata->phy_if);
517 xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
518 xgbe_init_function_ptrs_desc(&pdata->desc_if);
520 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
524 axgbe_set_counts(if_ctx_t ctx)
526 struct axgbe_if_softc *sc = iflib_get_softc(ctx);;
527 struct xgbe_prv_data *pdata = &sc->pdata;
532 /* Set all function pointers */
533 xgbe_init_all_fptrs(pdata);
535 /* Populate the hardware features */
536 xgbe_get_all_hw_features(pdata);
538 if (!pdata->tx_max_channel_count)
539 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
540 if (!pdata->rx_max_channel_count)
541 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
543 if (!pdata->tx_max_q_count)
544 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
545 if (!pdata->rx_max_q_count)
546 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
549 * Calculate the number of Tx and Rx rings to be created
550 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
551 * the number of Tx queues to the number of Tx channels
553 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
554 * number of Rx queues or maximum allowed
557 /* Get cpu count from sysctl */
558 len = sizeof(cpu_count);
559 err = kernel_sysctlbyname(curthread, "hw.ncpu", &cpu_count, &len, NULL,
562 axgbe_error("Unable to fetch number of cpus\n");
566 if (bus_get_cpus(pdata->dev, INTR_CPUS, sizeof(lcpus), &lcpus) != 0) {
567 axgbe_error("Unable to fetch CPU list\n");
568 /* TODO - handle CPU_COPY(&all_cpus, &lcpus); */
571 DBGPR("ncpu %d intrcpu %d\n", cpu_count, CPU_COUNT(&lcpus));
573 pdata->tx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.tx_ch_cnt);
574 pdata->tx_ring_count = min(pdata->tx_ring_count,
575 pdata->tx_max_channel_count);
576 pdata->tx_ring_count = min(pdata->tx_ring_count, pdata->tx_max_q_count);
578 pdata->tx_q_count = pdata->tx_ring_count;
580 pdata->rx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.rx_ch_cnt);
581 pdata->rx_ring_count = min(pdata->rx_ring_count,
582 pdata->rx_max_channel_count);
584 pdata->rx_q_count = min(pdata->hw_feat.rx_q_cnt, pdata->rx_max_q_count);
586 DBGPR("TX/RX max channel count = %u/%u\n",
587 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
588 DBGPR("TX/RX max queue count = %u/%u\n",
589 pdata->tx_max_q_count, pdata->rx_max_q_count);
590 DBGPR("TX/RX DMA ring count = %u/%u\n",
591 pdata->tx_ring_count, pdata->rx_ring_count);
592 DBGPR("TX/RX hardware queue count = %u/%u\n",
593 pdata->tx_q_count, pdata->rx_q_count);
594 } /* axgbe_set_counts */
597 axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *sc)
599 struct xgbe_prv_data *pdata = &sc->pdata;
600 if_softc_ctx_t scctx = sc->scctx;
601 if_shared_ctx_t sctx = sc->sctx;
604 scctx->isc_nrxqsets = pdata->rx_q_count;
605 scctx->isc_ntxqsets = pdata->tx_q_count;
606 scctx->isc_msix_bar = pci_msix_table_bar(pdata->dev);
607 scctx->isc_tx_nsegments = 32;
609 for (i = 0; i < sctx->isc_ntxqs; i++) {
610 scctx->isc_txqsizes[i] =
611 roundup2(scctx->isc_ntxd[i] * sizeof(struct xgbe_ring_desc),
613 scctx->isc_txd_size[i] = sizeof(struct xgbe_ring_desc);
616 for (i = 0; i < sctx->isc_nrxqs; i++) {
617 scctx->isc_rxqsizes[i] =
618 roundup2(scctx->isc_nrxd[i] * sizeof(struct xgbe_ring_desc),
620 scctx->isc_rxd_size[i] = sizeof(struct xgbe_ring_desc);
623 scctx->isc_tx_tso_segments_max = 32;
624 scctx->isc_tx_tso_size_max = XGBE_TSO_MAX_SIZE;
625 scctx->isc_tx_tso_segsize_max = PAGE_SIZE;
629 * 1) IFLIB automatically adds IFCAP_HWSTATS, so need to set explicitly
630 * 2) isc_tx_csum_flags is mandatory if IFCAP_TXCSUM (included in
631 * IFCAP_HWCSUM) is set
633 scctx->isc_tx_csum_flags = (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP |
634 CSUM_TCP_IPV6 | CSUM_UDP_IPV6 | CSUM_SCTP_IPV6 |
636 scctx->isc_capenable = (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
638 IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER |
640 IFCAP_TSO | IFCAP_VLAN_HWTSO);
641 scctx->isc_capabilities = scctx->isc_capenable;
644 * Set rss_table_size alone when adding RSS support. rss_table_mask
645 * will be set by IFLIB based on rss_table_size
647 scctx->isc_rss_table_size = XGBE_RSS_MAX_TABLE_SIZE;
649 scctx->isc_ntxqsets_max = XGBE_MAX_QUEUES;
650 scctx->isc_nrxqsets_max = XGBE_MAX_QUEUES;
652 scctx->isc_txrx = &axgbe_txrx;
656 axgbe_alloc_channels(if_ctx_t ctx)
658 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
659 struct xgbe_prv_data *pdata = &sc->pdata;
660 struct xgbe_channel *channel;
663 DBGPR("%s: txqs %d rxqs %d\n", __func__, pdata->tx_ring_count,
664 pdata->rx_ring_count);
666 /* Iflibe sets based on isc_ntxqsets/nrxqsets */
667 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
669 /* Allocate channel memory */
670 for (i = 0; i < count ; i++) {
671 channel = (struct xgbe_channel*)malloc(sizeof(struct xgbe_channel),
672 M_AXGBE, M_NOWAIT | M_ZERO);
674 if (channel == NULL) {
675 for (j = 0; j < i; j++) {
676 free(pdata->channel[j], M_AXGBE);
677 pdata->channel[j] = NULL;
682 pdata->channel[i] = channel;
685 pdata->total_channel_count = count;
686 DBGPR("Channel count set to: %u\n", pdata->total_channel_count);
688 for (i = 0; i < count; i++) {
690 channel = pdata->channel[i];
691 snprintf(channel->name, sizeof(channel->name), "channel-%d",i);
693 channel->pdata = pdata;
694 channel->queue_index = i;
695 channel->dma_tag = rman_get_bustag(pdata->xgmac_res);
696 bus_space_subregion(channel->dma_tag,
697 rman_get_bushandle(pdata->xgmac_res),
698 DMA_CH_BASE + (DMA_CH_INC * i), DMA_CH_INC,
699 &channel->dma_handle);
700 channel->tx_ring = NULL;
701 channel->rx_ring = NULL;
705 } /* axgbe_alloc_channels */
708 xgbe_service(void *ctx, int pending)
710 struct xgbe_prv_data *pdata = ctx;
711 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)pdata;
712 bool prev_state = false;
714 /* Get previous link status */
715 prev_state = pdata->phy.link;
717 pdata->phy_if.phy_status(pdata);
719 if (prev_state != pdata->phy.link) {
720 pdata->phy_link = pdata->phy.link;
721 axgbe_if_update_admin_status(sc->ctx);
724 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
728 xgbe_service_timer(void *data)
730 struct xgbe_prv_data *pdata = data;
732 taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work);
736 xgbe_init_timers(struct xgbe_prv_data *pdata)
738 callout_init(&pdata->service_timer, 1*hz);
742 xgbe_start_timers(struct xgbe_prv_data *pdata)
744 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
748 xgbe_stop_timers(struct xgbe_prv_data *pdata)
750 callout_drain(&pdata->service_timer);
751 callout_stop(&pdata->service_timer);
755 xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
757 axgbe_printf(1, "\n************* PHY Reg dump *********************\n");
759 axgbe_printf(1, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
760 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
761 axgbe_printf(1, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
762 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
763 axgbe_printf(1, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
764 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
765 axgbe_printf(1, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
766 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
767 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
768 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
769 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
770 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
771 axgbe_printf(1, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
772 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
773 axgbe_printf(1, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
774 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
775 axgbe_printf(1, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
777 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
778 axgbe_printf(1, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
779 MDIO_AN_ADVERTISE + 1,
780 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
781 axgbe_printf(1, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
782 MDIO_AN_ADVERTISE + 2,
783 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
784 axgbe_printf(1, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
786 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
788 axgbe_printf(1, "\n************************************************\n");
792 xgbe_dump_prop_registers(struct xgbe_prv_data *pdata)
796 axgbe_printf(1, "\n************* PROP Reg dump ********************\n");
798 for (i = 0 ; i < 38 ; i++) {
799 axgbe_printf(1, "PROP Offset 0x%08x = %08x\n",
800 (XP_PROP_0 + (i * 4)), XP_IOREAD(pdata,
801 (XP_PROP_0 + (i * 4))));
806 xgbe_dump_dma_registers(struct xgbe_prv_data *pdata, int ch)
808 struct xgbe_channel *channel;
811 axgbe_printf(1, "\n************* DMA Reg dump *********************\n");
813 axgbe_printf(1, "DMA MR Reg (%08x) = %08x\n", DMA_MR,
814 XGMAC_IOREAD(pdata, DMA_MR));
815 axgbe_printf(1, "DMA SBMR Reg (%08x) = %08x\n", DMA_SBMR,
816 XGMAC_IOREAD(pdata, DMA_SBMR));
817 axgbe_printf(1, "DMA ISR Reg (%08x) = %08x\n", DMA_ISR,
818 XGMAC_IOREAD(pdata, DMA_ISR));
819 axgbe_printf(1, "DMA AXIARCR Reg (%08x) = %08x\n", DMA_AXIARCR,
820 XGMAC_IOREAD(pdata, DMA_AXIARCR));
821 axgbe_printf(1, "DMA AXIAWCR Reg (%08x) = %08x\n", DMA_AXIAWCR,
822 XGMAC_IOREAD(pdata, DMA_AXIAWCR));
823 axgbe_printf(1, "DMA AXIAWARCR Reg (%08x) = %08x\n", DMA_AXIAWARCR,
824 XGMAC_IOREAD(pdata, DMA_AXIAWARCR));
825 axgbe_printf(1, "DMA DSR0 Reg (%08x) = %08x\n", DMA_DSR0,
826 XGMAC_IOREAD(pdata, DMA_DSR0));
827 axgbe_printf(1, "DMA DSR1 Reg (%08x) = %08x\n", DMA_DSR1,
828 XGMAC_IOREAD(pdata, DMA_DSR1));
829 axgbe_printf(1, "DMA DSR2 Reg (%08x) = %08x\n", DMA_DSR2,
830 XGMAC_IOREAD(pdata, DMA_DSR2));
831 axgbe_printf(1, "DMA DSR3 Reg (%08x) = %08x\n", DMA_DSR3,
832 XGMAC_IOREAD(pdata, DMA_DSR3));
833 axgbe_printf(1, "DMA DSR4 Reg (%08x) = %08x\n", DMA_DSR4,
834 XGMAC_IOREAD(pdata, DMA_DSR4));
835 axgbe_printf(1, "DMA TXEDMACR Reg (%08x) = %08x\n", DMA_TXEDMACR,
836 XGMAC_IOREAD(pdata, DMA_TXEDMACR));
837 axgbe_printf(1, "DMA RXEDMACR Reg (%08x) = %08x\n", DMA_RXEDMACR,
838 XGMAC_IOREAD(pdata, DMA_RXEDMACR));
840 for (i = 0 ; i < 8 ; i++ ) {
847 channel = pdata->channel[i];
849 axgbe_printf(1, "\n************* DMA CH %d dump ****************\n", i);
851 axgbe_printf(1, "DMA_CH_CR Reg (%08x) = %08x\n",
852 DMA_CH_CR, XGMAC_DMA_IOREAD(channel, DMA_CH_CR));
853 axgbe_printf(1, "DMA_CH_TCR Reg (%08x) = %08x\n",
854 DMA_CH_TCR, XGMAC_DMA_IOREAD(channel, DMA_CH_TCR));
855 axgbe_printf(1, "DMA_CH_RCR Reg (%08x) = %08x\n",
856 DMA_CH_RCR, XGMAC_DMA_IOREAD(channel, DMA_CH_RCR));
857 axgbe_printf(1, "DMA_CH_TDLR_HI Reg (%08x) = %08x\n",
858 DMA_CH_TDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_HI));
859 axgbe_printf(1, "DMA_CH_TDLR_LO Reg (%08x) = %08x\n",
860 DMA_CH_TDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_LO));
861 axgbe_printf(1, "DMA_CH_RDLR_HI Reg (%08x) = %08x\n",
862 DMA_CH_RDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_HI));
863 axgbe_printf(1, "DMA_CH_RDLR_LO Reg (%08x) = %08x\n",
864 DMA_CH_RDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_LO));
865 axgbe_printf(1, "DMA_CH_TDTR_LO Reg (%08x) = %08x\n",
866 DMA_CH_TDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTR_LO));
867 axgbe_printf(1, "DMA_CH_RDTR_LO Reg (%08x) = %08x\n",
868 DMA_CH_RDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTR_LO));
869 axgbe_printf(1, "DMA_CH_TDRLR Reg (%08x) = %08x\n",
870 DMA_CH_TDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_TDRLR));
871 axgbe_printf(1, "DMA_CH_RDRLR Reg (%08x) = %08x\n",
872 DMA_CH_RDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_RDRLR));
873 axgbe_printf(1, "DMA_CH_IER Reg (%08x) = %08x\n",
874 DMA_CH_IER, XGMAC_DMA_IOREAD(channel, DMA_CH_IER));
875 axgbe_printf(1, "DMA_CH_RIWT Reg (%08x) = %08x\n",
876 DMA_CH_RIWT, XGMAC_DMA_IOREAD(channel, DMA_CH_RIWT));
877 axgbe_printf(1, "DMA_CH_CATDR_LO Reg (%08x) = %08x\n",
878 DMA_CH_CATDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATDR_LO));
879 axgbe_printf(1, "DMA_CH_CARDR_LO Reg (%08x) = %08x\n",
880 DMA_CH_CARDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARDR_LO));
881 axgbe_printf(1, "DMA_CH_CATBR_HI Reg (%08x) = %08x\n",
882 DMA_CH_CATBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_HI));
883 axgbe_printf(1, "DMA_CH_CATBR_LO Reg (%08x) = %08x\n",
884 DMA_CH_CATBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_LO));
885 axgbe_printf(1, "DMA_CH_CARBR_HI Reg (%08x) = %08x\n",
886 DMA_CH_CARBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_HI));
887 axgbe_printf(1, "DMA_CH_CARBR_LO Reg (%08x) = %08x\n",
888 DMA_CH_CARBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_LO));
889 axgbe_printf(1, "DMA_CH_SR Reg (%08x) = %08x\n",
890 DMA_CH_SR, XGMAC_DMA_IOREAD(channel, DMA_CH_SR));
891 axgbe_printf(1, "DMA_CH_DSR Reg (%08x) = %08x\n",
892 DMA_CH_DSR, XGMAC_DMA_IOREAD(channel, DMA_CH_DSR));
893 axgbe_printf(1, "DMA_CH_DCFL Reg (%08x) = %08x\n",
894 DMA_CH_DCFL, XGMAC_DMA_IOREAD(channel, DMA_CH_DCFL));
895 axgbe_printf(1, "DMA_CH_MFC Reg (%08x) = %08x\n",
896 DMA_CH_MFC, XGMAC_DMA_IOREAD(channel, DMA_CH_MFC));
897 axgbe_printf(1, "DMA_CH_TDTRO Reg (%08x) = %08x\n",
898 DMA_CH_TDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTRO));
899 axgbe_printf(1, "DMA_CH_RDTRO Reg (%08x) = %08x\n",
900 DMA_CH_RDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTRO));
901 axgbe_printf(1, "DMA_CH_TDWRO Reg (%08x) = %08x\n",
902 DMA_CH_TDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDWRO));
903 axgbe_printf(1, "DMA_CH_RDWRO Reg (%08x) = %08x\n",
904 DMA_CH_RDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDWRO));
909 xgbe_dump_mtl_registers(struct xgbe_prv_data *pdata)
913 axgbe_printf(1, "\n************* MTL Reg dump *********************\n");
915 axgbe_printf(1, "MTL OMR Reg (%08x) = %08x\n", MTL_OMR,
916 XGMAC_IOREAD(pdata, MTL_OMR));
917 axgbe_printf(1, "MTL FDCR Reg (%08x) = %08x\n", MTL_FDCR,
918 XGMAC_IOREAD(pdata, MTL_FDCR));
919 axgbe_printf(1, "MTL FDSR Reg (%08x) = %08x\n", MTL_FDSR,
920 XGMAC_IOREAD(pdata, MTL_FDSR));
921 axgbe_printf(1, "MTL FDDR Reg (%08x) = %08x\n", MTL_FDDR,
922 XGMAC_IOREAD(pdata, MTL_FDDR));
923 axgbe_printf(1, "MTL ISR Reg (%08x) = %08x\n", MTL_ISR,
924 XGMAC_IOREAD(pdata, MTL_ISR));
925 axgbe_printf(1, "MTL RQDCM0R Reg (%08x) = %08x\n", MTL_RQDCM0R,
926 XGMAC_IOREAD(pdata, MTL_RQDCM0R));
927 axgbe_printf(1, "MTL RQDCM1R Reg (%08x) = %08x\n", MTL_RQDCM1R,
928 XGMAC_IOREAD(pdata, MTL_RQDCM1R));
929 axgbe_printf(1, "MTL RQDCM2R Reg (%08x) = %08x\n", MTL_RQDCM2R,
930 XGMAC_IOREAD(pdata, MTL_RQDCM2R));
931 axgbe_printf(1, "MTL TCPM0R Reg (%08x) = %08x\n", MTL_TCPM0R,
932 XGMAC_IOREAD(pdata, MTL_TCPM0R));
933 axgbe_printf(1, "MTL TCPM1R Reg (%08x) = %08x\n", MTL_TCPM1R,
934 XGMAC_IOREAD(pdata, MTL_TCPM1R));
936 for (i = 0 ; i < 8 ; i++ ) {
938 axgbe_printf(1, "\n************* MTL CH %d dump ****************\n", i);
940 axgbe_printf(1, "MTL_Q_TQOMR Reg (%08x) = %08x\n",
941 MTL_Q_TQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR));
942 axgbe_printf(1, "MTL_Q_TQUR Reg (%08x) = %08x\n",
943 MTL_Q_TQUR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQUR));
944 axgbe_printf(1, "MTL_Q_TQDR Reg (%08x) = %08x\n",
945 MTL_Q_TQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQDR));
946 axgbe_printf(1, "MTL_Q_TC0ETSCR Reg (%08x) = %08x\n",
947 MTL_Q_TC0ETSCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSCR));
948 axgbe_printf(1, "MTL_Q_TC0ETSSR Reg (%08x) = %08x\n",
949 MTL_Q_TC0ETSSR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSSR));
950 axgbe_printf(1, "MTL_Q_TC0QWR Reg (%08x) = %08x\n",
951 MTL_Q_TC0QWR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0QWR));
953 axgbe_printf(1, "MTL_Q_RQOMR Reg (%08x) = %08x\n",
954 MTL_Q_RQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR));
955 axgbe_printf(1, "MTL_Q_RQMPOCR Reg (%08x) = %08x\n",
956 MTL_Q_RQMPOCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQMPOCR));
957 axgbe_printf(1, "MTL_Q_RQDR Reg (%08x) = %08x\n",
958 MTL_Q_RQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQDR));
959 axgbe_printf(1, "MTL_Q_RQCR Reg (%08x) = %08x\n",
960 MTL_Q_RQCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQCR));
961 axgbe_printf(1, "MTL_Q_RQFCR Reg (%08x) = %08x\n",
962 MTL_Q_RQFCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR));
963 axgbe_printf(1, "MTL_Q_IER Reg (%08x) = %08x\n",
964 MTL_Q_IER, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_IER));
965 axgbe_printf(1, "MTL_Q_ISR Reg (%08x) = %08x\n",
966 MTL_Q_ISR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR));
971 xgbe_dump_mac_registers(struct xgbe_prv_data *pdata)
973 axgbe_printf(1, "\n************* MAC Reg dump **********************\n");
975 axgbe_printf(1, "MAC TCR Reg (%08x) = %08x\n", MAC_TCR,
976 XGMAC_IOREAD(pdata, MAC_TCR));
977 axgbe_printf(1, "MAC RCR Reg (%08x) = %08x\n", MAC_RCR,
978 XGMAC_IOREAD(pdata, MAC_RCR));
979 axgbe_printf(1, "MAC PFR Reg (%08x) = %08x\n", MAC_PFR,
980 XGMAC_IOREAD(pdata, MAC_PFR));
981 axgbe_printf(1, "MAC WTR Reg (%08x) = %08x\n", MAC_WTR,
982 XGMAC_IOREAD(pdata, MAC_WTR));
983 axgbe_printf(1, "MAC HTR0 Reg (%08x) = %08x\n", MAC_HTR0,
984 XGMAC_IOREAD(pdata, MAC_HTR0));
985 axgbe_printf(1, "MAC HTR1 Reg (%08x) = %08x\n", MAC_HTR1,
986 XGMAC_IOREAD(pdata, MAC_HTR1));
987 axgbe_printf(1, "MAC HTR2 Reg (%08x) = %08x\n", MAC_HTR2,
988 XGMAC_IOREAD(pdata, MAC_HTR2));
989 axgbe_printf(1, "MAC HTR3 Reg (%08x) = %08x\n", MAC_HTR3,
990 XGMAC_IOREAD(pdata, MAC_HTR3));
991 axgbe_printf(1, "MAC HTR4 Reg (%08x) = %08x\n", MAC_HTR4,
992 XGMAC_IOREAD(pdata, MAC_HTR4));
993 axgbe_printf(1, "MAC HTR5 Reg (%08x) = %08x\n", MAC_HTR5,
994 XGMAC_IOREAD(pdata, MAC_HTR5));
995 axgbe_printf(1, "MAC HTR6 Reg (%08x) = %08x\n", MAC_HTR6,
996 XGMAC_IOREAD(pdata, MAC_HTR6));
997 axgbe_printf(1, "MAC HTR7 Reg (%08x) = %08x\n", MAC_HTR7,
998 XGMAC_IOREAD(pdata, MAC_HTR7));
999 axgbe_printf(1, "MAC VLANTR Reg (%08x) = %08x\n", MAC_VLANTR,
1000 XGMAC_IOREAD(pdata, MAC_VLANTR));
1001 axgbe_printf(1, "MAC VLANHTR Reg (%08x) = %08x\n", MAC_VLANHTR,
1002 XGMAC_IOREAD(pdata, MAC_VLANHTR));
1003 axgbe_printf(1, "MAC VLANIR Reg (%08x) = %08x\n", MAC_VLANIR,
1004 XGMAC_IOREAD(pdata, MAC_VLANIR));
1005 axgbe_printf(1, "MAC IVLANIR Reg (%08x) = %08x\n", MAC_IVLANIR,
1006 XGMAC_IOREAD(pdata, MAC_IVLANIR));
1007 axgbe_printf(1, "MAC RETMR Reg (%08x) = %08x\n", MAC_RETMR,
1008 XGMAC_IOREAD(pdata, MAC_RETMR));
1009 axgbe_printf(1, "MAC Q0TFCR Reg (%08x) = %08x\n", MAC_Q0TFCR,
1010 XGMAC_IOREAD(pdata, MAC_Q0TFCR));
1011 axgbe_printf(1, "MAC Q1TFCR Reg (%08x) = %08x\n", MAC_Q1TFCR,
1012 XGMAC_IOREAD(pdata, MAC_Q1TFCR));
1013 axgbe_printf(1, "MAC Q2TFCR Reg (%08x) = %08x\n", MAC_Q2TFCR,
1014 XGMAC_IOREAD(pdata, MAC_Q2TFCR));
1015 axgbe_printf(1, "MAC Q3TFCR Reg (%08x) = %08x\n", MAC_Q3TFCR,
1016 XGMAC_IOREAD(pdata, MAC_Q3TFCR));
1017 axgbe_printf(1, "MAC Q4TFCR Reg (%08x) = %08x\n", MAC_Q4TFCR,
1018 XGMAC_IOREAD(pdata, MAC_Q4TFCR));
1019 axgbe_printf(1, "MAC Q5TFCR Reg (%08x) = %08x\n", MAC_Q5TFCR,
1020 XGMAC_IOREAD(pdata, MAC_Q5TFCR));
1021 axgbe_printf(1, "MAC Q6TFCR Reg (%08x) = %08x\n", MAC_Q6TFCR,
1022 XGMAC_IOREAD(pdata, MAC_Q6TFCR));
1023 axgbe_printf(1, "MAC Q7TFCR Reg (%08x) = %08x\n", MAC_Q7TFCR,
1024 XGMAC_IOREAD(pdata, MAC_Q7TFCR));
1025 axgbe_printf(1, "MAC RFCR Reg (%08x) = %08x\n", MAC_RFCR,
1026 XGMAC_IOREAD(pdata, MAC_RFCR));
1027 axgbe_printf(1, "MAC RQC0R Reg (%08x) = %08x\n", MAC_RQC0R,
1028 XGMAC_IOREAD(pdata, MAC_RQC0R));
1029 axgbe_printf(1, "MAC RQC1R Reg (%08x) = %08x\n", MAC_RQC1R,
1030 XGMAC_IOREAD(pdata, MAC_RQC1R));
1031 axgbe_printf(1, "MAC RQC2R Reg (%08x) = %08x\n", MAC_RQC2R,
1032 XGMAC_IOREAD(pdata, MAC_RQC2R));
1033 axgbe_printf(1, "MAC RQC3R Reg (%08x) = %08x\n", MAC_RQC3R,
1034 XGMAC_IOREAD(pdata, MAC_RQC3R));
1035 axgbe_printf(1, "MAC ISR Reg (%08x) = %08x\n", MAC_ISR,
1036 XGMAC_IOREAD(pdata, MAC_ISR));
1037 axgbe_printf(1, "MAC IER Reg (%08x) = %08x\n", MAC_IER,
1038 XGMAC_IOREAD(pdata, MAC_IER));
1039 axgbe_printf(1, "MAC RTSR Reg (%08x) = %08x\n", MAC_RTSR,
1040 XGMAC_IOREAD(pdata, MAC_RTSR));
1041 axgbe_printf(1, "MAC PMTCSR Reg (%08x) = %08x\n", MAC_PMTCSR,
1042 XGMAC_IOREAD(pdata, MAC_PMTCSR));
1043 axgbe_printf(1, "MAC RWKPFR Reg (%08x) = %08x\n", MAC_RWKPFR,
1044 XGMAC_IOREAD(pdata, MAC_RWKPFR));
1045 axgbe_printf(1, "MAC LPICSR Reg (%08x) = %08x\n", MAC_LPICSR,
1046 XGMAC_IOREAD(pdata, MAC_LPICSR));
1047 axgbe_printf(1, "MAC LPITCR Reg (%08x) = %08x\n", MAC_LPITCR,
1048 XGMAC_IOREAD(pdata, MAC_LPITCR));
1049 axgbe_printf(1, "MAC TIR Reg (%08x) = %08x\n", MAC_TIR,
1050 XGMAC_IOREAD(pdata, MAC_TIR));
1051 axgbe_printf(1, "MAC VR Reg (%08x) = %08x\n", MAC_VR,
1052 XGMAC_IOREAD(pdata, MAC_VR));
1053 axgbe_printf(1, "MAC DR Reg (%08x) = %08x\n", MAC_DR,
1054 XGMAC_IOREAD(pdata, MAC_DR));
1055 axgbe_printf(1, "MAC HWF0R Reg (%08x) = %08x\n", MAC_HWF0R,
1056 XGMAC_IOREAD(pdata, MAC_HWF0R));
1057 axgbe_printf(1, "MAC HWF1R Reg (%08x) = %08x\n", MAC_HWF1R,
1058 XGMAC_IOREAD(pdata, MAC_HWF1R));
1059 axgbe_printf(1, "MAC HWF2R Reg (%08x) = %08x\n", MAC_HWF2R,
1060 XGMAC_IOREAD(pdata, MAC_HWF2R));
1061 axgbe_printf(1, "MAC MDIOSCAR Reg (%08x) = %08x\n", MAC_MDIOSCAR,
1062 XGMAC_IOREAD(pdata, MAC_MDIOSCAR));
1063 axgbe_printf(1, "MAC MDIOSCCDR Reg (%08x) = %08x\n", MAC_MDIOSCCDR,
1064 XGMAC_IOREAD(pdata, MAC_MDIOSCCDR));
1065 axgbe_printf(1, "MAC MDIOISR Reg (%08x) = %08x\n", MAC_MDIOISR,
1066 XGMAC_IOREAD(pdata, MAC_MDIOISR));
1067 axgbe_printf(1, "MAC MDIOIER Reg (%08x) = %08x\n", MAC_MDIOIER,
1068 XGMAC_IOREAD(pdata, MAC_MDIOIER));
1069 axgbe_printf(1, "MAC MDIOCL22R Reg (%08x) = %08x\n", MAC_MDIOCL22R,
1070 XGMAC_IOREAD(pdata, MAC_MDIOCL22R));
1071 axgbe_printf(1, "MAC GPIOCR Reg (%08x) = %08x\n", MAC_GPIOCR,
1072 XGMAC_IOREAD(pdata, MAC_GPIOCR));
1073 axgbe_printf(1, "MAC GPIOSR Reg (%08x) = %08x\n", MAC_GPIOSR,
1074 XGMAC_IOREAD(pdata, MAC_GPIOSR));
1075 axgbe_printf(1, "MAC MACA0HR Reg (%08x) = %08x\n", MAC_MACA0HR,
1076 XGMAC_IOREAD(pdata, MAC_MACA0HR));
1077 axgbe_printf(1, "MAC MACA0LR Reg (%08x) = %08x\n", MAC_TCR,
1078 XGMAC_IOREAD(pdata, MAC_MACA0LR));
1079 axgbe_printf(1, "MAC MACA1HR Reg (%08x) = %08x\n", MAC_MACA1HR,
1080 XGMAC_IOREAD(pdata, MAC_MACA1HR));
1081 axgbe_printf(1, "MAC MACA1LR Reg (%08x) = %08x\n", MAC_MACA1LR,
1082 XGMAC_IOREAD(pdata, MAC_MACA1LR));
1083 axgbe_printf(1, "MAC RSSCR Reg (%08x) = %08x\n", MAC_RSSCR,
1084 XGMAC_IOREAD(pdata, MAC_RSSCR));
1085 axgbe_printf(1, "MAC RSSDR Reg (%08x) = %08x\n", MAC_RSSDR,
1086 XGMAC_IOREAD(pdata, MAC_RSSDR));
1087 axgbe_printf(1, "MAC RSSAR Reg (%08x) = %08x\n", MAC_RSSAR,
1088 XGMAC_IOREAD(pdata, MAC_RSSAR));
1089 axgbe_printf(1, "MAC TSCR Reg (%08x) = %08x\n", MAC_TSCR,
1090 XGMAC_IOREAD(pdata, MAC_TSCR));
1091 axgbe_printf(1, "MAC SSIR Reg (%08x) = %08x\n", MAC_SSIR,
1092 XGMAC_IOREAD(pdata, MAC_SSIR));
1093 axgbe_printf(1, "MAC STSR Reg (%08x) = %08x\n", MAC_STSR,
1094 XGMAC_IOREAD(pdata, MAC_STSR));
1095 axgbe_printf(1, "MAC STNR Reg (%08x) = %08x\n", MAC_STNR,
1096 XGMAC_IOREAD(pdata, MAC_STNR));
1097 axgbe_printf(1, "MAC STSUR Reg (%08x) = %08x\n", MAC_STSUR,
1098 XGMAC_IOREAD(pdata, MAC_STSUR));
1099 axgbe_printf(1, "MAC STNUR Reg (%08x) = %08x\n", MAC_STNUR,
1100 XGMAC_IOREAD(pdata, MAC_STNUR));
1101 axgbe_printf(1, "MAC TSAR Reg (%08x) = %08x\n", MAC_TSAR,
1102 XGMAC_IOREAD(pdata, MAC_TSAR));
1103 axgbe_printf(1, "MAC TSSR Reg (%08x) = %08x\n", MAC_TSSR,
1104 XGMAC_IOREAD(pdata, MAC_TSSR));
1105 axgbe_printf(1, "MAC TXSNR Reg (%08x) = %08x\n", MAC_TXSNR,
1106 XGMAC_IOREAD(pdata, MAC_TXSNR));
1107 axgbe_printf(1, "MAC TXSSR Reg (%08x) = %08x\n", MAC_TXSSR,
1108 XGMAC_IOREAD(pdata, MAC_TXSSR));
1112 xgbe_dump_rmon_counters(struct xgbe_prv_data *pdata)
1114 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
1116 axgbe_printf(1, "\n************* RMON counters dump ***************\n");
1118 pdata->hw_if.read_mmc_stats(pdata);
1120 axgbe_printf(1, "rmon txoctetcount_gb (%08x) = %08lx\n",
1121 MMC_TXOCTETCOUNT_GB_LO, stats->txoctetcount_gb);
1122 axgbe_printf(1, "rmon txframecount_gb (%08x) = %08lx\n",
1123 MMC_TXFRAMECOUNT_GB_LO, stats->txframecount_gb);
1124 axgbe_printf(1, "rmon txbroadcastframes_g (%08x) = %08lx\n",
1125 MMC_TXBROADCASTFRAMES_G_LO, stats->txbroadcastframes_g);
1126 axgbe_printf(1, "rmon txmulticastframes_g (%08x) = %08lx\n",
1127 MMC_TXMULTICASTFRAMES_G_LO, stats->txmulticastframes_g);
1128 axgbe_printf(1, "rmon tx64octets_gb (%08x) = %08lx\n",
1129 MMC_TX64OCTETS_GB_LO, stats->tx64octets_gb);
1130 axgbe_printf(1, "rmon tx65to127octets_gb (%08x) = %08lx\n",
1131 MMC_TX65TO127OCTETS_GB_LO, stats->tx65to127octets_gb);
1132 axgbe_printf(1, "rmon tx128to255octets_gb (%08x) = %08lx\n",
1133 MMC_TX128TO255OCTETS_GB_LO, stats->tx128to255octets_gb);
1134 axgbe_printf(1, "rmon tx256to511octets_gb (%08x) = %08lx\n",
1135 MMC_TX256TO511OCTETS_GB_LO, stats->tx256to511octets_gb);
1136 axgbe_printf(1, "rmon tx512to1023octets_gb (%08x) = %08lx\n",
1137 MMC_TX512TO1023OCTETS_GB_LO, stats->tx512to1023octets_gb);
1138 axgbe_printf(1, "rmon tx1024tomaxoctets_gb (%08x) = %08lx\n",
1139 MMC_TX1024TOMAXOCTETS_GB_LO, stats->tx1024tomaxoctets_gb);
1140 axgbe_printf(1, "rmon txunicastframes_gb (%08x) = %08lx\n",
1141 MMC_TXUNICASTFRAMES_GB_LO, stats->txunicastframes_gb);
1142 axgbe_printf(1, "rmon txmulticastframes_gb (%08x) = %08lx\n",
1143 MMC_TXMULTICASTFRAMES_GB_LO, stats->txmulticastframes_gb);
1144 axgbe_printf(1, "rmon txbroadcastframes_gb (%08x) = %08lx\n",
1145 MMC_TXBROADCASTFRAMES_GB_LO, stats->txbroadcastframes_gb);
1146 axgbe_printf(1, "rmon txunderflowerror (%08x) = %08lx\n",
1147 MMC_TXUNDERFLOWERROR_LO, stats->txunderflowerror);
1148 axgbe_printf(1, "rmon txoctetcount_g (%08x) = %08lx\n",
1149 MMC_TXOCTETCOUNT_G_LO, stats->txoctetcount_g);
1150 axgbe_printf(1, "rmon txframecount_g (%08x) = %08lx\n",
1151 MMC_TXFRAMECOUNT_G_LO, stats->txframecount_g);
1152 axgbe_printf(1, "rmon txpauseframes (%08x) = %08lx\n",
1153 MMC_TXPAUSEFRAMES_LO, stats->txpauseframes);
1154 axgbe_printf(1, "rmon txvlanframes_g (%08x) = %08lx\n",
1155 MMC_TXVLANFRAMES_G_LO, stats->txvlanframes_g);
1156 axgbe_printf(1, "rmon rxframecount_gb (%08x) = %08lx\n",
1157 MMC_RXFRAMECOUNT_GB_LO, stats->rxframecount_gb);
1158 axgbe_printf(1, "rmon rxoctetcount_gb (%08x) = %08lx\n",
1159 MMC_RXOCTETCOUNT_GB_LO, stats->rxoctetcount_gb);
1160 axgbe_printf(1, "rmon rxoctetcount_g (%08x) = %08lx\n",
1161 MMC_RXOCTETCOUNT_G_LO, stats->rxoctetcount_g);
1162 axgbe_printf(1, "rmon rxbroadcastframes_g (%08x) = %08lx\n",
1163 MMC_RXBROADCASTFRAMES_G_LO, stats->rxbroadcastframes_g);
1164 axgbe_printf(1, "rmon rxmulticastframes_g (%08x) = %08lx\n",
1165 MMC_RXMULTICASTFRAMES_G_LO, stats->rxmulticastframes_g);
1166 axgbe_printf(1, "rmon rxcrcerror (%08x) = %08lx\n",
1167 MMC_RXCRCERROR_LO, stats->rxcrcerror);
1168 axgbe_printf(1, "rmon rxrunterror (%08x) = %08lx\n",
1169 MMC_RXRUNTERROR, stats->rxrunterror);
1170 axgbe_printf(1, "rmon rxjabbererror (%08x) = %08lx\n",
1171 MMC_RXJABBERERROR, stats->rxjabbererror);
1172 axgbe_printf(1, "rmon rxundersize_g (%08x) = %08lx\n",
1173 MMC_RXUNDERSIZE_G, stats->rxundersize_g);
1174 axgbe_printf(1, "rmon rxoversize_g (%08x) = %08lx\n",
1175 MMC_RXOVERSIZE_G, stats->rxoversize_g);
1176 axgbe_printf(1, "rmon rx64octets_gb (%08x) = %08lx\n",
1177 MMC_RX64OCTETS_GB_LO, stats->rx64octets_gb);
1178 axgbe_printf(1, "rmon rx65to127octets_gb (%08x) = %08lx\n",
1179 MMC_RX65TO127OCTETS_GB_LO, stats->rx65to127octets_gb);
1180 axgbe_printf(1, "rmon rx128to255octets_gb (%08x) = %08lx\n",
1181 MMC_RX128TO255OCTETS_GB_LO, stats->rx128to255octets_gb);
1182 axgbe_printf(1, "rmon rx256to511octets_gb (%08x) = %08lx\n",
1183 MMC_RX256TO511OCTETS_GB_LO, stats->rx256to511octets_gb);
1184 axgbe_printf(1, "rmon rx512to1023octets_gb (%08x) = %08lx\n",
1185 MMC_RX512TO1023OCTETS_GB_LO, stats->rx512to1023octets_gb);
1186 axgbe_printf(1, "rmon rx1024tomaxoctets_gb (%08x) = %08lx\n",
1187 MMC_RX1024TOMAXOCTETS_GB_LO, stats->rx1024tomaxoctets_gb);
1188 axgbe_printf(1, "rmon rxunicastframes_g (%08x) = %08lx\n",
1189 MMC_RXUNICASTFRAMES_G_LO, stats->rxunicastframes_g);
1190 axgbe_printf(1, "rmon rxlengtherror (%08x) = %08lx\n",
1191 MMC_RXLENGTHERROR_LO, stats->rxlengtherror);
1192 axgbe_printf(1, "rmon rxoutofrangetype (%08x) = %08lx\n",
1193 MMC_RXOUTOFRANGETYPE_LO, stats->rxoutofrangetype);
1194 axgbe_printf(1, "rmon rxpauseframes (%08x) = %08lx\n",
1195 MMC_RXPAUSEFRAMES_LO, stats->rxpauseframes);
1196 axgbe_printf(1, "rmon rxfifooverflow (%08x) = %08lx\n",
1197 MMC_RXFIFOOVERFLOW_LO, stats->rxfifooverflow);
1198 axgbe_printf(1, "rmon rxvlanframes_gb (%08x) = %08lx\n",
1199 MMC_RXVLANFRAMES_GB_LO, stats->rxvlanframes_gb);
1200 axgbe_printf(1, "rmon rxwatchdogerror (%08x) = %08lx\n",
1201 MMC_RXWATCHDOGERROR, stats->rxwatchdogerror);
1205 xgbe_dump_i2c_registers(struct xgbe_prv_data *pdata)
1207 axgbe_printf(1, "*************** I2C Registers **************\n");
1208 axgbe_printf(1, " IC_CON : %010x\n",
1209 XI2C_IOREAD(pdata, 0x00));
1210 axgbe_printf(1, " IC_TAR : %010x\n",
1211 XI2C_IOREAD(pdata, 0x04));
1212 axgbe_printf(1, " IC_HS_MADDR : %010x\n",
1213 XI2C_IOREAD(pdata, 0x0c));
1214 axgbe_printf(1, " IC_INTR_STAT : %010x\n",
1215 XI2C_IOREAD(pdata, 0x2c));
1216 axgbe_printf(1, " IC_INTR_MASK : %010x\n",
1217 XI2C_IOREAD(pdata, 0x30));
1218 axgbe_printf(1, " IC_RAW_INTR_STAT : %010x\n",
1219 XI2C_IOREAD(pdata, 0x34));
1220 axgbe_printf(1, " IC_RX_TL : %010x\n",
1221 XI2C_IOREAD(pdata, 0x38));
1222 axgbe_printf(1, " IC_TX_TL : %010x\n",
1223 XI2C_IOREAD(pdata, 0x3c));
1224 axgbe_printf(1, " IC_ENABLE : %010x\n",
1225 XI2C_IOREAD(pdata, 0x6c));
1226 axgbe_printf(1, " IC_STATUS : %010x\n",
1227 XI2C_IOREAD(pdata, 0x70));
1228 axgbe_printf(1, " IC_TXFLR : %010x\n",
1229 XI2C_IOREAD(pdata, 0x74));
1230 axgbe_printf(1, " IC_RXFLR : %010x\n",
1231 XI2C_IOREAD(pdata, 0x78));
1232 axgbe_printf(1, " IC_ENABLE_STATUS : %010x\n",
1233 XI2C_IOREAD(pdata, 0x9c));
1234 axgbe_printf(1, " IC_COMP_PARAM1 : %010x\n",
1235 XI2C_IOREAD(pdata, 0xf4));
1239 xgbe_dump_active_vlans(struct xgbe_prv_data *pdata)
1243 for(i=0 ; i<BITS_TO_LONGS(VLAN_NVID); i++) {
1244 if (i && (i%8 == 0))
1245 axgbe_printf(1, "\n");
1246 axgbe_printf(1, "vlans[%d]: 0x%08lx ", i, pdata->active_vlans[i]);
1248 axgbe_printf(1, "\n");
1252 xgbe_default_config(struct xgbe_prv_data *pdata)
1254 pdata->blen = DMA_SBMR_BLEN_64;
1255 pdata->pbl = DMA_PBL_128;
1257 pdata->rd_osr_limit = 8;
1258 pdata->wr_osr_limit = 8;
1259 pdata->tx_sf_mode = MTL_TSF_ENABLE;
1260 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
1261 pdata->tx_osp_mode = DMA_OSP_ENABLE;
1262 pdata->rx_sf_mode = MTL_RSF_DISABLE;
1263 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
1264 pdata->pause_autoneg = 1;
1265 pdata->tx_pause = 1;
1266 pdata->rx_pause = 1;
1267 pdata->phy_speed = SPEED_UNKNOWN;
1268 pdata->power_down = 0;
1269 pdata->enable_rss = 1;
1273 axgbe_setup_sysctl(struct xgbe_prv_data *pdata)
1275 struct sysctl_ctx_list *clist;
1276 struct sysctl_oid *parent;
1277 struct sysctl_oid_list *top;
1279 clist = device_get_sysctl_ctx(pdata->dev);
1280 parent = device_get_sysctl_tree(pdata->dev);
1281 top = SYSCTL_CHILDREN(parent);
1285 axgbe_if_attach_post(if_ctx_t ctx)
1287 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1288 struct xgbe_prv_data *pdata = &sc->pdata;
1289 struct ifnet *ifp = pdata->netdev;
1290 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1291 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1292 if_softc_ctx_t scctx = sc->scctx;
1295 /* Initialize ECC timestamps */
1296 pdata->tx_sec_period = ticks;
1297 pdata->tx_ded_period = ticks;
1298 pdata->rx_sec_period = ticks;
1299 pdata->rx_ded_period = ticks;
1300 pdata->desc_sec_period = ticks;
1301 pdata->desc_ded_period = ticks;
1303 /* Reset the hardware */
1304 ret = hw_if->exit(&sc->pdata);
1306 axgbe_error("%s: exit error %d\n", __func__, ret);
1308 /* Configure the defaults */
1309 xgbe_default_config(pdata);
1311 /* Set default max values if not provided */
1312 if (!pdata->tx_max_fifo_size)
1313 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
1314 if (!pdata->rx_max_fifo_size)
1315 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
1317 DBGPR("%s: tx fifo 0x%x rx fifo 0x%x\n", __func__,
1318 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
1320 /* Set and validate the number of descriptors for a ring */
1321 MPASS(powerof2(XGBE_TX_DESC_CNT));
1322 pdata->tx_desc_count = XGBE_TX_DESC_CNT;
1323 MPASS(powerof2(XGBE_RX_DESC_CNT));
1324 pdata->rx_desc_count = XGBE_RX_DESC_CNT;
1326 /* Adjust the number of queues based on interrupts assigned */
1327 if (pdata->channel_irq_count) {
1328 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
1329 pdata->channel_irq_count);
1330 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
1331 pdata->channel_irq_count);
1333 DBGPR("adjusted TX %u/%u RX %u/%u\n",
1334 pdata->tx_ring_count, pdata->tx_q_count,
1335 pdata->rx_ring_count, pdata->rx_q_count);
1338 /* Set channel count based on interrupts assigned */
1339 pdata->channel_count = max_t(unsigned int, scctx->isc_ntxqsets,
1340 scctx->isc_nrxqsets);
1341 DBGPR("Channel count set to: %u\n", pdata->channel_count);
1345 rss_getkey((uint8_t *)pdata->rss_key);
1347 arc4rand(&pdata->rss_key, ARRAY_SIZE(pdata->rss_key), 0);
1349 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
1350 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
1351 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
1353 /* Initialize the PHY device */
1354 pdata->sysctl_an_cdr_workaround = pdata->vdata->an_cdr_workaround;
1355 phy_if->phy_init(pdata);
1357 /* Set the coalescing */
1358 xgbe_init_rx_coalesce(&sc->pdata);
1359 xgbe_init_tx_coalesce(&sc->pdata);
1361 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL);
1362 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL);
1363 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SFI, 0, NULL);
1364 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL);
1365 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL);
1366 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0, NULL);
1367 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1368 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
1369 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SGMII, 0, NULL);
1370 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1371 ifmedia_add(sc->media, IFM_ETHER | IFM_100_SGMII, 0, NULL);
1372 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1373 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
1375 /* Initialize the phy */
1376 pdata->phy_link = -1;
1377 pdata->phy_speed = SPEED_UNKNOWN;
1378 ret = phy_if->phy_reset(pdata);
1382 /* Calculate the Rx buffer size before allocating rings */
1383 ret = xgbe_calc_rx_buf_size(pdata->netdev, if_getmtu(pdata->netdev));
1384 pdata->rx_buf_size = ret;
1385 DBGPR("%s: rx_buf_size %d\n", __func__, ret);
1387 /* Setup RSS lookup table */
1388 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
1389 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
1390 i % pdata->rx_ring_count);
1393 * Mark the device down until it is initialized, which happens
1394 * when the device is accessed first (for configuring the iface,
1397 set_bit(XGBE_DOWN, &pdata->dev_state);
1399 DBGPR("mtu %d\n", ifp->if_mtu);
1400 scctx->isc_max_frame_size = ifp->if_mtu + 18;
1401 scctx->isc_min_frame_size = XGMAC_MIN_PACKET;
1403 axgbe_setup_sysctl(pdata);
1405 axgbe_sysctl_init(pdata);
1408 } /* axgbe_if_attach_post */
1411 xgbe_free_intr(struct xgbe_prv_data *pdata, struct resource *res, void *tag,
1415 bus_teardown_intr(pdata->dev, res, tag);
1418 bus_release_resource(pdata->dev, SYS_RES_IRQ, rid, res);
1422 axgbe_interrupts_free(if_ctx_t ctx)
1424 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1425 struct xgbe_prv_data *pdata = &sc->pdata;
1426 if_softc_ctx_t scctx = sc->scctx;
1427 struct xgbe_channel *channel;
1431 axgbe_printf(2, "%s: mode %d\n", __func__, scctx->isc_intr);
1434 iflib_irq_free(ctx, &pdata->dev_irq);
1437 xgbe_free_intr(pdata, pdata->ecc_irq_res, pdata->ecc_irq_tag,
1441 xgbe_free_intr(pdata, pdata->i2c_irq_res, pdata->i2c_irq_tag,
1445 xgbe_free_intr(pdata, pdata->an_irq_res, pdata->an_irq_tag,
1448 for (i = 0; i < scctx->isc_nrxqsets; i++) {
1450 channel = pdata->channel[i];
1451 axgbe_printf(2, "%s: rid %d\n", __func__, channel->dma_irq_rid);
1452 irq.ii_res = channel->dma_irq_res;
1453 irq.ii_tag = channel->dma_irq_tag;
1454 iflib_irq_free(ctx, &irq);
1459 axgbe_if_detach(if_ctx_t ctx)
1461 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1462 struct xgbe_prv_data *pdata = &sc->pdata;
1463 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1464 struct resource *mac_res[2];
1466 mac_res[0] = pdata->xgmac_res;
1467 mac_res[1] = pdata->xpcs_res;
1469 phy_if->phy_exit(pdata);
1471 /* Free Interrupts */
1472 axgbe_interrupts_free(ctx);
1474 /* Free workqueues */
1475 taskqueue_free(pdata->dev_workqueue);
1477 /* Release bus resources */
1478 bus_release_resources(iflib_get_dev(ctx), axgbe_pci_mac_spec, mac_res);
1480 /* Free VLAN bitmap */
1481 free(pdata->active_vlans, M_AXGBE);
1483 axgbe_sysctl_exit(pdata);
1486 } /* axgbe_if_detach */
1489 axgbe_pci_init(struct xgbe_prv_data *pdata)
1491 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1492 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1497 ret = phy_if->phy_start(pdata);
1499 axgbe_error("%s: phy start %d\n", __func__, ret);
1500 ret = hw_if->exit(pdata);
1502 axgbe_error("%s: exit error %d\n", __func__, ret);
1506 hw_if->enable_tx(pdata);
1507 hw_if->enable_rx(pdata);
1509 xgbe_start_timers(pdata);
1511 clear_bit(XGBE_DOWN, &pdata->dev_state);
1513 xgbe_dump_phy_registers(pdata);
1514 xgbe_dump_prop_registers(pdata);
1515 xgbe_dump_dma_registers(pdata, -1);
1516 xgbe_dump_mtl_registers(pdata);
1517 xgbe_dump_mac_registers(pdata);
1518 xgbe_dump_rmon_counters(pdata);
1522 axgbe_if_init(if_ctx_t ctx)
1524 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1525 struct xgbe_prv_data *pdata = &sc->pdata;
1527 axgbe_pci_init(pdata);
1531 axgbe_pci_stop(if_ctx_t ctx)
1533 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1534 struct xgbe_prv_data *pdata = &sc->pdata;
1535 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1536 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1539 if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state))) {
1540 axgbe_printf(1, "%s: Stopping when XGBE_DOWN\n", __func__);
1544 xgbe_stop_timers(pdata);
1545 taskqueue_drain_all(pdata->dev_workqueue);
1547 hw_if->disable_tx(pdata);
1548 hw_if->disable_rx(pdata);
1550 phy_if->phy_stop(pdata);
1552 ret = hw_if->exit(pdata);
1554 axgbe_error("%s: exit error %d\n", __func__, ret);
1556 set_bit(XGBE_DOWN, &pdata->dev_state);
1560 axgbe_if_stop(if_ctx_t ctx)
1562 axgbe_pci_stop(ctx);
1566 axgbe_if_disable_intr(if_ctx_t ctx)
1568 /* TODO - implement */
1572 axgbe_if_enable_intr(if_ctx_t ctx)
1574 /* TODO - implement */
1578 axgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int ntxqs,
1581 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1582 struct xgbe_prv_data *pdata = &sc->pdata;
1583 if_softc_ctx_t scctx = sc->scctx;
1584 struct xgbe_channel *channel;
1585 struct xgbe_ring *tx_ring;
1588 MPASS(scctx->isc_ntxqsets > 0);
1589 MPASS(scctx->isc_ntxqsets == ntxqsets);
1592 axgbe_printf(1, "%s: txqsets %d/%d txqs %d\n", __func__,
1593 scctx->isc_ntxqsets, ntxqsets, ntxqs);
1595 for (i = 0 ; i < ntxqsets; i++) {
1597 channel = pdata->channel[i];
1599 tx_ring = (struct xgbe_ring*)malloc(ntxqs *
1600 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1602 if (tx_ring == NULL) {
1603 axgbe_error("Unable to allocate TX ring memory\n");
1607 channel->tx_ring = tx_ring;
1609 for (j = 0; j < ntxqs; j++, tx_ring++) {
1611 (struct xgbe_ring_data*)malloc(scctx->isc_ntxd[j] *
1612 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1614 /* Get the virtual & physical address of hw queues */
1615 tx_ring->rdesc = (struct xgbe_ring_desc *)va[i*ntxqs + j];
1616 tx_ring->rdesc_paddr = pa[i*ntxqs + j];
1617 tx_ring->rdesc_count = scctx->isc_ntxd[j];
1618 spin_lock_init(&tx_ring->lock);
1622 axgbe_printf(1, "allocated for %d tx queues\n", scctx->isc_ntxqsets);
1628 for (j = 0; j < i ; j++) {
1630 channel = pdata->channel[j];
1632 tx_ring = channel->tx_ring;
1633 for (k = 0; k < ntxqs ; k++, tx_ring++) {
1634 if (tx_ring && tx_ring->rdata)
1635 free(tx_ring->rdata, M_AXGBE);
1637 free(channel->tx_ring, M_AXGBE);
1639 channel->tx_ring = NULL;
1644 } /* axgbe_if_tx_queues_alloc */
1647 axgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int nrxqs,
1650 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1651 struct xgbe_prv_data *pdata = &sc->pdata;
1652 if_softc_ctx_t scctx = sc->scctx;
1653 struct xgbe_channel *channel;
1654 struct xgbe_ring *rx_ring;
1657 MPASS(scctx->isc_nrxqsets > 0);
1658 MPASS(scctx->isc_nrxqsets == nrxqsets);
1661 axgbe_printf(1, "%s: rxqsets %d/%d rxqs %d\n", __func__,
1662 scctx->isc_nrxqsets, nrxqsets, nrxqs);
1664 for (i = 0 ; i < nrxqsets; i++) {
1666 channel = pdata->channel[i];
1668 rx_ring = (struct xgbe_ring*)malloc(nrxqs *
1669 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1671 if (rx_ring == NULL) {
1672 axgbe_error("Unable to allocate RX ring memory\n");
1676 channel->rx_ring = rx_ring;
1678 for (j = 0; j < nrxqs; j++, rx_ring++) {
1680 (struct xgbe_ring_data*)malloc(scctx->isc_nrxd[j] *
1681 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1683 /* Get the virtual and physical address of the hw queues */
1684 rx_ring->rdesc = (struct xgbe_ring_desc *)va[i*nrxqs + j];
1685 rx_ring->rdesc_paddr = pa[i*nrxqs + j];
1686 rx_ring->rdesc_count = scctx->isc_nrxd[j];
1687 spin_lock_init(&rx_ring->lock);
1691 axgbe_printf(2, "allocated for %d rx queues\n", scctx->isc_nrxqsets);
1697 for (j = 0 ; j < i ; j++) {
1699 channel = pdata->channel[j];
1701 rx_ring = channel->rx_ring;
1702 for (k = 0; k < nrxqs ; k++, rx_ring++) {
1703 if (rx_ring && rx_ring->rdata)
1704 free(rx_ring->rdata, M_AXGBE);
1706 free(channel->rx_ring, M_AXGBE);
1708 channel->rx_ring = NULL;
1713 } /* axgbe_if_rx_queues_alloc */
1716 axgbe_if_queues_free(if_ctx_t ctx)
1718 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1719 struct xgbe_prv_data *pdata = &sc->pdata;
1720 if_softc_ctx_t scctx = sc->scctx;
1721 if_shared_ctx_t sctx = sc->sctx;
1722 struct xgbe_channel *channel;
1723 struct xgbe_ring *tx_ring;
1724 struct xgbe_ring *rx_ring;
1727 for (i = 0 ; i < scctx->isc_ntxqsets; i++) {
1729 channel = pdata->channel[i];
1731 tx_ring = channel->tx_ring;
1732 for (j = 0; j < sctx->isc_ntxqs ; j++, tx_ring++) {
1733 if (tx_ring && tx_ring->rdata)
1734 free(tx_ring->rdata, M_AXGBE);
1736 free(channel->tx_ring, M_AXGBE);
1737 channel->tx_ring = NULL;
1740 for (i = 0 ; i < scctx->isc_nrxqsets; i++) {
1742 channel = pdata->channel[i];
1744 rx_ring = channel->rx_ring;
1745 for (j = 0; j < sctx->isc_nrxqs ; j++, rx_ring++) {
1746 if (rx_ring && rx_ring->rdata)
1747 free(rx_ring->rdata, M_AXGBE);
1749 free(channel->rx_ring, M_AXGBE);
1750 channel->rx_ring = NULL;
1754 for (i = 0; i < pdata->total_channel_count ; i++) {
1755 free(pdata->channel[i], M_AXGBE);
1756 pdata->channel[i] = NULL;
1759 pdata->total_channel_count = 0;
1760 pdata->channel_count = 0;
1761 } /* axgbe_if_queues_free */
1764 axgbe_if_vlan_register(if_ctx_t ctx, uint16_t vtag)
1766 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1767 struct xgbe_prv_data *pdata = &sc->pdata;
1768 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1770 if (!bit_test(pdata->active_vlans, vtag)) {
1771 axgbe_printf(0, "Registering VLAN %d\n", vtag);
1773 bit_set(pdata->active_vlans, vtag);
1774 hw_if->update_vlan_hash_table(pdata);
1775 pdata->num_active_vlans++;
1777 axgbe_printf(1, "Total active vlans: %d\n",
1778 pdata->num_active_vlans);
1780 axgbe_printf(0, "VLAN %d already registered\n", vtag);
1782 xgbe_dump_active_vlans(pdata);
1786 axgbe_if_vlan_unregister(if_ctx_t ctx, uint16_t vtag)
1788 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1789 struct xgbe_prv_data *pdata = &sc->pdata;
1790 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1792 if (pdata->num_active_vlans == 0) {
1793 axgbe_printf(1, "No active VLANs to unregister\n");
1797 if (bit_test(pdata->active_vlans, vtag)){
1798 axgbe_printf(0, "Un-Registering VLAN %d\n", vtag);
1800 bit_clear(pdata->active_vlans, vtag);
1801 hw_if->update_vlan_hash_table(pdata);
1802 pdata->num_active_vlans--;
1804 axgbe_printf(1, "Total active vlans: %d\n",
1805 pdata->num_active_vlans);
1807 axgbe_printf(0, "VLAN %d already unregistered\n", vtag);
1809 xgbe_dump_active_vlans(pdata);
1812 #if __FreeBSD_version >= 1300000
1814 axgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
1817 case IFLIB_RESTART_VLAN_CONFIG:
1825 axgbe_if_msix_intr_assign(if_ctx_t ctx, int msix)
1827 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1828 struct xgbe_prv_data *pdata = &sc->pdata;
1829 if_softc_ctx_t scctx = sc->scctx;
1830 struct xgbe_channel *channel;
1832 int i, error, rid = 0, flags;
1835 MPASS(scctx->isc_intr != IFLIB_INTR_LEGACY);
1837 pdata->isr_as_tasklet = 1;
1839 if (scctx->isc_intr == IFLIB_INTR_MSI) {
1840 pdata->irq_count = 1;
1841 pdata->channel_irq_count = 1;
1845 axgbe_printf(1, "%s: msix %d txqsets %d rxqsets %d\n", __func__, msix,
1846 scctx->isc_ntxqsets, scctx->isc_nrxqsets);
1850 /* DEV INTR SETUP */
1852 error = iflib_irq_alloc_generic(ctx, &pdata->dev_irq, rid,
1853 IFLIB_INTR_ADMIN, axgbe_dev_isr, sc, 0, "dev_irq");
1855 axgbe_error("Failed to register device interrupt rid %d name %s\n",
1860 /* ECC INTR SETUP */
1862 pdata->ecc_rid = rid;
1863 pdata->ecc_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1865 if (!pdata->ecc_irq_res) {
1866 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1871 error = bus_setup_intr(pdata->dev, pdata->ecc_irq_res, INTR_MPSAFE |
1872 INTR_TYPE_NET, NULL, axgbe_ecc_isr, sc, &pdata->ecc_irq_tag);
1874 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1875 rid, "ecc_irq", error);
1879 /* I2C INTR SETUP */
1881 pdata->i2c_rid = rid;
1882 pdata->i2c_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1884 if (!pdata->i2c_irq_res) {
1885 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1890 error = bus_setup_intr(pdata->dev, pdata->i2c_irq_res, INTR_MPSAFE |
1891 INTR_TYPE_NET, NULL, axgbe_i2c_isr, sc, &pdata->i2c_irq_tag);
1893 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1894 rid, "i2c_irq", error);
1900 pdata->an_rid = rid;
1901 pdata->an_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1903 if (!pdata->an_irq_res) {
1904 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1909 error = bus_setup_intr(pdata->dev, pdata->an_irq_res, INTR_MPSAFE |
1910 INTR_TYPE_NET, NULL, axgbe_an_isr, sc, &pdata->an_irq_tag);
1912 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1913 rid, "an_irq", error);
1917 pdata->per_channel_irq = 1;
1918 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;
1920 for (i = 0; i < scctx->isc_nrxqsets; i++, rid++) {
1922 channel = pdata->channel[i];
1924 snprintf(buf, sizeof(buf), "rxq%d", i);
1925 error = iflib_irq_alloc_generic(ctx, &irq, rid, IFLIB_INTR_RX,
1926 axgbe_msix_que, channel, channel->queue_index, buf);
1929 axgbe_error("Failed to allocated que int %d err: %d\n",
1934 channel->dma_irq_rid = rid;
1935 channel->dma_irq_res = irq.ii_res;
1936 channel->dma_irq_tag = irq.ii_tag;
1937 axgbe_printf(1, "%s: channel count %d idx %d irq %d\n",
1938 __func__, scctx->isc_nrxqsets, i, rid);
1940 pdata->irq_count = msix;
1941 pdata->channel_irq_count = scctx->isc_nrxqsets;
1943 for (i = 0; i < scctx->isc_ntxqsets; i++) {
1945 channel = pdata->channel[i];
1947 snprintf(buf, sizeof(buf), "txq%d", i);
1948 irq.ii_res = channel->dma_irq_res;
1949 iflib_softirq_alloc_generic(ctx, &irq, IFLIB_INTR_TX, channel,
1950 channel->queue_index, buf);
1954 } /* axgbe_if_msix_intr_assign */
1957 xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
1959 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1960 enum xgbe_int int_id;
1962 if (channel->tx_ring && channel->rx_ring)
1963 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
1964 else if (channel->tx_ring)
1965 int_id = XGMAC_INT_DMA_CH_SR_TI;
1966 else if (channel->rx_ring)
1967 int_id = XGMAC_INT_DMA_CH_SR_RI;
1971 axgbe_printf(1, "%s channel: %d rx_tx interrupt enabled %d\n",
1972 __func__, channel->queue_index, int_id);
1973 return (hw_if->enable_int(channel, int_id));
1977 xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
1979 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1980 enum xgbe_int int_id;
1982 if (channel->tx_ring && channel->rx_ring)
1983 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
1984 else if (channel->tx_ring)
1985 int_id = XGMAC_INT_DMA_CH_SR_TI;
1986 else if (channel->rx_ring)
1987 int_id = XGMAC_INT_DMA_CH_SR_RI;
1991 axgbe_printf(1, "%s channel: %d rx_tx interrupt disabled %d\n",
1992 __func__, channel->queue_index, int_id);
1993 hw_if->disable_int(channel, int_id);
1997 xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
2001 for (i = 0; i < pdata->channel_count; i++)
2002 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
2006 axgbe_msix_que(void *arg)
2008 struct xgbe_channel *channel = (struct xgbe_channel *)arg;
2009 struct xgbe_prv_data *pdata = channel->pdata;
2010 unsigned int dma_ch_isr, dma_status;
2012 axgbe_printf(1, "%s: Channel: %d SR 0x%04x DSR 0x%04x IER:0x%04x D_ISR:0x%04x M_ISR:0x%04x\n",
2013 __func__, channel->queue_index,
2014 XGMAC_DMA_IOREAD(channel, DMA_CH_SR),
2015 XGMAC_DMA_IOREAD(channel, DMA_CH_DSR),
2016 XGMAC_DMA_IOREAD(channel, DMA_CH_IER),
2017 XGMAC_IOREAD(pdata, DMA_ISR),
2018 XGMAC_IOREAD(pdata, MAC_ISR));
2020 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2022 /* Disable Tx and Rx channel interrupts */
2023 xgbe_disable_rx_tx_int(pdata, channel);
2025 /* Clear the interrupts */
2027 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
2028 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
2029 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
2031 return (FILTER_SCHEDULE_THREAD);
2035 axgbe_dev_isr(void *arg)
2037 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2038 struct xgbe_prv_data *pdata = &sc->pdata;
2039 struct xgbe_channel *channel;
2040 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2041 unsigned int i, dma_isr, dma_ch_isr;
2042 unsigned int mac_isr, mac_mdioisr;
2043 int ret = FILTER_HANDLED;
2045 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
2046 axgbe_printf(2, "%s DMA ISR: 0x%x\n", __func__, dma_isr);
2049 return (FILTER_HANDLED);
2051 for (i = 0; i < pdata->channel_count; i++) {
2053 if (!(dma_isr & (1 << i)))
2056 channel = pdata->channel[i];
2058 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2059 axgbe_printf(2, "%s: channel %d SR 0x%x DSR 0x%x\n", __func__,
2060 channel->queue_index, dma_ch_isr, XGMAC_DMA_IOREAD(channel,
2064 * The TI or RI interrupt bits may still be set even if using
2065 * per channel DMA interrupts. Check to be sure those are not
2066 * enabled before using the private data napi structure.
2068 if (!pdata->per_channel_irq &&
2069 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
2070 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
2072 /* Disable Tx and Rx interrupts */
2073 xgbe_disable_rx_tx_ints(pdata);
2077 * Don't clear Rx/Tx status if doing per channel DMA
2078 * interrupts, these will be cleared by the ISR for
2079 * per channel DMA interrupts
2081 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
2082 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
2085 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
2086 pdata->ext_stats.rx_buffer_unavailable++;
2088 /* Restart the device on a Fatal Bus Error */
2089 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
2090 axgbe_error("%s: Fatal bus error reported 0x%x\n",
2091 __func__, dma_ch_isr);
2093 /* Clear all interrupt signals */
2094 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
2096 ret = FILTER_SCHEDULE_THREAD;
2099 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
2101 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
2102 axgbe_printf(2, "%s MAC ISR: 0x%x\n", __func__, mac_isr);
2104 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
2105 hw_if->tx_mmc_int(pdata);
2107 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
2108 hw_if->rx_mmc_int(pdata);
2110 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
2111 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
2113 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
2121 } /* axgbe_dev_isr */
2124 axgbe_i2c_isr(void *arg)
2126 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2128 sc->pdata.i2c_if.i2c_isr(&sc->pdata);
2132 axgbe_ecc_isr(void *arg)
2134 /* TODO - implement */
2138 axgbe_an_isr(void *arg)
2140 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2142 sc->pdata.phy_if.an_isr(&sc->pdata);
2146 axgbe_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2148 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2149 struct xgbe_prv_data *pdata = &sc->pdata;
2152 if (qid < pdata->tx_q_count) {
2153 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2155 axgbe_error("Enable TX INT failed\n");
2159 axgbe_error("Queue ID exceed channel count\n");
2165 axgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2167 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2168 struct xgbe_prv_data *pdata = &sc->pdata;
2171 if (qid < pdata->rx_q_count) {
2172 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2174 axgbe_error("Enable RX INT failed\n");
2178 axgbe_error("Queue ID exceed channel count\n");
2184 axgbe_if_update_admin_status(if_ctx_t ctx)
2186 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2187 struct xgbe_prv_data *pdata = &sc->pdata;
2189 axgbe_printf(1, "%s: phy_link %d status %d speed %d\n", __func__,
2190 pdata->phy_link, sc->link_status, pdata->phy.speed);
2192 if (pdata->phy_link < 0)
2195 if (pdata->phy_link) {
2196 if (sc->link_status == LINK_STATE_DOWN) {
2197 sc->link_status = LINK_STATE_UP;
2198 if (pdata->phy.speed & SPEED_10000)
2199 iflib_link_state_change(ctx, LINK_STATE_UP,
2201 else if (pdata->phy.speed & SPEED_2500)
2202 iflib_link_state_change(ctx, LINK_STATE_UP,
2204 else if (pdata->phy.speed & SPEED_1000)
2205 iflib_link_state_change(ctx, LINK_STATE_UP,
2207 else if (pdata->phy.speed & SPEED_100)
2208 iflib_link_state_change(ctx, LINK_STATE_UP,
2210 else if (pdata->phy.speed & SPEED_10)
2211 iflib_link_state_change(ctx, LINK_STATE_UP,
2215 if (sc->link_status == LINK_STATE_UP) {
2216 sc->link_status = LINK_STATE_DOWN;
2217 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
2223 axgbe_if_media_change(if_ctx_t ctx)
2225 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2226 struct ifmedia *ifm = iflib_get_media(ctx);
2228 sx_xlock(&sc->pdata.an_mutex);
2229 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2232 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2234 sc->pdata.phy.speed = SPEED_10000;
2235 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2238 sc->pdata.phy.speed = SPEED_2500;
2239 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2242 sc->pdata.phy.speed = SPEED_1000;
2243 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2246 sc->pdata.phy.speed = SPEED_100;
2247 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2250 sc->pdata.phy.autoneg = AUTONEG_ENABLE;
2253 sx_xunlock(&sc->pdata.an_mutex);
2255 return (-sc->pdata.phy_if.phy_config_aneg(&sc->pdata));
2259 axgbe_if_promisc_set(if_ctx_t ctx, int flags)
2261 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2263 if (XGMAC_IOREAD_BITS(&sc->pdata, MAC_PFR, PR) == 1)
2266 XGMAC_IOWRITE_BITS(&sc->pdata, MAC_PFR, PR, 1);
2267 XGMAC_IOWRITE_BITS(&sc->pdata, MAC_PFR, VTFE, 0);
2273 axgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt)
2275 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2276 struct ifnet *ifp = iflib_get_ifp(ctx);
2277 struct xgbe_prv_data *pdata = &sc->pdata;
2278 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2280 pdata->hw_if.read_mmc_stats(pdata);
2283 case IFCOUNTER_IPACKETS:
2284 return (pstats->rxframecount_gb);
2285 case IFCOUNTER_IERRORS:
2286 return (pstats->rxframecount_gb - pstats->rxbroadcastframes_g -
2287 pstats->rxmulticastframes_g - pstats->rxunicastframes_g);
2288 case IFCOUNTER_OPACKETS:
2289 return (pstats->txframecount_gb);
2290 case IFCOUNTER_OERRORS:
2291 return (pstats->txframecount_gb - pstats->txframecount_g);
2292 case IFCOUNTER_IBYTES:
2293 return (pstats->rxoctetcount_gb);
2294 case IFCOUNTER_OBYTES:
2295 return (pstats->txoctetcount_gb);
2297 return (if_get_counter_default(ifp, cnt));
2302 axgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
2304 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2305 struct xgbe_prv_data *pdata = &sc->pdata;
2308 if (mtu > XGMAC_JUMBO_PACKET_MTU)
2311 ret = xgbe_calc_rx_buf_size(pdata->netdev, mtu);
2312 pdata->rx_buf_size = ret;
2313 axgbe_printf(1, "%s: rx_buf_size %d\n", __func__, ret);
2315 sc->scctx->isc_max_frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2320 axgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr)
2322 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2323 struct xgbe_prv_data *pdata = &sc->pdata;
2325 ifmr->ifm_status = IFM_AVALID;
2326 if (!sc->pdata.phy.link)
2329 ifmr->ifm_active = IFM_ETHER;
2330 ifmr->ifm_status |= IFM_ACTIVE;
2332 axgbe_printf(1, "Speed 0x%x Mode %d\n", sc->pdata.phy.speed,
2333 pdata->phy_if.phy_impl.cur_mode(pdata));
2334 pdata->phy_if.phy_impl.get_type(pdata, ifmr);
2336 ifmr->ifm_active |= IFM_FDX;
2337 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2338 ifmr->ifm_active |= IFM_ETH_RXPAUSE;