2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2020 Advanced Micro Devices, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * Contact Information :
28 * Rajesh Kumar <rajesh1.kumar@amd.com>
29 * Shreyank Amartya <Shreyank.Amartya@amd.com>
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/module.h>
40 #include <sys/mutex.h>
42 #include <sys/socket.h>
43 #include <sys/sysctl.h>
44 #include <sys/systm.h>
47 #include <net/if_media.h>
49 #include <dev/mii/mii.h>
50 #include <dev/mii/miivar.h>
52 #include <dev/pci/pcireg.h>
53 #include <dev/pci/pcivar.h>
56 #include "xgbe-common.h"
58 #include "miibus_if.h"
61 #include "opt_inet6.h"
63 MALLOC_DEFINE(M_AXGBE, "axgbe", "axgbe data");
65 extern struct if_txrx axgbe_txrx;
66 static int axgbe_sph_enable;
68 /* Function prototypes */
69 static void *axgbe_register(device_t);
70 static int axgbe_if_attach_pre(if_ctx_t);
71 static int axgbe_if_attach_post(if_ctx_t);
72 static int axgbe_if_detach(if_ctx_t);
73 static void axgbe_if_stop(if_ctx_t);
74 static void axgbe_if_init(if_ctx_t);
76 /* Queue related routines */
77 static int axgbe_if_tx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
78 static int axgbe_if_rx_queues_alloc(if_ctx_t, caddr_t *, uint64_t *, int, int);
79 static int axgbe_alloc_channels(if_ctx_t);
80 static void axgbe_free_channels(struct axgbe_if_softc *);
81 static void axgbe_if_queues_free(if_ctx_t);
82 static int axgbe_if_tx_queue_intr_enable(if_ctx_t, uint16_t);
83 static int axgbe_if_rx_queue_intr_enable(if_ctx_t, uint16_t);
85 /* Interrupt related routines */
86 static void axgbe_if_disable_intr(if_ctx_t);
87 static void axgbe_if_enable_intr(if_ctx_t);
88 static int axgbe_if_msix_intr_assign(if_ctx_t, int);
89 static void xgbe_free_intr(struct xgbe_prv_data *, struct resource *, void *, int);
91 /* Init and Iflib routines */
92 static void axgbe_pci_init(struct xgbe_prv_data *);
93 static void axgbe_pci_stop(if_ctx_t);
94 static void xgbe_disable_rx_tx_int(struct xgbe_prv_data *, struct xgbe_channel *);
95 static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *);
96 static int axgbe_if_mtu_set(if_ctx_t, uint32_t);
97 static void axgbe_if_update_admin_status(if_ctx_t);
98 static void axgbe_if_media_status(if_ctx_t, struct ifmediareq *);
99 static int axgbe_if_media_change(if_ctx_t);
100 static int axgbe_if_promisc_set(if_ctx_t, int);
101 static uint64_t axgbe_if_get_counter(if_ctx_t, ift_counter);
102 static void axgbe_if_vlan_register(if_ctx_t, uint16_t);
103 static void axgbe_if_vlan_unregister(if_ctx_t, uint16_t);
104 #if __FreeBSD_version >= 1300000
105 static bool axgbe_if_needs_restart(if_ctx_t, enum iflib_restart_event);
107 static void axgbe_set_counts(if_ctx_t);
108 static void axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *);
110 /* MII interface registered functions */
111 static int axgbe_miibus_readreg(device_t, int, int);
112 static int axgbe_miibus_writereg(device_t, int, int, int);
113 static void axgbe_miibus_statchg(device_t);
116 static int axgbe_dev_isr(void *);
117 static void axgbe_ecc_isr(void *);
118 static void axgbe_i2c_isr(void *);
119 static void axgbe_an_isr(void *);
120 static int axgbe_msix_que(void *);
123 static void xgbe_service(void *, int);
124 static void xgbe_service_timer(void *);
125 static void xgbe_init_timers(struct xgbe_prv_data *);
126 static void xgbe_stop_timers(struct xgbe_prv_data *);
129 static void xgbe_dump_prop_registers(struct xgbe_prv_data *);
132 * Allocate only for MAC (BAR0) and PCS (BAR1) registers, and just point the
133 * MSI-X table bar (BAR5) to iflib. iflib will do the allocation for MSI-X
136 static struct resource_spec axgbe_pci_mac_spec[] = {
137 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* MAC regs */
138 { SYS_RES_MEMORY, PCIR_BAR(1), RF_ACTIVE }, /* PCS regs */
142 static pci_vendor_info_t axgbe_vendor_info_array[] =
144 PVID(0x1022, 0x1458, "AMD 10 Gigabit Ethernet Driver"),
145 PVID(0x1022, 0x1459, "AMD 10 Gigabit Ethernet Driver"),
149 static struct xgbe_version_data xgbe_v2a = {
150 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
151 .xpcs_access = XGBE_XPCS_ACCESS_V2,
153 .tx_max_fifo_size = 229376,
154 .rx_max_fifo_size = 229376,
155 .tx_tstamp_workaround = 1,
158 .irq_reissue_support = 1,
159 .tx_desc_prefetch = 5,
160 .rx_desc_prefetch = 5,
161 .an_cdr_workaround = 1,
164 static struct xgbe_version_data xgbe_v2b = {
165 .init_function_ptrs_phy_impl = xgbe_init_function_ptrs_phy_v2,
166 .xpcs_access = XGBE_XPCS_ACCESS_V2,
168 .tx_max_fifo_size = 65536,
169 .rx_max_fifo_size = 65536,
170 .tx_tstamp_workaround = 1,
173 .irq_reissue_support = 1,
174 .tx_desc_prefetch = 5,
175 .rx_desc_prefetch = 5,
176 .an_cdr_workaround = 1,
179 /* Device Interface */
180 static device_method_t ax_methods[] = {
181 DEVMETHOD(device_register, axgbe_register),
182 DEVMETHOD(device_probe, iflib_device_probe),
183 DEVMETHOD(device_attach, iflib_device_attach),
184 DEVMETHOD(device_detach, iflib_device_detach),
187 DEVMETHOD(miibus_readreg, axgbe_miibus_readreg),
188 DEVMETHOD(miibus_writereg, axgbe_miibus_writereg),
189 DEVMETHOD(miibus_statchg, axgbe_miibus_statchg),
194 static driver_t ax_driver = {
195 "ax", ax_methods, sizeof(struct axgbe_if_softc),
198 devclass_t ax_devclass;
199 DRIVER_MODULE(axp, pci, ax_driver, ax_devclass, 0, 0);
200 DRIVER_MODULE(miibus, ax, miibus_driver, 0, 0);
201 IFLIB_PNP_INFO(pci, ax_driver, axgbe_vendor_info_array);
203 MODULE_DEPEND(ax, pci, 1, 1, 1);
204 MODULE_DEPEND(ax, ether, 1, 1, 1);
205 MODULE_DEPEND(ax, iflib, 1, 1, 1);
206 MODULE_DEPEND(ax, miibus, 1, 1, 1);
208 /* Iflib Interface */
209 static device_method_t axgbe_if_methods[] = {
210 DEVMETHOD(ifdi_attach_pre, axgbe_if_attach_pre),
211 DEVMETHOD(ifdi_attach_post, axgbe_if_attach_post),
212 DEVMETHOD(ifdi_detach, axgbe_if_detach),
213 DEVMETHOD(ifdi_init, axgbe_if_init),
214 DEVMETHOD(ifdi_stop, axgbe_if_stop),
215 DEVMETHOD(ifdi_msix_intr_assign, axgbe_if_msix_intr_assign),
216 DEVMETHOD(ifdi_intr_enable, axgbe_if_enable_intr),
217 DEVMETHOD(ifdi_intr_disable, axgbe_if_disable_intr),
218 DEVMETHOD(ifdi_tx_queue_intr_enable, axgbe_if_tx_queue_intr_enable),
219 DEVMETHOD(ifdi_rx_queue_intr_enable, axgbe_if_rx_queue_intr_enable),
220 DEVMETHOD(ifdi_tx_queues_alloc, axgbe_if_tx_queues_alloc),
221 DEVMETHOD(ifdi_rx_queues_alloc, axgbe_if_rx_queues_alloc),
222 DEVMETHOD(ifdi_queues_free, axgbe_if_queues_free),
223 DEVMETHOD(ifdi_update_admin_status, axgbe_if_update_admin_status),
224 DEVMETHOD(ifdi_mtu_set, axgbe_if_mtu_set),
225 DEVMETHOD(ifdi_media_status, axgbe_if_media_status),
226 DEVMETHOD(ifdi_media_change, axgbe_if_media_change),
227 DEVMETHOD(ifdi_promisc_set, axgbe_if_promisc_set),
228 DEVMETHOD(ifdi_get_counter, axgbe_if_get_counter),
229 DEVMETHOD(ifdi_vlan_register, axgbe_if_vlan_register),
230 DEVMETHOD(ifdi_vlan_unregister, axgbe_if_vlan_unregister),
231 #if __FreeBSD_version >= 1300000
232 DEVMETHOD(ifdi_needs_restart, axgbe_if_needs_restart),
237 static driver_t axgbe_if_driver = {
238 "axgbe_if", axgbe_if_methods, sizeof(struct axgbe_if_softc)
241 /* Iflib Shared Context */
242 static struct if_shared_ctx axgbe_sctx_init = {
243 .isc_magic = IFLIB_MAGIC,
244 .isc_driver = &axgbe_if_driver,
245 .isc_q_align = PAGE_SIZE,
246 .isc_tx_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
247 .isc_tx_maxsegsize = PAGE_SIZE,
248 .isc_tso_maxsize = XGBE_TSO_MAX_SIZE + sizeof(struct ether_vlan_header),
249 .isc_tso_maxsegsize = PAGE_SIZE,
250 .isc_rx_maxsize = MJUM9BYTES,
251 .isc_rx_maxsegsize = MJUM9BYTES,
252 .isc_rx_nsegments = 1,
253 .isc_admin_intrcnt = 4,
255 .isc_vendor_info = axgbe_vendor_info_array,
256 .isc_driver_version = XGBE_DRV_VERSION,
258 .isc_ntxd_min = {XGBE_TX_DESC_CNT_MIN},
259 .isc_ntxd_default = {XGBE_TX_DESC_CNT_DEFAULT},
260 .isc_ntxd_max = {XGBE_TX_DESC_CNT_MAX},
263 .isc_flags = IFLIB_TSO_INIT_IP | IFLIB_NEED_SCRATCH |
264 IFLIB_NEED_ZERO_CSUM | IFLIB_NEED_ETHER_PAD,
268 axgbe_register(device_t dev)
275 value = kern_getenv("dev.ax.sph_enable");
277 axgbe_sph_enable = strtol(value, NULL, 10);
281 * No tunable found, generate one with default values
282 * Note: only a reboot will reveal the new kenv
284 error = kern_setenv("dev.ax.sph_enable", "1");
286 printf("Error setting tunable, using default driver values\n");
288 axgbe_sph_enable = 1;
291 if (!axgbe_sph_enable) {
299 axgbe_sctx_init.isc_nfl = axgbe_nfl;
300 axgbe_sctx_init.isc_nrxqs = axgbe_nrxqs;
302 for (i = 0 ; i < axgbe_nrxqs ; i++) {
303 axgbe_sctx_init.isc_nrxd_min[i] = XGBE_RX_DESC_CNT_MIN;
304 axgbe_sctx_init.isc_nrxd_default[i] = XGBE_RX_DESC_CNT_DEFAULT;
305 axgbe_sctx_init.isc_nrxd_max[i] = XGBE_RX_DESC_CNT_MAX;
308 return (&axgbe_sctx_init);
311 /* MII Interface Functions */
313 axgbe_miibus_readreg(device_t dev, int phy, int reg)
315 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
316 struct xgbe_prv_data *pdata = &sc->pdata;
319 axgbe_printf(3, "%s: phy %d reg %d\n", __func__, phy, reg);
321 val = xgbe_phy_mii_read(pdata, phy, reg);
323 axgbe_printf(2, "%s: val 0x%x\n", __func__, val);
324 return (val & 0xFFFF);
328 axgbe_miibus_writereg(device_t dev, int phy, int reg, int val)
330 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
331 struct xgbe_prv_data *pdata = &sc->pdata;
333 axgbe_printf(3, "%s: phy %d reg %d val 0x%x\n", __func__, phy, reg, val);
335 xgbe_phy_mii_write(pdata, phy, reg, val);
341 axgbe_miibus_statchg(device_t dev)
343 struct axgbe_if_softc *sc = iflib_get_softc(device_get_softc(dev));
344 struct xgbe_prv_data *pdata = &sc->pdata;
345 struct mii_data *mii = device_get_softc(pdata->axgbe_miibus);
346 struct ifnet *ifp = pdata->netdev;
349 axgbe_printf(2, "%s: Link %d/%d\n", __func__, pdata->phy.link,
352 if (mii == NULL || ifp == NULL ||
353 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
356 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
357 (IFM_ACTIVE | IFM_AVALID)) {
359 switch (IFM_SUBTYPE(mii->mii_media_active)) {
376 bmsr = axgbe_miibus_readreg(pdata->dev, pdata->mdio_addr, MII_BMSR);
377 if (bmsr & BMSR_ANEG) {
379 axgbe_printf(2, "%s: Autoneg Done\n", __func__);
381 /* Raise AN Interrupt */
382 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK,
383 XGBE_AN_CL73_INT_MASK);
388 axgbe_if_attach_pre(if_ctx_t ctx)
390 struct axgbe_if_softc *sc;
391 struct xgbe_prv_data *pdata;
392 struct resource *mac_res[2];
393 if_softc_ctx_t scctx;
394 if_shared_ctx_t sctx;
396 unsigned int ma_lo, ma_hi;
400 sc = iflib_get_softc(ctx);
401 sc->pdata.dev = dev = iflib_get_dev(ctx);
402 sc->sctx = sctx = iflib_get_sctx(ctx);
403 sc->scctx = scctx = iflib_get_softc_ctx(ctx);
404 sc->media = iflib_get_media(ctx);
406 sc->link_status = LINK_STATE_DOWN;
408 pdata->netdev = iflib_get_ifp(ctx);
410 spin_lock_init(&pdata->xpcs_lock);
412 /* Initialize locks */
413 mtx_init(&pdata->rss_mutex, "xgbe rss mutex lock", NULL, MTX_DEF);
414 mtx_init(&pdata->mdio_mutex, "xgbe MDIO mutex lock", NULL, MTX_SPIN);
416 /* Allocate VLAN bitmap */
417 pdata->active_vlans = bit_alloc(VLAN_NVID, M_AXGBE, M_WAITOK|M_ZERO);
418 pdata->num_active_vlans = 0;
420 /* Get the version data */
421 DBGPR("%s: Device ID: 0x%x\n", __func__, pci_get_device(dev));
422 if (pci_get_device(dev) == 0x1458)
423 sc->pdata.vdata = &xgbe_v2a;
424 else if (pci_get_device(dev) == 0x1459)
425 sc->pdata.vdata = &xgbe_v2b;
428 if (bus_alloc_resources(dev, axgbe_pci_mac_spec, mac_res)) {
429 axgbe_error("Unable to allocate bus resources\n");
434 sc->pdata.xgmac_res = mac_res[0];
435 sc->pdata.xpcs_res = mac_res[1];
437 /* Set the PCS indirect addressing definition registers*/
438 pdata->xpcs_window_def_reg = PCS_V2_WINDOW_DEF;
439 pdata->xpcs_window_sel_reg = PCS_V2_WINDOW_SELECT;
441 /* Configure the PCS indirect addressing support */
442 reg = XPCS32_IOREAD(pdata, pdata->xpcs_window_def_reg);
443 pdata->xpcs_window = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, OFFSET);
444 pdata->xpcs_window <<= 6;
445 pdata->xpcs_window_size = XPCS_GET_BITS(reg, PCS_V2_WINDOW_DEF, SIZE);
446 pdata->xpcs_window_size = 1 << (pdata->xpcs_window_size + 7);
447 pdata->xpcs_window_mask = pdata->xpcs_window_size - 1;
448 DBGPR("xpcs window def : %#010x\n",
449 pdata->xpcs_window_def_reg);
450 DBGPR("xpcs window sel : %#010x\n",
451 pdata->xpcs_window_sel_reg);
452 DBGPR("xpcs window : %#010x\n",
454 DBGPR("xpcs window size : %#010x\n",
455 pdata->xpcs_window_size);
456 DBGPR("xpcs window mask : %#010x\n",
457 pdata->xpcs_window_mask);
459 /* Enable all interrupts in the hardware */
460 XP_IOWRITE(pdata, XP_INT_EN, 0x1fffff);
462 /* Retrieve the MAC address */
463 ma_lo = XP_IOREAD(pdata, XP_MAC_ADDR_LO);
464 ma_hi = XP_IOREAD(pdata, XP_MAC_ADDR_HI);
465 pdata->mac_addr[0] = ma_lo & 0xff;
466 pdata->mac_addr[1] = (ma_lo >> 8) & 0xff;
467 pdata->mac_addr[2] = (ma_lo >>16) & 0xff;
468 pdata->mac_addr[3] = (ma_lo >> 24) & 0xff;
469 pdata->mac_addr[4] = ma_hi & 0xff;
470 pdata->mac_addr[5] = (ma_hi >> 8) & 0xff;
471 if (!XP_GET_BITS(ma_hi, XP_MAC_ADDR_HI, VALID)) {
472 axgbe_error("Invalid mac address\n");
474 goto release_bus_resource;
476 iflib_set_mac(ctx, pdata->mac_addr);
479 pdata->sysclk_rate = XGBE_V2_DMA_CLOCK_FREQ;
480 pdata->ptpclk_rate = XGBE_V2_PTP_CLOCK_FREQ;
482 /* Set the DMA coherency values */
484 pdata->arcr = XGBE_DMA_PCI_ARCR;
485 pdata->awcr = XGBE_DMA_PCI_AWCR;
486 pdata->awarcr = XGBE_DMA_PCI_AWARCR;
488 /* Read the port property registers */
489 pdata->pp0 = XP_IOREAD(pdata, XP_PROP_0);
490 pdata->pp1 = XP_IOREAD(pdata, XP_PROP_1);
491 pdata->pp2 = XP_IOREAD(pdata, XP_PROP_2);
492 pdata->pp3 = XP_IOREAD(pdata, XP_PROP_3);
493 pdata->pp4 = XP_IOREAD(pdata, XP_PROP_4);
494 DBGPR("port property 0 = %#010x\n", pdata->pp0);
495 DBGPR("port property 1 = %#010x\n", pdata->pp1);
496 DBGPR("port property 2 = %#010x\n", pdata->pp2);
497 DBGPR("port property 3 = %#010x\n", pdata->pp3);
498 DBGPR("port property 4 = %#010x\n", pdata->pp4);
500 /* Set the maximum channels and queues */
501 pdata->tx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
503 pdata->rx_max_channel_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
505 pdata->tx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
507 pdata->rx_max_q_count = XP_GET_BITS(pdata->pp1, XP_PROP_1,
509 DBGPR("max tx/rx channel count = %u/%u\n",
510 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
511 DBGPR("max tx/rx hw queue count = %u/%u\n",
512 pdata->tx_max_q_count, pdata->rx_max_q_count);
514 axgbe_set_counts(ctx);
516 /* Set the maximum fifo amounts */
517 pdata->tx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
519 pdata->tx_max_fifo_size *= 16384;
520 pdata->tx_max_fifo_size = min(pdata->tx_max_fifo_size,
521 pdata->vdata->tx_max_fifo_size);
522 pdata->rx_max_fifo_size = XP_GET_BITS(pdata->pp2, XP_PROP_2,
524 pdata->rx_max_fifo_size *= 16384;
525 pdata->rx_max_fifo_size = min(pdata->rx_max_fifo_size,
526 pdata->vdata->rx_max_fifo_size);
527 DBGPR("max tx/rx max fifo size = %u/%u\n",
528 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
530 /* Initialize IFLIB if_softc_ctx_t */
531 axgbe_init_iflib_softc_ctx(sc);
534 if (axgbe_alloc_channels(ctx)) {
535 axgbe_error("Unable to allocate channel memory\n");
537 goto release_bus_resource;
540 TASK_INIT(&pdata->service_work, 0, xgbe_service, pdata);
542 /* create the workqueue */
543 pdata->dev_workqueue = taskqueue_create("axgbe", M_WAITOK,
544 taskqueue_thread_enqueue, &pdata->dev_workqueue);
545 if (pdata->dev_workqueue == NULL) {
546 axgbe_error("Unable to allocate workqueue\n");
550 ret = taskqueue_start_threads(&pdata->dev_workqueue, 1, PI_NET,
553 axgbe_error("Unable to start taskqueue\n");
555 goto free_task_queue;
559 xgbe_init_timers(pdata);
564 taskqueue_free(pdata->dev_workqueue);
567 axgbe_free_channels(sc);
569 release_bus_resource:
570 bus_release_resources(dev, axgbe_pci_mac_spec, mac_res);
573 free(pdata->active_vlans, M_AXGBE);
576 } /* axgbe_if_attach_pre */
579 xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
581 xgbe_init_function_ptrs_dev(&pdata->hw_if);
582 xgbe_init_function_ptrs_phy(&pdata->phy_if);
583 xgbe_init_function_ptrs_i2c(&pdata->i2c_if);
584 xgbe_init_function_ptrs_desc(&pdata->desc_if);
586 pdata->vdata->init_function_ptrs_phy_impl(&pdata->phy_if);
590 axgbe_set_counts(if_ctx_t ctx)
592 struct axgbe_if_softc *sc = iflib_get_softc(ctx);;
593 struct xgbe_prv_data *pdata = &sc->pdata;
598 /* Set all function pointers */
599 xgbe_init_all_fptrs(pdata);
601 /* Populate the hardware features */
602 xgbe_get_all_hw_features(pdata);
604 if (!pdata->tx_max_channel_count)
605 pdata->tx_max_channel_count = pdata->hw_feat.tx_ch_cnt;
606 if (!pdata->rx_max_channel_count)
607 pdata->rx_max_channel_count = pdata->hw_feat.rx_ch_cnt;
609 if (!pdata->tx_max_q_count)
610 pdata->tx_max_q_count = pdata->hw_feat.tx_q_cnt;
611 if (!pdata->rx_max_q_count)
612 pdata->rx_max_q_count = pdata->hw_feat.rx_q_cnt;
615 * Calculate the number of Tx and Rx rings to be created
616 * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
617 * the number of Tx queues to the number of Tx channels
619 * -Rx (DMA) Channels do not map 1-to-1 so use the actual
620 * number of Rx queues or maximum allowed
623 /* Get cpu count from sysctl */
624 len = sizeof(cpu_count);
625 err = kernel_sysctlbyname(curthread, "hw.ncpu", &cpu_count, &len, NULL,
628 axgbe_error("Unable to fetch number of cpus\n");
632 if (bus_get_cpus(pdata->dev, INTR_CPUS, sizeof(lcpus), &lcpus) != 0) {
633 axgbe_error("Unable to fetch CPU list\n");
634 /* TODO - handle CPU_COPY(&all_cpus, &lcpus); */
637 DBGPR("ncpu %d intrcpu %d\n", cpu_count, CPU_COUNT(&lcpus));
639 pdata->tx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.tx_ch_cnt);
640 pdata->tx_ring_count = min(pdata->tx_ring_count,
641 pdata->tx_max_channel_count);
642 pdata->tx_ring_count = min(pdata->tx_ring_count, pdata->tx_max_q_count);
644 pdata->tx_q_count = pdata->tx_ring_count;
646 pdata->rx_ring_count = min(CPU_COUNT(&lcpus), pdata->hw_feat.rx_ch_cnt);
647 pdata->rx_ring_count = min(pdata->rx_ring_count,
648 pdata->rx_max_channel_count);
650 pdata->rx_q_count = min(pdata->hw_feat.rx_q_cnt, pdata->rx_max_q_count);
652 DBGPR("TX/RX max channel count = %u/%u\n",
653 pdata->tx_max_channel_count, pdata->rx_max_channel_count);
654 DBGPR("TX/RX max queue count = %u/%u\n",
655 pdata->tx_max_q_count, pdata->rx_max_q_count);
656 DBGPR("TX/RX DMA ring count = %u/%u\n",
657 pdata->tx_ring_count, pdata->rx_ring_count);
658 DBGPR("TX/RX hardware queue count = %u/%u\n",
659 pdata->tx_q_count, pdata->rx_q_count);
660 } /* axgbe_set_counts */
663 axgbe_init_iflib_softc_ctx(struct axgbe_if_softc *sc)
665 struct xgbe_prv_data *pdata = &sc->pdata;
666 if_softc_ctx_t scctx = sc->scctx;
667 if_shared_ctx_t sctx = sc->sctx;
670 scctx->isc_nrxqsets = pdata->rx_q_count;
671 scctx->isc_ntxqsets = pdata->tx_q_count;
672 scctx->isc_msix_bar = pci_msix_table_bar(pdata->dev);
673 scctx->isc_tx_nsegments = 32;
675 for (i = 0; i < sctx->isc_ntxqs; i++) {
676 scctx->isc_txqsizes[i] =
677 roundup2(scctx->isc_ntxd[i] * sizeof(struct xgbe_ring_desc),
679 scctx->isc_txd_size[i] = sizeof(struct xgbe_ring_desc);
682 for (i = 0; i < sctx->isc_nrxqs; i++) {
683 scctx->isc_rxqsizes[i] =
684 roundup2(scctx->isc_nrxd[i] * sizeof(struct xgbe_ring_desc),
686 scctx->isc_rxd_size[i] = sizeof(struct xgbe_ring_desc);
689 scctx->isc_tx_tso_segments_max = 32;
690 scctx->isc_tx_tso_size_max = XGBE_TSO_MAX_SIZE;
691 scctx->isc_tx_tso_segsize_max = PAGE_SIZE;
695 * 1) IFLIB automatically adds IFCAP_HWSTATS, so need to set explicitly
696 * 2) isc_tx_csum_flags is mandatory if IFCAP_TXCSUM (included in
697 * IFCAP_HWCSUM) is set
699 scctx->isc_tx_csum_flags = (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_SCTP |
700 CSUM_TCP_IPV6 | CSUM_UDP_IPV6 | CSUM_SCTP_IPV6 |
702 scctx->isc_capenable = (IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
704 IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWFILTER |
706 IFCAP_TSO | IFCAP_VLAN_HWTSO);
707 scctx->isc_capabilities = scctx->isc_capenable;
710 * Set rss_table_size alone when adding RSS support. rss_table_mask
711 * will be set by IFLIB based on rss_table_size
713 scctx->isc_rss_table_size = XGBE_RSS_MAX_TABLE_SIZE;
715 scctx->isc_ntxqsets_max = XGBE_MAX_QUEUES;
716 scctx->isc_nrxqsets_max = XGBE_MAX_QUEUES;
718 scctx->isc_txrx = &axgbe_txrx;
722 axgbe_alloc_channels(if_ctx_t ctx)
724 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
725 struct xgbe_prv_data *pdata = &sc->pdata;
726 struct xgbe_channel *channel;
729 DBGPR("%s: txqs %d rxqs %d\n", __func__, pdata->tx_ring_count,
730 pdata->rx_ring_count);
732 /* Iflibe sets based on isc_ntxqsets/nrxqsets */
733 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
735 /* Allocate channel memory */
736 for (i = 0; i < count ; i++) {
737 channel = (struct xgbe_channel*)malloc(sizeof(struct xgbe_channel),
738 M_AXGBE, M_NOWAIT | M_ZERO);
740 if (channel == NULL) {
741 for (j = 0; j < i; j++) {
742 free(pdata->channel[j], M_AXGBE);
743 pdata->channel[j] = NULL;
748 pdata->channel[i] = channel;
751 pdata->total_channel_count = count;
752 DBGPR("Channel count set to: %u\n", pdata->total_channel_count);
754 for (i = 0; i < count; i++) {
756 channel = pdata->channel[i];
757 snprintf(channel->name, sizeof(channel->name), "channel-%d",i);
759 channel->pdata = pdata;
760 channel->queue_index = i;
761 channel->dma_tag = rman_get_bustag(pdata->xgmac_res);
762 bus_space_subregion(channel->dma_tag,
763 rman_get_bushandle(pdata->xgmac_res),
764 DMA_CH_BASE + (DMA_CH_INC * i), DMA_CH_INC,
765 &channel->dma_handle);
766 channel->tx_ring = NULL;
767 channel->rx_ring = NULL;
771 } /* axgbe_alloc_channels */
774 axgbe_free_channels(struct axgbe_if_softc *sc)
776 struct xgbe_prv_data *pdata = &sc->pdata;
779 for (i = 0; i < pdata->total_channel_count ; i++) {
780 free(pdata->channel[i], M_AXGBE);
781 pdata->channel[i] = NULL;
784 pdata->total_channel_count = 0;
785 pdata->channel_count = 0;
789 xgbe_service(void *ctx, int pending)
791 struct xgbe_prv_data *pdata = ctx;
792 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)pdata;
793 bool prev_state = false;
795 /* Get previous link status */
796 prev_state = pdata->phy.link;
798 pdata->phy_if.phy_status(pdata);
800 if (prev_state != pdata->phy.link) {
801 pdata->phy_link = pdata->phy.link;
802 axgbe_if_update_admin_status(sc->ctx);
805 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
809 xgbe_service_timer(void *data)
811 struct xgbe_prv_data *pdata = data;
813 taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work);
817 xgbe_init_timers(struct xgbe_prv_data *pdata)
819 callout_init(&pdata->service_timer, 1);
823 xgbe_start_timers(struct xgbe_prv_data *pdata)
825 callout_reset(&pdata->service_timer, 1*hz, xgbe_service_timer, pdata);
829 xgbe_stop_timers(struct xgbe_prv_data *pdata)
831 callout_drain(&pdata->service_timer);
832 callout_stop(&pdata->service_timer);
836 xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
838 axgbe_printf(1, "\n************* PHY Reg dump *********************\n");
840 axgbe_printf(1, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
841 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
842 axgbe_printf(1, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
843 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
844 axgbe_printf(1, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
845 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
846 axgbe_printf(1, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
847 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
848 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
849 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
850 axgbe_printf(1, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
851 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
852 axgbe_printf(1, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
853 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
854 axgbe_printf(1, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
855 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
856 axgbe_printf(1, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
858 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
859 axgbe_printf(1, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
860 MDIO_AN_ADVERTISE + 1,
861 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
862 axgbe_printf(1, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
863 MDIO_AN_ADVERTISE + 2,
864 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
865 axgbe_printf(1, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
867 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
869 axgbe_printf(1, "\n************************************************\n");
873 xgbe_dump_prop_registers(struct xgbe_prv_data *pdata)
877 axgbe_printf(1, "\n************* PROP Reg dump ********************\n");
879 for (i = 0 ; i < 38 ; i++) {
880 axgbe_printf(1, "PROP Offset 0x%08x = %08x\n",
881 (XP_PROP_0 + (i * 4)), XP_IOREAD(pdata,
882 (XP_PROP_0 + (i * 4))));
887 xgbe_dump_dma_registers(struct xgbe_prv_data *pdata, int ch)
889 struct xgbe_channel *channel;
892 axgbe_printf(1, "\n************* DMA Reg dump *********************\n");
894 axgbe_printf(1, "DMA MR Reg (%08x) = %08x\n", DMA_MR,
895 XGMAC_IOREAD(pdata, DMA_MR));
896 axgbe_printf(1, "DMA SBMR Reg (%08x) = %08x\n", DMA_SBMR,
897 XGMAC_IOREAD(pdata, DMA_SBMR));
898 axgbe_printf(1, "DMA ISR Reg (%08x) = %08x\n", DMA_ISR,
899 XGMAC_IOREAD(pdata, DMA_ISR));
900 axgbe_printf(1, "DMA AXIARCR Reg (%08x) = %08x\n", DMA_AXIARCR,
901 XGMAC_IOREAD(pdata, DMA_AXIARCR));
902 axgbe_printf(1, "DMA AXIAWCR Reg (%08x) = %08x\n", DMA_AXIAWCR,
903 XGMAC_IOREAD(pdata, DMA_AXIAWCR));
904 axgbe_printf(1, "DMA AXIAWARCR Reg (%08x) = %08x\n", DMA_AXIAWARCR,
905 XGMAC_IOREAD(pdata, DMA_AXIAWARCR));
906 axgbe_printf(1, "DMA DSR0 Reg (%08x) = %08x\n", DMA_DSR0,
907 XGMAC_IOREAD(pdata, DMA_DSR0));
908 axgbe_printf(1, "DMA DSR1 Reg (%08x) = %08x\n", DMA_DSR1,
909 XGMAC_IOREAD(pdata, DMA_DSR1));
910 axgbe_printf(1, "DMA DSR2 Reg (%08x) = %08x\n", DMA_DSR2,
911 XGMAC_IOREAD(pdata, DMA_DSR2));
912 axgbe_printf(1, "DMA DSR3 Reg (%08x) = %08x\n", DMA_DSR3,
913 XGMAC_IOREAD(pdata, DMA_DSR3));
914 axgbe_printf(1, "DMA DSR4 Reg (%08x) = %08x\n", DMA_DSR4,
915 XGMAC_IOREAD(pdata, DMA_DSR4));
916 axgbe_printf(1, "DMA TXEDMACR Reg (%08x) = %08x\n", DMA_TXEDMACR,
917 XGMAC_IOREAD(pdata, DMA_TXEDMACR));
918 axgbe_printf(1, "DMA RXEDMACR Reg (%08x) = %08x\n", DMA_RXEDMACR,
919 XGMAC_IOREAD(pdata, DMA_RXEDMACR));
921 for (i = 0 ; i < 8 ; i++ ) {
928 channel = pdata->channel[i];
930 axgbe_printf(1, "\n************* DMA CH %d dump ****************\n", i);
932 axgbe_printf(1, "DMA_CH_CR Reg (%08x) = %08x\n",
933 DMA_CH_CR, XGMAC_DMA_IOREAD(channel, DMA_CH_CR));
934 axgbe_printf(1, "DMA_CH_TCR Reg (%08x) = %08x\n",
935 DMA_CH_TCR, XGMAC_DMA_IOREAD(channel, DMA_CH_TCR));
936 axgbe_printf(1, "DMA_CH_RCR Reg (%08x) = %08x\n",
937 DMA_CH_RCR, XGMAC_DMA_IOREAD(channel, DMA_CH_RCR));
938 axgbe_printf(1, "DMA_CH_TDLR_HI Reg (%08x) = %08x\n",
939 DMA_CH_TDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_HI));
940 axgbe_printf(1, "DMA_CH_TDLR_LO Reg (%08x) = %08x\n",
941 DMA_CH_TDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDLR_LO));
942 axgbe_printf(1, "DMA_CH_RDLR_HI Reg (%08x) = %08x\n",
943 DMA_CH_RDLR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_HI));
944 axgbe_printf(1, "DMA_CH_RDLR_LO Reg (%08x) = %08x\n",
945 DMA_CH_RDLR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDLR_LO));
946 axgbe_printf(1, "DMA_CH_TDTR_LO Reg (%08x) = %08x\n",
947 DMA_CH_TDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTR_LO));
948 axgbe_printf(1, "DMA_CH_RDTR_LO Reg (%08x) = %08x\n",
949 DMA_CH_RDTR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTR_LO));
950 axgbe_printf(1, "DMA_CH_TDRLR Reg (%08x) = %08x\n",
951 DMA_CH_TDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_TDRLR));
952 axgbe_printf(1, "DMA_CH_RDRLR Reg (%08x) = %08x\n",
953 DMA_CH_RDRLR, XGMAC_DMA_IOREAD(channel, DMA_CH_RDRLR));
954 axgbe_printf(1, "DMA_CH_IER Reg (%08x) = %08x\n",
955 DMA_CH_IER, XGMAC_DMA_IOREAD(channel, DMA_CH_IER));
956 axgbe_printf(1, "DMA_CH_RIWT Reg (%08x) = %08x\n",
957 DMA_CH_RIWT, XGMAC_DMA_IOREAD(channel, DMA_CH_RIWT));
958 axgbe_printf(1, "DMA_CH_CATDR_LO Reg (%08x) = %08x\n",
959 DMA_CH_CATDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATDR_LO));
960 axgbe_printf(1, "DMA_CH_CARDR_LO Reg (%08x) = %08x\n",
961 DMA_CH_CARDR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARDR_LO));
962 axgbe_printf(1, "DMA_CH_CATBR_HI Reg (%08x) = %08x\n",
963 DMA_CH_CATBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_HI));
964 axgbe_printf(1, "DMA_CH_CATBR_LO Reg (%08x) = %08x\n",
965 DMA_CH_CATBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CATBR_LO));
966 axgbe_printf(1, "DMA_CH_CARBR_HI Reg (%08x) = %08x\n",
967 DMA_CH_CARBR_HI, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_HI));
968 axgbe_printf(1, "DMA_CH_CARBR_LO Reg (%08x) = %08x\n",
969 DMA_CH_CARBR_LO, XGMAC_DMA_IOREAD(channel, DMA_CH_CARBR_LO));
970 axgbe_printf(1, "DMA_CH_SR Reg (%08x) = %08x\n",
971 DMA_CH_SR, XGMAC_DMA_IOREAD(channel, DMA_CH_SR));
972 axgbe_printf(1, "DMA_CH_DSR Reg (%08x) = %08x\n",
973 DMA_CH_DSR, XGMAC_DMA_IOREAD(channel, DMA_CH_DSR));
974 axgbe_printf(1, "DMA_CH_DCFL Reg (%08x) = %08x\n",
975 DMA_CH_DCFL, XGMAC_DMA_IOREAD(channel, DMA_CH_DCFL));
976 axgbe_printf(1, "DMA_CH_MFC Reg (%08x) = %08x\n",
977 DMA_CH_MFC, XGMAC_DMA_IOREAD(channel, DMA_CH_MFC));
978 axgbe_printf(1, "DMA_CH_TDTRO Reg (%08x) = %08x\n",
979 DMA_CH_TDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDTRO));
980 axgbe_printf(1, "DMA_CH_RDTRO Reg (%08x) = %08x\n",
981 DMA_CH_RDTRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDTRO));
982 axgbe_printf(1, "DMA_CH_TDWRO Reg (%08x) = %08x\n",
983 DMA_CH_TDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_TDWRO));
984 axgbe_printf(1, "DMA_CH_RDWRO Reg (%08x) = %08x\n",
985 DMA_CH_RDWRO, XGMAC_DMA_IOREAD(channel, DMA_CH_RDWRO));
990 xgbe_dump_mtl_registers(struct xgbe_prv_data *pdata)
994 axgbe_printf(1, "\n************* MTL Reg dump *********************\n");
996 axgbe_printf(1, "MTL OMR Reg (%08x) = %08x\n", MTL_OMR,
997 XGMAC_IOREAD(pdata, MTL_OMR));
998 axgbe_printf(1, "MTL FDCR Reg (%08x) = %08x\n", MTL_FDCR,
999 XGMAC_IOREAD(pdata, MTL_FDCR));
1000 axgbe_printf(1, "MTL FDSR Reg (%08x) = %08x\n", MTL_FDSR,
1001 XGMAC_IOREAD(pdata, MTL_FDSR));
1002 axgbe_printf(1, "MTL FDDR Reg (%08x) = %08x\n", MTL_FDDR,
1003 XGMAC_IOREAD(pdata, MTL_FDDR));
1004 axgbe_printf(1, "MTL ISR Reg (%08x) = %08x\n", MTL_ISR,
1005 XGMAC_IOREAD(pdata, MTL_ISR));
1006 axgbe_printf(1, "MTL RQDCM0R Reg (%08x) = %08x\n", MTL_RQDCM0R,
1007 XGMAC_IOREAD(pdata, MTL_RQDCM0R));
1008 axgbe_printf(1, "MTL RQDCM1R Reg (%08x) = %08x\n", MTL_RQDCM1R,
1009 XGMAC_IOREAD(pdata, MTL_RQDCM1R));
1010 axgbe_printf(1, "MTL RQDCM2R Reg (%08x) = %08x\n", MTL_RQDCM2R,
1011 XGMAC_IOREAD(pdata, MTL_RQDCM2R));
1012 axgbe_printf(1, "MTL TCPM0R Reg (%08x) = %08x\n", MTL_TCPM0R,
1013 XGMAC_IOREAD(pdata, MTL_TCPM0R));
1014 axgbe_printf(1, "MTL TCPM1R Reg (%08x) = %08x\n", MTL_TCPM1R,
1015 XGMAC_IOREAD(pdata, MTL_TCPM1R));
1017 for (i = 0 ; i < 8 ; i++ ) {
1019 axgbe_printf(1, "\n************* MTL CH %d dump ****************\n", i);
1021 axgbe_printf(1, "MTL_Q_TQOMR Reg (%08x) = %08x\n",
1022 MTL_Q_TQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQOMR));
1023 axgbe_printf(1, "MTL_Q_TQUR Reg (%08x) = %08x\n",
1024 MTL_Q_TQUR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQUR));
1025 axgbe_printf(1, "MTL_Q_TQDR Reg (%08x) = %08x\n",
1026 MTL_Q_TQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TQDR));
1027 axgbe_printf(1, "MTL_Q_TC0ETSCR Reg (%08x) = %08x\n",
1028 MTL_Q_TC0ETSCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSCR));
1029 axgbe_printf(1, "MTL_Q_TC0ETSSR Reg (%08x) = %08x\n",
1030 MTL_Q_TC0ETSSR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0ETSSR));
1031 axgbe_printf(1, "MTL_Q_TC0QWR Reg (%08x) = %08x\n",
1032 MTL_Q_TC0QWR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_TC0QWR));
1034 axgbe_printf(1, "MTL_Q_RQOMR Reg (%08x) = %08x\n",
1035 MTL_Q_RQOMR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQOMR));
1036 axgbe_printf(1, "MTL_Q_RQMPOCR Reg (%08x) = %08x\n",
1037 MTL_Q_RQMPOCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQMPOCR));
1038 axgbe_printf(1, "MTL_Q_RQDR Reg (%08x) = %08x\n",
1039 MTL_Q_RQDR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQDR));
1040 axgbe_printf(1, "MTL_Q_RQCR Reg (%08x) = %08x\n",
1041 MTL_Q_RQCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQCR));
1042 axgbe_printf(1, "MTL_Q_RQFCR Reg (%08x) = %08x\n",
1043 MTL_Q_RQFCR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_RQFCR));
1044 axgbe_printf(1, "MTL_Q_IER Reg (%08x) = %08x\n",
1045 MTL_Q_IER, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_IER));
1046 axgbe_printf(1, "MTL_Q_ISR Reg (%08x) = %08x\n",
1047 MTL_Q_ISR, XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR));
1052 xgbe_dump_mac_registers(struct xgbe_prv_data *pdata)
1054 axgbe_printf(1, "\n************* MAC Reg dump **********************\n");
1056 axgbe_printf(1, "MAC TCR Reg (%08x) = %08x\n", MAC_TCR,
1057 XGMAC_IOREAD(pdata, MAC_TCR));
1058 axgbe_printf(1, "MAC RCR Reg (%08x) = %08x\n", MAC_RCR,
1059 XGMAC_IOREAD(pdata, MAC_RCR));
1060 axgbe_printf(1, "MAC PFR Reg (%08x) = %08x\n", MAC_PFR,
1061 XGMAC_IOREAD(pdata, MAC_PFR));
1062 axgbe_printf(1, "MAC WTR Reg (%08x) = %08x\n", MAC_WTR,
1063 XGMAC_IOREAD(pdata, MAC_WTR));
1064 axgbe_printf(1, "MAC HTR0 Reg (%08x) = %08x\n", MAC_HTR0,
1065 XGMAC_IOREAD(pdata, MAC_HTR0));
1066 axgbe_printf(1, "MAC HTR1 Reg (%08x) = %08x\n", MAC_HTR1,
1067 XGMAC_IOREAD(pdata, MAC_HTR1));
1068 axgbe_printf(1, "MAC HTR2 Reg (%08x) = %08x\n", MAC_HTR2,
1069 XGMAC_IOREAD(pdata, MAC_HTR2));
1070 axgbe_printf(1, "MAC HTR3 Reg (%08x) = %08x\n", MAC_HTR3,
1071 XGMAC_IOREAD(pdata, MAC_HTR3));
1072 axgbe_printf(1, "MAC HTR4 Reg (%08x) = %08x\n", MAC_HTR4,
1073 XGMAC_IOREAD(pdata, MAC_HTR4));
1074 axgbe_printf(1, "MAC HTR5 Reg (%08x) = %08x\n", MAC_HTR5,
1075 XGMAC_IOREAD(pdata, MAC_HTR5));
1076 axgbe_printf(1, "MAC HTR6 Reg (%08x) = %08x\n", MAC_HTR6,
1077 XGMAC_IOREAD(pdata, MAC_HTR6));
1078 axgbe_printf(1, "MAC HTR7 Reg (%08x) = %08x\n", MAC_HTR7,
1079 XGMAC_IOREAD(pdata, MAC_HTR7));
1080 axgbe_printf(1, "MAC VLANTR Reg (%08x) = %08x\n", MAC_VLANTR,
1081 XGMAC_IOREAD(pdata, MAC_VLANTR));
1082 axgbe_printf(1, "MAC VLANHTR Reg (%08x) = %08x\n", MAC_VLANHTR,
1083 XGMAC_IOREAD(pdata, MAC_VLANHTR));
1084 axgbe_printf(1, "MAC VLANIR Reg (%08x) = %08x\n", MAC_VLANIR,
1085 XGMAC_IOREAD(pdata, MAC_VLANIR));
1086 axgbe_printf(1, "MAC IVLANIR Reg (%08x) = %08x\n", MAC_IVLANIR,
1087 XGMAC_IOREAD(pdata, MAC_IVLANIR));
1088 axgbe_printf(1, "MAC RETMR Reg (%08x) = %08x\n", MAC_RETMR,
1089 XGMAC_IOREAD(pdata, MAC_RETMR));
1090 axgbe_printf(1, "MAC Q0TFCR Reg (%08x) = %08x\n", MAC_Q0TFCR,
1091 XGMAC_IOREAD(pdata, MAC_Q0TFCR));
1092 axgbe_printf(1, "MAC Q1TFCR Reg (%08x) = %08x\n", MAC_Q1TFCR,
1093 XGMAC_IOREAD(pdata, MAC_Q1TFCR));
1094 axgbe_printf(1, "MAC Q2TFCR Reg (%08x) = %08x\n", MAC_Q2TFCR,
1095 XGMAC_IOREAD(pdata, MAC_Q2TFCR));
1096 axgbe_printf(1, "MAC Q3TFCR Reg (%08x) = %08x\n", MAC_Q3TFCR,
1097 XGMAC_IOREAD(pdata, MAC_Q3TFCR));
1098 axgbe_printf(1, "MAC Q4TFCR Reg (%08x) = %08x\n", MAC_Q4TFCR,
1099 XGMAC_IOREAD(pdata, MAC_Q4TFCR));
1100 axgbe_printf(1, "MAC Q5TFCR Reg (%08x) = %08x\n", MAC_Q5TFCR,
1101 XGMAC_IOREAD(pdata, MAC_Q5TFCR));
1102 axgbe_printf(1, "MAC Q6TFCR Reg (%08x) = %08x\n", MAC_Q6TFCR,
1103 XGMAC_IOREAD(pdata, MAC_Q6TFCR));
1104 axgbe_printf(1, "MAC Q7TFCR Reg (%08x) = %08x\n", MAC_Q7TFCR,
1105 XGMAC_IOREAD(pdata, MAC_Q7TFCR));
1106 axgbe_printf(1, "MAC RFCR Reg (%08x) = %08x\n", MAC_RFCR,
1107 XGMAC_IOREAD(pdata, MAC_RFCR));
1108 axgbe_printf(1, "MAC RQC0R Reg (%08x) = %08x\n", MAC_RQC0R,
1109 XGMAC_IOREAD(pdata, MAC_RQC0R));
1110 axgbe_printf(1, "MAC RQC1R Reg (%08x) = %08x\n", MAC_RQC1R,
1111 XGMAC_IOREAD(pdata, MAC_RQC1R));
1112 axgbe_printf(1, "MAC RQC2R Reg (%08x) = %08x\n", MAC_RQC2R,
1113 XGMAC_IOREAD(pdata, MAC_RQC2R));
1114 axgbe_printf(1, "MAC RQC3R Reg (%08x) = %08x\n", MAC_RQC3R,
1115 XGMAC_IOREAD(pdata, MAC_RQC3R));
1116 axgbe_printf(1, "MAC ISR Reg (%08x) = %08x\n", MAC_ISR,
1117 XGMAC_IOREAD(pdata, MAC_ISR));
1118 axgbe_printf(1, "MAC IER Reg (%08x) = %08x\n", MAC_IER,
1119 XGMAC_IOREAD(pdata, MAC_IER));
1120 axgbe_printf(1, "MAC RTSR Reg (%08x) = %08x\n", MAC_RTSR,
1121 XGMAC_IOREAD(pdata, MAC_RTSR));
1122 axgbe_printf(1, "MAC PMTCSR Reg (%08x) = %08x\n", MAC_PMTCSR,
1123 XGMAC_IOREAD(pdata, MAC_PMTCSR));
1124 axgbe_printf(1, "MAC RWKPFR Reg (%08x) = %08x\n", MAC_RWKPFR,
1125 XGMAC_IOREAD(pdata, MAC_RWKPFR));
1126 axgbe_printf(1, "MAC LPICSR Reg (%08x) = %08x\n", MAC_LPICSR,
1127 XGMAC_IOREAD(pdata, MAC_LPICSR));
1128 axgbe_printf(1, "MAC LPITCR Reg (%08x) = %08x\n", MAC_LPITCR,
1129 XGMAC_IOREAD(pdata, MAC_LPITCR));
1130 axgbe_printf(1, "MAC TIR Reg (%08x) = %08x\n", MAC_TIR,
1131 XGMAC_IOREAD(pdata, MAC_TIR));
1132 axgbe_printf(1, "MAC VR Reg (%08x) = %08x\n", MAC_VR,
1133 XGMAC_IOREAD(pdata, MAC_VR));
1134 axgbe_printf(1, "MAC DR Reg (%08x) = %08x\n", MAC_DR,
1135 XGMAC_IOREAD(pdata, MAC_DR));
1136 axgbe_printf(1, "MAC HWF0R Reg (%08x) = %08x\n", MAC_HWF0R,
1137 XGMAC_IOREAD(pdata, MAC_HWF0R));
1138 axgbe_printf(1, "MAC HWF1R Reg (%08x) = %08x\n", MAC_HWF1R,
1139 XGMAC_IOREAD(pdata, MAC_HWF1R));
1140 axgbe_printf(1, "MAC HWF2R Reg (%08x) = %08x\n", MAC_HWF2R,
1141 XGMAC_IOREAD(pdata, MAC_HWF2R));
1142 axgbe_printf(1, "MAC MDIOSCAR Reg (%08x) = %08x\n", MAC_MDIOSCAR,
1143 XGMAC_IOREAD(pdata, MAC_MDIOSCAR));
1144 axgbe_printf(1, "MAC MDIOSCCDR Reg (%08x) = %08x\n", MAC_MDIOSCCDR,
1145 XGMAC_IOREAD(pdata, MAC_MDIOSCCDR));
1146 axgbe_printf(1, "MAC MDIOISR Reg (%08x) = %08x\n", MAC_MDIOISR,
1147 XGMAC_IOREAD(pdata, MAC_MDIOISR));
1148 axgbe_printf(1, "MAC MDIOIER Reg (%08x) = %08x\n", MAC_MDIOIER,
1149 XGMAC_IOREAD(pdata, MAC_MDIOIER));
1150 axgbe_printf(1, "MAC MDIOCL22R Reg (%08x) = %08x\n", MAC_MDIOCL22R,
1151 XGMAC_IOREAD(pdata, MAC_MDIOCL22R));
1152 axgbe_printf(1, "MAC GPIOCR Reg (%08x) = %08x\n", MAC_GPIOCR,
1153 XGMAC_IOREAD(pdata, MAC_GPIOCR));
1154 axgbe_printf(1, "MAC GPIOSR Reg (%08x) = %08x\n", MAC_GPIOSR,
1155 XGMAC_IOREAD(pdata, MAC_GPIOSR));
1156 axgbe_printf(1, "MAC MACA0HR Reg (%08x) = %08x\n", MAC_MACA0HR,
1157 XGMAC_IOREAD(pdata, MAC_MACA0HR));
1158 axgbe_printf(1, "MAC MACA0LR Reg (%08x) = %08x\n", MAC_TCR,
1159 XGMAC_IOREAD(pdata, MAC_MACA0LR));
1160 axgbe_printf(1, "MAC MACA1HR Reg (%08x) = %08x\n", MAC_MACA1HR,
1161 XGMAC_IOREAD(pdata, MAC_MACA1HR));
1162 axgbe_printf(1, "MAC MACA1LR Reg (%08x) = %08x\n", MAC_MACA1LR,
1163 XGMAC_IOREAD(pdata, MAC_MACA1LR));
1164 axgbe_printf(1, "MAC RSSCR Reg (%08x) = %08x\n", MAC_RSSCR,
1165 XGMAC_IOREAD(pdata, MAC_RSSCR));
1166 axgbe_printf(1, "MAC RSSDR Reg (%08x) = %08x\n", MAC_RSSDR,
1167 XGMAC_IOREAD(pdata, MAC_RSSDR));
1168 axgbe_printf(1, "MAC RSSAR Reg (%08x) = %08x\n", MAC_RSSAR,
1169 XGMAC_IOREAD(pdata, MAC_RSSAR));
1170 axgbe_printf(1, "MAC TSCR Reg (%08x) = %08x\n", MAC_TSCR,
1171 XGMAC_IOREAD(pdata, MAC_TSCR));
1172 axgbe_printf(1, "MAC SSIR Reg (%08x) = %08x\n", MAC_SSIR,
1173 XGMAC_IOREAD(pdata, MAC_SSIR));
1174 axgbe_printf(1, "MAC STSR Reg (%08x) = %08x\n", MAC_STSR,
1175 XGMAC_IOREAD(pdata, MAC_STSR));
1176 axgbe_printf(1, "MAC STNR Reg (%08x) = %08x\n", MAC_STNR,
1177 XGMAC_IOREAD(pdata, MAC_STNR));
1178 axgbe_printf(1, "MAC STSUR Reg (%08x) = %08x\n", MAC_STSUR,
1179 XGMAC_IOREAD(pdata, MAC_STSUR));
1180 axgbe_printf(1, "MAC STNUR Reg (%08x) = %08x\n", MAC_STNUR,
1181 XGMAC_IOREAD(pdata, MAC_STNUR));
1182 axgbe_printf(1, "MAC TSAR Reg (%08x) = %08x\n", MAC_TSAR,
1183 XGMAC_IOREAD(pdata, MAC_TSAR));
1184 axgbe_printf(1, "MAC TSSR Reg (%08x) = %08x\n", MAC_TSSR,
1185 XGMAC_IOREAD(pdata, MAC_TSSR));
1186 axgbe_printf(1, "MAC TXSNR Reg (%08x) = %08x\n", MAC_TXSNR,
1187 XGMAC_IOREAD(pdata, MAC_TXSNR));
1188 axgbe_printf(1, "MAC TXSSR Reg (%08x) = %08x\n", MAC_TXSSR,
1189 XGMAC_IOREAD(pdata, MAC_TXSSR));
1193 xgbe_dump_rmon_counters(struct xgbe_prv_data *pdata)
1195 struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
1197 axgbe_printf(1, "\n************* RMON counters dump ***************\n");
1199 pdata->hw_if.read_mmc_stats(pdata);
1201 axgbe_printf(1, "rmon txoctetcount_gb (%08x) = %08lx\n",
1202 MMC_TXOCTETCOUNT_GB_LO, stats->txoctetcount_gb);
1203 axgbe_printf(1, "rmon txframecount_gb (%08x) = %08lx\n",
1204 MMC_TXFRAMECOUNT_GB_LO, stats->txframecount_gb);
1205 axgbe_printf(1, "rmon txbroadcastframes_g (%08x) = %08lx\n",
1206 MMC_TXBROADCASTFRAMES_G_LO, stats->txbroadcastframes_g);
1207 axgbe_printf(1, "rmon txmulticastframes_g (%08x) = %08lx\n",
1208 MMC_TXMULTICASTFRAMES_G_LO, stats->txmulticastframes_g);
1209 axgbe_printf(1, "rmon tx64octets_gb (%08x) = %08lx\n",
1210 MMC_TX64OCTETS_GB_LO, stats->tx64octets_gb);
1211 axgbe_printf(1, "rmon tx65to127octets_gb (%08x) = %08lx\n",
1212 MMC_TX65TO127OCTETS_GB_LO, stats->tx65to127octets_gb);
1213 axgbe_printf(1, "rmon tx128to255octets_gb (%08x) = %08lx\n",
1214 MMC_TX128TO255OCTETS_GB_LO, stats->tx128to255octets_gb);
1215 axgbe_printf(1, "rmon tx256to511octets_gb (%08x) = %08lx\n",
1216 MMC_TX256TO511OCTETS_GB_LO, stats->tx256to511octets_gb);
1217 axgbe_printf(1, "rmon tx512to1023octets_gb (%08x) = %08lx\n",
1218 MMC_TX512TO1023OCTETS_GB_LO, stats->tx512to1023octets_gb);
1219 axgbe_printf(1, "rmon tx1024tomaxoctets_gb (%08x) = %08lx\n",
1220 MMC_TX1024TOMAXOCTETS_GB_LO, stats->tx1024tomaxoctets_gb);
1221 axgbe_printf(1, "rmon txunicastframes_gb (%08x) = %08lx\n",
1222 MMC_TXUNICASTFRAMES_GB_LO, stats->txunicastframes_gb);
1223 axgbe_printf(1, "rmon txmulticastframes_gb (%08x) = %08lx\n",
1224 MMC_TXMULTICASTFRAMES_GB_LO, stats->txmulticastframes_gb);
1225 axgbe_printf(1, "rmon txbroadcastframes_gb (%08x) = %08lx\n",
1226 MMC_TXBROADCASTFRAMES_GB_LO, stats->txbroadcastframes_gb);
1227 axgbe_printf(1, "rmon txunderflowerror (%08x) = %08lx\n",
1228 MMC_TXUNDERFLOWERROR_LO, stats->txunderflowerror);
1229 axgbe_printf(1, "rmon txoctetcount_g (%08x) = %08lx\n",
1230 MMC_TXOCTETCOUNT_G_LO, stats->txoctetcount_g);
1231 axgbe_printf(1, "rmon txframecount_g (%08x) = %08lx\n",
1232 MMC_TXFRAMECOUNT_G_LO, stats->txframecount_g);
1233 axgbe_printf(1, "rmon txpauseframes (%08x) = %08lx\n",
1234 MMC_TXPAUSEFRAMES_LO, stats->txpauseframes);
1235 axgbe_printf(1, "rmon txvlanframes_g (%08x) = %08lx\n",
1236 MMC_TXVLANFRAMES_G_LO, stats->txvlanframes_g);
1237 axgbe_printf(1, "rmon rxframecount_gb (%08x) = %08lx\n",
1238 MMC_RXFRAMECOUNT_GB_LO, stats->rxframecount_gb);
1239 axgbe_printf(1, "rmon rxoctetcount_gb (%08x) = %08lx\n",
1240 MMC_RXOCTETCOUNT_GB_LO, stats->rxoctetcount_gb);
1241 axgbe_printf(1, "rmon rxoctetcount_g (%08x) = %08lx\n",
1242 MMC_RXOCTETCOUNT_G_LO, stats->rxoctetcount_g);
1243 axgbe_printf(1, "rmon rxbroadcastframes_g (%08x) = %08lx\n",
1244 MMC_RXBROADCASTFRAMES_G_LO, stats->rxbroadcastframes_g);
1245 axgbe_printf(1, "rmon rxmulticastframes_g (%08x) = %08lx\n",
1246 MMC_RXMULTICASTFRAMES_G_LO, stats->rxmulticastframes_g);
1247 axgbe_printf(1, "rmon rxcrcerror (%08x) = %08lx\n",
1248 MMC_RXCRCERROR_LO, stats->rxcrcerror);
1249 axgbe_printf(1, "rmon rxrunterror (%08x) = %08lx\n",
1250 MMC_RXRUNTERROR, stats->rxrunterror);
1251 axgbe_printf(1, "rmon rxjabbererror (%08x) = %08lx\n",
1252 MMC_RXJABBERERROR, stats->rxjabbererror);
1253 axgbe_printf(1, "rmon rxundersize_g (%08x) = %08lx\n",
1254 MMC_RXUNDERSIZE_G, stats->rxundersize_g);
1255 axgbe_printf(1, "rmon rxoversize_g (%08x) = %08lx\n",
1256 MMC_RXOVERSIZE_G, stats->rxoversize_g);
1257 axgbe_printf(1, "rmon rx64octets_gb (%08x) = %08lx\n",
1258 MMC_RX64OCTETS_GB_LO, stats->rx64octets_gb);
1259 axgbe_printf(1, "rmon rx65to127octets_gb (%08x) = %08lx\n",
1260 MMC_RX65TO127OCTETS_GB_LO, stats->rx65to127octets_gb);
1261 axgbe_printf(1, "rmon rx128to255octets_gb (%08x) = %08lx\n",
1262 MMC_RX128TO255OCTETS_GB_LO, stats->rx128to255octets_gb);
1263 axgbe_printf(1, "rmon rx256to511octets_gb (%08x) = %08lx\n",
1264 MMC_RX256TO511OCTETS_GB_LO, stats->rx256to511octets_gb);
1265 axgbe_printf(1, "rmon rx512to1023octets_gb (%08x) = %08lx\n",
1266 MMC_RX512TO1023OCTETS_GB_LO, stats->rx512to1023octets_gb);
1267 axgbe_printf(1, "rmon rx1024tomaxoctets_gb (%08x) = %08lx\n",
1268 MMC_RX1024TOMAXOCTETS_GB_LO, stats->rx1024tomaxoctets_gb);
1269 axgbe_printf(1, "rmon rxunicastframes_g (%08x) = %08lx\n",
1270 MMC_RXUNICASTFRAMES_G_LO, stats->rxunicastframes_g);
1271 axgbe_printf(1, "rmon rxlengtherror (%08x) = %08lx\n",
1272 MMC_RXLENGTHERROR_LO, stats->rxlengtherror);
1273 axgbe_printf(1, "rmon rxoutofrangetype (%08x) = %08lx\n",
1274 MMC_RXOUTOFRANGETYPE_LO, stats->rxoutofrangetype);
1275 axgbe_printf(1, "rmon rxpauseframes (%08x) = %08lx\n",
1276 MMC_RXPAUSEFRAMES_LO, stats->rxpauseframes);
1277 axgbe_printf(1, "rmon rxfifooverflow (%08x) = %08lx\n",
1278 MMC_RXFIFOOVERFLOW_LO, stats->rxfifooverflow);
1279 axgbe_printf(1, "rmon rxvlanframes_gb (%08x) = %08lx\n",
1280 MMC_RXVLANFRAMES_GB_LO, stats->rxvlanframes_gb);
1281 axgbe_printf(1, "rmon rxwatchdogerror (%08x) = %08lx\n",
1282 MMC_RXWATCHDOGERROR, stats->rxwatchdogerror);
1286 xgbe_dump_i2c_registers(struct xgbe_prv_data *pdata)
1288 axgbe_printf(1, "*************** I2C Registers **************\n");
1289 axgbe_printf(1, " IC_CON : %010x\n",
1290 XI2C_IOREAD(pdata, 0x00));
1291 axgbe_printf(1, " IC_TAR : %010x\n",
1292 XI2C_IOREAD(pdata, 0x04));
1293 axgbe_printf(1, " IC_HS_MADDR : %010x\n",
1294 XI2C_IOREAD(pdata, 0x0c));
1295 axgbe_printf(1, " IC_INTR_STAT : %010x\n",
1296 XI2C_IOREAD(pdata, 0x2c));
1297 axgbe_printf(1, " IC_INTR_MASK : %010x\n",
1298 XI2C_IOREAD(pdata, 0x30));
1299 axgbe_printf(1, " IC_RAW_INTR_STAT : %010x\n",
1300 XI2C_IOREAD(pdata, 0x34));
1301 axgbe_printf(1, " IC_RX_TL : %010x\n",
1302 XI2C_IOREAD(pdata, 0x38));
1303 axgbe_printf(1, " IC_TX_TL : %010x\n",
1304 XI2C_IOREAD(pdata, 0x3c));
1305 axgbe_printf(1, " IC_ENABLE : %010x\n",
1306 XI2C_IOREAD(pdata, 0x6c));
1307 axgbe_printf(1, " IC_STATUS : %010x\n",
1308 XI2C_IOREAD(pdata, 0x70));
1309 axgbe_printf(1, " IC_TXFLR : %010x\n",
1310 XI2C_IOREAD(pdata, 0x74));
1311 axgbe_printf(1, " IC_RXFLR : %010x\n",
1312 XI2C_IOREAD(pdata, 0x78));
1313 axgbe_printf(1, " IC_ENABLE_STATUS : %010x\n",
1314 XI2C_IOREAD(pdata, 0x9c));
1315 axgbe_printf(1, " IC_COMP_PARAM1 : %010x\n",
1316 XI2C_IOREAD(pdata, 0xf4));
1320 xgbe_dump_active_vlans(struct xgbe_prv_data *pdata)
1324 for(i=0 ; i<BITS_TO_LONGS(VLAN_NVID); i++) {
1325 if (i && (i%8 == 0))
1326 axgbe_printf(1, "\n");
1327 axgbe_printf(1, "vlans[%d]: 0x%08lx ", i, pdata->active_vlans[i]);
1329 axgbe_printf(1, "\n");
1333 xgbe_default_config(struct xgbe_prv_data *pdata)
1335 pdata->blen = DMA_SBMR_BLEN_64;
1336 pdata->pbl = DMA_PBL_128;
1338 pdata->rd_osr_limit = 8;
1339 pdata->wr_osr_limit = 8;
1340 pdata->tx_sf_mode = MTL_TSF_ENABLE;
1341 pdata->tx_threshold = MTL_TX_THRESHOLD_64;
1342 pdata->tx_osp_mode = DMA_OSP_ENABLE;
1343 pdata->rx_sf_mode = MTL_RSF_DISABLE;
1344 pdata->rx_threshold = MTL_RX_THRESHOLD_64;
1345 pdata->pause_autoneg = 1;
1346 pdata->tx_pause = 1;
1347 pdata->rx_pause = 1;
1348 pdata->phy_speed = SPEED_UNKNOWN;
1349 pdata->power_down = 0;
1350 pdata->enable_rss = 1;
1354 axgbe_if_attach_post(if_ctx_t ctx)
1356 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1357 struct xgbe_prv_data *pdata = &sc->pdata;
1358 struct ifnet *ifp = pdata->netdev;
1359 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1360 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1361 if_softc_ctx_t scctx = sc->scctx;
1364 /* set split header support based on tunable */
1365 pdata->sph_enable = axgbe_sph_enable;
1367 /* Initialize ECC timestamps */
1368 pdata->tx_sec_period = ticks;
1369 pdata->tx_ded_period = ticks;
1370 pdata->rx_sec_period = ticks;
1371 pdata->rx_ded_period = ticks;
1372 pdata->desc_sec_period = ticks;
1373 pdata->desc_ded_period = ticks;
1375 /* Reset the hardware */
1376 ret = hw_if->exit(&sc->pdata);
1378 axgbe_error("%s: exit error %d\n", __func__, ret);
1380 /* Configure the defaults */
1381 xgbe_default_config(pdata);
1383 /* Set default max values if not provided */
1384 if (!pdata->tx_max_fifo_size)
1385 pdata->tx_max_fifo_size = pdata->hw_feat.tx_fifo_size;
1386 if (!pdata->rx_max_fifo_size)
1387 pdata->rx_max_fifo_size = pdata->hw_feat.rx_fifo_size;
1389 DBGPR("%s: tx fifo 0x%x rx fifo 0x%x\n", __func__,
1390 pdata->tx_max_fifo_size, pdata->rx_max_fifo_size);
1392 /* Set and validate the number of descriptors for a ring */
1393 MPASS(powerof2(XGBE_TX_DESC_CNT));
1394 pdata->tx_desc_count = XGBE_TX_DESC_CNT;
1395 MPASS(powerof2(XGBE_RX_DESC_CNT));
1396 pdata->rx_desc_count = XGBE_RX_DESC_CNT;
1398 /* Adjust the number of queues based on interrupts assigned */
1399 if (pdata->channel_irq_count) {
1400 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count,
1401 pdata->channel_irq_count);
1402 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count,
1403 pdata->channel_irq_count);
1405 DBGPR("adjusted TX %u/%u RX %u/%u\n",
1406 pdata->tx_ring_count, pdata->tx_q_count,
1407 pdata->rx_ring_count, pdata->rx_q_count);
1410 /* Set channel count based on interrupts assigned */
1411 pdata->channel_count = max_t(unsigned int, scctx->isc_ntxqsets,
1412 scctx->isc_nrxqsets);
1413 DBGPR("Channel count set to: %u\n", pdata->channel_count);
1417 rss_getkey((uint8_t *)pdata->rss_key);
1419 arc4rand(&pdata->rss_key, ARRAY_SIZE(pdata->rss_key), 0);
1421 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
1422 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
1423 XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
1425 /* Initialize the PHY device */
1426 pdata->sysctl_an_cdr_workaround = pdata->vdata->an_cdr_workaround;
1427 phy_if->phy_init(pdata);
1429 /* Set the coalescing */
1430 xgbe_init_rx_coalesce(&sc->pdata);
1431 xgbe_init_tx_coalesce(&sc->pdata);
1433 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_KR, 0, NULL);
1434 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_T, 0, NULL);
1435 ifmedia_add(sc->media, IFM_ETHER | IFM_10G_SFI, 0, NULL);
1436 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_KX, 0, NULL);
1437 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_CX, 0, NULL);
1438 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_LX, 0, NULL);
1439 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1440 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
1441 ifmedia_add(sc->media, IFM_ETHER | IFM_1000_SGMII, 0, NULL);
1442 ifmedia_add(sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1443 ifmedia_add(sc->media, IFM_ETHER | IFM_100_SGMII, 0, NULL);
1444 ifmedia_add(sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1445 ifmedia_set(sc->media, IFM_ETHER | IFM_AUTO);
1447 /* Initialize the phy */
1448 pdata->phy_link = -1;
1449 pdata->phy_speed = SPEED_UNKNOWN;
1450 ret = phy_if->phy_reset(pdata);
1454 /* Calculate the Rx buffer size before allocating rings */
1455 ret = xgbe_calc_rx_buf_size(pdata->netdev, if_getmtu(pdata->netdev));
1456 pdata->rx_buf_size = ret;
1457 DBGPR("%s: rx_buf_size %d\n", __func__, ret);
1459 /* Setup RSS lookup table */
1460 for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
1461 XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
1462 i % pdata->rx_ring_count);
1465 * Mark the device down until it is initialized, which happens
1466 * when the device is accessed first (for configuring the iface,
1469 set_bit(XGBE_DOWN, &pdata->dev_state);
1471 DBGPR("mtu %d\n", ifp->if_mtu);
1472 scctx->isc_max_frame_size = ifp->if_mtu + 18;
1473 scctx->isc_min_frame_size = XGMAC_MIN_PACKET;
1475 axgbe_sysctl_init(pdata);
1477 axgbe_pci_init(pdata);
1480 } /* axgbe_if_attach_post */
1483 xgbe_free_intr(struct xgbe_prv_data *pdata, struct resource *res, void *tag,
1487 bus_teardown_intr(pdata->dev, res, tag);
1490 bus_release_resource(pdata->dev, SYS_RES_IRQ, rid, res);
1494 axgbe_interrupts_free(if_ctx_t ctx)
1496 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1497 struct xgbe_prv_data *pdata = &sc->pdata;
1498 if_softc_ctx_t scctx = sc->scctx;
1499 struct xgbe_channel *channel;
1503 axgbe_printf(2, "%s: mode %d\n", __func__, scctx->isc_intr);
1506 iflib_irq_free(ctx, &pdata->dev_irq);
1509 xgbe_free_intr(pdata, pdata->ecc_irq_res, pdata->ecc_irq_tag,
1513 xgbe_free_intr(pdata, pdata->i2c_irq_res, pdata->i2c_irq_tag,
1517 xgbe_free_intr(pdata, pdata->an_irq_res, pdata->an_irq_tag,
1520 for (i = 0; i < scctx->isc_nrxqsets; i++) {
1522 channel = pdata->channel[i];
1523 axgbe_printf(2, "%s: rid %d\n", __func__, channel->dma_irq_rid);
1524 irq.ii_res = channel->dma_irq_res;
1525 irq.ii_tag = channel->dma_irq_tag;
1526 iflib_irq_free(ctx, &irq);
1531 axgbe_if_detach(if_ctx_t ctx)
1533 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1534 struct xgbe_prv_data *pdata = &sc->pdata;
1535 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1536 struct resource *mac_res[2];
1538 mac_res[0] = pdata->xgmac_res;
1539 mac_res[1] = pdata->xpcs_res;
1541 phy_if->phy_exit(pdata);
1543 /* Free Interrupts */
1544 axgbe_interrupts_free(ctx);
1546 /* Free workqueues */
1547 taskqueue_free(pdata->dev_workqueue);
1549 /* Release bus resources */
1550 bus_release_resources(iflib_get_dev(ctx), axgbe_pci_mac_spec, mac_res);
1552 /* Free VLAN bitmap */
1553 free(pdata->active_vlans, M_AXGBE);
1555 axgbe_sysctl_exit(pdata);
1558 } /* axgbe_if_detach */
1561 axgbe_pci_init(struct xgbe_prv_data *pdata)
1563 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1564 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1567 if (!__predict_false((test_bit(XGBE_DOWN, &pdata->dev_state)))) {
1568 axgbe_printf(1, "%s: Starting when XGBE_UP\n", __func__);
1574 ret = phy_if->phy_start(pdata);
1576 axgbe_error("%s: phy start %d\n", __func__, ret);
1577 ret = hw_if->exit(pdata);
1579 axgbe_error("%s: exit error %d\n", __func__, ret);
1583 hw_if->enable_tx(pdata);
1584 hw_if->enable_rx(pdata);
1586 xgbe_start_timers(pdata);
1588 clear_bit(XGBE_DOWN, &pdata->dev_state);
1590 xgbe_dump_phy_registers(pdata);
1591 xgbe_dump_prop_registers(pdata);
1592 xgbe_dump_dma_registers(pdata, -1);
1593 xgbe_dump_mtl_registers(pdata);
1594 xgbe_dump_mac_registers(pdata);
1595 xgbe_dump_rmon_counters(pdata);
1599 axgbe_if_init(if_ctx_t ctx)
1601 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1602 struct xgbe_prv_data *pdata = &sc->pdata;
1604 axgbe_pci_init(pdata);
1608 axgbe_pci_stop(if_ctx_t ctx)
1610 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1611 struct xgbe_prv_data *pdata = &sc->pdata;
1612 struct xgbe_phy_if *phy_if = &pdata->phy_if;
1613 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1616 if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state))) {
1617 axgbe_printf(1, "%s: Stopping when XGBE_DOWN\n", __func__);
1621 xgbe_stop_timers(pdata);
1622 taskqueue_drain_all(pdata->dev_workqueue);
1624 hw_if->disable_tx(pdata);
1625 hw_if->disable_rx(pdata);
1627 phy_if->phy_stop(pdata);
1629 ret = hw_if->exit(pdata);
1631 axgbe_error("%s: exit error %d\n", __func__, ret);
1633 set_bit(XGBE_DOWN, &pdata->dev_state);
1637 axgbe_if_stop(if_ctx_t ctx)
1639 axgbe_pci_stop(ctx);
1643 axgbe_if_disable_intr(if_ctx_t ctx)
1645 /* TODO - implement */
1649 axgbe_if_enable_intr(if_ctx_t ctx)
1651 /* TODO - implement */
1655 axgbe_if_tx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int ntxqs,
1658 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1659 struct xgbe_prv_data *pdata = &sc->pdata;
1660 if_softc_ctx_t scctx = sc->scctx;
1661 struct xgbe_channel *channel;
1662 struct xgbe_ring *tx_ring;
1665 MPASS(scctx->isc_ntxqsets > 0);
1666 MPASS(scctx->isc_ntxqsets == ntxqsets);
1669 axgbe_printf(1, "%s: txqsets %d/%d txqs %d\n", __func__,
1670 scctx->isc_ntxqsets, ntxqsets, ntxqs);
1672 for (i = 0 ; i < ntxqsets; i++) {
1674 channel = pdata->channel[i];
1676 tx_ring = (struct xgbe_ring*)malloc(ntxqs *
1677 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1679 if (tx_ring == NULL) {
1680 axgbe_error("Unable to allocate TX ring memory\n");
1684 channel->tx_ring = tx_ring;
1686 for (j = 0; j < ntxqs; j++, tx_ring++) {
1688 (struct xgbe_ring_data*)malloc(scctx->isc_ntxd[j] *
1689 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1691 /* Get the virtual & physical address of hw queues */
1692 tx_ring->rdesc = (struct xgbe_ring_desc *)va[i*ntxqs + j];
1693 tx_ring->rdesc_paddr = pa[i*ntxqs + j];
1694 tx_ring->rdesc_count = scctx->isc_ntxd[j];
1695 spin_lock_init(&tx_ring->lock);
1699 axgbe_printf(1, "allocated for %d tx queues\n", scctx->isc_ntxqsets);
1705 for (j = 0; j < i ; j++) {
1707 channel = pdata->channel[j];
1709 tx_ring = channel->tx_ring;
1710 for (k = 0; k < ntxqs ; k++, tx_ring++) {
1711 if (tx_ring && tx_ring->rdata)
1712 free(tx_ring->rdata, M_AXGBE);
1714 free(channel->tx_ring, M_AXGBE);
1716 channel->tx_ring = NULL;
1721 } /* axgbe_if_tx_queues_alloc */
1724 axgbe_if_rx_queues_alloc(if_ctx_t ctx, caddr_t *va, uint64_t *pa, int nrxqs,
1727 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1728 struct xgbe_prv_data *pdata = &sc->pdata;
1729 if_softc_ctx_t scctx = sc->scctx;
1730 struct xgbe_channel *channel;
1731 struct xgbe_ring *rx_ring;
1734 MPASS(scctx->isc_nrxqsets > 0);
1735 MPASS(scctx->isc_nrxqsets == nrxqsets);
1736 if (!pdata->sph_enable) {
1742 axgbe_printf(1, "%s: rxqsets %d/%d rxqs %d\n", __func__,
1743 scctx->isc_nrxqsets, nrxqsets, nrxqs);
1745 for (i = 0 ; i < nrxqsets; i++) {
1747 channel = pdata->channel[i];
1749 rx_ring = (struct xgbe_ring*)malloc(nrxqs *
1750 sizeof(struct xgbe_ring), M_AXGBE, M_NOWAIT | M_ZERO);
1752 if (rx_ring == NULL) {
1753 axgbe_error("Unable to allocate RX ring memory\n");
1757 channel->rx_ring = rx_ring;
1759 for (j = 0; j < nrxqs; j++, rx_ring++) {
1761 (struct xgbe_ring_data*)malloc(scctx->isc_nrxd[j] *
1762 sizeof(struct xgbe_ring_data), M_AXGBE, M_NOWAIT);
1764 /* Get the virtual and physical address of the hw queues */
1765 rx_ring->rdesc = (struct xgbe_ring_desc *)va[i*nrxqs + j];
1766 rx_ring->rdesc_paddr = pa[i*nrxqs + j];
1767 rx_ring->rdesc_count = scctx->isc_nrxd[j];
1768 spin_lock_init(&rx_ring->lock);
1772 axgbe_printf(2, "allocated for %d rx queues\n", scctx->isc_nrxqsets);
1778 for (j = 0 ; j < i ; j++) {
1780 channel = pdata->channel[j];
1782 rx_ring = channel->rx_ring;
1783 for (k = 0; k < nrxqs ; k++, rx_ring++) {
1784 if (rx_ring && rx_ring->rdata)
1785 free(rx_ring->rdata, M_AXGBE);
1787 free(channel->rx_ring, M_AXGBE);
1789 channel->rx_ring = NULL;
1794 } /* axgbe_if_rx_queues_alloc */
1797 axgbe_if_queues_free(if_ctx_t ctx)
1799 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1800 struct xgbe_prv_data *pdata = &sc->pdata;
1801 if_softc_ctx_t scctx = sc->scctx;
1802 if_shared_ctx_t sctx = sc->sctx;
1803 struct xgbe_channel *channel;
1804 struct xgbe_ring *tx_ring;
1805 struct xgbe_ring *rx_ring;
1808 for (i = 0 ; i < scctx->isc_ntxqsets; i++) {
1810 channel = pdata->channel[i];
1812 tx_ring = channel->tx_ring;
1813 for (j = 0; j < sctx->isc_ntxqs ; j++, tx_ring++) {
1814 if (tx_ring && tx_ring->rdata)
1815 free(tx_ring->rdata, M_AXGBE);
1817 free(channel->tx_ring, M_AXGBE);
1818 channel->tx_ring = NULL;
1821 for (i = 0 ; i < scctx->isc_nrxqsets; i++) {
1823 channel = pdata->channel[i];
1825 rx_ring = channel->rx_ring;
1826 for (j = 0; j < sctx->isc_nrxqs ; j++, rx_ring++) {
1827 if (rx_ring && rx_ring->rdata)
1828 free(rx_ring->rdata, M_AXGBE);
1830 free(channel->rx_ring, M_AXGBE);
1831 channel->rx_ring = NULL;
1834 axgbe_free_channels(sc);
1835 } /* axgbe_if_queues_free */
1838 axgbe_if_vlan_register(if_ctx_t ctx, uint16_t vtag)
1840 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1841 struct xgbe_prv_data *pdata = &sc->pdata;
1842 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1844 if (!bit_test(pdata->active_vlans, vtag)) {
1845 axgbe_printf(0, "Registering VLAN %d\n", vtag);
1847 bit_set(pdata->active_vlans, vtag);
1848 hw_if->update_vlan_hash_table(pdata);
1849 pdata->num_active_vlans++;
1851 axgbe_printf(1, "Total active vlans: %d\n",
1852 pdata->num_active_vlans);
1854 axgbe_printf(0, "VLAN %d already registered\n", vtag);
1856 xgbe_dump_active_vlans(pdata);
1860 axgbe_if_vlan_unregister(if_ctx_t ctx, uint16_t vtag)
1862 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1863 struct xgbe_prv_data *pdata = &sc->pdata;
1864 struct xgbe_hw_if *hw_if = &pdata->hw_if;
1866 if (pdata->num_active_vlans == 0) {
1867 axgbe_printf(1, "No active VLANs to unregister\n");
1871 if (bit_test(pdata->active_vlans, vtag)){
1872 axgbe_printf(0, "Un-Registering VLAN %d\n", vtag);
1874 bit_clear(pdata->active_vlans, vtag);
1875 hw_if->update_vlan_hash_table(pdata);
1876 pdata->num_active_vlans--;
1878 axgbe_printf(1, "Total active vlans: %d\n",
1879 pdata->num_active_vlans);
1881 axgbe_printf(0, "VLAN %d already unregistered\n", vtag);
1883 xgbe_dump_active_vlans(pdata);
1886 #if __FreeBSD_version >= 1300000
1888 axgbe_if_needs_restart(if_ctx_t ctx __unused, enum iflib_restart_event event)
1891 case IFLIB_RESTART_VLAN_CONFIG:
1899 axgbe_if_msix_intr_assign(if_ctx_t ctx, int msix)
1901 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
1902 struct xgbe_prv_data *pdata = &sc->pdata;
1903 if_softc_ctx_t scctx = sc->scctx;
1904 struct xgbe_channel *channel;
1906 int i, error, rid = 0, flags;
1909 MPASS(scctx->isc_intr != IFLIB_INTR_LEGACY);
1911 pdata->isr_as_tasklet = 1;
1913 if (scctx->isc_intr == IFLIB_INTR_MSI) {
1914 pdata->irq_count = 1;
1915 pdata->channel_irq_count = 1;
1919 axgbe_printf(1, "%s: msix %d txqsets %d rxqsets %d\n", __func__, msix,
1920 scctx->isc_ntxqsets, scctx->isc_nrxqsets);
1924 /* DEV INTR SETUP */
1926 error = iflib_irq_alloc_generic(ctx, &pdata->dev_irq, rid,
1927 IFLIB_INTR_ADMIN, axgbe_dev_isr, sc, 0, "dev_irq");
1929 axgbe_error("Failed to register device interrupt rid %d name %s\n",
1934 /* ECC INTR SETUP */
1936 pdata->ecc_rid = rid;
1937 pdata->ecc_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1939 if (!pdata->ecc_irq_res) {
1940 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1945 error = bus_setup_intr(pdata->dev, pdata->ecc_irq_res, INTR_MPSAFE |
1946 INTR_TYPE_NET, NULL, axgbe_ecc_isr, sc, &pdata->ecc_irq_tag);
1948 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1949 rid, "ecc_irq", error);
1953 /* I2C INTR SETUP */
1955 pdata->i2c_rid = rid;
1956 pdata->i2c_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1958 if (!pdata->i2c_irq_res) {
1959 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1964 error = bus_setup_intr(pdata->dev, pdata->i2c_irq_res, INTR_MPSAFE |
1965 INTR_TYPE_NET, NULL, axgbe_i2c_isr, sc, &pdata->i2c_irq_tag);
1967 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1968 rid, "i2c_irq", error);
1974 pdata->an_rid = rid;
1975 pdata->an_irq_res = bus_alloc_resource_any(pdata->dev, SYS_RES_IRQ,
1977 if (!pdata->an_irq_res) {
1978 axgbe_error("failed to allocate IRQ for rid %d, name %s.\n",
1983 error = bus_setup_intr(pdata->dev, pdata->an_irq_res, INTR_MPSAFE |
1984 INTR_TYPE_NET, NULL, axgbe_an_isr, sc, &pdata->an_irq_tag);
1986 axgbe_error("failed to setup interrupt for rid %d, name %s: %d\n",
1987 rid, "an_irq", error);
1991 pdata->per_channel_irq = 1;
1992 pdata->channel_irq_mode = XGBE_IRQ_MODE_LEVEL;
1994 for (i = 0; i < scctx->isc_nrxqsets; i++, rid++) {
1996 channel = pdata->channel[i];
1998 snprintf(buf, sizeof(buf), "rxq%d", i);
1999 error = iflib_irq_alloc_generic(ctx, &irq, rid, IFLIB_INTR_RXTX,
2000 axgbe_msix_que, channel, channel->queue_index, buf);
2003 axgbe_error("Failed to allocated que int %d err: %d\n",
2008 channel->dma_irq_rid = rid;
2009 channel->dma_irq_res = irq.ii_res;
2010 channel->dma_irq_tag = irq.ii_tag;
2011 axgbe_printf(1, "%s: channel count %d idx %d irq %d\n",
2012 __func__, scctx->isc_nrxqsets, i, rid);
2014 pdata->irq_count = msix;
2015 pdata->channel_irq_count = scctx->isc_nrxqsets;
2017 for (i = 0; i < scctx->isc_ntxqsets; i++) {
2019 channel = pdata->channel[i];
2021 snprintf(buf, sizeof(buf), "txq%d", i);
2022 irq.ii_res = channel->dma_irq_res;
2023 iflib_softirq_alloc_generic(ctx, &irq, IFLIB_INTR_TX, channel,
2024 channel->queue_index, buf);
2028 } /* axgbe_if_msix_intr_assign */
2031 xgbe_enable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2033 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2034 enum xgbe_int int_id;
2036 if (channel->tx_ring && channel->rx_ring)
2037 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
2038 else if (channel->tx_ring)
2039 int_id = XGMAC_INT_DMA_CH_SR_TI;
2040 else if (channel->rx_ring)
2041 int_id = XGMAC_INT_DMA_CH_SR_RI;
2045 axgbe_printf(1, "%s channel: %d rx_tx interrupt enabled %d\n",
2046 __func__, channel->queue_index, int_id);
2047 return (hw_if->enable_int(channel, int_id));
2051 xgbe_disable_rx_tx_int(struct xgbe_prv_data *pdata, struct xgbe_channel *channel)
2053 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2054 enum xgbe_int int_id;
2056 if (channel->tx_ring && channel->rx_ring)
2057 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
2058 else if (channel->tx_ring)
2059 int_id = XGMAC_INT_DMA_CH_SR_TI;
2060 else if (channel->rx_ring)
2061 int_id = XGMAC_INT_DMA_CH_SR_RI;
2065 axgbe_printf(1, "%s channel: %d rx_tx interrupt disabled %d\n",
2066 __func__, channel->queue_index, int_id);
2067 hw_if->disable_int(channel, int_id);
2071 xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
2075 for (i = 0; i < pdata->channel_count; i++)
2076 xgbe_disable_rx_tx_int(pdata, pdata->channel[i]);
2080 axgbe_msix_que(void *arg)
2082 struct xgbe_channel *channel = (struct xgbe_channel *)arg;
2083 struct xgbe_prv_data *pdata = channel->pdata;
2084 unsigned int dma_status;
2086 axgbe_printf(1, "%s: Channel: %d SR 0x%04x DSR 0x%04x IER:0x%04x D_ISR:0x%04x M_ISR:0x%04x\n",
2087 __func__, channel->queue_index,
2088 XGMAC_DMA_IOREAD(channel, DMA_CH_SR),
2089 XGMAC_DMA_IOREAD(channel, DMA_CH_DSR),
2090 XGMAC_DMA_IOREAD(channel, DMA_CH_IER),
2091 XGMAC_IOREAD(pdata, DMA_ISR),
2092 XGMAC_IOREAD(pdata, MAC_ISR));
2094 (void)XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2096 /* Disable Tx and Rx channel interrupts */
2097 xgbe_disable_rx_tx_int(pdata, channel);
2099 /* Clear the interrupts */
2101 XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
2102 XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
2103 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_status);
2105 return (FILTER_SCHEDULE_THREAD);
2109 axgbe_dev_isr(void *arg)
2111 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2112 struct xgbe_prv_data *pdata = &sc->pdata;
2113 struct xgbe_channel *channel;
2114 struct xgbe_hw_if *hw_if = &pdata->hw_if;
2115 unsigned int i, dma_isr, dma_ch_isr;
2116 unsigned int mac_isr, mac_mdioisr;
2117 int ret = FILTER_HANDLED;
2119 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
2120 axgbe_printf(2, "%s DMA ISR: 0x%x\n", __func__, dma_isr);
2123 return (FILTER_HANDLED);
2125 for (i = 0; i < pdata->channel_count; i++) {
2127 if (!(dma_isr & (1 << i)))
2130 channel = pdata->channel[i];
2132 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
2133 axgbe_printf(2, "%s: channel %d SR 0x%x DSR 0x%x\n", __func__,
2134 channel->queue_index, dma_ch_isr, XGMAC_DMA_IOREAD(channel,
2138 * The TI or RI interrupt bits may still be set even if using
2139 * per channel DMA interrupts. Check to be sure those are not
2140 * enabled before using the private data napi structure.
2142 if (!pdata->per_channel_irq &&
2143 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
2144 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
2146 /* Disable Tx and Rx interrupts */
2147 xgbe_disable_rx_tx_ints(pdata);
2151 * Don't clear Rx/Tx status if doing per channel DMA
2152 * interrupts, these will be cleared by the ISR for
2153 * per channel DMA interrupts
2155 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
2156 XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
2159 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
2160 pdata->ext_stats.rx_buffer_unavailable++;
2162 /* Restart the device on a Fatal Bus Error */
2163 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
2164 axgbe_error("%s: Fatal bus error reported 0x%x\n",
2165 __func__, dma_ch_isr);
2167 /* Clear all interrupt signals */
2168 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
2170 ret = FILTER_SCHEDULE_THREAD;
2173 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
2175 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
2176 axgbe_printf(2, "%s MAC ISR: 0x%x\n", __func__, mac_isr);
2178 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
2179 hw_if->tx_mmc_int(pdata);
2181 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
2182 hw_if->rx_mmc_int(pdata);
2184 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, SMI)) {
2185 mac_mdioisr = XGMAC_IOREAD(pdata, MAC_MDIOISR);
2187 if (XGMAC_GET_BITS(mac_mdioisr, MAC_MDIOISR,
2195 } /* axgbe_dev_isr */
2198 axgbe_i2c_isr(void *arg)
2200 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2202 sc->pdata.i2c_if.i2c_isr(&sc->pdata);
2206 axgbe_ecc_isr(void *arg)
2208 /* TODO - implement */
2212 axgbe_an_isr(void *arg)
2214 struct axgbe_if_softc *sc = (struct axgbe_if_softc *)arg;
2216 sc->pdata.phy_if.an_isr(&sc->pdata);
2220 axgbe_if_tx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2222 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2223 struct xgbe_prv_data *pdata = &sc->pdata;
2226 if (qid < pdata->tx_q_count) {
2227 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2229 axgbe_error("Enable TX INT failed\n");
2233 axgbe_error("Queue ID exceed channel count\n");
2239 axgbe_if_rx_queue_intr_enable(if_ctx_t ctx, uint16_t qid)
2241 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2242 struct xgbe_prv_data *pdata = &sc->pdata;
2245 if (qid < pdata->rx_q_count) {
2246 ret = xgbe_enable_rx_tx_int(pdata, pdata->channel[qid]);
2248 axgbe_error("Enable RX INT failed\n");
2252 axgbe_error("Queue ID exceed channel count\n");
2258 axgbe_if_update_admin_status(if_ctx_t ctx)
2260 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2261 struct xgbe_prv_data *pdata = &sc->pdata;
2263 axgbe_printf(1, "%s: phy_link %d status %d speed %d\n", __func__,
2264 pdata->phy_link, sc->link_status, pdata->phy.speed);
2266 if (pdata->phy_link < 0)
2269 if (pdata->phy_link) {
2270 if (sc->link_status == LINK_STATE_DOWN) {
2271 sc->link_status = LINK_STATE_UP;
2272 if (pdata->phy.speed & SPEED_10000)
2273 iflib_link_state_change(ctx, LINK_STATE_UP,
2275 else if (pdata->phy.speed & SPEED_2500)
2276 iflib_link_state_change(ctx, LINK_STATE_UP,
2278 else if (pdata->phy.speed & SPEED_1000)
2279 iflib_link_state_change(ctx, LINK_STATE_UP,
2281 else if (pdata->phy.speed & SPEED_100)
2282 iflib_link_state_change(ctx, LINK_STATE_UP,
2284 else if (pdata->phy.speed & SPEED_10)
2285 iflib_link_state_change(ctx, LINK_STATE_UP,
2289 if (sc->link_status == LINK_STATE_UP) {
2290 sc->link_status = LINK_STATE_DOWN;
2291 iflib_link_state_change(ctx, LINK_STATE_DOWN, 0);
2297 axgbe_if_media_change(if_ctx_t ctx)
2299 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2300 struct ifmedia *ifm = iflib_get_media(ctx);
2302 sx_xlock(&sc->pdata.an_mutex);
2303 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2306 switch (IFM_SUBTYPE(ifm->ifm_media)) {
2308 sc->pdata.phy.speed = SPEED_10000;
2309 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2312 sc->pdata.phy.speed = SPEED_2500;
2313 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2316 sc->pdata.phy.speed = SPEED_1000;
2317 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2320 sc->pdata.phy.speed = SPEED_100;
2321 sc->pdata.phy.autoneg = AUTONEG_DISABLE;
2324 sc->pdata.phy.autoneg = AUTONEG_ENABLE;
2327 sx_xunlock(&sc->pdata.an_mutex);
2329 return (-sc->pdata.phy_if.phy_config_aneg(&sc->pdata));
2333 axgbe_if_promisc_set(if_ctx_t ctx, int flags)
2335 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2336 struct xgbe_prv_data *pdata = &sc->pdata;
2337 struct ifnet *ifp = pdata->netdev;
2339 axgbe_printf(1, "%s: MAC_PFR 0x%x drv_flags 0x%x if_flags 0x%x\n",
2340 __func__, XGMAC_IOREAD(pdata, MAC_PFR), ifp->if_drv_flags, ifp->if_flags);
2342 if (ifp->if_flags & IFF_PPROMISC) {
2344 axgbe_printf(1, "User requested to enter promisc mode\n");
2346 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 1) {
2347 axgbe_printf(1, "Already in promisc mode\n");
2351 axgbe_printf(1, "Entering promisc mode\n");
2352 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 1);
2353 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
2356 axgbe_printf(1, "User requested to leave promisc mode\n");
2358 if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == 0) {
2359 axgbe_printf(1, "Already not in promisc mode\n");
2363 axgbe_printf(1, "Leaving promisc mode\n");
2364 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, 0);
2365 XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
2372 axgbe_if_get_counter(if_ctx_t ctx, ift_counter cnt)
2374 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2375 struct ifnet *ifp = iflib_get_ifp(ctx);
2376 struct xgbe_prv_data *pdata = &sc->pdata;
2377 struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
2379 pdata->hw_if.read_mmc_stats(pdata);
2382 case IFCOUNTER_IPACKETS:
2383 return (pstats->rxframecount_gb);
2384 case IFCOUNTER_IERRORS:
2385 return (pstats->rxframecount_gb - pstats->rxbroadcastframes_g -
2386 pstats->rxmulticastframes_g - pstats->rxunicastframes_g);
2387 case IFCOUNTER_OPACKETS:
2388 return (pstats->txframecount_gb);
2389 case IFCOUNTER_OERRORS:
2390 return (pstats->txframecount_gb - pstats->txframecount_g);
2391 case IFCOUNTER_IBYTES:
2392 return (pstats->rxoctetcount_gb);
2393 case IFCOUNTER_OBYTES:
2394 return (pstats->txoctetcount_gb);
2396 return (if_get_counter_default(ifp, cnt));
2401 axgbe_if_mtu_set(if_ctx_t ctx, uint32_t mtu)
2403 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2404 struct xgbe_prv_data *pdata = &sc->pdata;
2407 if (mtu > XGMAC_JUMBO_PACKET_MTU)
2410 ret = xgbe_calc_rx_buf_size(pdata->netdev, mtu);
2411 pdata->rx_buf_size = ret;
2412 axgbe_printf(1, "%s: rx_buf_size %d\n", __func__, ret);
2414 sc->scctx->isc_max_frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2419 axgbe_if_media_status(if_ctx_t ctx, struct ifmediareq * ifmr)
2421 struct axgbe_if_softc *sc = iflib_get_softc(ctx);
2422 struct xgbe_prv_data *pdata = &sc->pdata;
2424 ifmr->ifm_status = IFM_AVALID;
2425 if (!sc->pdata.phy.link)
2428 ifmr->ifm_active = IFM_ETHER;
2429 ifmr->ifm_status |= IFM_ACTIVE;
2431 axgbe_printf(1, "Speed 0x%x Mode %d\n", sc->pdata.phy.speed,
2432 pdata->phy_if.phy_impl.cur_mode(pdata));
2433 pdata->phy_if.phy_impl.get_type(pdata, ifmr);
2435 ifmr->ifm_active |= IFM_FDX;
2436 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2437 ifmr->ifm_active |= IFM_ETH_RXPAUSE;