2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
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74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
119 #ifndef __XGBE_COMMON_H__
120 #define __XGBE_COMMON_H__
123 #include <sys/rman.h>
125 /* DMA register offsets */
126 #define DMA_MR 0x3000
127 #define DMA_SBMR 0x3004
128 #define DMA_ISR 0x3008
129 #define DMA_AXIARCR 0x3010
130 #define DMA_AXIAWCR 0x3018
131 #define DMA_DSR0 0x3020
132 #define DMA_DSR1 0x3024
134 /* DMA register entry bit positions and sizes */
135 #define DMA_AXIARCR_DRC_INDEX 0
136 #define DMA_AXIARCR_DRC_WIDTH 4
137 #define DMA_AXIARCR_DRD_INDEX 4
138 #define DMA_AXIARCR_DRD_WIDTH 2
139 #define DMA_AXIARCR_TEC_INDEX 8
140 #define DMA_AXIARCR_TEC_WIDTH 4
141 #define DMA_AXIARCR_TED_INDEX 12
142 #define DMA_AXIARCR_TED_WIDTH 2
143 #define DMA_AXIARCR_THC_INDEX 16
144 #define DMA_AXIARCR_THC_WIDTH 4
145 #define DMA_AXIARCR_THD_INDEX 20
146 #define DMA_AXIARCR_THD_WIDTH 2
147 #define DMA_AXIAWCR_DWC_INDEX 0
148 #define DMA_AXIAWCR_DWC_WIDTH 4
149 #define DMA_AXIAWCR_DWD_INDEX 4
150 #define DMA_AXIAWCR_DWD_WIDTH 2
151 #define DMA_AXIAWCR_RPC_INDEX 8
152 #define DMA_AXIAWCR_RPC_WIDTH 4
153 #define DMA_AXIAWCR_RPD_INDEX 12
154 #define DMA_AXIAWCR_RPD_WIDTH 2
155 #define DMA_AXIAWCR_RHC_INDEX 16
156 #define DMA_AXIAWCR_RHC_WIDTH 4
157 #define DMA_AXIAWCR_RHD_INDEX 20
158 #define DMA_AXIAWCR_RHD_WIDTH 2
159 #define DMA_AXIAWCR_TDC_INDEX 24
160 #define DMA_AXIAWCR_TDC_WIDTH 4
161 #define DMA_AXIAWCR_TDD_INDEX 28
162 #define DMA_AXIAWCR_TDD_WIDTH 2
163 #define DMA_ISR_MACIS_INDEX 17
164 #define DMA_ISR_MACIS_WIDTH 1
165 #define DMA_ISR_MTLIS_INDEX 16
166 #define DMA_ISR_MTLIS_WIDTH 1
167 #define DMA_MR_SWR_INDEX 0
168 #define DMA_MR_SWR_WIDTH 1
169 #define DMA_SBMR_EAME_INDEX 11
170 #define DMA_SBMR_EAME_WIDTH 1
171 #define DMA_SBMR_BLEN_256_INDEX 7
172 #define DMA_SBMR_BLEN_256_WIDTH 1
173 #define DMA_SBMR_UNDEF_INDEX 0
174 #define DMA_SBMR_UNDEF_WIDTH 1
176 /* DMA register values */
177 #define DMA_DSR_RPS_WIDTH 4
178 #define DMA_DSR_TPS_WIDTH 4
179 #define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH)
180 #define DMA_DSR0_RPS_START 8
181 #define DMA_DSR0_TPS_START 12
182 #define DMA_DSRX_FIRST_QUEUE 3
183 #define DMA_DSRX_INC 4
184 #define DMA_DSRX_QPR 4
185 #define DMA_DSRX_RPS_START 0
186 #define DMA_DSRX_TPS_START 4
187 #define DMA_TPS_STOPPED 0x00
188 #define DMA_TPS_SUSPENDED 0x06
190 /* DMA channel register offsets
191 * Multiple channels can be active. The first channel has registers
192 * that begin at 0x3100. Each subsequent channel has registers that
193 * are accessed using an offset of 0x80 from the previous channel.
195 #define DMA_CH_BASE 0x3100
196 #define DMA_CH_INC 0x80
198 #define DMA_CH_CR 0x00
199 #define DMA_CH_TCR 0x04
200 #define DMA_CH_RCR 0x08
201 #define DMA_CH_TDLR_HI 0x10
202 #define DMA_CH_TDLR_LO 0x14
203 #define DMA_CH_RDLR_HI 0x18
204 #define DMA_CH_RDLR_LO 0x1c
205 #define DMA_CH_TDTR_LO 0x24
206 #define DMA_CH_RDTR_LO 0x2c
207 #define DMA_CH_TDRLR 0x30
208 #define DMA_CH_RDRLR 0x34
209 #define DMA_CH_IER 0x38
210 #define DMA_CH_RIWT 0x3c
211 #define DMA_CH_CATDR_LO 0x44
212 #define DMA_CH_CARDR_LO 0x4c
213 #define DMA_CH_CATBR_HI 0x50
214 #define DMA_CH_CATBR_LO 0x54
215 #define DMA_CH_CARBR_HI 0x58
216 #define DMA_CH_CARBR_LO 0x5c
217 #define DMA_CH_SR 0x60
219 /* DMA channel register entry bit positions and sizes */
220 #define DMA_CH_CR_PBLX8_INDEX 16
221 #define DMA_CH_CR_PBLX8_WIDTH 1
222 #define DMA_CH_CR_SPH_INDEX 24
223 #define DMA_CH_CR_SPH_WIDTH 1
224 #define DMA_CH_IER_AIE_INDEX 15
225 #define DMA_CH_IER_AIE_WIDTH 1
226 #define DMA_CH_IER_FBEE_INDEX 12
227 #define DMA_CH_IER_FBEE_WIDTH 1
228 #define DMA_CH_IER_NIE_INDEX 16
229 #define DMA_CH_IER_NIE_WIDTH 1
230 #define DMA_CH_IER_RBUE_INDEX 7
231 #define DMA_CH_IER_RBUE_WIDTH 1
232 #define DMA_CH_IER_RIE_INDEX 6
233 #define DMA_CH_IER_RIE_WIDTH 1
234 #define DMA_CH_IER_RSE_INDEX 8
235 #define DMA_CH_IER_RSE_WIDTH 1
236 #define DMA_CH_IER_TBUE_INDEX 2
237 #define DMA_CH_IER_TBUE_WIDTH 1
238 #define DMA_CH_IER_TIE_INDEX 0
239 #define DMA_CH_IER_TIE_WIDTH 1
240 #define DMA_CH_IER_TXSE_INDEX 1
241 #define DMA_CH_IER_TXSE_WIDTH 1
242 #define DMA_CH_RCR_PBL_INDEX 16
243 #define DMA_CH_RCR_PBL_WIDTH 6
244 #define DMA_CH_RCR_RBSZ_INDEX 1
245 #define DMA_CH_RCR_RBSZ_WIDTH 14
246 #define DMA_CH_RCR_SR_INDEX 0
247 #define DMA_CH_RCR_SR_WIDTH 1
248 #define DMA_CH_RIWT_RWT_INDEX 0
249 #define DMA_CH_RIWT_RWT_WIDTH 8
250 #define DMA_CH_SR_FBE_INDEX 12
251 #define DMA_CH_SR_FBE_WIDTH 1
252 #define DMA_CH_SR_RBU_INDEX 7
253 #define DMA_CH_SR_RBU_WIDTH 1
254 #define DMA_CH_SR_RI_INDEX 6
255 #define DMA_CH_SR_RI_WIDTH 1
256 #define DMA_CH_SR_RPS_INDEX 8
257 #define DMA_CH_SR_RPS_WIDTH 1
258 #define DMA_CH_SR_TBU_INDEX 2
259 #define DMA_CH_SR_TBU_WIDTH 1
260 #define DMA_CH_SR_TI_INDEX 0
261 #define DMA_CH_SR_TI_WIDTH 1
262 #define DMA_CH_SR_TPS_INDEX 1
263 #define DMA_CH_SR_TPS_WIDTH 1
264 #define DMA_CH_TCR_OSP_INDEX 4
265 #define DMA_CH_TCR_OSP_WIDTH 1
266 #define DMA_CH_TCR_PBL_INDEX 16
267 #define DMA_CH_TCR_PBL_WIDTH 6
268 #define DMA_CH_TCR_ST_INDEX 0
269 #define DMA_CH_TCR_ST_WIDTH 1
270 #define DMA_CH_TCR_TSE_INDEX 12
271 #define DMA_CH_TCR_TSE_WIDTH 1
273 /* DMA channel register values */
274 #define DMA_OSP_DISABLE 0x00
275 #define DMA_OSP_ENABLE 0x01
280 #define DMA_PBL_16 16
281 #define DMA_PBL_32 32
282 #define DMA_PBL_64 64 /* 8 x 8 */
283 #define DMA_PBL_128 128 /* 8 x 16 */
284 #define DMA_PBL_256 256 /* 8 x 32 */
285 #define DMA_PBL_X8_DISABLE 0x00
286 #define DMA_PBL_X8_ENABLE 0x01
288 /* MAC register offsets */
289 #define MAC_TCR 0x0000
290 #define MAC_RCR 0x0004
291 #define MAC_PFR 0x0008
292 #define MAC_WTR 0x000c
293 #define MAC_HTR0 0x0010
294 #define MAC_VLANTR 0x0050
295 #define MAC_VLANHTR 0x0058
296 #define MAC_VLANIR 0x0060
297 #define MAC_IVLANIR 0x0064
298 #define MAC_RETMR 0x006c
299 #define MAC_Q0TFCR 0x0070
300 #define MAC_RFCR 0x0090
301 #define MAC_RQC0R 0x00a0
302 #define MAC_RQC1R 0x00a4
303 #define MAC_RQC2R 0x00a8
304 #define MAC_RQC3R 0x00ac
305 #define MAC_ISR 0x00b0
306 #define MAC_IER 0x00b4
307 #define MAC_RTSR 0x00b8
308 #define MAC_PMTCSR 0x00c0
309 #define MAC_RWKPFR 0x00c4
310 #define MAC_LPICSR 0x00d0
311 #define MAC_LPITCR 0x00d4
312 #define MAC_VR 0x0110
313 #define MAC_DR 0x0114
314 #define MAC_HWF0R 0x011c
315 #define MAC_HWF1R 0x0120
316 #define MAC_HWF2R 0x0124
317 #define MAC_GPIOCR 0x0278
318 #define MAC_GPIOSR 0x027c
319 #define MAC_MACA0HR 0x0300
320 #define MAC_MACA0LR 0x0304
321 #define MAC_MACA1HR 0x0308
322 #define MAC_MACA1LR 0x030c
323 #define MAC_RSSCR 0x0c80
324 #define MAC_RSSAR 0x0c88
325 #define MAC_RSSDR 0x0c8c
326 #define MAC_TSCR 0x0d00
327 #define MAC_SSIR 0x0d04
328 #define MAC_STSR 0x0d08
329 #define MAC_STNR 0x0d0c
330 #define MAC_STSUR 0x0d10
331 #define MAC_STNUR 0x0d14
332 #define MAC_TSAR 0x0d18
333 #define MAC_TSSR 0x0d20
334 #define MAC_TXSNR 0x0d30
335 #define MAC_TXSSR 0x0d34
337 #define MAC_QTFCR_INC 4
338 #define MAC_MACA_INC 4
339 #define MAC_HTR_INC 4
341 #define MAC_RQC2_INC 4
342 #define MAC_RQC2_Q_PER_REG 4
344 /* MAC register entry bit positions and sizes */
345 #define MAC_HWF0R_ADDMACADRSEL_INDEX 18
346 #define MAC_HWF0R_ADDMACADRSEL_WIDTH 5
347 #define MAC_HWF0R_ARPOFFSEL_INDEX 9
348 #define MAC_HWF0R_ARPOFFSEL_WIDTH 1
349 #define MAC_HWF0R_EEESEL_INDEX 13
350 #define MAC_HWF0R_EEESEL_WIDTH 1
351 #define MAC_HWF0R_GMIISEL_INDEX 1
352 #define MAC_HWF0R_GMIISEL_WIDTH 1
353 #define MAC_HWF0R_MGKSEL_INDEX 7
354 #define MAC_HWF0R_MGKSEL_WIDTH 1
355 #define MAC_HWF0R_MMCSEL_INDEX 8
356 #define MAC_HWF0R_MMCSEL_WIDTH 1
357 #define MAC_HWF0R_RWKSEL_INDEX 6
358 #define MAC_HWF0R_RWKSEL_WIDTH 1
359 #define MAC_HWF0R_RXCOESEL_INDEX 16
360 #define MAC_HWF0R_RXCOESEL_WIDTH 1
361 #define MAC_HWF0R_SAVLANINS_INDEX 27
362 #define MAC_HWF0R_SAVLANINS_WIDTH 1
363 #define MAC_HWF0R_SMASEL_INDEX 5
364 #define MAC_HWF0R_SMASEL_WIDTH 1
365 #define MAC_HWF0R_TSSEL_INDEX 12
366 #define MAC_HWF0R_TSSEL_WIDTH 1
367 #define MAC_HWF0R_TSSTSSEL_INDEX 25
368 #define MAC_HWF0R_TSSTSSEL_WIDTH 2
369 #define MAC_HWF0R_TXCOESEL_INDEX 14
370 #define MAC_HWF0R_TXCOESEL_WIDTH 1
371 #define MAC_HWF0R_VLHASH_INDEX 4
372 #define MAC_HWF0R_VLHASH_WIDTH 1
373 #define MAC_HWF1R_ADDR64_INDEX 14
374 #define MAC_HWF1R_ADDR64_WIDTH 2
375 #define MAC_HWF1R_ADVTHWORD_INDEX 13
376 #define MAC_HWF1R_ADVTHWORD_WIDTH 1
377 #define MAC_HWF1R_DBGMEMA_INDEX 19
378 #define MAC_HWF1R_DBGMEMA_WIDTH 1
379 #define MAC_HWF1R_DCBEN_INDEX 16
380 #define MAC_HWF1R_DCBEN_WIDTH 1
381 #define MAC_HWF1R_HASHTBLSZ_INDEX 24
382 #define MAC_HWF1R_HASHTBLSZ_WIDTH 3
383 #define MAC_HWF1R_L3L4FNUM_INDEX 27
384 #define MAC_HWF1R_L3L4FNUM_WIDTH 4
385 #define MAC_HWF1R_NUMTC_INDEX 21
386 #define MAC_HWF1R_NUMTC_WIDTH 3
387 #define MAC_HWF1R_RSSEN_INDEX 20
388 #define MAC_HWF1R_RSSEN_WIDTH 1
389 #define MAC_HWF1R_RXFIFOSIZE_INDEX 0
390 #define MAC_HWF1R_RXFIFOSIZE_WIDTH 5
391 #define MAC_HWF1R_SPHEN_INDEX 17
392 #define MAC_HWF1R_SPHEN_WIDTH 1
393 #define MAC_HWF1R_TSOEN_INDEX 18
394 #define MAC_HWF1R_TSOEN_WIDTH 1
395 #define MAC_HWF1R_TXFIFOSIZE_INDEX 6
396 #define MAC_HWF1R_TXFIFOSIZE_WIDTH 5
397 #define MAC_HWF2R_AUXSNAPNUM_INDEX 28
398 #define MAC_HWF2R_AUXSNAPNUM_WIDTH 3
399 #define MAC_HWF2R_PPSOUTNUM_INDEX 24
400 #define MAC_HWF2R_PPSOUTNUM_WIDTH 3
401 #define MAC_HWF2R_RXCHCNT_INDEX 12
402 #define MAC_HWF2R_RXCHCNT_WIDTH 4
403 #define MAC_HWF2R_RXQCNT_INDEX 0
404 #define MAC_HWF2R_RXQCNT_WIDTH 4
405 #define MAC_HWF2R_TXCHCNT_INDEX 18
406 #define MAC_HWF2R_TXCHCNT_WIDTH 4
407 #define MAC_HWF2R_TXQCNT_INDEX 6
408 #define MAC_HWF2R_TXQCNT_WIDTH 4
409 #define MAC_IER_TSIE_INDEX 12
410 #define MAC_IER_TSIE_WIDTH 1
411 #define MAC_ISR_MMCRXIS_INDEX 9
412 #define MAC_ISR_MMCRXIS_WIDTH 1
413 #define MAC_ISR_MMCTXIS_INDEX 10
414 #define MAC_ISR_MMCTXIS_WIDTH 1
415 #define MAC_ISR_PMTIS_INDEX 4
416 #define MAC_ISR_PMTIS_WIDTH 1
417 #define MAC_ISR_TSIS_INDEX 12
418 #define MAC_ISR_TSIS_WIDTH 1
419 #define MAC_MACA1HR_AE_INDEX 31
420 #define MAC_MACA1HR_AE_WIDTH 1
421 #define MAC_PFR_HMC_INDEX 2
422 #define MAC_PFR_HMC_WIDTH 1
423 #define MAC_PFR_HPF_INDEX 10
424 #define MAC_PFR_HPF_WIDTH 1
425 #define MAC_PFR_HUC_INDEX 1
426 #define MAC_PFR_HUC_WIDTH 1
427 #define MAC_PFR_PM_INDEX 4
428 #define MAC_PFR_PM_WIDTH 1
429 #define MAC_PFR_PR_INDEX 0
430 #define MAC_PFR_PR_WIDTH 1
431 #define MAC_PFR_VTFE_INDEX 16
432 #define MAC_PFR_VTFE_WIDTH 1
433 #define MAC_PMTCSR_MGKPKTEN_INDEX 1
434 #define MAC_PMTCSR_MGKPKTEN_WIDTH 1
435 #define MAC_PMTCSR_PWRDWN_INDEX 0
436 #define MAC_PMTCSR_PWRDWN_WIDTH 1
437 #define MAC_PMTCSR_RWKFILTRST_INDEX 31
438 #define MAC_PMTCSR_RWKFILTRST_WIDTH 1
439 #define MAC_PMTCSR_RWKPKTEN_INDEX 2
440 #define MAC_PMTCSR_RWKPKTEN_WIDTH 1
441 #define MAC_Q0TFCR_PT_INDEX 16
442 #define MAC_Q0TFCR_PT_WIDTH 16
443 #define MAC_Q0TFCR_TFE_INDEX 1
444 #define MAC_Q0TFCR_TFE_WIDTH 1
445 #define MAC_RCR_ACS_INDEX 1
446 #define MAC_RCR_ACS_WIDTH 1
447 #define MAC_RCR_CST_INDEX 2
448 #define MAC_RCR_CST_WIDTH 1
449 #define MAC_RCR_DCRCC_INDEX 3
450 #define MAC_RCR_DCRCC_WIDTH 1
451 #define MAC_RCR_HDSMS_INDEX 12
452 #define MAC_RCR_HDSMS_WIDTH 3
453 #define MAC_RCR_IPC_INDEX 9
454 #define MAC_RCR_IPC_WIDTH 1
455 #define MAC_RCR_JE_INDEX 8
456 #define MAC_RCR_JE_WIDTH 1
457 #define MAC_RCR_LM_INDEX 10
458 #define MAC_RCR_LM_WIDTH 1
459 #define MAC_RCR_RE_INDEX 0
460 #define MAC_RCR_RE_WIDTH 1
461 #define MAC_RFCR_PFCE_INDEX 8
462 #define MAC_RFCR_PFCE_WIDTH 1
463 #define MAC_RFCR_RFE_INDEX 0
464 #define MAC_RFCR_RFE_WIDTH 1
465 #define MAC_RFCR_UP_INDEX 1
466 #define MAC_RFCR_UP_WIDTH 1
467 #define MAC_RQC0R_RXQ0EN_INDEX 0
468 #define MAC_RQC0R_RXQ0EN_WIDTH 2
469 #define MAC_RSSAR_ADDRT_INDEX 2
470 #define MAC_RSSAR_ADDRT_WIDTH 1
471 #define MAC_RSSAR_CT_INDEX 1
472 #define MAC_RSSAR_CT_WIDTH 1
473 #define MAC_RSSAR_OB_INDEX 0
474 #define MAC_RSSAR_OB_WIDTH 1
475 #define MAC_RSSAR_RSSIA_INDEX 8
476 #define MAC_RSSAR_RSSIA_WIDTH 8
477 #define MAC_RSSCR_IP2TE_INDEX 1
478 #define MAC_RSSCR_IP2TE_WIDTH 1
479 #define MAC_RSSCR_RSSE_INDEX 0
480 #define MAC_RSSCR_RSSE_WIDTH 1
481 #define MAC_RSSCR_TCP4TE_INDEX 2
482 #define MAC_RSSCR_TCP4TE_WIDTH 1
483 #define MAC_RSSCR_UDP4TE_INDEX 3
484 #define MAC_RSSCR_UDP4TE_WIDTH 1
485 #define MAC_RSSDR_DMCH_INDEX 0
486 #define MAC_RSSDR_DMCH_WIDTH 4
487 #define MAC_SSIR_SNSINC_INDEX 8
488 #define MAC_SSIR_SNSINC_WIDTH 8
489 #define MAC_SSIR_SSINC_INDEX 16
490 #define MAC_SSIR_SSINC_WIDTH 8
491 #define MAC_TCR_SS_INDEX 29
492 #define MAC_TCR_SS_WIDTH 2
493 #define MAC_TCR_TE_INDEX 0
494 #define MAC_TCR_TE_WIDTH 1
495 #define MAC_TSCR_AV8021ASMEN_INDEX 28
496 #define MAC_TSCR_AV8021ASMEN_WIDTH 1
497 #define MAC_TSCR_SNAPTYPSEL_INDEX 16
498 #define MAC_TSCR_SNAPTYPSEL_WIDTH 2
499 #define MAC_TSCR_TSADDREG_INDEX 5
500 #define MAC_TSCR_TSADDREG_WIDTH 1
501 #define MAC_TSCR_TSCFUPDT_INDEX 1
502 #define MAC_TSCR_TSCFUPDT_WIDTH 1
503 #define MAC_TSCR_TSCTRLSSR_INDEX 9
504 #define MAC_TSCR_TSCTRLSSR_WIDTH 1
505 #define MAC_TSCR_TSENA_INDEX 0
506 #define MAC_TSCR_TSENA_WIDTH 1
507 #define MAC_TSCR_TSENALL_INDEX 8
508 #define MAC_TSCR_TSENALL_WIDTH 1
509 #define MAC_TSCR_TSEVNTENA_INDEX 14
510 #define MAC_TSCR_TSEVNTENA_WIDTH 1
511 #define MAC_TSCR_TSINIT_INDEX 2
512 #define MAC_TSCR_TSINIT_WIDTH 1
513 #define MAC_TSCR_TSIPENA_INDEX 11
514 #define MAC_TSCR_TSIPENA_WIDTH 1
515 #define MAC_TSCR_TSIPV4ENA_INDEX 13
516 #define MAC_TSCR_TSIPV4ENA_WIDTH 1
517 #define MAC_TSCR_TSIPV6ENA_INDEX 12
518 #define MAC_TSCR_TSIPV6ENA_WIDTH 1
519 #define MAC_TSCR_TSMSTRENA_INDEX 15
520 #define MAC_TSCR_TSMSTRENA_WIDTH 1
521 #define MAC_TSCR_TSVER2ENA_INDEX 10
522 #define MAC_TSCR_TSVER2ENA_WIDTH 1
523 #define MAC_TSCR_TXTSSTSM_INDEX 24
524 #define MAC_TSCR_TXTSSTSM_WIDTH 1
525 #define MAC_TSSR_TXTSC_INDEX 15
526 #define MAC_TSSR_TXTSC_WIDTH 1
527 #define MAC_TXSNR_TXTSSTSMIS_INDEX 31
528 #define MAC_TXSNR_TXTSSTSMIS_WIDTH 1
529 #define MAC_VLANHTR_VLHT_INDEX 0
530 #define MAC_VLANHTR_VLHT_WIDTH 16
531 #define MAC_VLANIR_VLTI_INDEX 20
532 #define MAC_VLANIR_VLTI_WIDTH 1
533 #define MAC_VLANIR_CSVL_INDEX 19
534 #define MAC_VLANIR_CSVL_WIDTH 1
535 #define MAC_VLANTR_DOVLTC_INDEX 20
536 #define MAC_VLANTR_DOVLTC_WIDTH 1
537 #define MAC_VLANTR_ERSVLM_INDEX 19
538 #define MAC_VLANTR_ERSVLM_WIDTH 1
539 #define MAC_VLANTR_ESVL_INDEX 18
540 #define MAC_VLANTR_ESVL_WIDTH 1
541 #define MAC_VLANTR_ETV_INDEX 16
542 #define MAC_VLANTR_ETV_WIDTH 1
543 #define MAC_VLANTR_EVLS_INDEX 21
544 #define MAC_VLANTR_EVLS_WIDTH 2
545 #define MAC_VLANTR_EVLRXS_INDEX 24
546 #define MAC_VLANTR_EVLRXS_WIDTH 1
547 #define MAC_VLANTR_VL_INDEX 0
548 #define MAC_VLANTR_VL_WIDTH 16
549 #define MAC_VLANTR_VTHM_INDEX 25
550 #define MAC_VLANTR_VTHM_WIDTH 1
551 #define MAC_VLANTR_VTIM_INDEX 17
552 #define MAC_VLANTR_VTIM_WIDTH 1
553 #define MAC_VR_DEVID_INDEX 8
554 #define MAC_VR_DEVID_WIDTH 8
555 #define MAC_VR_SNPSVER_INDEX 0
556 #define MAC_VR_SNPSVER_WIDTH 8
557 #define MAC_VR_USERVER_INDEX 16
558 #define MAC_VR_USERVER_WIDTH 8
560 /* MMC register offsets */
561 #define MMC_CR 0x0800
562 #define MMC_RISR 0x0804
563 #define MMC_TISR 0x0808
564 #define MMC_RIER 0x080c
565 #define MMC_TIER 0x0810
566 #define MMC_TXOCTETCOUNT_GB_LO 0x0814
567 #define MMC_TXOCTETCOUNT_GB_HI 0x0818
568 #define MMC_TXFRAMECOUNT_GB_LO 0x081c
569 #define MMC_TXFRAMECOUNT_GB_HI 0x0820
570 #define MMC_TXBROADCASTFRAMES_G_LO 0x0824
571 #define MMC_TXBROADCASTFRAMES_G_HI 0x0828
572 #define MMC_TXMULTICASTFRAMES_G_LO 0x082c
573 #define MMC_TXMULTICASTFRAMES_G_HI 0x0830
574 #define MMC_TX64OCTETS_GB_LO 0x0834
575 #define MMC_TX64OCTETS_GB_HI 0x0838
576 #define MMC_TX65TO127OCTETS_GB_LO 0x083c
577 #define MMC_TX65TO127OCTETS_GB_HI 0x0840
578 #define MMC_TX128TO255OCTETS_GB_LO 0x0844
579 #define MMC_TX128TO255OCTETS_GB_HI 0x0848
580 #define MMC_TX256TO511OCTETS_GB_LO 0x084c
581 #define MMC_TX256TO511OCTETS_GB_HI 0x0850
582 #define MMC_TX512TO1023OCTETS_GB_LO 0x0854
583 #define MMC_TX512TO1023OCTETS_GB_HI 0x0858
584 #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c
585 #define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860
586 #define MMC_TXUNICASTFRAMES_GB_LO 0x0864
587 #define MMC_TXUNICASTFRAMES_GB_HI 0x0868
588 #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c
589 #define MMC_TXMULTICASTFRAMES_GB_HI 0x0870
590 #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874
591 #define MMC_TXBROADCASTFRAMES_GB_HI 0x0878
592 #define MMC_TXUNDERFLOWERROR_LO 0x087c
593 #define MMC_TXUNDERFLOWERROR_HI 0x0880
594 #define MMC_TXOCTETCOUNT_G_LO 0x0884
595 #define MMC_TXOCTETCOUNT_G_HI 0x0888
596 #define MMC_TXFRAMECOUNT_G_LO 0x088c
597 #define MMC_TXFRAMECOUNT_G_HI 0x0890
598 #define MMC_TXPAUSEFRAMES_LO 0x0894
599 #define MMC_TXPAUSEFRAMES_HI 0x0898
600 #define MMC_TXVLANFRAMES_G_LO 0x089c
601 #define MMC_TXVLANFRAMES_G_HI 0x08a0
602 #define MMC_RXFRAMECOUNT_GB_LO 0x0900
603 #define MMC_RXFRAMECOUNT_GB_HI 0x0904
604 #define MMC_RXOCTETCOUNT_GB_LO 0x0908
605 #define MMC_RXOCTETCOUNT_GB_HI 0x090c
606 #define MMC_RXOCTETCOUNT_G_LO 0x0910
607 #define MMC_RXOCTETCOUNT_G_HI 0x0914
608 #define MMC_RXBROADCASTFRAMES_G_LO 0x0918
609 #define MMC_RXBROADCASTFRAMES_G_HI 0x091c
610 #define MMC_RXMULTICASTFRAMES_G_LO 0x0920
611 #define MMC_RXMULTICASTFRAMES_G_HI 0x0924
612 #define MMC_RXCRCERROR_LO 0x0928
613 #define MMC_RXCRCERROR_HI 0x092c
614 #define MMC_RXRUNTERROR 0x0930
615 #define MMC_RXJABBERERROR 0x0934
616 #define MMC_RXUNDERSIZE_G 0x0938
617 #define MMC_RXOVERSIZE_G 0x093c
618 #define MMC_RX64OCTETS_GB_LO 0x0940
619 #define MMC_RX64OCTETS_GB_HI 0x0944
620 #define MMC_RX65TO127OCTETS_GB_LO 0x0948
621 #define MMC_RX65TO127OCTETS_GB_HI 0x094c
622 #define MMC_RX128TO255OCTETS_GB_LO 0x0950
623 #define MMC_RX128TO255OCTETS_GB_HI 0x0954
624 #define MMC_RX256TO511OCTETS_GB_LO 0x0958
625 #define MMC_RX256TO511OCTETS_GB_HI 0x095c
626 #define MMC_RX512TO1023OCTETS_GB_LO 0x0960
627 #define MMC_RX512TO1023OCTETS_GB_HI 0x0964
628 #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968
629 #define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c
630 #define MMC_RXUNICASTFRAMES_G_LO 0x0970
631 #define MMC_RXUNICASTFRAMES_G_HI 0x0974
632 #define MMC_RXLENGTHERROR_LO 0x0978
633 #define MMC_RXLENGTHERROR_HI 0x097c
634 #define MMC_RXOUTOFRANGETYPE_LO 0x0980
635 #define MMC_RXOUTOFRANGETYPE_HI 0x0984
636 #define MMC_RXPAUSEFRAMES_LO 0x0988
637 #define MMC_RXPAUSEFRAMES_HI 0x098c
638 #define MMC_RXFIFOOVERFLOW_LO 0x0990
639 #define MMC_RXFIFOOVERFLOW_HI 0x0994
640 #define MMC_RXVLANFRAMES_GB_LO 0x0998
641 #define MMC_RXVLANFRAMES_GB_HI 0x099c
642 #define MMC_RXWATCHDOGERROR 0x09a0
644 /* MMC register entry bit positions and sizes */
645 #define MMC_CR_CR_INDEX 0
646 #define MMC_CR_CR_WIDTH 1
647 #define MMC_CR_CSR_INDEX 1
648 #define MMC_CR_CSR_WIDTH 1
649 #define MMC_CR_ROR_INDEX 2
650 #define MMC_CR_ROR_WIDTH 1
651 #define MMC_CR_MCF_INDEX 3
652 #define MMC_CR_MCF_WIDTH 1
653 #define MMC_CR_MCT_INDEX 4
654 #define MMC_CR_MCT_WIDTH 2
655 #define MMC_RIER_ALL_INTERRUPTS_INDEX 0
656 #define MMC_RIER_ALL_INTERRUPTS_WIDTH 23
657 #define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0
658 #define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1
659 #define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1
660 #define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1
661 #define MMC_RISR_RXOCTETCOUNT_G_INDEX 2
662 #define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1
663 #define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3
664 #define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1
665 #define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4
666 #define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1
667 #define MMC_RISR_RXCRCERROR_INDEX 5
668 #define MMC_RISR_RXCRCERROR_WIDTH 1
669 #define MMC_RISR_RXRUNTERROR_INDEX 6
670 #define MMC_RISR_RXRUNTERROR_WIDTH 1
671 #define MMC_RISR_RXJABBERERROR_INDEX 7
672 #define MMC_RISR_RXJABBERERROR_WIDTH 1
673 #define MMC_RISR_RXUNDERSIZE_G_INDEX 8
674 #define MMC_RISR_RXUNDERSIZE_G_WIDTH 1
675 #define MMC_RISR_RXOVERSIZE_G_INDEX 9
676 #define MMC_RISR_RXOVERSIZE_G_WIDTH 1
677 #define MMC_RISR_RX64OCTETS_GB_INDEX 10
678 #define MMC_RISR_RX64OCTETS_GB_WIDTH 1
679 #define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11
680 #define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1
681 #define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12
682 #define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1
683 #define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13
684 #define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1
685 #define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14
686 #define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1
687 #define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15
688 #define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1
689 #define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16
690 #define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1
691 #define MMC_RISR_RXLENGTHERROR_INDEX 17
692 #define MMC_RISR_RXLENGTHERROR_WIDTH 1
693 #define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18
694 #define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1
695 #define MMC_RISR_RXPAUSEFRAMES_INDEX 19
696 #define MMC_RISR_RXPAUSEFRAMES_WIDTH 1
697 #define MMC_RISR_RXFIFOOVERFLOW_INDEX 20
698 #define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1
699 #define MMC_RISR_RXVLANFRAMES_GB_INDEX 21
700 #define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1
701 #define MMC_RISR_RXWATCHDOGERROR_INDEX 22
702 #define MMC_RISR_RXWATCHDOGERROR_WIDTH 1
703 #define MMC_TIER_ALL_INTERRUPTS_INDEX 0
704 #define MMC_TIER_ALL_INTERRUPTS_WIDTH 18
705 #define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0
706 #define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1
707 #define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1
708 #define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1
709 #define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2
710 #define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1
711 #define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3
712 #define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1
713 #define MMC_TISR_TX64OCTETS_GB_INDEX 4
714 #define MMC_TISR_TX64OCTETS_GB_WIDTH 1
715 #define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5
716 #define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1
717 #define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6
718 #define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1
719 #define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7
720 #define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1
721 #define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8
722 #define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1
723 #define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9
724 #define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1
725 #define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10
726 #define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1
727 #define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11
728 #define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1
729 #define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12
730 #define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1
731 #define MMC_TISR_TXUNDERFLOWERROR_INDEX 13
732 #define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1
733 #define MMC_TISR_TXOCTETCOUNT_G_INDEX 14
734 #define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1
735 #define MMC_TISR_TXFRAMECOUNT_G_INDEX 15
736 #define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1
737 #define MMC_TISR_TXPAUSEFRAMES_INDEX 16
738 #define MMC_TISR_TXPAUSEFRAMES_WIDTH 1
739 #define MMC_TISR_TXVLANFRAMES_G_INDEX 17
740 #define MMC_TISR_TXVLANFRAMES_G_WIDTH 1
742 /* MTL register offsets */
743 #define MTL_OMR 0x1000
744 #define MTL_FDCR 0x1008
745 #define MTL_FDSR 0x100c
746 #define MTL_FDDR 0x1010
747 #define MTL_ISR 0x1020
748 #define MTL_RQDCM0R 0x1030
749 #define MTL_TCPM0R 0x1040
750 #define MTL_TCPM1R 0x1044
752 #define MTL_RQDCM_INC 4
753 #define MTL_RQDCM_Q_PER_REG 4
754 #define MTL_TCPM_INC 4
755 #define MTL_TCPM_TC_PER_REG 4
757 /* MTL register entry bit positions and sizes */
758 #define MTL_OMR_ETSALG_INDEX 5
759 #define MTL_OMR_ETSALG_WIDTH 2
760 #define MTL_OMR_RAA_INDEX 2
761 #define MTL_OMR_RAA_WIDTH 1
763 /* MTL queue register offsets
764 * Multiple queues can be active. The first queue has registers
765 * that begin at 0x1100. Each subsequent queue has registers that
766 * are accessed using an offset of 0x80 from the previous queue.
768 #define MTL_Q_BASE 0x1100
769 #define MTL_Q_INC 0x80
771 #define MTL_Q_TQOMR 0x00
772 #define MTL_Q_TQUR 0x04
773 #define MTL_Q_TQDR 0x08
774 #define MTL_Q_RQOMR 0x40
775 #define MTL_Q_RQMPOCR 0x44
776 #define MTL_Q_RQDR 0x48
777 #define MTL_Q_RQFCR 0x50
778 #define MTL_Q_IER 0x70
779 #define MTL_Q_ISR 0x74
781 /* MTL queue register entry bit positions and sizes */
782 #define MTL_Q_RQDR_PRXQ_INDEX 16
783 #define MTL_Q_RQDR_PRXQ_WIDTH 14
784 #define MTL_Q_RQDR_RXQSTS_INDEX 4
785 #define MTL_Q_RQDR_RXQSTS_WIDTH 2
786 #define MTL_Q_RQFCR_RFA_INDEX 1
787 #define MTL_Q_RQFCR_RFA_WIDTH 6
788 #define MTL_Q_RQFCR_RFD_INDEX 17
789 #define MTL_Q_RQFCR_RFD_WIDTH 6
790 #define MTL_Q_RQOMR_EHFC_INDEX 7
791 #define MTL_Q_RQOMR_EHFC_WIDTH 1
792 #define MTL_Q_RQOMR_RQS_INDEX 16
793 #define MTL_Q_RQOMR_RQS_WIDTH 9
794 #define MTL_Q_RQOMR_RSF_INDEX 5
795 #define MTL_Q_RQOMR_RSF_WIDTH 1
796 #define MTL_Q_RQOMR_RTC_INDEX 0
797 #define MTL_Q_RQOMR_RTC_WIDTH 2
798 #define MTL_Q_TQOMR_FTQ_INDEX 0
799 #define MTL_Q_TQOMR_FTQ_WIDTH 1
800 #define MTL_Q_TQOMR_Q2TCMAP_INDEX 8
801 #define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3
802 #define MTL_Q_TQOMR_TQS_INDEX 16
803 #define MTL_Q_TQOMR_TQS_WIDTH 10
804 #define MTL_Q_TQOMR_TSF_INDEX 1
805 #define MTL_Q_TQOMR_TSF_WIDTH 1
806 #define MTL_Q_TQOMR_TTC_INDEX 4
807 #define MTL_Q_TQOMR_TTC_WIDTH 3
808 #define MTL_Q_TQOMR_TXQEN_INDEX 2
809 #define MTL_Q_TQOMR_TXQEN_WIDTH 2
811 /* MTL queue register value */
812 #define MTL_RSF_DISABLE 0x00
813 #define MTL_RSF_ENABLE 0x01
814 #define MTL_TSF_DISABLE 0x00
815 #define MTL_TSF_ENABLE 0x01
817 #define MTL_RX_THRESHOLD_64 0x00
818 #define MTL_RX_THRESHOLD_96 0x02
819 #define MTL_RX_THRESHOLD_128 0x03
820 #define MTL_TX_THRESHOLD_32 0x01
821 #define MTL_TX_THRESHOLD_64 0x00
822 #define MTL_TX_THRESHOLD_96 0x02
823 #define MTL_TX_THRESHOLD_128 0x03
824 #define MTL_TX_THRESHOLD_192 0x04
825 #define MTL_TX_THRESHOLD_256 0x05
826 #define MTL_TX_THRESHOLD_384 0x06
827 #define MTL_TX_THRESHOLD_512 0x07
829 #define MTL_ETSALG_WRR 0x00
830 #define MTL_ETSALG_WFQ 0x01
831 #define MTL_ETSALG_DWRR 0x02
832 #define MTL_RAA_SP 0x00
833 #define MTL_RAA_WSP 0x01
835 #define MTL_Q_DISABLED 0x00
836 #define MTL_Q_ENABLED 0x02
838 /* MTL traffic class register offsets
839 * Multiple traffic classes can be active. The first class has registers
840 * that begin at 0x1100. Each subsequent queue has registers that
841 * are accessed using an offset of 0x80 from the previous queue.
843 #define MTL_TC_BASE MTL_Q_BASE
844 #define MTL_TC_INC MTL_Q_INC
846 #define MTL_TC_ETSCR 0x10
847 #define MTL_TC_ETSSR 0x14
848 #define MTL_TC_QWR 0x18
850 /* MTL traffic class register entry bit positions and sizes */
851 #define MTL_TC_ETSCR_TSA_INDEX 0
852 #define MTL_TC_ETSCR_TSA_WIDTH 2
853 #define MTL_TC_QWR_QW_INDEX 0
854 #define MTL_TC_QWR_QW_WIDTH 21
856 /* MTL traffic class register value */
857 #define MTL_TSA_SP 0x00
858 #define MTL_TSA_ETS 0x02
860 /* PCS MMD select register offset
861 * The MMD select register is used for accessing PCS registers
862 * when the underlying APB3 interface is using indirect addressing.
863 * Indirect addressing requires accessing registers in two phases,
864 * an address phase and a data phase. The address phases requires
865 * writing an address selection value to the MMD select regiesters.
867 #define PCS_MMD_SELECT 0xff
869 /* SerDes integration register offsets */
870 #define SIR0_KR_RT_1 0x002c
871 #define SIR0_STATUS 0x0040
872 #define SIR1_SPEED 0x0000
874 /* SerDes integration register entry bit positions and sizes */
875 #define SIR0_KR_RT_1_RESET_INDEX 11
876 #define SIR0_KR_RT_1_RESET_WIDTH 1
877 #define SIR0_STATUS_RX_READY_INDEX 0
878 #define SIR0_STATUS_RX_READY_WIDTH 1
879 #define SIR0_STATUS_TX_READY_INDEX 8
880 #define SIR0_STATUS_TX_READY_WIDTH 1
881 #define SIR1_SPEED_CDR_RATE_INDEX 12
882 #define SIR1_SPEED_CDR_RATE_WIDTH 4
883 #define SIR1_SPEED_DATARATE_INDEX 4
884 #define SIR1_SPEED_DATARATE_WIDTH 2
885 #define SIR1_SPEED_PLLSEL_INDEX 3
886 #define SIR1_SPEED_PLLSEL_WIDTH 1
887 #define SIR1_SPEED_RATECHANGE_INDEX 6
888 #define SIR1_SPEED_RATECHANGE_WIDTH 1
889 #define SIR1_SPEED_TXAMP_INDEX 8
890 #define SIR1_SPEED_TXAMP_WIDTH 4
891 #define SIR1_SPEED_WORDMODE_INDEX 0
892 #define SIR1_SPEED_WORDMODE_WIDTH 3
894 /* SerDes RxTx register offsets */
895 #define RXTX_REG6 0x0018
896 #define RXTX_REG20 0x0050
897 #define RXTX_REG22 0x0058
898 #define RXTX_REG114 0x01c8
899 #define RXTX_REG129 0x0204
901 /* SerDes RxTx register entry bit positions and sizes */
902 #define RXTX_REG6_RESETB_RXD_INDEX 8
903 #define RXTX_REG6_RESETB_RXD_WIDTH 1
904 #define RXTX_REG20_BLWC_ENA_INDEX 2
905 #define RXTX_REG20_BLWC_ENA_WIDTH 1
906 #define RXTX_REG114_PQ_REG_INDEX 9
907 #define RXTX_REG114_PQ_REG_WIDTH 7
908 #define RXTX_REG129_RXDFE_CONFIG_INDEX 14
909 #define RXTX_REG129_RXDFE_CONFIG_WIDTH 2
911 /* Descriptor/Packet entry bit positions and sizes */
912 #define RX_PACKET_ERRORS_CRC_INDEX 2
913 #define RX_PACKET_ERRORS_CRC_WIDTH 1
914 #define RX_PACKET_ERRORS_FRAME_INDEX 3
915 #define RX_PACKET_ERRORS_FRAME_WIDTH 1
916 #define RX_PACKET_ERRORS_LENGTH_INDEX 0
917 #define RX_PACKET_ERRORS_LENGTH_WIDTH 1
918 #define RX_PACKET_ERRORS_OVERRUN_INDEX 1
919 #define RX_PACKET_ERRORS_OVERRUN_WIDTH 1
921 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0
922 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1
923 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1
924 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
925 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX 2
926 #define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH 1
927 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3
928 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1
929 #define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4
930 #define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1
931 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5
932 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1
933 #define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6
934 #define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1
936 #define RX_NORMAL_DESC0_OVT_INDEX 0
937 #define RX_NORMAL_DESC0_OVT_WIDTH 16
938 #define RX_NORMAL_DESC2_HL_INDEX 0
939 #define RX_NORMAL_DESC2_HL_WIDTH 10
940 #define RX_NORMAL_DESC3_CDA_INDEX 27
941 #define RX_NORMAL_DESC3_CDA_WIDTH 1
942 #define RX_NORMAL_DESC3_CTXT_INDEX 30
943 #define RX_NORMAL_DESC3_CTXT_WIDTH 1
944 #define RX_NORMAL_DESC3_ES_INDEX 15
945 #define RX_NORMAL_DESC3_ES_WIDTH 1
946 #define RX_NORMAL_DESC3_ETLT_INDEX 16
947 #define RX_NORMAL_DESC3_ETLT_WIDTH 4
948 #define RX_NORMAL_DESC3_FD_INDEX 29
949 #define RX_NORMAL_DESC3_FD_WIDTH 1
950 #define RX_NORMAL_DESC3_INTE_INDEX 30
951 #define RX_NORMAL_DESC3_INTE_WIDTH 1
952 #define RX_NORMAL_DESC3_L34T_INDEX 20
953 #define RX_NORMAL_DESC3_L34T_WIDTH 4
954 #define RX_NORMAL_DESC3_LD_INDEX 28
955 #define RX_NORMAL_DESC3_LD_WIDTH 1
956 #define RX_NORMAL_DESC3_OWN_INDEX 31
957 #define RX_NORMAL_DESC3_OWN_WIDTH 1
958 #define RX_NORMAL_DESC3_PL_INDEX 0
959 #define RX_NORMAL_DESC3_PL_WIDTH 14
960 #define RX_NORMAL_DESC3_RSV_INDEX 26
961 #define RX_NORMAL_DESC3_RSV_WIDTH 1
963 #define RX_DESC3_L34T_IPV4_TCP 1
964 #define RX_DESC3_L34T_IPV4_UDP 2
965 #define RX_DESC3_L34T_IPV4_ICMP 3
966 #define RX_DESC3_L34T_IPV6_TCP 9
967 #define RX_DESC3_L34T_IPV6_UDP 10
968 #define RX_DESC3_L34T_IPV6_ICMP 11
970 #define RX_CONTEXT_DESC3_TSA_INDEX 4
971 #define RX_CONTEXT_DESC3_TSA_WIDTH 1
972 #define RX_CONTEXT_DESC3_TSD_INDEX 6
973 #define RX_CONTEXT_DESC3_TSD_WIDTH 1
975 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0
976 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1
977 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1
978 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1
979 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2
980 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
981 #define TX_PACKET_ATTRIBUTES_PTP_INDEX 3
982 #define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1
984 #define TX_CONTEXT_DESC2_MSS_INDEX 0
985 #define TX_CONTEXT_DESC2_MSS_WIDTH 15
986 #define TX_CONTEXT_DESC3_CTXT_INDEX 30
987 #define TX_CONTEXT_DESC3_CTXT_WIDTH 1
988 #define TX_CONTEXT_DESC3_TCMSSV_INDEX 26
989 #define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1
990 #define TX_CONTEXT_DESC3_VLTV_INDEX 16
991 #define TX_CONTEXT_DESC3_VLTV_WIDTH 1
992 #define TX_CONTEXT_DESC3_VT_INDEX 0
993 #define TX_CONTEXT_DESC3_VT_WIDTH 16
995 #define TX_NORMAL_DESC2_HL_B1L_INDEX 0
996 #define TX_NORMAL_DESC2_HL_B1L_WIDTH 14
997 #define TX_NORMAL_DESC2_IC_INDEX 31
998 #define TX_NORMAL_DESC2_IC_WIDTH 1
999 #define TX_NORMAL_DESC2_TTSE_INDEX 30
1000 #define TX_NORMAL_DESC2_TTSE_WIDTH 1
1001 #define TX_NORMAL_DESC2_VTIR_INDEX 14
1002 #define TX_NORMAL_DESC2_VTIR_WIDTH 2
1003 #define TX_NORMAL_DESC3_CIC_INDEX 16
1004 #define TX_NORMAL_DESC3_CIC_WIDTH 2
1005 #define TX_NORMAL_DESC3_CPC_INDEX 26
1006 #define TX_NORMAL_DESC3_CPC_WIDTH 2
1007 #define TX_NORMAL_DESC3_CTXT_INDEX 30
1008 #define TX_NORMAL_DESC3_CTXT_WIDTH 1
1009 #define TX_NORMAL_DESC3_FD_INDEX 29
1010 #define TX_NORMAL_DESC3_FD_WIDTH 1
1011 #define TX_NORMAL_DESC3_FL_INDEX 0
1012 #define TX_NORMAL_DESC3_FL_WIDTH 15
1013 #define TX_NORMAL_DESC3_LD_INDEX 28
1014 #define TX_NORMAL_DESC3_LD_WIDTH 1
1015 #define TX_NORMAL_DESC3_OWN_INDEX 31
1016 #define TX_NORMAL_DESC3_OWN_WIDTH 1
1017 #define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19
1018 #define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4
1019 #define TX_NORMAL_DESC3_TCPPL_INDEX 0
1020 #define TX_NORMAL_DESC3_TCPPL_WIDTH 18
1021 #define TX_NORMAL_DESC3_TSE_INDEX 18
1022 #define TX_NORMAL_DESC3_TSE_WIDTH 1
1024 #define TX_NORMAL_DESC2_VLAN_INSERT 0x2
1026 /* MDIO undefined or vendor specific registers */
1027 #ifndef MDIO_PMA_10GBR_PMD_CTRL
1028 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096
1031 #ifndef MDIO_PMA_10GBR_FECCTRL
1032 #define MDIO_PMA_10GBR_FECCTRL 0x00ab
1036 #define MDIO_AN_XNP 0x0016
1040 #define MDIO_AN_LPX 0x0019
1043 #ifndef MDIO_AN_COMP_STAT
1044 #define MDIO_AN_COMP_STAT 0x0030
1047 #ifndef MDIO_AN_INTMASK
1048 #define MDIO_AN_INTMASK 0x8001
1052 #define MDIO_AN_INT 0x8002
1055 #ifndef MDIO_CTRL1_SPEED1G
1056 #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
1059 /* MDIO mask values */
1060 #define XGBE_XNP_MCF_NULL_MESSAGE 0x001
1061 #define XGBE_XNP_ACK_PROCESSED BIT(12)
1062 #define XGBE_XNP_MP_FORMATTED BIT(13)
1063 #define XGBE_XNP_NP_EXCHANGE BIT(15)
1065 #define XGBE_KR_TRAINING_START BIT(0)
1066 #define XGBE_KR_TRAINING_ENABLE BIT(1)
1068 /* Bit setting and getting macros
1069 * The get macro will extract the current bit field value from within
1072 * The set macro will clear the current bit field value within the
1073 * variable and then set the bit field of the variable to the
1076 #define GET_BITS(_var, _index, _width) \
1077 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
1079 #define SET_BITS(_var, _index, _width, _val) \
1081 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
1082 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
1085 #define GET_BITS_LE(_var, _index, _width) \
1086 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
1088 #define SET_BITS_LE(_var, _index, _width, _val) \
1090 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \
1091 (_var) |= cpu_to_le32((((_val) & \
1092 ((0x1 << (_width)) - 1)) << (_index))); \
1095 /* Bit setting and getting macros based on register fields
1096 * The get macro uses the bit field definitions formed using the input
1097 * names to extract the current bit field value from within the
1100 * The set macro uses the bit field definitions formed using the input
1101 * names to set the bit field of the variable to the specified value
1103 #define XGMAC_GET_BITS(_var, _prefix, _field) \
1105 _prefix##_##_field##_INDEX, \
1106 _prefix##_##_field##_WIDTH)
1108 #define XGMAC_SET_BITS(_var, _prefix, _field, _val) \
1110 _prefix##_##_field##_INDEX, \
1111 _prefix##_##_field##_WIDTH, (_val))
1113 #define XGMAC_GET_BITS_LE(_var, _prefix, _field) \
1114 GET_BITS_LE((_var), \
1115 _prefix##_##_field##_INDEX, \
1116 _prefix##_##_field##_WIDTH)
1118 #define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \
1119 SET_BITS_LE((_var), \
1120 _prefix##_##_field##_INDEX, \
1121 _prefix##_##_field##_WIDTH, (_val))
1123 /* Macros for reading or writing registers
1124 * The ioread macros will get bit fields or full values using the
1125 * register definitions formed using the input names
1127 * The iowrite macros will set bit fields or full values using the
1128 * register definitions formed using the input names
1130 #define XGMAC_IOREAD(_pdata, _reg) \
1131 bus_read_4((_pdata)->xgmac_res, _reg)
1133 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \
1134 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \
1135 _reg##_##_field##_INDEX, \
1136 _reg##_##_field##_WIDTH)
1138 #define XGMAC_IOWRITE(_pdata, _reg, _val) \
1139 bus_write_4((_pdata)->xgmac_res, _reg, (_val))
1141 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1143 u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \
1145 _reg##_##_field##_INDEX, \
1146 _reg##_##_field##_WIDTH, (_val)); \
1147 XGMAC_IOWRITE((_pdata), _reg, reg_val); \
1150 /* Macros for reading or writing MTL queue or traffic class registers
1151 * Similar to the standard read and write macros except that the
1152 * base register value is calculated by the queue or traffic class number
1154 #define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \
1155 bus_read_4((_pdata)->xgmac_res, \
1156 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg)
1158 #define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \
1159 GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \
1160 _reg##_##_field##_INDEX, \
1161 _reg##_##_field##_WIDTH)
1163 #define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \
1164 bus_write_4((_pdata)->xgmac_res, \
1165 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg, (_val))
1167 #define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \
1169 u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \
1171 _reg##_##_field##_INDEX, \
1172 _reg##_##_field##_WIDTH, (_val)); \
1173 XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \
1176 /* Macros for reading or writing DMA channel registers
1177 * Similar to the standard read and write macros except that the
1178 * base register value is obtained from the ring
1180 #define XGMAC_DMA_IOREAD(_channel, _reg) \
1181 bus_space_read_4((_channel)->dma_tag, (_channel)->dma_handle, _reg)
1183 #define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \
1184 GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \
1185 _reg##_##_field##_INDEX, \
1186 _reg##_##_field##_WIDTH)
1188 #define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \
1189 bus_space_write_4((_channel)->dma_tag, (_channel)->dma_handle, \
1192 #define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \
1194 u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \
1196 _reg##_##_field##_INDEX, \
1197 _reg##_##_field##_WIDTH, (_val)); \
1198 XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \
1201 /* Macros for building, reading or writing register values or bits
1202 * within the register values of XPCS registers.
1204 #define XPCS_IOWRITE(_pdata, _off, _val) \
1205 bus_write_4((_pdata)->xpcs_res, (_off), _val)
1207 #define XPCS_IOREAD(_pdata, _off) \
1208 bus_read_4((_pdata)->xpcs_res, (_off))
1210 /* Macros for building, reading or writing register values or bits
1211 * within the register values of SerDes integration registers.
1213 #define XSIR_GET_BITS(_var, _prefix, _field) \
1215 _prefix##_##_field##_INDEX, \
1216 _prefix##_##_field##_WIDTH)
1218 #define XSIR_SET_BITS(_var, _prefix, _field, _val) \
1220 _prefix##_##_field##_INDEX, \
1221 _prefix##_##_field##_WIDTH, (_val))
1223 #define XSIR0_IOREAD(_pdata, _reg) \
1224 bus_read_2((_pdata)->sir0_res, _reg)
1226 #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \
1227 GET_BITS(XSIR0_IOREAD((_pdata), _reg), \
1228 _reg##_##_field##_INDEX, \
1229 _reg##_##_field##_WIDTH)
1231 #define XSIR0_IOWRITE(_pdata, _reg, _val) \
1232 bus_write_2((_pdata)->sir0_res, _reg, (_val))
1234 #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1236 u16 reg_val = XSIR0_IOREAD((_pdata), _reg); \
1238 _reg##_##_field##_INDEX, \
1239 _reg##_##_field##_WIDTH, (_val)); \
1240 XSIR0_IOWRITE((_pdata), _reg, reg_val); \
1243 #define XSIR1_IOREAD(_pdata, _reg) \
1244 bus_read_2((_pdata)->sir1_res, _reg)
1246 #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \
1247 GET_BITS(XSIR1_IOREAD((_pdata), _reg), \
1248 _reg##_##_field##_INDEX, \
1249 _reg##_##_field##_WIDTH)
1251 #define XSIR1_IOWRITE(_pdata, _reg, _val) \
1252 bus_write_2((_pdata)->sir1_res, _reg, (_val))
1254 #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1256 u16 reg_val = XSIR1_IOREAD((_pdata), _reg); \
1258 _reg##_##_field##_INDEX, \
1259 _reg##_##_field##_WIDTH, (_val)); \
1260 XSIR1_IOWRITE((_pdata), _reg, reg_val); \
1263 /* Macros for building, reading or writing register values or bits
1264 * within the register values of SerDes RxTx registers.
1266 #define XRXTX_IOREAD(_pdata, _reg) \
1267 bus_read_2((_pdata)->rxtx_res, _reg)
1269 #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \
1270 GET_BITS(XRXTX_IOREAD((_pdata), _reg), \
1271 _reg##_##_field##_INDEX, \
1272 _reg##_##_field##_WIDTH)
1274 #define XRXTX_IOWRITE(_pdata, _reg, _val) \
1275 bus_write_2((_pdata)->rxtx_res, _reg, (_val))
1277 #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1279 u16 reg_val = XRXTX_IOREAD((_pdata), _reg); \
1281 _reg##_##_field##_INDEX, \
1282 _reg##_##_field##_WIDTH, (_val)); \
1283 XRXTX_IOWRITE((_pdata), _reg, reg_val); \
1286 /* Macros for building, reading or writing register values or bits
1287 * using MDIO. Different from above because of the use of standardized
1288 * Linux include values. No shifting is performed with the bit
1289 * operations, everything works on mask values.
1291 #define XMDIO_READ(_pdata, _mmd, _reg) \
1292 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \
1293 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff)))
1295 #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \
1296 (XMDIO_READ((_pdata), _mmd, _reg) & _mask)
1298 #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \
1299 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \
1300 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val)))
1302 #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \
1304 u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \
1305 mmd_val &= ~_mask; \
1306 mmd_val |= (_val); \
1307 XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \