2 * AMD 10Gb Ethernet driver
4 * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc.
6 * This file is available to you under your choice of the following two
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24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
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42 * in all copies or substantial portions of the Software.
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77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81 * This file incorporates work covered by the following copyright and
83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
85 * Inc. unless otherwise expressly agreed to in writing between Synopsys
88 * The Software IS NOT an item of Licensed Software or Licensed Product
89 * under any End User Software License Agreement or Agreement for Licensed
90 * Product with Synopsys or any supplement thereto. Permission is hereby
91 * granted, free of charge, to any person obtaining a copy of this software
92 * annotated with this license and the Software, to deal in the Software
93 * without restriction, including without limitation the rights to use,
94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
95 * of the Software, and to permit persons to whom the Software is furnished
96 * to do so, subject to the following conditions:
98 * The above copyright notice and this permission notice shall be included
99 * in all copies or substantial portions of the Software.
101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
111 * THE POSSIBILITY OF SUCH DAMAGE.
116 #ifndef __XGBE_COMMON_H__
117 #define __XGBE_COMMON_H__
120 #include <sys/rman.h>
122 /* DMA register offsets */
123 #define DMA_MR 0x3000
124 #define DMA_SBMR 0x3004
125 #define DMA_ISR 0x3008
126 #define DMA_AXIARCR 0x3010
127 #define DMA_AXIAWCR 0x3018
128 #define DMA_AXIAWARCR 0x301c
129 #define DMA_DSR0 0x3020
130 #define DMA_DSR1 0x3024
131 #define DMA_DSR2 0x3028
132 #define DMA_DSR3 0x302C
133 #define DMA_DSR4 0x3030
134 #define DMA_TXEDMACR 0x3040
135 #define DMA_RXEDMACR 0x3044
137 /* DMA register entry bit positions and sizes */
138 #define DMA_ISR_MACIS_INDEX 17
139 #define DMA_ISR_MACIS_WIDTH 1
140 #define DMA_ISR_MTLIS_INDEX 16
141 #define DMA_ISR_MTLIS_WIDTH 1
142 #define DMA_MR_INTM_INDEX 12
143 #define DMA_MR_INTM_WIDTH 2
144 #define DMA_MR_SWR_INDEX 0
145 #define DMA_MR_SWR_WIDTH 1
146 #define DMA_RXEDMACR_RDPS_INDEX 0
147 #define DMA_RXEDMACR_RDPS_WIDTH 3
148 #define DMA_SBMR_AAL_INDEX 12
149 #define DMA_SBMR_AAL_WIDTH 1
150 #define DMA_SBMR_EAME_INDEX 11
151 #define DMA_SBMR_EAME_WIDTH 1
152 #define DMA_SBMR_BLEN_INDEX 1
153 #define DMA_SBMR_BLEN_WIDTH 7
154 #define DMA_SBMR_RD_OSR_LMT_INDEX 16
155 #define DMA_SBMR_RD_OSR_LMT_WIDTH 6
156 #define DMA_SBMR_UNDEF_INDEX 0
157 #define DMA_SBMR_UNDEF_WIDTH 1
158 #define DMA_SBMR_WR_OSR_LMT_INDEX 24
159 #define DMA_SBMR_WR_OSR_LMT_WIDTH 6
160 #define DMA_TXEDMACR_TDPS_INDEX 0
161 #define DMA_TXEDMACR_TDPS_WIDTH 3
163 /* DMA register values */
164 #define DMA_SBMR_BLEN_256 256
165 #define DMA_SBMR_BLEN_128 128
166 #define DMA_SBMR_BLEN_64 64
167 #define DMA_SBMR_BLEN_32 32
168 #define DMA_SBMR_BLEN_16 16
169 #define DMA_SBMR_BLEN_8 8
170 #define DMA_SBMR_BLEN_4 4
171 #define DMA_DSR_RPS_WIDTH 4
172 #define DMA_DSR_TPS_WIDTH 4
173 #define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH)
174 #define DMA_DSR0_RPS_START 8
175 #define DMA_DSR0_TPS_START 12
176 #define DMA_DSRX_FIRST_QUEUE 3
177 #define DMA_DSRX_INC 4
178 #define DMA_DSRX_QPR 4
179 #define DMA_DSRX_RPS_START 0
180 #define DMA_DSRX_TPS_START 4
181 #define DMA_TPS_STOPPED 0x00
182 #define DMA_TPS_SUSPENDED 0x06
184 /* DMA channel register offsets
185 * Multiple channels can be active. The first channel has registers
186 * that begin at 0x3100. Each subsequent channel has registers that
187 * are accessed using an offset of 0x80 from the previous channel.
189 #define DMA_CH_BASE 0x3100
190 #define DMA_CH_INC 0x80
192 #define DMA_CH_CR 0x00
193 #define DMA_CH_TCR 0x04
194 #define DMA_CH_RCR 0x08
195 #define DMA_CH_TDLR_HI 0x10
196 #define DMA_CH_TDLR_LO 0x14
197 #define DMA_CH_RDLR_HI 0x18
198 #define DMA_CH_RDLR_LO 0x1c
199 #define DMA_CH_TDTR_LO 0x24
200 #define DMA_CH_RDTR_LO 0x2c
201 #define DMA_CH_TDRLR 0x30
202 #define DMA_CH_RDRLR 0x34
203 #define DMA_CH_IER 0x38
204 #define DMA_CH_RIWT 0x3c
205 #define DMA_CH_CATDR_LO 0x44
206 #define DMA_CH_CARDR_LO 0x4c
207 #define DMA_CH_CATBR_HI 0x50
208 #define DMA_CH_CATBR_LO 0x54
209 #define DMA_CH_CARBR_HI 0x58
210 #define DMA_CH_CARBR_LO 0x5c
211 #define DMA_CH_SR 0x60
212 #define DMA_CH_DSR 0x64
213 #define DMA_CH_DCFL 0x68
214 #define DMA_CH_MFC 0x6c
215 #define DMA_CH_TDTRO 0x70
216 #define DMA_CH_RDTRO 0x74
217 #define DMA_CH_TDWRO 0x78
218 #define DMA_CH_RDWRO 0x7C
220 /* DMA channel register entry bit positions and sizes */
221 #define DMA_CH_CR_PBLX8_INDEX 16
222 #define DMA_CH_CR_PBLX8_WIDTH 1
223 #define DMA_CH_CR_SPH_INDEX 24
224 #define DMA_CH_CR_SPH_WIDTH 1
225 #define DMA_CH_IER_AIE20_INDEX 15
226 #define DMA_CH_IER_AIE20_WIDTH 1
227 #define DMA_CH_IER_AIE_INDEX 14
228 #define DMA_CH_IER_AIE_WIDTH 1
229 #define DMA_CH_IER_FBEE_INDEX 12
230 #define DMA_CH_IER_FBEE_WIDTH 1
231 #define DMA_CH_IER_NIE20_INDEX 16
232 #define DMA_CH_IER_NIE20_WIDTH 1
233 #define DMA_CH_IER_NIE_INDEX 15
234 #define DMA_CH_IER_NIE_WIDTH 1
235 #define DMA_CH_IER_RBUE_INDEX 7
236 #define DMA_CH_IER_RBUE_WIDTH 1
237 #define DMA_CH_IER_RIE_INDEX 6
238 #define DMA_CH_IER_RIE_WIDTH 1
239 #define DMA_CH_IER_RSE_INDEX 8
240 #define DMA_CH_IER_RSE_WIDTH 1
241 #define DMA_CH_IER_TBUE_INDEX 2
242 #define DMA_CH_IER_TBUE_WIDTH 1
243 #define DMA_CH_IER_TIE_INDEX 0
244 #define DMA_CH_IER_TIE_WIDTH 1
245 #define DMA_CH_IER_TXSE_INDEX 1
246 #define DMA_CH_IER_TXSE_WIDTH 1
247 #define DMA_CH_RCR_PBL_INDEX 16
248 #define DMA_CH_RCR_PBL_WIDTH 6
249 #define DMA_CH_RCR_RBSZ_INDEX 1
250 #define DMA_CH_RCR_RBSZ_WIDTH 14
251 #define DMA_CH_RCR_SR_INDEX 0
252 #define DMA_CH_RCR_SR_WIDTH 1
253 #define DMA_CH_RIWT_RWT_INDEX 0
254 #define DMA_CH_RIWT_RWT_WIDTH 8
255 #define DMA_CH_SR_FBE_INDEX 12
256 #define DMA_CH_SR_FBE_WIDTH 1
257 #define DMA_CH_SR_RBU_INDEX 7
258 #define DMA_CH_SR_RBU_WIDTH 1
259 #define DMA_CH_SR_RI_INDEX 6
260 #define DMA_CH_SR_RI_WIDTH 1
261 #define DMA_CH_SR_RPS_INDEX 8
262 #define DMA_CH_SR_RPS_WIDTH 1
263 #define DMA_CH_SR_TBU_INDEX 2
264 #define DMA_CH_SR_TBU_WIDTH 1
265 #define DMA_CH_SR_TI_INDEX 0
266 #define DMA_CH_SR_TI_WIDTH 1
267 #define DMA_CH_SR_TPS_INDEX 1
268 #define DMA_CH_SR_TPS_WIDTH 1
269 #define DMA_CH_TCR_OSP_INDEX 4
270 #define DMA_CH_TCR_OSP_WIDTH 1
271 #define DMA_CH_TCR_PBL_INDEX 16
272 #define DMA_CH_TCR_PBL_WIDTH 6
273 #define DMA_CH_TCR_ST_INDEX 0
274 #define DMA_CH_TCR_ST_WIDTH 1
275 #define DMA_CH_TCR_TSE_INDEX 12
276 #define DMA_CH_TCR_TSE_WIDTH 1
278 /* DMA channel register values */
279 #define DMA_OSP_DISABLE 0x00
280 #define DMA_OSP_ENABLE 0x01
285 #define DMA_PBL_16 16
286 #define DMA_PBL_32 32
287 #define DMA_PBL_64 64 /* 8 x 8 */
288 #define DMA_PBL_128 128 /* 8 x 16 */
289 #define DMA_PBL_256 256 /* 8 x 32 */
290 #define DMA_PBL_X8_DISABLE 0x00
291 #define DMA_PBL_X8_ENABLE 0x01
293 /* MAC register offsets */
294 #define MAC_TCR 0x0000
295 #define MAC_RCR 0x0004
296 #define MAC_PFR 0x0008
297 #define MAC_WTR 0x000c
298 #define MAC_HTR0 0x0010
299 #define MAC_HTR1 0x0014
300 #define MAC_HTR2 0x0018
301 #define MAC_HTR3 0x001c
302 #define MAC_HTR4 0x0020
303 #define MAC_HTR5 0x0024
304 #define MAC_HTR6 0x0028
305 #define MAC_HTR7 0x002c
306 #define MAC_VLANTR 0x0050
307 #define MAC_VLANHTR 0x0058
308 #define MAC_VLANIR 0x0060
309 #define MAC_IVLANIR 0x0064
310 #define MAC_RETMR 0x006c
311 #define MAC_Q0TFCR 0x0070
312 #define MAC_Q1TFCR 0x0074
313 #define MAC_Q2TFCR 0x0078
314 #define MAC_Q3TFCR 0x007c
315 #define MAC_Q4TFCR 0x0080
316 #define MAC_Q5TFCR 0x0084
317 #define MAC_Q6TFCR 0x0088
318 #define MAC_Q7TFCR 0x008c
319 #define MAC_RFCR 0x0090
320 #define MAC_RQC0R 0x00a0
321 #define MAC_RQC1R 0x00a4
322 #define MAC_RQC2R 0x00a8
323 #define MAC_RQC3R 0x00ac
324 #define MAC_ISR 0x00b0
325 #define MAC_IER 0x00b4
326 #define MAC_RTSR 0x00b8
327 #define MAC_PMTCSR 0x00c0
328 #define MAC_RWKPFR 0x00c4
329 #define MAC_LPICSR 0x00d0
330 #define MAC_LPITCR 0x00d4
331 #define MAC_TIR 0x00e0
332 #define MAC_VR 0x0110
333 #define MAC_DR 0x0114
334 #define MAC_HWF0R 0x011c
335 #define MAC_HWF1R 0x0120
336 #define MAC_HWF2R 0x0124
337 #define MAC_MDIOSCAR 0x0200
338 #define MAC_MDIOSCCDR 0x0204
339 #define MAC_MDIOISR 0x0214
340 #define MAC_MDIOIER 0x0218
341 #define MAC_MDIOCL22R 0x0220
342 #define MAC_GPIOCR 0x0278
343 #define MAC_GPIOSR 0x027c
344 #define MAC_MACA0HR 0x0300
345 #define MAC_MACA0LR 0x0304
346 #define MAC_MACA1HR 0x0308
347 #define MAC_MACA1LR 0x030c
348 #define MAC_RSSCR 0x0c80
349 #define MAC_RSSAR 0x0c88
350 #define MAC_RSSDR 0x0c8c
351 #define MAC_TSCR 0x0d00
352 #define MAC_SSIR 0x0d04
353 #define MAC_STSR 0x0d08
354 #define MAC_STNR 0x0d0c
355 #define MAC_STSUR 0x0d10
356 #define MAC_STNUR 0x0d14
357 #define MAC_TSAR 0x0d18
358 #define MAC_TSSR 0x0d20
359 #define MAC_TXSNR 0x0d30
360 #define MAC_TXSSR 0x0d34
362 #define MAC_QTFCR_INC 4
363 #define MAC_MACA_INC 4
364 #define MAC_HTR_INC 4
366 #define MAC_RQC2_INC 4
367 #define MAC_RQC2_Q_PER_REG 4
369 /* MAC register entry bit positions and sizes */
370 #define MAC_HWF0R_ADDMACADRSEL_INDEX 18
371 #define MAC_HWF0R_ADDMACADRSEL_WIDTH 5
372 #define MAC_HWF0R_ARPOFFSEL_INDEX 9
373 #define MAC_HWF0R_ARPOFFSEL_WIDTH 1
374 #define MAC_HWF0R_EEESEL_INDEX 13
375 #define MAC_HWF0R_EEESEL_WIDTH 1
376 #define MAC_HWF0R_GMIISEL_INDEX 1
377 #define MAC_HWF0R_GMIISEL_WIDTH 1
378 #define MAC_HWF0R_MGKSEL_INDEX 7
379 #define MAC_HWF0R_MGKSEL_WIDTH 1
380 #define MAC_HWF0R_MMCSEL_INDEX 8
381 #define MAC_HWF0R_MMCSEL_WIDTH 1
382 #define MAC_HWF0R_RWKSEL_INDEX 6
383 #define MAC_HWF0R_RWKSEL_WIDTH 1
384 #define MAC_HWF0R_RXCOESEL_INDEX 16
385 #define MAC_HWF0R_RXCOESEL_WIDTH 1
386 #define MAC_HWF0R_SAVLANINS_INDEX 27
387 #define MAC_HWF0R_SAVLANINS_WIDTH 1
388 #define MAC_HWF0R_SMASEL_INDEX 5
389 #define MAC_HWF0R_SMASEL_WIDTH 1
390 #define MAC_HWF0R_TSSEL_INDEX 12
391 #define MAC_HWF0R_TSSEL_WIDTH 1
392 #define MAC_HWF0R_TSSTSSEL_INDEX 25
393 #define MAC_HWF0R_TSSTSSEL_WIDTH 2
394 #define MAC_HWF0R_TXCOESEL_INDEX 14
395 #define MAC_HWF0R_TXCOESEL_WIDTH 1
396 #define MAC_HWF0R_VLHASH_INDEX 4
397 #define MAC_HWF0R_VLHASH_WIDTH 1
398 #define MAC_HWF0R_VXN_INDEX 29
399 #define MAC_HWF0R_VXN_WIDTH 1
400 #define MAC_HWF1R_ADDR64_INDEX 14
401 #define MAC_HWF1R_ADDR64_WIDTH 2
402 #define MAC_HWF1R_ADVTHWORD_INDEX 13
403 #define MAC_HWF1R_ADVTHWORD_WIDTH 1
404 #define MAC_HWF1R_DBGMEMA_INDEX 19
405 #define MAC_HWF1R_DBGMEMA_WIDTH 1
406 #define MAC_HWF1R_DCBEN_INDEX 16
407 #define MAC_HWF1R_DCBEN_WIDTH 1
408 #define MAC_HWF1R_HASHTBLSZ_INDEX 24
409 #define MAC_HWF1R_HASHTBLSZ_WIDTH 3
410 #define MAC_HWF1R_L3L4FNUM_INDEX 27
411 #define MAC_HWF1R_L3L4FNUM_WIDTH 4
412 #define MAC_HWF1R_NUMTC_INDEX 21
413 #define MAC_HWF1R_NUMTC_WIDTH 3
414 #define MAC_HWF1R_RSSEN_INDEX 20
415 #define MAC_HWF1R_RSSEN_WIDTH 1
416 #define MAC_HWF1R_RXFIFOSIZE_INDEX 0
417 #define MAC_HWF1R_RXFIFOSIZE_WIDTH 5
418 #define MAC_HWF1R_SPHEN_INDEX 17
419 #define MAC_HWF1R_SPHEN_WIDTH 1
420 #define MAC_HWF1R_TSOEN_INDEX 18
421 #define MAC_HWF1R_TSOEN_WIDTH 1
422 #define MAC_HWF1R_TXFIFOSIZE_INDEX 6
423 #define MAC_HWF1R_TXFIFOSIZE_WIDTH 5
424 #define MAC_HWF2R_AUXSNAPNUM_INDEX 28
425 #define MAC_HWF2R_AUXSNAPNUM_WIDTH 3
426 #define MAC_HWF2R_PPSOUTNUM_INDEX 24
427 #define MAC_HWF2R_PPSOUTNUM_WIDTH 3
428 #define MAC_HWF2R_RXCHCNT_INDEX 12
429 #define MAC_HWF2R_RXCHCNT_WIDTH 4
430 #define MAC_HWF2R_RXQCNT_INDEX 0
431 #define MAC_HWF2R_RXQCNT_WIDTH 4
432 #define MAC_HWF2R_TXCHCNT_INDEX 18
433 #define MAC_HWF2R_TXCHCNT_WIDTH 4
434 #define MAC_HWF2R_TXQCNT_INDEX 6
435 #define MAC_HWF2R_TXQCNT_WIDTH 4
436 #define MAC_IER_TSIE_INDEX 12
437 #define MAC_IER_TSIE_WIDTH 1
438 #define MAC_ISR_MMCRXIS_INDEX 9
439 #define MAC_ISR_MMCRXIS_WIDTH 1
440 #define MAC_ISR_MMCTXIS_INDEX 10
441 #define MAC_ISR_MMCTXIS_WIDTH 1
442 #define MAC_ISR_PMTIS_INDEX 4
443 #define MAC_ISR_PMTIS_WIDTH 1
444 #define MAC_ISR_SMI_INDEX 1
445 #define MAC_ISR_SMI_WIDTH 1
446 #define MAC_ISR_TSIS_INDEX 12
447 #define MAC_ISR_TSIS_WIDTH 1
448 #define MAC_MACA1HR_AE_INDEX 31
449 #define MAC_MACA1HR_AE_WIDTH 1
450 #define MAC_MDIOIER_SNGLCOMPIE_INDEX 12
451 #define MAC_MDIOIER_SNGLCOMPIE_WIDTH 1
452 #define MAC_MDIOISR_SNGLCOMPINT_INDEX 12
453 #define MAC_MDIOISR_SNGLCOMPINT_WIDTH 1
454 #define MAC_MDIOSCAR_DA_INDEX 21
455 #define MAC_MDIOSCAR_DA_WIDTH 5
456 #define MAC_MDIOSCAR_PA_INDEX 16
457 #define MAC_MDIOSCAR_PA_WIDTH 5
458 #define MAC_MDIOSCAR_RA_INDEX 0
459 #define MAC_MDIOSCAR_RA_WIDTH 16
460 #define MAC_MDIOSCCDR_BUSY_INDEX 22
461 #define MAC_MDIOSCCDR_BUSY_WIDTH 1
462 #define MAC_MDIOSCCDR_CMD_INDEX 16
463 #define MAC_MDIOSCCDR_CMD_WIDTH 2
464 #define MAC_MDIOSCCDR_CR_INDEX 19
465 #define MAC_MDIOSCCDR_CR_WIDTH 3
466 #define MAC_MDIOSCCDR_DATA_INDEX 0
467 #define MAC_MDIOSCCDR_DATA_WIDTH 16
468 #define MAC_MDIOSCCDR_SADDR_INDEX 18
469 #define MAC_MDIOSCCDR_SADDR_WIDTH 1
470 #define MAC_PFR_HMC_INDEX 2
471 #define MAC_PFR_HMC_WIDTH 1
472 #define MAC_PFR_HPF_INDEX 10
473 #define MAC_PFR_HPF_WIDTH 1
474 #define MAC_PFR_HUC_INDEX 1
475 #define MAC_PFR_HUC_WIDTH 1
476 #define MAC_PFR_PM_INDEX 4
477 #define MAC_PFR_PM_WIDTH 1
478 #define MAC_PFR_PR_INDEX 0
479 #define MAC_PFR_PR_WIDTH 1
480 #define MAC_PFR_VTFE_INDEX 16
481 #define MAC_PFR_VTFE_WIDTH 1
482 #define MAC_PFR_VUCC_INDEX 22
483 #define MAC_PFR_VUCC_WIDTH 1
484 #define MAC_PMTCSR_MGKPKTEN_INDEX 1
485 #define MAC_PMTCSR_MGKPKTEN_WIDTH 1
486 #define MAC_PMTCSR_PWRDWN_INDEX 0
487 #define MAC_PMTCSR_PWRDWN_WIDTH 1
488 #define MAC_PMTCSR_RWKFILTRST_INDEX 31
489 #define MAC_PMTCSR_RWKFILTRST_WIDTH 1
490 #define MAC_PMTCSR_RWKPKTEN_INDEX 2
491 #define MAC_PMTCSR_RWKPKTEN_WIDTH 1
492 #define MAC_Q0TFCR_PT_INDEX 16
493 #define MAC_Q0TFCR_PT_WIDTH 16
494 #define MAC_Q0TFCR_TFE_INDEX 1
495 #define MAC_Q0TFCR_TFE_WIDTH 1
496 #define MAC_RCR_ACS_INDEX 1
497 #define MAC_RCR_ACS_WIDTH 1
498 #define MAC_RCR_CST_INDEX 2
499 #define MAC_RCR_CST_WIDTH 1
500 #define MAC_RCR_DCRCC_INDEX 3
501 #define MAC_RCR_DCRCC_WIDTH 1
502 #define MAC_RCR_HDSMS_INDEX 12
503 #define MAC_RCR_HDSMS_WIDTH 3
504 #define MAC_RCR_IPC_INDEX 9
505 #define MAC_RCR_IPC_WIDTH 1
506 #define MAC_RCR_JE_INDEX 8
507 #define MAC_RCR_JE_WIDTH 1
508 #define MAC_RCR_LM_INDEX 10
509 #define MAC_RCR_LM_WIDTH 1
510 #define MAC_RCR_RE_INDEX 0
511 #define MAC_RCR_RE_WIDTH 1
512 #define MAC_RCR_ARPEN_INDEX 31
513 #define MAC_RCR_ARPEN_WIDTH 1
514 #define MAC_RFCR_PFCE_INDEX 8
515 #define MAC_RFCR_PFCE_WIDTH 1
516 #define MAC_RFCR_RFE_INDEX 0
517 #define MAC_RFCR_RFE_WIDTH 1
518 #define MAC_RFCR_UP_INDEX 1
519 #define MAC_RFCR_UP_WIDTH 1
520 #define MAC_RQC0R_RXQ0EN_INDEX 0
521 #define MAC_RQC0R_RXQ0EN_WIDTH 2
522 #define MAC_RSSAR_ADDRT_INDEX 2
523 #define MAC_RSSAR_ADDRT_WIDTH 1
524 #define MAC_RSSAR_CT_INDEX 1
525 #define MAC_RSSAR_CT_WIDTH 1
526 #define MAC_RSSAR_OB_INDEX 0
527 #define MAC_RSSAR_OB_WIDTH 1
528 #define MAC_RSSAR_RSSIA_INDEX 8
529 #define MAC_RSSAR_RSSIA_WIDTH 8
530 #define MAC_RSSCR_IP2TE_INDEX 1
531 #define MAC_RSSCR_IP2TE_WIDTH 1
532 #define MAC_RSSCR_RSSE_INDEX 0
533 #define MAC_RSSCR_RSSE_WIDTH 1
534 #define MAC_RSSCR_TCP4TE_INDEX 2
535 #define MAC_RSSCR_TCP4TE_WIDTH 1
536 #define MAC_RSSCR_UDP4TE_INDEX 3
537 #define MAC_RSSCR_UDP4TE_WIDTH 1
538 #define MAC_RSSDR_DMCH_INDEX 0
539 #define MAC_RSSDR_DMCH_WIDTH 4
540 #define MAC_SSIR_SNSINC_INDEX 8
541 #define MAC_SSIR_SNSINC_WIDTH 8
542 #define MAC_SSIR_SSINC_INDEX 16
543 #define MAC_SSIR_SSINC_WIDTH 8
544 #define MAC_TCR_SS_INDEX 29
545 #define MAC_TCR_SS_WIDTH 2
546 #define MAC_TCR_TE_INDEX 0
547 #define MAC_TCR_TE_WIDTH 1
548 #define MAC_TCR_VNE_INDEX 24
549 #define MAC_TCR_VNE_WIDTH 1
550 #define MAC_TCR_VNM_INDEX 25
551 #define MAC_TCR_VNM_WIDTH 1
552 #define MAC_TIR_TNID_INDEX 0
553 #define MAC_TIR_TNID_WIDTH 16
554 #define MAC_TSCR_AV8021ASMEN_INDEX 28
555 #define MAC_TSCR_AV8021ASMEN_WIDTH 1
556 #define MAC_TSCR_SNAPTYPSEL_INDEX 16
557 #define MAC_TSCR_SNAPTYPSEL_WIDTH 2
558 #define MAC_TSCR_TSADDREG_INDEX 5
559 #define MAC_TSCR_TSADDREG_WIDTH 1
560 #define MAC_TSCR_TSCFUPDT_INDEX 1
561 #define MAC_TSCR_TSCFUPDT_WIDTH 1
562 #define MAC_TSCR_TSCTRLSSR_INDEX 9
563 #define MAC_TSCR_TSCTRLSSR_WIDTH 1
564 #define MAC_TSCR_TSENA_INDEX 0
565 #define MAC_TSCR_TSENA_WIDTH 1
566 #define MAC_TSCR_TSENALL_INDEX 8
567 #define MAC_TSCR_TSENALL_WIDTH 1
568 #define MAC_TSCR_TSEVNTENA_INDEX 14
569 #define MAC_TSCR_TSEVNTENA_WIDTH 1
570 #define MAC_TSCR_TSINIT_INDEX 2
571 #define MAC_TSCR_TSINIT_WIDTH 1
572 #define MAC_TSCR_TSIPENA_INDEX 11
573 #define MAC_TSCR_TSIPENA_WIDTH 1
574 #define MAC_TSCR_TSIPV4ENA_INDEX 13
575 #define MAC_TSCR_TSIPV4ENA_WIDTH 1
576 #define MAC_TSCR_TSIPV6ENA_INDEX 12
577 #define MAC_TSCR_TSIPV6ENA_WIDTH 1
578 #define MAC_TSCR_TSMSTRENA_INDEX 15
579 #define MAC_TSCR_TSMSTRENA_WIDTH 1
580 #define MAC_TSCR_TSVER2ENA_INDEX 10
581 #define MAC_TSCR_TSVER2ENA_WIDTH 1
582 #define MAC_TSCR_TXTSSTSM_INDEX 24
583 #define MAC_TSCR_TXTSSTSM_WIDTH 1
584 #define MAC_TSSR_TXTSC_INDEX 15
585 #define MAC_TSSR_TXTSC_WIDTH 1
586 #define MAC_TXSNR_TXTSSTSMIS_INDEX 31
587 #define MAC_TXSNR_TXTSSTSMIS_WIDTH 1
588 #define MAC_VLANHTR_VLHT_INDEX 0
589 #define MAC_VLANHTR_VLHT_WIDTH 16
590 #define MAC_VLANIR_VLTI_INDEX 20
591 #define MAC_VLANIR_VLTI_WIDTH 1
592 #define MAC_VLANIR_CSVL_INDEX 19
593 #define MAC_VLANIR_CSVL_WIDTH 1
594 #define MAC_VLANTR_DOVLTC_INDEX 20
595 #define MAC_VLANTR_DOVLTC_WIDTH 1
596 #define MAC_VLANTR_ERSVLM_INDEX 19
597 #define MAC_VLANTR_ERSVLM_WIDTH 1
598 #define MAC_VLANTR_ESVL_INDEX 18
599 #define MAC_VLANTR_ESVL_WIDTH 1
600 #define MAC_VLANTR_ETV_INDEX 16
601 #define MAC_VLANTR_ETV_WIDTH 1
602 #define MAC_VLANTR_EVLS_INDEX 21
603 #define MAC_VLANTR_EVLS_WIDTH 2
604 #define MAC_VLANTR_EVLRXS_INDEX 24
605 #define MAC_VLANTR_EVLRXS_WIDTH 1
606 #define MAC_VLANTR_VL_INDEX 0
607 #define MAC_VLANTR_VL_WIDTH 16
608 #define MAC_VLANTR_VTHM_INDEX 25
609 #define MAC_VLANTR_VTHM_WIDTH 1
610 #define MAC_VLANTR_VTIM_INDEX 17
611 #define MAC_VLANTR_VTIM_WIDTH 1
612 #define MAC_VR_DEVID_INDEX 8
613 #define MAC_VR_DEVID_WIDTH 8
614 #define MAC_VR_SNPSVER_INDEX 0
615 #define MAC_VR_SNPSVER_WIDTH 8
616 #define MAC_VR_USERVER_INDEX 16
617 #define MAC_VR_USERVER_WIDTH 8
619 /* MMC register offsets */
620 #define MMC_CR 0x0800
621 #define MMC_RISR 0x0804
622 #define MMC_TISR 0x0808
623 #define MMC_RIER 0x080c
624 #define MMC_TIER 0x0810
625 #define MMC_TXOCTETCOUNT_GB_LO 0x0814
626 #define MMC_TXOCTETCOUNT_GB_HI 0x0818
627 #define MMC_TXFRAMECOUNT_GB_LO 0x081c
628 #define MMC_TXFRAMECOUNT_GB_HI 0x0820
629 #define MMC_TXBROADCASTFRAMES_G_LO 0x0824
630 #define MMC_TXBROADCASTFRAMES_G_HI 0x0828
631 #define MMC_TXMULTICASTFRAMES_G_LO 0x082c
632 #define MMC_TXMULTICASTFRAMES_G_HI 0x0830
633 #define MMC_TX64OCTETS_GB_LO 0x0834
634 #define MMC_TX64OCTETS_GB_HI 0x0838
635 #define MMC_TX65TO127OCTETS_GB_LO 0x083c
636 #define MMC_TX65TO127OCTETS_GB_HI 0x0840
637 #define MMC_TX128TO255OCTETS_GB_LO 0x0844
638 #define MMC_TX128TO255OCTETS_GB_HI 0x0848
639 #define MMC_TX256TO511OCTETS_GB_LO 0x084c
640 #define MMC_TX256TO511OCTETS_GB_HI 0x0850
641 #define MMC_TX512TO1023OCTETS_GB_LO 0x0854
642 #define MMC_TX512TO1023OCTETS_GB_HI 0x0858
643 #define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c
644 #define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860
645 #define MMC_TXUNICASTFRAMES_GB_LO 0x0864
646 #define MMC_TXUNICASTFRAMES_GB_HI 0x0868
647 #define MMC_TXMULTICASTFRAMES_GB_LO 0x086c
648 #define MMC_TXMULTICASTFRAMES_GB_HI 0x0870
649 #define MMC_TXBROADCASTFRAMES_GB_LO 0x0874
650 #define MMC_TXBROADCASTFRAMES_GB_HI 0x0878
651 #define MMC_TXUNDERFLOWERROR_LO 0x087c
652 #define MMC_TXUNDERFLOWERROR_HI 0x0880
653 #define MMC_TXOCTETCOUNT_G_LO 0x0884
654 #define MMC_TXOCTETCOUNT_G_HI 0x0888
655 #define MMC_TXFRAMECOUNT_G_LO 0x088c
656 #define MMC_TXFRAMECOUNT_G_HI 0x0890
657 #define MMC_TXPAUSEFRAMES_LO 0x0894
658 #define MMC_TXPAUSEFRAMES_HI 0x0898
659 #define MMC_TXVLANFRAMES_G_LO 0x089c
660 #define MMC_TXVLANFRAMES_G_HI 0x08a0
661 #define MMC_RXFRAMECOUNT_GB_LO 0x0900
662 #define MMC_RXFRAMECOUNT_GB_HI 0x0904
663 #define MMC_RXOCTETCOUNT_GB_LO 0x0908
664 #define MMC_RXOCTETCOUNT_GB_HI 0x090c
665 #define MMC_RXOCTETCOUNT_G_LO 0x0910
666 #define MMC_RXOCTETCOUNT_G_HI 0x0914
667 #define MMC_RXBROADCASTFRAMES_G_LO 0x0918
668 #define MMC_RXBROADCASTFRAMES_G_HI 0x091c
669 #define MMC_RXMULTICASTFRAMES_G_LO 0x0920
670 #define MMC_RXMULTICASTFRAMES_G_HI 0x0924
671 #define MMC_RXCRCERROR_LO 0x0928
672 #define MMC_RXCRCERROR_HI 0x092c
673 #define MMC_RXRUNTERROR 0x0930
674 #define MMC_RXJABBERERROR 0x0934
675 #define MMC_RXUNDERSIZE_G 0x0938
676 #define MMC_RXOVERSIZE_G 0x093c
677 #define MMC_RX64OCTETS_GB_LO 0x0940
678 #define MMC_RX64OCTETS_GB_HI 0x0944
679 #define MMC_RX65TO127OCTETS_GB_LO 0x0948
680 #define MMC_RX65TO127OCTETS_GB_HI 0x094c
681 #define MMC_RX128TO255OCTETS_GB_LO 0x0950
682 #define MMC_RX128TO255OCTETS_GB_HI 0x0954
683 #define MMC_RX256TO511OCTETS_GB_LO 0x0958
684 #define MMC_RX256TO511OCTETS_GB_HI 0x095c
685 #define MMC_RX512TO1023OCTETS_GB_LO 0x0960
686 #define MMC_RX512TO1023OCTETS_GB_HI 0x0964
687 #define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968
688 #define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c
689 #define MMC_RXUNICASTFRAMES_G_LO 0x0970
690 #define MMC_RXUNICASTFRAMES_G_HI 0x0974
691 #define MMC_RXLENGTHERROR_LO 0x0978
692 #define MMC_RXLENGTHERROR_HI 0x097c
693 #define MMC_RXOUTOFRANGETYPE_LO 0x0980
694 #define MMC_RXOUTOFRANGETYPE_HI 0x0984
695 #define MMC_RXPAUSEFRAMES_LO 0x0988
696 #define MMC_RXPAUSEFRAMES_HI 0x098c
697 #define MMC_RXFIFOOVERFLOW_LO 0x0990
698 #define MMC_RXFIFOOVERFLOW_HI 0x0994
699 #define MMC_RXVLANFRAMES_GB_LO 0x0998
700 #define MMC_RXVLANFRAMES_GB_HI 0x099c
701 #define MMC_RXWATCHDOGERROR 0x09a0
703 /* MMC register entry bit positions and sizes */
704 #define MMC_CR_CR_INDEX 0
705 #define MMC_CR_CR_WIDTH 1
706 #define MMC_CR_CSR_INDEX 1
707 #define MMC_CR_CSR_WIDTH 1
708 #define MMC_CR_ROR_INDEX 2
709 #define MMC_CR_ROR_WIDTH 1
710 #define MMC_CR_MCF_INDEX 3
711 #define MMC_CR_MCF_WIDTH 1
712 #define MMC_CR_MCT_INDEX 4
713 #define MMC_CR_MCT_WIDTH 2
714 #define MMC_RIER_ALL_INTERRUPTS_INDEX 0
715 #define MMC_RIER_ALL_INTERRUPTS_WIDTH 23
716 #define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0
717 #define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1
718 #define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1
719 #define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1
720 #define MMC_RISR_RXOCTETCOUNT_G_INDEX 2
721 #define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1
722 #define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3
723 #define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1
724 #define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4
725 #define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1
726 #define MMC_RISR_RXCRCERROR_INDEX 5
727 #define MMC_RISR_RXCRCERROR_WIDTH 1
728 #define MMC_RISR_RXRUNTERROR_INDEX 6
729 #define MMC_RISR_RXRUNTERROR_WIDTH 1
730 #define MMC_RISR_RXJABBERERROR_INDEX 7
731 #define MMC_RISR_RXJABBERERROR_WIDTH 1
732 #define MMC_RISR_RXUNDERSIZE_G_INDEX 8
733 #define MMC_RISR_RXUNDERSIZE_G_WIDTH 1
734 #define MMC_RISR_RXOVERSIZE_G_INDEX 9
735 #define MMC_RISR_RXOVERSIZE_G_WIDTH 1
736 #define MMC_RISR_RX64OCTETS_GB_INDEX 10
737 #define MMC_RISR_RX64OCTETS_GB_WIDTH 1
738 #define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11
739 #define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1
740 #define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12
741 #define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1
742 #define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13
743 #define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1
744 #define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14
745 #define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1
746 #define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15
747 #define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1
748 #define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16
749 #define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1
750 #define MMC_RISR_RXLENGTHERROR_INDEX 17
751 #define MMC_RISR_RXLENGTHERROR_WIDTH 1
752 #define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18
753 #define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1
754 #define MMC_RISR_RXPAUSEFRAMES_INDEX 19
755 #define MMC_RISR_RXPAUSEFRAMES_WIDTH 1
756 #define MMC_RISR_RXFIFOOVERFLOW_INDEX 20
757 #define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1
758 #define MMC_RISR_RXVLANFRAMES_GB_INDEX 21
759 #define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1
760 #define MMC_RISR_RXWATCHDOGERROR_INDEX 22
761 #define MMC_RISR_RXWATCHDOGERROR_WIDTH 1
762 #define MMC_TIER_ALL_INTERRUPTS_INDEX 0
763 #define MMC_TIER_ALL_INTERRUPTS_WIDTH 18
764 #define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0
765 #define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1
766 #define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1
767 #define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1
768 #define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2
769 #define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1
770 #define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3
771 #define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1
772 #define MMC_TISR_TX64OCTETS_GB_INDEX 4
773 #define MMC_TISR_TX64OCTETS_GB_WIDTH 1
774 #define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5
775 #define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1
776 #define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6
777 #define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1
778 #define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7
779 #define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1
780 #define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8
781 #define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1
782 #define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9
783 #define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1
784 #define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10
785 #define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1
786 #define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11
787 #define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1
788 #define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12
789 #define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1
790 #define MMC_TISR_TXUNDERFLOWERROR_INDEX 13
791 #define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1
792 #define MMC_TISR_TXOCTETCOUNT_G_INDEX 14
793 #define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1
794 #define MMC_TISR_TXFRAMECOUNT_G_INDEX 15
795 #define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1
796 #define MMC_TISR_TXPAUSEFRAMES_INDEX 16
797 #define MMC_TISR_TXPAUSEFRAMES_WIDTH 1
798 #define MMC_TISR_TXVLANFRAMES_G_INDEX 17
799 #define MMC_TISR_TXVLANFRAMES_G_WIDTH 1
801 /* MTL register offsets */
802 #define MTL_OMR 0x1000
803 #define MTL_FDCR 0x1008
804 #define MTL_FDSR 0x100c
805 #define MTL_FDDR 0x1010
806 #define MTL_ISR 0x1020
807 #define MTL_RQDCM0R 0x1030
808 #define MTL_RQDCM1R 0x1034
809 #define MTL_RQDCM2R 0x1038
810 #define MTL_TCPM0R 0x1040
811 #define MTL_TCPM1R 0x1044
813 #define MTL_RQDCM_INC 4
814 #define MTL_RQDCM_Q_PER_REG 4
815 #define MTL_TCPM_INC 4
816 #define MTL_TCPM_TC_PER_REG 4
818 /* MTL register entry bit positions and sizes */
819 #define MTL_OMR_ETSALG_INDEX 5
820 #define MTL_OMR_ETSALG_WIDTH 2
821 #define MTL_OMR_RAA_INDEX 2
822 #define MTL_OMR_RAA_WIDTH 1
824 /* MTL queue register offsets
825 * Multiple queues can be active. The first queue has registers
826 * that begin at 0x1100. Each subsequent queue has registers that
827 * are accessed using an offset of 0x80 from the previous queue.
829 #define MTL_Q_BASE 0x1100
830 #define MTL_Q_INC 0x80
832 #define MTL_Q_TQOMR 0x00
833 #define MTL_Q_TQUR 0x04
834 #define MTL_Q_TQDR 0x08
835 #define MTL_Q_TC0ETSCR 0x10
836 #define MTL_Q_TC0ETSSR 0x14
837 #define MTL_Q_TC0QWR 0x18
838 #define MTL_Q_RQOMR 0x40
839 #define MTL_Q_RQMPOCR 0x44
840 #define MTL_Q_RQDR 0x48
841 #define MTL_Q_RQCR 0x4c
842 #define MTL_Q_RQFCR 0x50
843 #define MTL_Q_IER 0x70
844 #define MTL_Q_ISR 0x74
846 /* MTL queue register entry bit positions and sizes */
847 #define MTL_Q_RQDR_PRXQ_INDEX 16
848 #define MTL_Q_RQDR_PRXQ_WIDTH 14
849 #define MTL_Q_RQDR_RXQSTS_INDEX 4
850 #define MTL_Q_RQDR_RXQSTS_WIDTH 2
851 #define MTL_Q_RQFCR_RFA_INDEX 1
852 #define MTL_Q_RQFCR_RFA_WIDTH 6
853 #define MTL_Q_RQFCR_RFD_INDEX 17
854 #define MTL_Q_RQFCR_RFD_WIDTH 6
855 #define MTL_Q_RQOMR_EHFC_INDEX 7
856 #define MTL_Q_RQOMR_EHFC_WIDTH 1
857 #define MTL_Q_RQOMR_RQS_INDEX 16
858 #define MTL_Q_RQOMR_RQS_WIDTH 9
859 #define MTL_Q_RQOMR_RSF_INDEX 5
860 #define MTL_Q_RQOMR_RSF_WIDTH 1
861 #define MTL_Q_RQOMR_RTC_INDEX 0
862 #define MTL_Q_RQOMR_RTC_WIDTH 2
863 #define MTL_Q_TQDR_TRCSTS_INDEX 1
864 #define MTL_Q_TQDR_TRCSTS_WIDTH 2
865 #define MTL_Q_TQDR_TXQSTS_INDEX 4
866 #define MTL_Q_TQDR_TXQSTS_WIDTH 1
867 #define MTL_Q_TQOMR_FTQ_INDEX 0
868 #define MTL_Q_TQOMR_FTQ_WIDTH 1
869 #define MTL_Q_TQOMR_Q2TCMAP_INDEX 8
870 #define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3
871 #define MTL_Q_TQOMR_TQS_INDEX 16
872 #define MTL_Q_TQOMR_TQS_WIDTH 10
873 #define MTL_Q_TQOMR_TSF_INDEX 1
874 #define MTL_Q_TQOMR_TSF_WIDTH 1
875 #define MTL_Q_TQOMR_TTC_INDEX 4
876 #define MTL_Q_TQOMR_TTC_WIDTH 3
877 #define MTL_Q_TQOMR_TXQEN_INDEX 2
878 #define MTL_Q_TQOMR_TXQEN_WIDTH 2
880 /* MTL queue register value */
881 #define MTL_RSF_DISABLE 0x00
882 #define MTL_RSF_ENABLE 0x01
883 #define MTL_TSF_DISABLE 0x00
884 #define MTL_TSF_ENABLE 0x01
886 #define MTL_RX_THRESHOLD_64 0x00
887 #define MTL_RX_THRESHOLD_96 0x02
888 #define MTL_RX_THRESHOLD_128 0x03
889 #define MTL_TX_THRESHOLD_32 0x01
890 #define MTL_TX_THRESHOLD_64 0x00
891 #define MTL_TX_THRESHOLD_96 0x02
892 #define MTL_TX_THRESHOLD_128 0x03
893 #define MTL_TX_THRESHOLD_192 0x04
894 #define MTL_TX_THRESHOLD_256 0x05
895 #define MTL_TX_THRESHOLD_384 0x06
896 #define MTL_TX_THRESHOLD_512 0x07
898 #define MTL_ETSALG_WRR 0x00
899 #define MTL_ETSALG_WFQ 0x01
900 #define MTL_ETSALG_DWRR 0x02
901 #define MTL_RAA_SP 0x00
902 #define MTL_RAA_WSP 0x01
904 #define MTL_Q_DISABLED 0x00
905 #define MTL_Q_ENABLED 0x02
907 /* MTL traffic class register offsets
908 * Multiple traffic classes can be active. The first class has registers
909 * that begin at 0x1100. Each subsequent queue has registers that
910 * are accessed using an offset of 0x80 from the previous queue.
912 #define MTL_TC_BASE MTL_Q_BASE
913 #define MTL_TC_INC MTL_Q_INC
915 #define MTL_TC_ETSCR 0x10
916 #define MTL_TC_ETSSR 0x14
917 #define MTL_TC_QWR 0x18
919 /* MTL traffic class register entry bit positions and sizes */
920 #define MTL_TC_ETSCR_TSA_INDEX 0
921 #define MTL_TC_ETSCR_TSA_WIDTH 2
922 #define MTL_TC_QWR_QW_INDEX 0
923 #define MTL_TC_QWR_QW_WIDTH 21
925 /* MTL traffic class register value */
926 #define MTL_TSA_SP 0x00
927 #define MTL_TSA_ETS 0x02
929 /* PCS MMD select register offset
930 * The MMD select register is used for accessing PCS registers
931 * when the underlying APB3 interface is using indirect addressing.
932 * Indirect addressing requires accessing registers in two phases,
933 * an address phase and a data phase. The address phases requires
934 * writing an address selection value to the MMD select regiesters.
936 #define PCS_V1_WINDOW_SELECT 0x03fc
937 #define PCS_V2_WINDOW_DEF 0x9060
938 #define PCS_V2_WINDOW_SELECT 0x9064
939 #define PCS_V2_RV_WINDOW_DEF 0x1060
940 #define PCS_V2_RV_WINDOW_SELECT 0x1064
942 /* PCS register entry bit positions and sizes */
943 #define PCS_V2_WINDOW_DEF_OFFSET_INDEX 6
944 #define PCS_V2_WINDOW_DEF_OFFSET_WIDTH 14
945 #define PCS_V2_WINDOW_DEF_SIZE_INDEX 2
946 #define PCS_V2_WINDOW_DEF_SIZE_WIDTH 4
948 /* SerDes integration register offsets */
949 #define SIR0_KR_RT_1 0x002c
950 #define SIR0_STATUS 0x0040
951 #define SIR1_SPEED 0x0000
953 /* SerDes integration register entry bit positions and sizes */
954 #define SIR0_KR_RT_1_RESET_INDEX 11
955 #define SIR0_KR_RT_1_RESET_WIDTH 1
956 #define SIR0_STATUS_RX_READY_INDEX 0
957 #define SIR0_STATUS_RX_READY_WIDTH 1
958 #define SIR0_STATUS_TX_READY_INDEX 8
959 #define SIR0_STATUS_TX_READY_WIDTH 1
960 #define SIR1_SPEED_CDR_RATE_INDEX 12
961 #define SIR1_SPEED_CDR_RATE_WIDTH 4
962 #define SIR1_SPEED_DATARATE_INDEX 4
963 #define SIR1_SPEED_DATARATE_WIDTH 2
964 #define SIR1_SPEED_PLLSEL_INDEX 3
965 #define SIR1_SPEED_PLLSEL_WIDTH 1
966 #define SIR1_SPEED_RATECHANGE_INDEX 6
967 #define SIR1_SPEED_RATECHANGE_WIDTH 1
968 #define SIR1_SPEED_TXAMP_INDEX 8
969 #define SIR1_SPEED_TXAMP_WIDTH 4
970 #define SIR1_SPEED_WORDMODE_INDEX 0
971 #define SIR1_SPEED_WORDMODE_WIDTH 3
973 /* SerDes RxTx register offsets */
974 #define RXTX_REG6 0x0018
975 #define RXTX_REG20 0x0050
976 #define RXTX_REG22 0x0058
977 #define RXTX_REG114 0x01c8
978 #define RXTX_REG129 0x0204
980 /* SerDes RxTx register entry bit positions and sizes */
981 #define RXTX_REG6_RESETB_RXD_INDEX 8
982 #define RXTX_REG6_RESETB_RXD_WIDTH 1
983 #define RXTX_REG20_BLWC_ENA_INDEX 2
984 #define RXTX_REG20_BLWC_ENA_WIDTH 1
985 #define RXTX_REG114_PQ_REG_INDEX 9
986 #define RXTX_REG114_PQ_REG_WIDTH 7
987 #define RXTX_REG129_RXDFE_CONFIG_INDEX 14
988 #define RXTX_REG129_RXDFE_CONFIG_WIDTH 2
990 /* MAC Control register offsets */
991 #define XP_PROP_0 0x0000
992 #define XP_PROP_1 0x0004
993 #define XP_PROP_2 0x0008
994 #define XP_PROP_3 0x000c
995 #define XP_PROP_4 0x0010
996 #define XP_PROP_5 0x0014
997 #define XP_MAC_ADDR_LO 0x0020
998 #define XP_MAC_ADDR_HI 0x0024
999 #define XP_ECC_ISR 0x0030
1000 #define XP_ECC_IER 0x0034
1001 #define XP_ECC_CNT0 0x003c
1002 #define XP_ECC_CNT1 0x0040
1003 #define XP_DRIVER_INT_REQ 0x0060
1004 #define XP_DRIVER_INT_RO 0x0064
1005 #define XP_DRIVER_SCRATCH_0 0x0068
1006 #define XP_DRIVER_SCRATCH_1 0x006c
1007 #define XP_INT_REISSUE_EN 0x0074
1008 #define XP_INT_EN 0x0078
1009 #define XP_I2C_MUTEX 0x0080
1010 #define XP_MDIO_MUTEX 0x0084
1012 /* MAC Control register entry bit positions and sizes */
1013 #define XP_DRIVER_INT_REQ_REQUEST_INDEX 0
1014 #define XP_DRIVER_INT_REQ_REQUEST_WIDTH 1
1015 #define XP_DRIVER_INT_RO_STATUS_INDEX 0
1016 #define XP_DRIVER_INT_RO_STATUS_WIDTH 1
1017 #define XP_DRIVER_SCRATCH_0_COMMAND_INDEX 0
1018 #define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH 8
1019 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX 8
1020 #define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH 8
1021 #define XP_ECC_CNT0_RX_DED_INDEX 24
1022 #define XP_ECC_CNT0_RX_DED_WIDTH 8
1023 #define XP_ECC_CNT0_RX_SEC_INDEX 16
1024 #define XP_ECC_CNT0_RX_SEC_WIDTH 8
1025 #define XP_ECC_CNT0_TX_DED_INDEX 8
1026 #define XP_ECC_CNT0_TX_DED_WIDTH 8
1027 #define XP_ECC_CNT0_TX_SEC_INDEX 0
1028 #define XP_ECC_CNT0_TX_SEC_WIDTH 8
1029 #define XP_ECC_CNT1_DESC_DED_INDEX 8
1030 #define XP_ECC_CNT1_DESC_DED_WIDTH 8
1031 #define XP_ECC_CNT1_DESC_SEC_INDEX 0
1032 #define XP_ECC_CNT1_DESC_SEC_WIDTH 8
1033 #define XP_ECC_IER_DESC_DED_INDEX 5
1034 #define XP_ECC_IER_DESC_DED_WIDTH 1
1035 #define XP_ECC_IER_DESC_SEC_INDEX 4
1036 #define XP_ECC_IER_DESC_SEC_WIDTH 1
1037 #define XP_ECC_IER_RX_DED_INDEX 3
1038 #define XP_ECC_IER_RX_DED_WIDTH 1
1039 #define XP_ECC_IER_RX_SEC_INDEX 2
1040 #define XP_ECC_IER_RX_SEC_WIDTH 1
1041 #define XP_ECC_IER_TX_DED_INDEX 1
1042 #define XP_ECC_IER_TX_DED_WIDTH 1
1043 #define XP_ECC_IER_TX_SEC_INDEX 0
1044 #define XP_ECC_IER_TX_SEC_WIDTH 1
1045 #define XP_ECC_ISR_DESC_DED_INDEX 5
1046 #define XP_ECC_ISR_DESC_DED_WIDTH 1
1047 #define XP_ECC_ISR_DESC_SEC_INDEX 4
1048 #define XP_ECC_ISR_DESC_SEC_WIDTH 1
1049 #define XP_ECC_ISR_RX_DED_INDEX 3
1050 #define XP_ECC_ISR_RX_DED_WIDTH 1
1051 #define XP_ECC_ISR_RX_SEC_INDEX 2
1052 #define XP_ECC_ISR_RX_SEC_WIDTH 1
1053 #define XP_ECC_ISR_TX_DED_INDEX 1
1054 #define XP_ECC_ISR_TX_DED_WIDTH 1
1055 #define XP_ECC_ISR_TX_SEC_INDEX 0
1056 #define XP_ECC_ISR_TX_SEC_WIDTH 1
1057 #define XP_I2C_MUTEX_BUSY_INDEX 31
1058 #define XP_I2C_MUTEX_BUSY_WIDTH 1
1059 #define XP_I2C_MUTEX_ID_INDEX 29
1060 #define XP_I2C_MUTEX_ID_WIDTH 2
1061 #define XP_I2C_MUTEX_ACTIVE_INDEX 0
1062 #define XP_I2C_MUTEX_ACTIVE_WIDTH 1
1063 #define XP_MAC_ADDR_HI_VALID_INDEX 31
1064 #define XP_MAC_ADDR_HI_VALID_WIDTH 1
1065 #define XP_PROP_0_CONN_TYPE_INDEX 28
1066 #define XP_PROP_0_CONN_TYPE_WIDTH 3
1067 #define XP_PROP_0_MDIO_ADDR_INDEX 16
1068 #define XP_PROP_0_MDIO_ADDR_WIDTH 5
1069 #define XP_PROP_0_PORT_ID_INDEX 0
1070 #define XP_PROP_0_PORT_ID_WIDTH 8
1071 #define XP_PROP_0_PORT_MODE_INDEX 8
1072 #define XP_PROP_0_PORT_MODE_WIDTH 4
1073 #define XP_PROP_0_PORT_SPEEDS_INDEX 23
1074 #define XP_PROP_0_PORT_SPEEDS_WIDTH 4
1075 #define XP_PROP_1_MAX_RX_DMA_INDEX 24
1076 #define XP_PROP_1_MAX_RX_DMA_WIDTH 5
1077 #define XP_PROP_1_MAX_RX_QUEUES_INDEX 8
1078 #define XP_PROP_1_MAX_RX_QUEUES_WIDTH 5
1079 #define XP_PROP_1_MAX_TX_DMA_INDEX 16
1080 #define XP_PROP_1_MAX_TX_DMA_WIDTH 5
1081 #define XP_PROP_1_MAX_TX_QUEUES_INDEX 0
1082 #define XP_PROP_1_MAX_TX_QUEUES_WIDTH 5
1083 #define XP_PROP_2_RX_FIFO_SIZE_INDEX 16
1084 #define XP_PROP_2_RX_FIFO_SIZE_WIDTH 16
1085 #define XP_PROP_2_TX_FIFO_SIZE_INDEX 0
1086 #define XP_PROP_2_TX_FIFO_SIZE_WIDTH 16
1087 #define XP_PROP_3_GPIO_MASK_INDEX 28
1088 #define XP_PROP_3_GPIO_MASK_WIDTH 4
1089 #define XP_PROP_3_GPIO_MOD_ABS_INDEX 20
1090 #define XP_PROP_3_GPIO_MOD_ABS_WIDTH 4
1091 #define XP_PROP_3_GPIO_RATE_SELECT_INDEX 16
1092 #define XP_PROP_3_GPIO_RATE_SELECT_WIDTH 4
1093 #define XP_PROP_3_GPIO_RX_LOS_INDEX 24
1094 #define XP_PROP_3_GPIO_RX_LOS_WIDTH 4
1095 #define XP_PROP_3_GPIO_TX_FAULT_INDEX 12
1096 #define XP_PROP_3_GPIO_TX_FAULT_WIDTH 4
1097 #define XP_PROP_3_GPIO_ADDR_INDEX 8
1098 #define XP_PROP_3_GPIO_ADDR_WIDTH 3
1099 #define XP_PROP_3_MDIO_RESET_INDEX 0
1100 #define XP_PROP_3_MDIO_RESET_WIDTH 2
1101 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_INDEX 8
1102 #define XP_PROP_3_MDIO_RESET_I2C_ADDR_WIDTH 3
1103 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_INDEX 12
1104 #define XP_PROP_3_MDIO_RESET_I2C_GPIO_WIDTH 4
1105 #define XP_PROP_3_MDIO_RESET_INT_GPIO_INDEX 4
1106 #define XP_PROP_3_MDIO_RESET_INT_GPIO_WIDTH 2
1107 #define XP_PROP_4_MUX_ADDR_HI_INDEX 8
1108 #define XP_PROP_4_MUX_ADDR_HI_WIDTH 5
1109 #define XP_PROP_4_MUX_ADDR_LO_INDEX 0
1110 #define XP_PROP_4_MUX_ADDR_LO_WIDTH 3
1111 #define XP_PROP_4_MUX_CHAN_INDEX 4
1112 #define XP_PROP_4_MUX_CHAN_WIDTH 3
1113 #define XP_PROP_4_REDRV_ADDR_INDEX 16
1114 #define XP_PROP_4_REDRV_ADDR_WIDTH 7
1115 #define XP_PROP_4_REDRV_IF_INDEX 23
1116 #define XP_PROP_4_REDRV_IF_WIDTH 1
1117 #define XP_PROP_4_REDRV_LANE_INDEX 24
1118 #define XP_PROP_4_REDRV_LANE_WIDTH 3
1119 #define XP_PROP_4_REDRV_MODEL_INDEX 28
1120 #define XP_PROP_4_REDRV_MODEL_WIDTH 3
1121 #define XP_PROP_4_REDRV_PRESENT_INDEX 31
1122 #define XP_PROP_4_REDRV_PRESENT_WIDTH 1
1124 /* I2C Control register offsets */
1125 #define IC_CON 0x0000
1126 #define IC_TAR 0x0004
1127 #define IC_DATA_CMD 0x0010
1128 #define IC_INTR_STAT 0x002c
1129 #define IC_INTR_MASK 0x0030
1130 #define IC_RAW_INTR_STAT 0x0034
1131 #define IC_CLR_INTR 0x0040
1132 #define IC_CLR_TX_ABRT 0x0054
1133 #define IC_CLR_STOP_DET 0x0060
1134 #define IC_ENABLE 0x006c
1135 #define IC_TXFLR 0x0074
1136 #define IC_RXFLR 0x0078
1137 #define IC_TX_ABRT_SOURCE 0x0080
1138 #define IC_ENABLE_STATUS 0x009c
1139 #define IC_COMP_PARAM_1 0x00f4
1141 /* I2C Control register entry bit positions and sizes */
1142 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_INDEX 2
1143 #define IC_COMP_PARAM_1_MAX_SPEED_MODE_WIDTH 2
1144 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_INDEX 8
1145 #define IC_COMP_PARAM_1_RX_BUFFER_DEPTH_WIDTH 8
1146 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_INDEX 16
1147 #define IC_COMP_PARAM_1_TX_BUFFER_DEPTH_WIDTH 8
1148 #define IC_CON_MASTER_MODE_INDEX 0
1149 #define IC_CON_MASTER_MODE_WIDTH 1
1150 #define IC_CON_RESTART_EN_INDEX 5
1151 #define IC_CON_RESTART_EN_WIDTH 1
1152 #define IC_CON_RX_FIFO_FULL_HOLD_INDEX 9
1153 #define IC_CON_RX_FIFO_FULL_HOLD_WIDTH 1
1154 #define IC_CON_SLAVE_DISABLE_INDEX 6
1155 #define IC_CON_SLAVE_DISABLE_WIDTH 1
1156 #define IC_CON_SPEED_INDEX 1
1157 #define IC_CON_SPEED_WIDTH 2
1158 #define IC_DATA_CMD_CMD_INDEX 8
1159 #define IC_DATA_CMD_CMD_WIDTH 1
1160 #define IC_DATA_CMD_STOP_INDEX 9
1161 #define IC_DATA_CMD_STOP_WIDTH 1
1162 #define IC_ENABLE_ABORT_INDEX 1
1163 #define IC_ENABLE_ABORT_WIDTH 1
1164 #define IC_ENABLE_EN_INDEX 0
1165 #define IC_ENABLE_EN_WIDTH 1
1166 #define IC_ENABLE_STATUS_EN_INDEX 0
1167 #define IC_ENABLE_STATUS_EN_WIDTH 1
1168 #define IC_INTR_MASK_TX_EMPTY_INDEX 4
1169 #define IC_INTR_MASK_TX_EMPTY_WIDTH 1
1170 #define IC_RAW_INTR_STAT_RX_FULL_INDEX 2
1171 #define IC_RAW_INTR_STAT_RX_FULL_WIDTH 1
1172 #define IC_RAW_INTR_STAT_STOP_DET_INDEX 9
1173 #define IC_RAW_INTR_STAT_STOP_DET_WIDTH 1
1174 #define IC_RAW_INTR_STAT_TX_ABRT_INDEX 6
1175 #define IC_RAW_INTR_STAT_TX_ABRT_WIDTH 1
1176 #define IC_RAW_INTR_STAT_TX_EMPTY_INDEX 4
1177 #define IC_RAW_INTR_STAT_TX_EMPTY_WIDTH 1
1179 /* I2C Control register value */
1180 #define IC_TX_ABRT_7B_ADDR_NOACK 0x0001
1181 #define IC_TX_ABRT_ARB_LOST 0x1000
1183 /* Descriptor/Packet entry bit positions and sizes */
1184 #define RX_PACKET_ERRORS_CRC_INDEX 2
1185 #define RX_PACKET_ERRORS_CRC_WIDTH 1
1186 #define RX_PACKET_ERRORS_FRAME_INDEX 3
1187 #define RX_PACKET_ERRORS_FRAME_WIDTH 1
1188 #define RX_PACKET_ERRORS_LENGTH_INDEX 0
1189 #define RX_PACKET_ERRORS_LENGTH_WIDTH 1
1190 #define RX_PACKET_ERRORS_OVERRUN_INDEX 1
1191 #define RX_PACKET_ERRORS_OVERRUN_WIDTH 1
1193 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0
1194 #define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1
1195 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1
1196 #define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
1197 #define RX_PACKET_ATTRIBUTES_LAST_INDEX 2
1198 #define RX_PACKET_ATTRIBUTES_LAST_WIDTH 1
1199 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3
1200 #define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1
1201 #define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4
1202 #define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1
1203 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5
1204 #define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1
1205 #define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6
1206 #define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1
1207 #define RX_PACKET_ATTRIBUTES_FIRST_INDEX 7
1208 #define RX_PACKET_ATTRIBUTES_FIRST_WIDTH 1
1209 #define RX_PACKET_ATTRIBUTES_TNP_INDEX 8
1210 #define RX_PACKET_ATTRIBUTES_TNP_WIDTH 1
1211 #define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_INDEX 9
1212 #define RX_PACKET_ATTRIBUTES_TNPCSUM_DONE_WIDTH 1
1214 #define RX_NORMAL_DESC0_OVT_INDEX 0
1215 #define RX_NORMAL_DESC0_OVT_WIDTH 16
1216 #define RX_NORMAL_DESC2_HL_INDEX 0
1217 #define RX_NORMAL_DESC2_HL_WIDTH 10
1218 #define RX_NORMAL_DESC2_TNP_INDEX 11
1219 #define RX_NORMAL_DESC2_TNP_WIDTH 1
1220 #define RX_NORMAL_DESC2_RPNG_INDEX 14
1221 #define RX_NORMAL_DESC2_RPNG_WIDTH 1
1222 #define RX_NORMAL_DESC3_CDA_INDEX 27
1223 #define RX_NORMAL_DESC3_CDA_WIDTH 1
1224 #define RX_NORMAL_DESC3_CTXT_INDEX 30
1225 #define RX_NORMAL_DESC3_CTXT_WIDTH 1
1226 #define RX_NORMAL_DESC3_ES_INDEX 15
1227 #define RX_NORMAL_DESC3_ES_WIDTH 1
1228 #define RX_NORMAL_DESC3_ETLT_INDEX 16
1229 #define RX_NORMAL_DESC3_ETLT_WIDTH 4
1230 #define RX_NORMAL_DESC3_FD_INDEX 29
1231 #define RX_NORMAL_DESC3_FD_WIDTH 1
1232 #define RX_NORMAL_DESC3_INTE_INDEX 30
1233 #define RX_NORMAL_DESC3_INTE_WIDTH 1
1234 #define RX_NORMAL_DESC3_L34T_INDEX 20
1235 #define RX_NORMAL_DESC3_L34T_WIDTH 4
1236 #define RX_NORMAL_DESC3_LD_INDEX 28
1237 #define RX_NORMAL_DESC3_LD_WIDTH 1
1238 #define RX_NORMAL_DESC3_OWN_INDEX 31
1239 #define RX_NORMAL_DESC3_OWN_WIDTH 1
1240 #define RX_NORMAL_DESC3_PL_INDEX 0
1241 #define RX_NORMAL_DESC3_PL_WIDTH 14
1242 #define RX_NORMAL_DESC3_RSV_INDEX 26
1243 #define RX_NORMAL_DESC3_RSV_WIDTH 1
1245 #define RX_DESC3_L34T_IPV4_TCP 1
1246 #define RX_DESC3_L34T_IPV4_UDP 2
1247 #define RX_DESC3_L34T_IPV4_ICMP 3
1248 #define RX_DESC3_L34T_IPV4_UNKNOWN 7
1249 #define RX_DESC3_L34T_IPV6_TCP 9
1250 #define RX_DESC3_L34T_IPV6_UDP 10
1251 #define RX_DESC3_L34T_IPV6_ICMP 11
1252 #define RX_DESC3_L34T_IPV6_UNKNOWN 15
1254 #define RX_CONTEXT_DESC3_TSA_INDEX 4
1255 #define RX_CONTEXT_DESC3_TSA_WIDTH 1
1256 #define RX_CONTEXT_DESC3_TSD_INDEX 6
1257 #define RX_CONTEXT_DESC3_TSD_WIDTH 1
1259 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0
1260 #define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1
1261 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1
1262 #define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1
1263 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2
1264 #define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
1265 #define TX_PACKET_ATTRIBUTES_PTP_INDEX 3
1266 #define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1
1267 #define TX_PACKET_ATTRIBUTES_VXLAN_INDEX 4
1268 #define TX_PACKET_ATTRIBUTES_VXLAN_WIDTH 1
1270 #define TX_CONTEXT_DESC2_MSS_INDEX 0
1271 #define TX_CONTEXT_DESC2_MSS_WIDTH 15
1272 #define TX_CONTEXT_DESC3_CTXT_INDEX 30
1273 #define TX_CONTEXT_DESC3_CTXT_WIDTH 1
1274 #define TX_CONTEXT_DESC3_TCMSSV_INDEX 26
1275 #define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1
1276 #define TX_CONTEXT_DESC3_VLTV_INDEX 16
1277 #define TX_CONTEXT_DESC3_VLTV_WIDTH 1
1278 #define TX_CONTEXT_DESC3_VT_INDEX 0
1279 #define TX_CONTEXT_DESC3_VT_WIDTH 16
1281 #define TX_NORMAL_DESC2_HL_B1L_INDEX 0
1282 #define TX_NORMAL_DESC2_HL_B1L_WIDTH 14
1283 #define TX_NORMAL_DESC2_IC_INDEX 31
1284 #define TX_NORMAL_DESC2_IC_WIDTH 1
1285 #define TX_NORMAL_DESC2_TTSE_INDEX 30
1286 #define TX_NORMAL_DESC2_TTSE_WIDTH 1
1287 #define TX_NORMAL_DESC2_VTIR_INDEX 14
1288 #define TX_NORMAL_DESC2_VTIR_WIDTH 2
1289 #define TX_NORMAL_DESC3_CIC_INDEX 16
1290 #define TX_NORMAL_DESC3_CIC_WIDTH 2
1291 #define TX_NORMAL_DESC3_CPC_INDEX 26
1292 #define TX_NORMAL_DESC3_CPC_WIDTH 2
1293 #define TX_NORMAL_DESC3_CTXT_INDEX 30
1294 #define TX_NORMAL_DESC3_CTXT_WIDTH 1
1295 #define TX_NORMAL_DESC3_FD_INDEX 29
1296 #define TX_NORMAL_DESC3_FD_WIDTH 1
1297 #define TX_NORMAL_DESC3_FL_INDEX 0
1298 #define TX_NORMAL_DESC3_FL_WIDTH 15
1299 #define TX_NORMAL_DESC3_LD_INDEX 28
1300 #define TX_NORMAL_DESC3_LD_WIDTH 1
1301 #define TX_NORMAL_DESC3_OWN_INDEX 31
1302 #define TX_NORMAL_DESC3_OWN_WIDTH 1
1303 #define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19
1304 #define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4
1305 #define TX_NORMAL_DESC3_TCPPL_INDEX 0
1306 #define TX_NORMAL_DESC3_TCPPL_WIDTH 18
1307 #define TX_NORMAL_DESC3_TSE_INDEX 18
1308 #define TX_NORMAL_DESC3_TSE_WIDTH 1
1309 #define TX_NORMAL_DESC3_VNP_INDEX 23
1310 #define TX_NORMAL_DESC3_VNP_WIDTH 3
1312 #define TX_NORMAL_DESC2_VLAN_INSERT 0x2
1313 #define TX_NORMAL_DESC3_VXLAN_PACKET 0x3
1315 /* MDIO undefined or vendor specific registers */
1316 #ifndef MDIO_PMA_10GBR_PMD_CTRL
1317 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096
1320 #ifndef MDIO_PMA_10GBR_FECCTRL
1321 #define MDIO_PMA_10GBR_FECCTRL 0x00ab
1324 #ifndef MDIO_PCS_DIG_CTRL
1325 #define MDIO_PCS_DIG_CTRL 0x8000
1329 #define MDIO_AN_XNP 0x0016
1333 #define MDIO_AN_LPX 0x0019
1336 #ifndef MDIO_AN_COMP_STAT
1337 #define MDIO_AN_COMP_STAT 0x0030
1340 #ifndef MDIO_AN_INTMASK
1341 #define MDIO_AN_INTMASK 0x8001
1345 #define MDIO_AN_INT 0x8002
1348 #ifndef MDIO_VEND2_AN_ADVERTISE
1349 #define MDIO_VEND2_AN_ADVERTISE 0x0004
1352 #ifndef MDIO_VEND2_AN_LP_ABILITY
1353 #define MDIO_VEND2_AN_LP_ABILITY 0x0005
1356 #ifndef MDIO_VEND2_AN_CTRL
1357 #define MDIO_VEND2_AN_CTRL 0x8001
1360 #ifndef MDIO_VEND2_AN_STAT
1361 #define MDIO_VEND2_AN_STAT 0x8002
1364 #ifndef MDIO_VEND2_PMA_CDR_CONTROL
1365 #define MDIO_VEND2_PMA_CDR_CONTROL 0x8056
1368 #ifndef MDIO_CTRL1_SPEED1G
1369 #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
1372 #ifndef MDIO_VEND2_CTRL1_AN_ENABLE
1373 #define MDIO_VEND2_CTRL1_AN_ENABLE BIT(12)
1376 #ifndef MDIO_VEND2_CTRL1_AN_RESTART
1377 #define MDIO_VEND2_CTRL1_AN_RESTART BIT(9)
1380 #ifndef MDIO_VEND2_CTRL1_SS6
1381 #define MDIO_VEND2_CTRL1_SS6 BIT(6)
1384 #ifndef MDIO_VEND2_CTRL1_SS13
1385 #define MDIO_VEND2_CTRL1_SS13 BIT(13)
1388 /* MDIO mask values */
1389 #define XGBE_AN_CL73_INT_CMPLT BIT(0)
1390 #define XGBE_AN_CL73_INC_LINK BIT(1)
1391 #define XGBE_AN_CL73_PG_RCV BIT(2)
1392 #define XGBE_AN_CL73_INT_MASK 0x07
1394 #define XGBE_XNP_MCF_NULL_MESSAGE 0x001
1395 #define XGBE_XNP_ACK_PROCESSED BIT(12)
1396 #define XGBE_XNP_MP_FORMATTED BIT(13)
1397 #define XGBE_XNP_NP_EXCHANGE BIT(15)
1399 #define XGBE_KR_TRAINING_START BIT(0)
1400 #define XGBE_KR_TRAINING_ENABLE BIT(1)
1402 #define XGBE_PCS_CL37_BP BIT(12)
1404 #define XGBE_AN_CL37_INT_CMPLT BIT(0)
1405 #define XGBE_AN_CL37_INT_MASK 0x01
1407 #define XGBE_AN_CL37_HD_MASK 0x40
1408 #define XGBE_AN_CL37_FD_MASK 0x20
1410 #define XGBE_AN_CL37_PCS_MODE_MASK 0x06
1411 #define XGBE_AN_CL37_PCS_MODE_BASEX 0x00
1412 #define XGBE_AN_CL37_PCS_MODE_SGMII 0x04
1413 #define XGBE_AN_CL37_TX_CONFIG_MASK 0x08
1414 #define XGBE_AN_CL37_MII_CTRL_8BIT 0x0100
1416 #define XGBE_PMA_CDR_TRACK_EN_MASK 0x01
1417 #define XGBE_PMA_CDR_TRACK_EN_OFF 0x00
1418 #define XGBE_PMA_CDR_TRACK_EN_ON 0x01
1420 /* Bit setting and getting macros
1421 * The get macro will extract the current bit field value from within
1424 * The set macro will clear the current bit field value within the
1425 * variable and then set the bit field of the variable to the
1428 #define GET_BITS(_var, _index, _width) \
1429 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
1431 #define SET_BITS(_var, _index, _width, _val) \
1433 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
1434 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
1437 #define GET_BITS_LE(_var, _index, _width) \
1438 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
1440 #define SET_BITS_LE(_var, _index, _width, _val) \
1442 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \
1443 (_var) |= cpu_to_le32((((_val) & \
1444 ((0x1 << (_width)) - 1)) << (_index))); \
1447 /* Bit setting and getting macros based on register fields
1448 * The get macro uses the bit field definitions formed using the input
1449 * names to extract the current bit field value from within the
1452 * The set macro uses the bit field definitions formed using the input
1453 * names to set the bit field of the variable to the specified value
1455 #define XGMAC_GET_BITS(_var, _prefix, _field) \
1457 _prefix##_##_field##_INDEX, \
1458 _prefix##_##_field##_WIDTH)
1460 #define XGMAC_SET_BITS(_var, _prefix, _field, _val) \
1462 _prefix##_##_field##_INDEX, \
1463 _prefix##_##_field##_WIDTH, (_val))
1465 #define XGMAC_GET_BITS_LE(_var, _prefix, _field) \
1466 GET_BITS_LE((_var), \
1467 _prefix##_##_field##_INDEX, \
1468 _prefix##_##_field##_WIDTH)
1470 #define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \
1471 SET_BITS_LE((_var), \
1472 _prefix##_##_field##_INDEX, \
1473 _prefix##_##_field##_WIDTH, (_val))
1475 /* Macros for reading or writing registers
1476 * The ioread macros will get bit fields or full values using the
1477 * register definitions formed using the input names
1479 * The iowrite macros will set bit fields or full values using the
1480 * register definitions formed using the input names
1482 #define XGMAC_IOREAD(_pdata, _reg) \
1483 bus_read_4((_pdata)->xgmac_res, _reg)
1485 #define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \
1486 GET_BITS(XGMAC_IOREAD((_pdata), _reg), \
1487 _reg##_##_field##_INDEX, \
1488 _reg##_##_field##_WIDTH)
1490 #define XGMAC_IOWRITE(_pdata, _reg, _val) \
1491 bus_write_4((_pdata)->xgmac_res, _reg, (_val))
1493 #define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1495 uint32_t reg_val = XGMAC_IOREAD((_pdata), _reg); \
1497 _reg##_##_field##_INDEX, \
1498 _reg##_##_field##_WIDTH, (_val)); \
1499 XGMAC_IOWRITE((_pdata), _reg, reg_val); \
1502 /* Macros for reading or writing MTL queue or traffic class registers
1503 * Similar to the standard read and write macros except that the
1504 * base register value is calculated by the queue or traffic class number
1506 #define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \
1507 bus_read_4((_pdata)->xgmac_res, \
1508 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg)
1510 #define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \
1511 GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \
1512 _reg##_##_field##_INDEX, \
1513 _reg##_##_field##_WIDTH)
1515 #define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \
1516 bus_write_4((_pdata)->xgmac_res, \
1517 MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg, (_val))
1519 #define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \
1521 uint32_t reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \
1523 _reg##_##_field##_INDEX, \
1524 _reg##_##_field##_WIDTH, (_val)); \
1525 XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \
1528 /* Macros for reading or writing DMA channel registers
1529 * Similar to the standard read and write macros except that the
1530 * base register value is obtained from the ring
1532 #define XGMAC_DMA_IOREAD(_channel, _reg) \
1533 bus_space_read_4((_channel)->dma_tag, (_channel)->dma_handle, _reg)
1535 #define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \
1536 GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \
1537 _reg##_##_field##_INDEX, \
1538 _reg##_##_field##_WIDTH)
1540 #define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \
1541 bus_space_write_4((_channel)->dma_tag, (_channel)->dma_handle, \
1544 #define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \
1546 uint32_t reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \
1548 _reg##_##_field##_INDEX, \
1549 _reg##_##_field##_WIDTH, (_val)); \
1550 XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \
1553 /* Macros for building, reading or writing register values or bits
1554 * within the register values of XPCS registers.
1556 #define XPCS_GET_BITS(_var, _prefix, _field) \
1558 _prefix##_##_field##_INDEX, \
1559 _prefix##_##_field##_WIDTH)
1561 #define XPCS_SET_BITS(_var, _prefix, _field, _val) \
1563 _prefix##_##_field##_INDEX, \
1564 _prefix##_##_field##_WIDTH, (_val))
1566 #define XPCS32_IOWRITE(_pdata, _off, _val) \
1567 bus_write_4((_pdata)->xpcs_res, (_off), _val)
1569 #define XPCS32_IOREAD(_pdata, _off) \
1570 bus_read_4((_pdata)->xpcs_res, (_off))
1572 #define XPCS16_IOWRITE(_pdata, _off, _val) \
1573 bus_write_2((_pdata)->xpcs_res, (_off), _val)
1575 #define XPCS16_IOREAD(_pdata, _off) \
1576 bus_read_2((_pdata)->xpcs_res, (_off))
1578 /* Macros for building, reading or writing register values or bits
1579 * within the register values of SerDes integration registers.
1581 #define XSIR_GET_BITS(_var, _prefix, _field) \
1583 _prefix##_##_field##_INDEX, \
1584 _prefix##_##_field##_WIDTH)
1586 #define XSIR_SET_BITS(_var, _prefix, _field, _val) \
1588 _prefix##_##_field##_INDEX, \
1589 _prefix##_##_field##_WIDTH, (_val))
1591 #define XSIR0_IOREAD(_pdata, _reg) \
1592 bus_read_2((_pdata)->sir0_res, _reg)
1594 #define XSIR0_IOREAD_BITS(_pdata, _reg, _field) \
1595 GET_BITS(XSIR0_IOREAD((_pdata), _reg), \
1596 _reg##_##_field##_INDEX, \
1597 _reg##_##_field##_WIDTH)
1599 #define XSIR0_IOWRITE(_pdata, _reg, _val) \
1600 bus_write_2((_pdata)->sir0_res, _reg, (_val))
1602 #define XSIR0_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1604 uint16_t reg_val = XSIR0_IOREAD((_pdata), _reg); \
1606 _reg##_##_field##_INDEX, \
1607 _reg##_##_field##_WIDTH, (_val)); \
1608 XSIR0_IOWRITE((_pdata), _reg, reg_val); \
1611 #define XSIR1_IOREAD(_pdata, _reg) \
1612 bus_read_2((_pdata)->sir1_res, _reg)
1614 #define XSIR1_IOREAD_BITS(_pdata, _reg, _field) \
1615 GET_BITS(XSIR1_IOREAD((_pdata), _reg), \
1616 _reg##_##_field##_INDEX, \
1617 _reg##_##_field##_WIDTH)
1619 #define XSIR1_IOWRITE(_pdata, _reg, _val) \
1620 bus_write_2((_pdata)->sir1_res, _reg, (_val))
1622 #define XSIR1_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1624 uint16_t reg_val = XSIR1_IOREAD((_pdata), _reg); \
1626 _reg##_##_field##_INDEX, \
1627 _reg##_##_field##_WIDTH, (_val)); \
1628 XSIR1_IOWRITE((_pdata), _reg, reg_val); \
1631 /* Macros for building, reading or writing register values or bits
1632 * within the register values of SerDes RxTx registers.
1634 #define XRXTX_IOREAD(_pdata, _reg) \
1635 bus_read_2((_pdata)->rxtx_res, _reg)
1637 #define XRXTX_IOREAD_BITS(_pdata, _reg, _field) \
1638 GET_BITS(XRXTX_IOREAD((_pdata), _reg), \
1639 _reg##_##_field##_INDEX, \
1640 _reg##_##_field##_WIDTH)
1642 #define XRXTX_IOWRITE(_pdata, _reg, _val) \
1643 bus_write_2((_pdata)->rxtx_res, _reg, (_val))
1645 #define XRXTX_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1647 uint16_t reg_val = XRXTX_IOREAD((_pdata), _reg); \
1649 _reg##_##_field##_INDEX, \
1650 _reg##_##_field##_WIDTH, (_val)); \
1651 XRXTX_IOWRITE((_pdata), _reg, reg_val); \
1654 /* Macros for building, reading or writing register values or bits
1655 * within the register values of MAC Control registers.
1657 #define XP_GET_BITS(_var, _prefix, _field) \
1659 _prefix##_##_field##_INDEX, \
1660 _prefix##_##_field##_WIDTH)
1662 #define XP_SET_BITS(_var, _prefix, _field, _val) \
1664 _prefix##_##_field##_INDEX, \
1665 _prefix##_##_field##_WIDTH, (_val))
1667 #define XP_IOREAD(_pdata, _reg) \
1668 bus_read_4((_pdata)->xgmac_res, _reg + XGBE_MAC_PROP_OFFSET)
1670 #define XP_IOREAD_BITS(_pdata, _reg, _field) \
1671 GET_BITS(XP_IOREAD((_pdata), (_reg)), \
1672 _reg##_##_field##_INDEX, \
1673 _reg##_##_field##_WIDTH)
1675 #define XP_IOWRITE(_pdata, _reg, _val) \
1676 bus_write_4((_pdata)->xgmac_res, _reg + XGBE_MAC_PROP_OFFSET, \
1679 #define XP_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1681 uint32_t reg_val = XP_IOREAD((_pdata), (_reg)); \
1683 _reg##_##_field##_INDEX, \
1684 _reg##_##_field##_WIDTH, (_val)); \
1685 XP_IOWRITE((_pdata), (_reg), reg_val); \
1688 /* Macros for building, reading or writing register values or bits
1689 * within the register values of I2C Control registers.
1691 #define XI2C_GET_BITS(_var, _prefix, _field) \
1693 _prefix##_##_field##_INDEX, \
1694 _prefix##_##_field##_WIDTH)
1696 #define XI2C_SET_BITS(_var, _prefix, _field, _val) \
1698 _prefix##_##_field##_INDEX, \
1699 _prefix##_##_field##_WIDTH, (_val))
1701 #define XI2C_IOREAD(_pdata, _reg) \
1702 bus_read_4((_pdata)->xgmac_res, _reg + XGBE_I2C_CTRL_OFFSET)
1704 #define XI2C_IOREAD_BITS(_pdata, _reg, _field) \
1705 GET_BITS(XI2C_IOREAD((_pdata), (_reg)), \
1706 _reg##_##_field##_INDEX, \
1707 _reg##_##_field##_WIDTH)
1709 #define XI2C_IOWRITE(_pdata, _reg, _val) \
1710 bus_write_4((_pdata)->xgmac_res, _reg + XGBE_I2C_CTRL_OFFSET, \
1713 #define XI2C_IOWRITE_BITS(_pdata, _reg, _field, _val) \
1715 uint32_t reg_val = XI2C_IOREAD((_pdata), (_reg)); \
1717 _reg##_##_field##_INDEX, \
1718 _reg##_##_field##_WIDTH, (_val)); \
1719 XI2C_IOWRITE((_pdata), (_reg), reg_val); \
1722 /* Macros for building, reading or writing register values or bits
1723 * using MDIO. Different from above because of the use of standardized
1724 * Linux include values. No shifting is performed with the bit
1725 * operations, everything works on mask values.
1727 #define XMDIO_READ(_pdata, _mmd, _reg) \
1728 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \
1729 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff)))
1731 #define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \
1732 (XMDIO_READ((_pdata), _mmd, _reg) & _mask)
1734 #define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \
1735 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \
1736 MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val)))
1738 #define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \
1740 uint32_t mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \
1741 mmd_val &= ~_mask; \
1742 mmd_val |= (_val); \
1743 XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \