2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <sys/cdefs.h>
118 __FBSDID("$FreeBSD$");
120 #include <sys/param.h>
121 #include <sys/kernel.h>
124 #include "xgbe-common.h"
126 static int xgbe_one_poll(struct xgbe_channel *channel, int budget);
127 static int xgbe_all_poll(struct xgbe_prv_data *pdata, int budget);
129 static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
131 struct xgbe_channel *channel_mem, *channel;
132 struct xgbe_ring *tx_ring, *rx_ring;
133 unsigned int count, i;
136 count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
138 channel_mem = malloc(count * sizeof(struct xgbe_channel), M_AXGBE,
140 tx_ring = malloc(pdata->tx_ring_count * sizeof(struct xgbe_ring),
141 M_AXGBE, M_WAITOK | M_ZERO);
142 rx_ring = malloc(pdata->rx_ring_count * sizeof(struct xgbe_ring),
143 M_AXGBE, M_WAITOK | M_ZERO);
145 for (i = 0, channel = channel_mem; i < count; i++, channel++) {
146 snprintf(channel->name, sizeof(channel->name), "channel-%d", i);
147 channel->pdata = pdata;
148 channel->queue_index = i;
149 channel->dma_tag = rman_get_bustag(pdata->xgmac_res);
150 bus_space_subregion(channel->dma_tag,
151 rman_get_bushandle(pdata->xgmac_res),
152 DMA_CH_BASE + (DMA_CH_INC * i), DMA_CH_INC,
153 &channel->dma_handle);
155 if (pdata->per_channel_irq) {
156 if (pdata->chan_irq_res[i] == NULL)
159 channel->dma_irq_res = pdata->chan_irq_res[i];
162 if (i < pdata->tx_ring_count) {
163 spin_lock_init(&tx_ring->lock);
164 channel->tx_ring = tx_ring++;
167 if (i < pdata->rx_ring_count) {
168 spin_lock_init(&rx_ring->lock);
169 channel->rx_ring = rx_ring++;
173 pdata->channel = channel_mem;
174 pdata->channel_count = count;
179 free(rx_ring, M_AXGBE);
180 free(tx_ring, M_AXGBE);
181 free(channel_mem, M_AXGBE);
186 static void xgbe_free_channels(struct xgbe_prv_data *pdata)
191 free(pdata->channel->rx_ring, M_AXGBE);
192 free(pdata->channel->tx_ring, M_AXGBE);
193 free(pdata->channel, M_AXGBE);
195 pdata->channel = NULL;
196 pdata->channel_count = 0;
199 static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
201 return (ring->rdesc_count - (ring->cur - ring->dirty));
204 static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
206 return (ring->cur - ring->dirty);
209 static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
210 struct xgbe_ring *ring, unsigned int count)
212 struct xgbe_prv_data *pdata = channel->pdata;
214 if (count > xgbe_tx_avail_desc(ring)) {
215 /* If we haven't notified the hardware because of xmit_more
216 * support, tell it now
218 if (ring->tx.xmit_more)
219 pdata->hw_if.tx_start_xmit(channel, ring);
227 static int xgbe_calc_rx_buf_size(struct ifnet *netdev, unsigned int mtu)
229 unsigned int rx_buf_size;
231 if (mtu > XGMAC_JUMBO_PACKET_MTU) {
235 rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
236 rx_buf_size = MIN(XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
238 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
239 ~(XGBE_RX_BUF_ALIGN - 1);
244 static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
246 struct xgbe_hw_if *hw_if = &pdata->hw_if;
247 struct xgbe_channel *channel;
248 enum xgbe_int int_id;
251 channel = pdata->channel;
252 for (i = 0; i < pdata->channel_count; i++, channel++) {
253 if (channel->tx_ring && channel->rx_ring)
254 int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
255 else if (channel->tx_ring)
256 int_id = XGMAC_INT_DMA_CH_SR_TI;
257 else if (channel->rx_ring)
258 int_id = XGMAC_INT_DMA_CH_SR_RI;
262 hw_if->enable_int(channel, int_id);
266 static void xgbe_isr(void *data)
268 struct xgbe_prv_data *pdata = data;
269 struct xgbe_hw_if *hw_if = &pdata->hw_if;
270 struct xgbe_channel *channel;
271 unsigned int dma_isr, dma_ch_isr;
272 unsigned int mac_isr;
275 /* The DMA interrupt status register also reports MAC and MTL
276 * interrupts. So for polling mode, we just need to check for
277 * this register to be non-zero
279 dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
283 for (i = 0; i < pdata->channel_count; i++) {
284 if (!(dma_isr & (1 << i)))
287 channel = pdata->channel + i;
289 dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
291 /* The TI or RI interrupt bits may still be set even if using
292 * per channel DMA interrupts. Check to be sure those are not
293 * enabled before using the private data napi structure.
295 if (!pdata->per_channel_irq &&
296 (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
297 XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI))) {
298 xgbe_all_poll(pdata, 16);
301 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RBU))
302 pdata->ext_stats.rx_buffer_unavailable++;
304 /* Restart the device on a Fatal Bus Error */
305 if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
306 taskqueue_enqueue(taskqueue_thread,
307 &pdata->restart_work);
309 /* Clear all interrupt signals */
310 XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
313 if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
314 mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
316 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
317 hw_if->tx_mmc_int(pdata);
319 if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
320 hw_if->rx_mmc_int(pdata);
324 static void xgbe_dma_isr(void *data)
326 struct xgbe_channel *channel = data;
328 xgbe_one_poll(channel, 16);
331 static void xgbe_service(void *ctx, int pending)
333 struct xgbe_prv_data *pdata = ctx;
335 pdata->phy_if.phy_status(pdata);
338 static void xgbe_service_timer(void *data)
340 struct xgbe_prv_data *pdata = data;
342 DBGPR("--> xgbe_service_timer\n");
343 taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work);
345 callout_reset(&pdata->service_timer, hz, xgbe_service_timer, pdata);
346 DBGPR("<-- xgbe_service_timer\n");
349 static void xgbe_init_timers(struct xgbe_prv_data *pdata)
352 callout_init(&pdata->service_timer, 1);
355 static void xgbe_start_timers(struct xgbe_prv_data *pdata)
357 callout_reset(&pdata->service_timer, hz, xgbe_service_timer, pdata);
360 static void xgbe_stop_timers(struct xgbe_prv_data *pdata)
363 callout_drain(&pdata->service_timer);
366 void xgbe_get_all_hw_features(struct xgbe_prv_data *pdata)
368 unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
369 struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
371 DBGPR("-->xgbe_get_all_hw_features\n");
373 mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
374 mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
375 mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
377 memset(hw_feat, 0, sizeof(*hw_feat));
379 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
381 /* Hardware feature register 0 */
382 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
383 hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
384 hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
385 hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
386 hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
387 hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
388 hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
389 hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
390 hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
391 hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
392 hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
393 hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
395 hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
396 hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
398 /* Hardware feature register 1 */
399 hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
401 hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
403 hw_feat->adv_ts_hi = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADVTHWORD);
404 hw_feat->dma_width = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, ADDR64);
405 hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
406 hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
407 hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
408 hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
409 hw_feat->rss = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, RSSEN);
410 hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
411 hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
413 hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
416 /* Hardware feature register 2 */
417 hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
418 hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
419 hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
420 hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
421 hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
422 hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
424 /* Translate the Hash Table size into actual number */
425 switch (hw_feat->hash_table_size) {
429 hw_feat->hash_table_size = 64;
432 hw_feat->hash_table_size = 128;
435 hw_feat->hash_table_size = 256;
439 /* Translate the address width setting into actual number */
440 switch (hw_feat->dma_width) {
442 hw_feat->dma_width = 32;
445 hw_feat->dma_width = 40;
448 hw_feat->dma_width = 48;
451 hw_feat->dma_width = 32;
454 /* The Queue, Channel and TC counts are zero based so increment them
455 * to get the actual number
459 hw_feat->rx_ch_cnt++;
460 hw_feat->tx_ch_cnt++;
463 DBGPR("<--xgbe_get_all_hw_features\n");
466 static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
468 struct xgbe_channel *channel;
472 ret = bus_setup_intr(pdata->dev, pdata->dev_irq_res,
473 INTR_MPSAFE | INTR_TYPE_NET, NULL, xgbe_isr, pdata,
474 &pdata->dev_irq_tag);
479 if (!pdata->per_channel_irq)
482 channel = pdata->channel;
483 for (i = 0; i < pdata->channel_count; i++, channel++) {
484 ret = bus_setup_intr(pdata->dev, channel->dma_irq_res,
485 INTR_MPSAFE | INTR_TYPE_NET, NULL, xgbe_dma_isr, channel,
486 &channel->dma_irq_tag);
495 /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
496 for (i--, channel--; i < pdata->channel_count; i--, channel--)
497 bus_teardown_intr(pdata->dev, channel->dma_irq_res,
498 channel->dma_irq_tag);
500 bus_teardown_intr(pdata->dev, pdata->dev_irq_res, pdata->dev_irq_tag);
505 static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
507 struct xgbe_channel *channel;
510 bus_teardown_intr(pdata->dev, pdata->dev_irq_res, pdata->dev_irq_tag);
512 if (!pdata->per_channel_irq)
515 channel = pdata->channel;
516 for (i = 0; i < pdata->channel_count; i++, channel++)
517 bus_teardown_intr(pdata->dev, channel->dma_irq_res,
518 channel->dma_irq_tag);
521 void xgbe_init_tx_coalesce(struct xgbe_prv_data *pdata)
523 struct xgbe_hw_if *hw_if = &pdata->hw_if;
525 DBGPR("-->xgbe_init_tx_coalesce\n");
527 pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
528 pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
530 hw_if->config_tx_coalesce(pdata);
532 DBGPR("<--xgbe_init_tx_coalesce\n");
535 void xgbe_init_rx_coalesce(struct xgbe_prv_data *pdata)
537 struct xgbe_hw_if *hw_if = &pdata->hw_if;
539 DBGPR("-->xgbe_init_rx_coalesce\n");
541 pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
542 pdata->rx_usecs = XGMAC_INIT_DMA_RX_USECS;
543 pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
545 hw_if->config_rx_coalesce(pdata);
547 DBGPR("<--xgbe_init_rx_coalesce\n");
550 static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
552 struct xgbe_desc_if *desc_if = &pdata->desc_if;
553 struct xgbe_channel *channel;
554 struct xgbe_ring *ring;
555 struct xgbe_ring_data *rdata;
558 DBGPR("-->xgbe_free_tx_data\n");
560 channel = pdata->channel;
561 for (i = 0; i < pdata->channel_count; i++, channel++) {
562 ring = channel->tx_ring;
566 for (j = 0; j < ring->rdesc_count; j++) {
567 rdata = XGBE_GET_DESC_DATA(ring, j);
568 desc_if->unmap_rdata(pdata, rdata);
572 DBGPR("<--xgbe_free_tx_data\n");
575 static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
577 struct xgbe_desc_if *desc_if = &pdata->desc_if;
578 struct xgbe_channel *channel;
579 struct xgbe_ring *ring;
580 struct xgbe_ring_data *rdata;
583 DBGPR("-->xgbe_free_rx_data\n");
585 channel = pdata->channel;
586 for (i = 0; i < pdata->channel_count; i++, channel++) {
587 ring = channel->rx_ring;
591 for (j = 0; j < ring->rdesc_count; j++) {
592 rdata = XGBE_GET_DESC_DATA(ring, j);
593 desc_if->unmap_rdata(pdata, rdata);
597 DBGPR("<--xgbe_free_rx_data\n");
600 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
602 pdata->phy_link = -1;
603 pdata->phy_speed = SPEED_UNKNOWN;
605 return pdata->phy_if.phy_reset(pdata);
608 static int xgbe_start(struct xgbe_prv_data *pdata)
610 struct xgbe_hw_if *hw_if = &pdata->hw_if;
611 struct xgbe_phy_if *phy_if = &pdata->phy_if;
614 DBGPR("-->xgbe_start\n");
618 ret = phy_if->phy_start(pdata);
622 ret = xgbe_request_irqs(pdata);
626 hw_if->enable_tx(pdata);
627 hw_if->enable_rx(pdata);
629 xgbe_enable_rx_tx_ints(pdata);
631 xgbe_start_timers(pdata);
632 taskqueue_enqueue(pdata->dev_workqueue, &pdata->service_work);
634 DBGPR("<--xgbe_start\n");
639 phy_if->phy_stop(pdata);
647 static void xgbe_stop(struct xgbe_prv_data *pdata)
649 struct xgbe_hw_if *hw_if = &pdata->hw_if;
650 struct xgbe_phy_if *phy_if = &pdata->phy_if;
652 DBGPR("-->xgbe_stop\n");
654 xgbe_stop_timers(pdata);
655 taskqueue_drain_all(pdata->dev_workqueue);
657 hw_if->disable_tx(pdata);
658 hw_if->disable_rx(pdata);
660 xgbe_free_irqs(pdata);
662 phy_if->phy_stop(pdata);
666 DBGPR("<--xgbe_stop\n");
669 static void xgbe_restart_dev(struct xgbe_prv_data *pdata)
671 DBGPR("-->xgbe_restart_dev\n");
673 /* If not running, "restart" will happen on open */
674 if ((pdata->netdev->if_drv_flags & IFF_DRV_RUNNING) == 0)
679 xgbe_free_tx_data(pdata);
680 xgbe_free_rx_data(pdata);
684 DBGPR("<--xgbe_restart_dev\n");
687 static void xgbe_restart(void *ctx, int pending)
689 struct xgbe_prv_data *pdata = ctx;
691 xgbe_restart_dev(pdata);
694 static void xgbe_packet_info(struct xgbe_prv_data *pdata,
695 struct xgbe_ring *ring, struct mbuf *m0,
696 struct xgbe_packet_data *packet)
703 packet->rdesc_count = 0;
705 packet->tx_packets = 1;
706 packet->tx_bytes = m_length(m0, NULL);
708 for (m = m0; m != NULL; m = m->m_next) {
709 for (len = m->m_len; len != 0;) {
710 packet->rdesc_count++;
711 len -= MIN(len, XGBE_TX_MAX_BUF_SIZE);
716 int xgbe_open(struct ifnet *netdev)
718 struct xgbe_prv_data *pdata = netdev->if_softc;
719 struct xgbe_desc_if *desc_if = &pdata->desc_if;
722 DBGPR("-->xgbe_open\n");
724 /* Initialize the phy */
725 ret = xgbe_phy_init(pdata);
729 /* Calculate the Rx buffer size before allocating rings */
730 ret = xgbe_calc_rx_buf_size(netdev, if_getmtu(netdev));
734 pdata->rx_buf_size = ret;
736 /* Allocate the channel and ring structures */
737 ret = xgbe_alloc_channels(pdata);
739 printf("xgbe_alloc_channels failed\n");
743 /* Allocate the ring descriptors and buffers */
744 ret = desc_if->alloc_ring_resources(pdata);
746 printf("desc_if->alloc_ring_resources failed\n");
750 TASK_INIT(&pdata->service_work, 0, xgbe_service, pdata);
751 TASK_INIT(&pdata->restart_work, 0, xgbe_restart, pdata);
752 xgbe_init_timers(pdata);
754 ret = xgbe_start(pdata);
758 clear_bit(XGBE_DOWN, &pdata->dev_state);
760 DBGPR("<--xgbe_open\n");
765 desc_if->free_ring_resources(pdata);
768 xgbe_free_channels(pdata);
775 int xgbe_close(struct ifnet *netdev)
777 struct xgbe_prv_data *pdata = netdev->if_softc;
778 struct xgbe_desc_if *desc_if = &pdata->desc_if;
780 DBGPR("-->xgbe_close\n");
782 /* Stop the device */
785 /* Free the ring descriptors and buffers */
786 desc_if->free_ring_resources(pdata);
788 /* Free the channel and ring structures */
789 xgbe_free_channels(pdata);
791 set_bit(XGBE_DOWN, &pdata->dev_state);
793 DBGPR("<--xgbe_close\n");
798 int xgbe_xmit(struct ifnet *ifp, struct mbuf *m)
800 struct xgbe_prv_data *pdata = ifp->if_softc;
801 struct xgbe_hw_if *hw_if = &pdata->hw_if;
802 struct xgbe_desc_if *desc_if = &pdata->desc_if;
803 struct xgbe_channel *channel;
804 struct xgbe_ring *ring;
805 struct xgbe_packet_data *packet;
809 MPASS(m->m_nextpkt == NULL);
811 if (__predict_false(test_bit(XGBE_DOWN, &pdata->dev_state) ||
817 channel = pdata->channel;
818 ring = channel->tx_ring;
819 packet = &ring->packet_data;
821 /* Calculate preliminary packet info */
822 memset(packet, 0, sizeof(*packet));
823 xgbe_packet_info(pdata, ring, m, packet);
825 /* Check that there are enough descriptors available */
826 ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
828 goto tx_netdev_return;
830 if (!desc_if->map_tx_skb(channel, m)) {
831 goto tx_netdev_return;
834 /* Configure required descriptor fields for transmission */
835 hw_if->dev_xmit(channel);
845 int xgbe_change_mtu(struct ifnet *netdev, int mtu)
847 struct xgbe_prv_data *pdata = netdev->if_softc;
850 DBGPR("-->xgbe_change_mtu\n");
852 ret = xgbe_calc_rx_buf_size(netdev, mtu);
856 pdata->rx_buf_size = ret;
857 netdev->if_mtu = mtu;
859 xgbe_restart_dev(pdata);
861 DBGPR("<--xgbe_change_mtu\n");
866 static void xgbe_rx_refresh(struct xgbe_channel *channel)
868 struct xgbe_prv_data *pdata = channel->pdata;
869 struct xgbe_hw_if *hw_if = &pdata->hw_if;
870 struct xgbe_desc_if *desc_if = &pdata->desc_if;
871 struct xgbe_ring *ring = channel->rx_ring;
872 struct xgbe_ring_data *rdata;
874 while (ring->dirty != ring->cur) {
875 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
877 /* Reset rdata values */
878 desc_if->unmap_rdata(pdata, rdata);
880 if (desc_if->map_rx_buffer(pdata, ring, rdata))
883 hw_if->rx_desc_reset(pdata, rdata, ring->dirty);
888 /* Make sure everything is written before the register write */
891 /* Update the Rx Tail Pointer Register with address of
892 * the last cleaned entry */
893 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
894 XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
895 lower_32_bits(rdata->rdata_paddr));
898 static int xgbe_tx_poll(struct xgbe_channel *channel)
900 struct xgbe_prv_data *pdata = channel->pdata;
901 struct xgbe_hw_if *hw_if = &pdata->hw_if;
902 struct xgbe_desc_if *desc_if = &pdata->desc_if;
903 struct xgbe_ring *ring = channel->tx_ring;
904 struct xgbe_ring_data *rdata;
905 struct xgbe_ring_desc *rdesc;
909 DBGPR("-->xgbe_tx_poll\n");
911 /* Nothing to do if there isn't a Tx ring for this channel */
917 /* Be sure we get ring->cur before accessing descriptor data */
920 while ((processed < XGBE_TX_DESC_MAX_PROC) &&
921 (ring->dirty != cur)) {
922 rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
923 rdesc = rdata->rdesc;
925 if (!hw_if->tx_complete(rdesc))
928 /* Make sure descriptor fields are read after reading the OWN
932 /* Free the SKB and reset the descriptor for re-use */
933 desc_if->unmap_rdata(pdata, rdata);
934 hw_if->tx_desc_reset(rdata);
943 DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
948 static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
950 struct xgbe_prv_data *pdata = channel->pdata;
951 struct xgbe_hw_if *hw_if = &pdata->hw_if;
952 struct xgbe_ring *ring = channel->rx_ring;
953 struct xgbe_ring_data *rdata;
954 struct xgbe_packet_data *packet;
955 struct ifnet *ifp = pdata->netdev;
957 unsigned int incomplete, context_next;
958 unsigned int received = 0;
959 int packet_count = 0;
961 DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
963 /* Nothing to do if there isn't a Rx ring for this channel */
970 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
971 packet = &ring->packet_data;
972 while (packet_count < budget) {
973 DBGPR(" cur = %d\n", ring->cur);
976 rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
978 if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
979 xgbe_rx_refresh(channel);
981 if (hw_if->dev_read(channel))
989 incomplete = XGMAC_GET_BITS(packet->attributes,
990 RX_PACKET_ATTRIBUTES,
992 context_next = XGMAC_GET_BITS(packet->attributes,
993 RX_PACKET_ATTRIBUTES,
996 /* Earlier error, just drain the remaining data */
997 if (incomplete || context_next) {
1001 if (packet->errors) {
1002 rdata->mbuf_free = 1;
1007 m->m_pkthdr.len = rdata->rx.hdr_len + rdata->rx.len;
1008 if (rdata->rx.hdr_len != 0) {
1009 m->m_len = rdata->rx.hdr_len;
1010 m->m_next->m_len = rdata->rx.len;
1012 m->m_len = rdata->rx.len;
1016 if_setrcvif(m, ifp);
1017 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1019 ifp->if_input(ifp, m);
1025 DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
1027 return packet_count;
1030 static int xgbe_one_poll(struct xgbe_channel *channel, int budget)
1034 DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
1036 /* Cleanup Tx ring first */
1037 xgbe_tx_poll(channel);
1039 /* Process Rx ring next */
1040 processed = xgbe_rx_poll(channel, budget);
1042 DBGPR("<--xgbe_one_poll: received = %d\n", processed);
1047 static int xgbe_all_poll(struct xgbe_prv_data *pdata, int budget)
1049 struct xgbe_channel *channel;
1051 int processed, last_processed;
1054 DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
1057 ring_budget = budget / pdata->rx_ring_count;
1059 last_processed = processed;
1061 channel = pdata->channel;
1062 for (i = 0; i < pdata->channel_count; i++, channel++) {
1063 /* Cleanup Tx ring first */
1064 xgbe_tx_poll(channel);
1066 /* Process Rx ring next */
1067 if (ring_budget > (budget - processed))
1068 ring_budget = budget - processed;
1069 processed += xgbe_rx_poll(channel, ring_budget);
1071 } while ((processed < budget) && (processed != last_processed));
1073 DBGPR("<--xgbe_all_poll: received = %d\n", processed);