2 * AMD 10Gb Ethernet driver
4 * Copyright (c) 2020 Advanced Micro Devices, Inc.
6 * This file is available to you under your choice of the following two
11 * This file is free software; you may copy, redistribute and/or modify
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24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
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38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
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51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
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77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81 * This file incorporates work covered by the following copyright and
83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
85 * Inc. unless otherwise expressly agreed to in writing between Synopsys
88 * The Software IS NOT an item of Licensed Software or Licensed Product
89 * under any End User Software License Agreement or Agreement for Licensed
90 * Product with Synopsys or any supplement thereto. Permission is hereby
91 * granted, free of charge, to any person obtaining a copy of this software
92 * annotated with this license and the Software, to deal in the Software
93 * without restriction, including without limitation the rights to use,
94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
95 * of the Software, and to permit persons to whom the Software is furnished
96 * to do so, subject to the following conditions:
98 * The above copyright notice and this permission notice shall be included
99 * in all copies or substantial portions of the Software.
101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
111 * THE POSSIBILITY OF SUCH DAMAGE.
114 #include <sys/cdefs.h>
115 __FBSDID("$FreeBSD$");
118 #include "xgbe-common.h"
120 #define XGBE_ABORT_COUNT 500
121 #define XGBE_DISABLE_COUNT 1000
123 #define XGBE_STD_SPEED 1
125 #define XGBE_INTR_RX_FULL BIT(IC_RAW_INTR_STAT_RX_FULL_INDEX)
126 #define XGBE_INTR_TX_EMPTY BIT(IC_RAW_INTR_STAT_TX_EMPTY_INDEX)
127 #define XGBE_INTR_TX_ABRT BIT(IC_RAW_INTR_STAT_TX_ABRT_INDEX)
128 #define XGBE_INTR_STOP_DET BIT(IC_RAW_INTR_STAT_STOP_DET_INDEX)
129 #define XGBE_DEFAULT_INT_MASK (XGBE_INTR_RX_FULL | \
130 XGBE_INTR_TX_EMPTY | \
131 XGBE_INTR_TX_ABRT | \
134 #define XGBE_I2C_READ BIT(8)
135 #define XGBE_I2C_STOP BIT(9)
138 xgbe_i2c_abort(struct xgbe_prv_data *pdata)
140 unsigned int wait = XGBE_ABORT_COUNT;
142 /* Must be enabled to recognize the abort request */
143 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, 1);
145 /* Issue the abort */
146 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, ABORT, 1);
149 if (!XI2C_IOREAD_BITS(pdata, IC_ENABLE, ABORT))
159 xgbe_i2c_set_enable(struct xgbe_prv_data *pdata, bool enable)
161 unsigned int wait = XGBE_DISABLE_COUNT;
162 unsigned int mode = enable ? 1 : 0;
165 XI2C_IOWRITE_BITS(pdata, IC_ENABLE, EN, mode);
166 if (XI2C_IOREAD_BITS(pdata, IC_ENABLE_STATUS, EN) == mode)
176 xgbe_i2c_disable(struct xgbe_prv_data *pdata)
180 ret = xgbe_i2c_set_enable(pdata, false);
182 /* Disable failed, try an abort */
183 ret = xgbe_i2c_abort(pdata);
185 axgbe_error("%s: i2c_abort %d\n", __func__, ret);
189 /* Abort succeeded, try to disable again */
190 ret = xgbe_i2c_set_enable(pdata, false);
193 axgbe_printf(3, "%s: final i2c_disable %d\n", __func__, ret);
198 xgbe_i2c_enable(struct xgbe_prv_data *pdata)
200 return (xgbe_i2c_set_enable(pdata, true));
204 xgbe_i2c_clear_all_interrupts(struct xgbe_prv_data *pdata)
206 XI2C_IOREAD(pdata, IC_CLR_INTR);
210 xgbe_i2c_disable_interrupts(struct xgbe_prv_data *pdata)
212 XI2C_IOWRITE(pdata, IC_INTR_MASK, 0);
216 xgbe_i2c_enable_interrupts(struct xgbe_prv_data *pdata)
218 XI2C_IOWRITE(pdata, IC_INTR_MASK, XGBE_DEFAULT_INT_MASK);
222 xgbe_i2c_write(struct xgbe_prv_data *pdata)
224 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
225 unsigned int tx_slots, cmd;
227 /* Configured to never receive Rx overflows, so fill up Tx fifo */
228 tx_slots = pdata->i2c.tx_fifo_size - XI2C_IOREAD(pdata, IC_TXFLR);
229 axgbe_printf(3, "%s: tx_slots %d tx_len %d\n", __func__, tx_slots,
232 while (tx_slots && state->tx_len) {
233 if (state->op->cmd == XGBE_I2C_CMD_READ)
236 cmd = *state->tx_buf++;
238 axgbe_printf(3, "%s: cmd %d tx_len %d\n", __func__, cmd,
241 if (state->tx_len == 1)
242 XI2C_SET_BITS(cmd, IC_DATA_CMD, STOP, 1);
244 XI2C_IOWRITE(pdata, IC_DATA_CMD, cmd);
250 /* No more Tx operations, so ignore TX_EMPTY and return */
252 XI2C_IOWRITE_BITS(pdata, IC_INTR_MASK, TX_EMPTY, 0);
256 xgbe_i2c_read(struct xgbe_prv_data *pdata)
258 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
259 unsigned int rx_slots;
261 /* Anything to be read? */
262 axgbe_printf(3, "%s: op cmd %d\n", __func__, state->op->cmd);
263 if (state->op->cmd != XGBE_I2C_CMD_READ)
266 rx_slots = XI2C_IOREAD(pdata, IC_RXFLR);
267 axgbe_printf(3, "%s: rx_slots %d rx_len %d\n", __func__, rx_slots,
270 while (rx_slots && state->rx_len) {
271 *state->rx_buf++ = XI2C_IOREAD(pdata, IC_DATA_CMD);
278 xgbe_i2c_clear_isr_interrupts(struct xgbe_prv_data *pdata, unsigned int isr)
280 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
282 if (isr & XGBE_INTR_TX_ABRT) {
283 state->tx_abort_source = XI2C_IOREAD(pdata, IC_TX_ABRT_SOURCE);
284 XI2C_IOREAD(pdata, IC_CLR_TX_ABRT);
287 if (isr & XGBE_INTR_STOP_DET)
288 XI2C_IOREAD(pdata, IC_CLR_STOP_DET);
292 xgbe_i2c_isr(void *data)
294 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
295 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
298 isr = XI2C_IOREAD(pdata, IC_RAW_INTR_STAT);
299 axgbe_printf(3, "%s: isr 0x%x\n", __func__, isr);
303 axgbe_printf(3, "%s: I2C interrupt status=%#010x\n", __func__, isr);
305 xgbe_i2c_clear_isr_interrupts(pdata, isr);
307 if (isr & XGBE_INTR_TX_ABRT) {
308 axgbe_printf(1, "%s: I2C TX_ABRT received (%#010x) for target "
309 "%#04x\n", __func__, state->tx_abort_source,
312 xgbe_i2c_disable_interrupts(pdata);
318 /* Check for data in the Rx fifo */
319 xgbe_i2c_read(pdata);
321 /* Fill up the Tx fifo next */
322 xgbe_i2c_write(pdata);
325 /* Complete on an error or STOP condition */
326 axgbe_printf(3, "%s: ret %d stop %d\n", __func__, state->ret,
327 XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET));
329 if (state->ret || XI2C_GET_BITS(isr, IC_RAW_INTR_STAT, STOP_DET))
330 pdata->i2c_complete = true;
335 /* Reissue interrupt if status is not clear */
336 if (pdata->vdata->irq_reissue_support)
337 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 2);
341 xgbe_i2c_set_mode(struct xgbe_prv_data *pdata)
345 reg = XI2C_IOREAD(pdata, IC_CON);
346 XI2C_SET_BITS(reg, IC_CON, MASTER_MODE, 1);
347 XI2C_SET_BITS(reg, IC_CON, SLAVE_DISABLE, 1);
348 XI2C_SET_BITS(reg, IC_CON, RESTART_EN, 1);
349 XI2C_SET_BITS(reg, IC_CON, SPEED, XGBE_STD_SPEED);
350 XI2C_SET_BITS(reg, IC_CON, RX_FIFO_FULL_HOLD, 1);
351 XI2C_IOWRITE(pdata, IC_CON, reg);
355 xgbe_i2c_get_features(struct xgbe_prv_data *pdata)
357 struct xgbe_i2c *i2c = &pdata->i2c;
360 reg = XI2C_IOREAD(pdata, IC_COMP_PARAM_1);
361 i2c->max_speed_mode = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
363 i2c->rx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
365 i2c->tx_fifo_size = XI2C_GET_BITS(reg, IC_COMP_PARAM_1,
368 axgbe_printf(3, "%s: I2C features: %s=%u, %s=%u, %s=%u\n", __func__,
369 "MAX_SPEED_MODE", i2c->max_speed_mode,
370 "RX_BUFFER_DEPTH", i2c->rx_fifo_size,
371 "TX_BUFFER_DEPTH", i2c->tx_fifo_size);
375 xgbe_i2c_set_target(struct xgbe_prv_data *pdata, unsigned int addr)
377 XI2C_IOWRITE(pdata, IC_TAR, addr);
381 xgbe_i2c_combined_isr(struct xgbe_prv_data *pdata)
387 xgbe_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *op)
389 struct xgbe_i2c_op_state *state = &pdata->i2c.op_state;
390 unsigned long timeout;
393 mtx_lock(&pdata->i2c_mutex);
395 axgbe_printf(3, "i2c xfer started ---->>>\n");
397 ret = xgbe_i2c_disable(pdata);
399 axgbe_error("failed to disable i2c master\n");
403 xgbe_i2c_set_target(pdata, op->target);
405 memset(state, 0, sizeof(*state));
407 state->tx_len = op->len;
408 state->tx_buf = op->buf;
409 state->rx_len = op->len;
410 state->rx_buf = op->buf;
412 xgbe_i2c_clear_all_interrupts(pdata);
413 ret = xgbe_i2c_enable(pdata);
415 axgbe_error("failed to enable i2c master\n");
419 /* Enabling the interrupts will cause the TX FIFO empty interrupt to
420 * fire and begin to process the command via the ISR.
422 xgbe_i2c_enable_interrupts(pdata);
424 timeout = ticks + (20 * hz);
425 while (ticks < timeout) {
427 if (!pdata->i2c_complete) {
432 axgbe_printf(1, "%s: I2C OP complete\n", __func__);
436 if ((ticks >= timeout) && !pdata->i2c_complete) {
437 axgbe_error("%s: operation timed out\n", __func__);
443 axgbe_printf(3, "%s: i2c xfer ret %d abrt_source 0x%x \n", __func__,
444 ret, state->tx_abort_source);
447 axgbe_error("%s: i2c xfer ret %d abrt_source 0x%x \n", __func__,
448 ret, state->tx_abort_source);
449 if (state->tx_abort_source & IC_TX_ABRT_7B_ADDR_NOACK)
451 else if (state->tx_abort_source & IC_TX_ABRT_ARB_LOST)
455 axgbe_printf(3, "i2c xfer finished ---->>>\n");
458 pdata->i2c_complete = false;
459 xgbe_i2c_disable_interrupts(pdata);
460 xgbe_i2c_disable(pdata);
463 mtx_unlock(&pdata->i2c_mutex);
468 xgbe_i2c_stop(struct xgbe_prv_data *pdata)
470 if (!pdata->i2c.started)
473 axgbe_printf(3, "stopping I2C\n");
475 pdata->i2c.started = 0;
477 xgbe_i2c_disable_interrupts(pdata);
478 xgbe_i2c_disable(pdata);
479 xgbe_i2c_clear_all_interrupts(pdata);
483 xgbe_i2c_start(struct xgbe_prv_data *pdata)
485 if (pdata->i2c.started)
488 pdata->i2c.started = 1;
494 xgbe_i2c_init(struct xgbe_prv_data *pdata)
498 /* initialize lock for i2c */
499 mtx_init(&pdata->i2c_mutex, "xgbe i2c mutex lock", NULL, MTX_DEF);
500 pdata->i2c_complete = false;
502 xgbe_i2c_disable_interrupts(pdata);
504 ret = xgbe_i2c_disable(pdata);
506 axgbe_error("failed to disable i2c master\n");
510 xgbe_i2c_get_features(pdata);
512 xgbe_i2c_set_mode(pdata);
514 xgbe_i2c_clear_all_interrupts(pdata);
516 xgbe_dump_i2c_registers(pdata);
522 xgbe_init_function_ptrs_i2c(struct xgbe_i2c_if *i2c_if)
524 i2c_if->i2c_init = xgbe_i2c_init;
526 i2c_if->i2c_start = xgbe_i2c_start;
527 i2c_if->i2c_stop = xgbe_i2c_stop;
529 i2c_if->i2c_xfer = xgbe_i2c_xfer;
531 i2c_if->i2c_isr = xgbe_i2c_combined_isr;