2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
117 #include <sys/cdefs.h>
118 __FBSDID("$FreeBSD$");
120 #include <sys/param.h>
121 #include <sys/kernel.h>
124 #include "xgbe-common.h"
126 static void xgbe_an_state_machine(struct xgbe_prv_data *pdata);
128 static void xgbe_an_enable_kr_training(struct xgbe_prv_data *pdata)
132 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
134 reg |= XGBE_KR_TRAINING_ENABLE;
135 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
138 static void xgbe_an_disable_kr_training(struct xgbe_prv_data *pdata)
142 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
144 reg &= ~XGBE_KR_TRAINING_ENABLE;
145 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
148 static void xgbe_pcs_power_cycle(struct xgbe_prv_data *pdata)
152 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
154 reg |= MDIO_CTRL1_LPOWER;
155 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
159 reg &= ~MDIO_CTRL1_LPOWER;
160 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
163 static void xgbe_serdes_start_ratechange(struct xgbe_prv_data *pdata)
165 /* Assert Rx and Tx ratechange */
166 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 1);
169 static void xgbe_serdes_complete_ratechange(struct xgbe_prv_data *pdata)
174 /* Release Rx and Tx ratechange */
175 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 0);
177 /* Wait for Rx and Tx ready */
178 wait = XGBE_RATECHANGE_COUNT;
182 status = XSIR0_IOREAD(pdata, SIR0_STATUS);
183 if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) &&
184 XSIR_GET_BITS(status, SIR0_STATUS, TX_READY))
189 /* Perform Rx reset for the DFE changes */
190 XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 0);
191 XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 1);
194 static void xgbe_xgmii_mode(struct xgbe_prv_data *pdata)
198 /* Enable KR training */
199 xgbe_an_enable_kr_training(pdata);
201 /* Set MAC to 10G speed */
202 pdata->hw_if.set_xgmii_speed(pdata);
204 /* Set PCS to KR/10G speed */
205 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
206 reg &= ~MDIO_PCS_CTRL2_TYPE;
207 reg |= MDIO_PCS_CTRL2_10GBR;
208 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
210 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
211 reg &= ~MDIO_CTRL1_SPEEDSEL;
212 reg |= MDIO_CTRL1_SPEED10G;
213 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
215 xgbe_pcs_power_cycle(pdata);
217 /* Set SerDes to 10G speed */
218 xgbe_serdes_start_ratechange(pdata);
220 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_10000_RATE);
221 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_10000_WORD);
222 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_10000_PLL);
224 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
225 pdata->serdes_cdr_rate[XGBE_SPEED_10000]);
226 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
227 pdata->serdes_tx_amp[XGBE_SPEED_10000]);
228 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
229 pdata->serdes_blwc[XGBE_SPEED_10000]);
230 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
231 pdata->serdes_pq_skew[XGBE_SPEED_10000]);
232 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
233 pdata->serdes_dfe_tap_cfg[XGBE_SPEED_10000]);
234 XRXTX_IOWRITE(pdata, RXTX_REG22,
235 pdata->serdes_dfe_tap_ena[XGBE_SPEED_10000]);
237 xgbe_serdes_complete_ratechange(pdata);
240 static void xgbe_gmii_2500_mode(struct xgbe_prv_data *pdata)
244 /* Disable KR training */
245 xgbe_an_disable_kr_training(pdata);
247 /* Set MAC to 2.5G speed */
248 pdata->hw_if.set_gmii_2500_speed(pdata);
250 /* Set PCS to KX/1G speed */
251 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
252 reg &= ~MDIO_PCS_CTRL2_TYPE;
253 reg |= MDIO_PCS_CTRL2_10GBX;
254 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
256 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
257 reg &= ~MDIO_CTRL1_SPEEDSEL;
258 reg |= MDIO_CTRL1_SPEED1G;
259 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
261 xgbe_pcs_power_cycle(pdata);
263 /* Set SerDes to 2.5G speed */
264 xgbe_serdes_start_ratechange(pdata);
266 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_2500_RATE);
267 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_2500_WORD);
268 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_2500_PLL);
270 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
271 pdata->serdes_cdr_rate[XGBE_SPEED_2500]);
272 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
273 pdata->serdes_tx_amp[XGBE_SPEED_2500]);
274 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
275 pdata->serdes_blwc[XGBE_SPEED_2500]);
276 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
277 pdata->serdes_pq_skew[XGBE_SPEED_2500]);
278 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
279 pdata->serdes_dfe_tap_cfg[XGBE_SPEED_2500]);
280 XRXTX_IOWRITE(pdata, RXTX_REG22,
281 pdata->serdes_dfe_tap_ena[XGBE_SPEED_2500]);
283 xgbe_serdes_complete_ratechange(pdata);
286 static void xgbe_gmii_mode(struct xgbe_prv_data *pdata)
290 /* Disable KR training */
291 xgbe_an_disable_kr_training(pdata);
293 /* Set MAC to 1G speed */
294 pdata->hw_if.set_gmii_speed(pdata);
296 /* Set PCS to KX/1G speed */
297 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
298 reg &= ~MDIO_PCS_CTRL2_TYPE;
299 reg |= MDIO_PCS_CTRL2_10GBX;
300 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
302 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
303 reg &= ~MDIO_CTRL1_SPEEDSEL;
304 reg |= MDIO_CTRL1_SPEED1G;
305 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
307 xgbe_pcs_power_cycle(pdata);
309 /* Set SerDes to 1G speed */
310 xgbe_serdes_start_ratechange(pdata);
312 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_1000_RATE);
313 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_1000_WORD);
314 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_1000_PLL);
316 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
317 pdata->serdes_cdr_rate[XGBE_SPEED_1000]);
318 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
319 pdata->serdes_tx_amp[XGBE_SPEED_1000]);
320 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
321 pdata->serdes_blwc[XGBE_SPEED_1000]);
322 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
323 pdata->serdes_pq_skew[XGBE_SPEED_1000]);
324 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
325 pdata->serdes_dfe_tap_cfg[XGBE_SPEED_1000]);
326 XRXTX_IOWRITE(pdata, RXTX_REG22,
327 pdata->serdes_dfe_tap_ena[XGBE_SPEED_1000]);
329 xgbe_serdes_complete_ratechange(pdata);
332 static void xgbe_cur_mode(struct xgbe_prv_data *pdata,
333 enum xgbe_mode *mode)
337 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
338 if ((reg & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
339 *mode = XGBE_MODE_KR;
341 *mode = XGBE_MODE_KX;
344 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
348 xgbe_cur_mode(pdata, &mode);
350 return (mode == XGBE_MODE_KR);
353 static void xgbe_switch_mode(struct xgbe_prv_data *pdata)
355 /* If we are in KR switch to KX, and vice-versa */
356 if (xgbe_in_kr_mode(pdata)) {
357 if (pdata->speed_set == XGBE_SPEEDSET_1000_10000)
358 xgbe_gmii_mode(pdata);
360 xgbe_gmii_2500_mode(pdata);
362 xgbe_xgmii_mode(pdata);
366 static void xgbe_set_mode(struct xgbe_prv_data *pdata,
369 enum xgbe_mode cur_mode;
371 xgbe_cur_mode(pdata, &cur_mode);
372 if (mode != cur_mode)
373 xgbe_switch_mode(pdata);
376 static bool xgbe_use_xgmii_mode(struct xgbe_prv_data *pdata)
378 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
379 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full)
382 if (pdata->phy.speed == SPEED_10000)
389 static bool xgbe_use_gmii_2500_mode(struct xgbe_prv_data *pdata)
391 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
392 if (pdata->phy.advertising & ADVERTISED_2500baseX_Full)
395 if (pdata->phy.speed == SPEED_2500)
402 static bool xgbe_use_gmii_mode(struct xgbe_prv_data *pdata)
404 if (pdata->phy.autoneg == AUTONEG_ENABLE) {
405 if (pdata->phy.advertising & ADVERTISED_1000baseKX_Full)
408 if (pdata->phy.speed == SPEED_1000)
415 static void xgbe_set_an(struct xgbe_prv_data *pdata, bool enable, bool restart)
419 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
420 reg &= ~MDIO_AN_CTRL1_ENABLE;
423 reg |= MDIO_AN_CTRL1_ENABLE;
426 reg |= MDIO_AN_CTRL1_RESTART;
428 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
431 static void xgbe_restart_an(struct xgbe_prv_data *pdata)
433 xgbe_set_an(pdata, true, true);
436 static void xgbe_disable_an(struct xgbe_prv_data *pdata)
438 xgbe_set_an(pdata, false, false);
441 static enum xgbe_an xgbe_an_tx_training(struct xgbe_prv_data *pdata,
444 unsigned int ad_reg, lp_reg, reg;
446 *state = XGBE_RX_COMPLETE;
448 /* If we're not in KR mode then we're done */
449 if (!xgbe_in_kr_mode(pdata))
450 return XGBE_AN_PAGE_RECEIVED;
452 /* Enable/Disable FEC */
453 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
454 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
456 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
457 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
458 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
459 reg |= pdata->fec_ability;
461 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
463 /* Start KR training */
464 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
465 if (reg & XGBE_KR_TRAINING_ENABLE) {
466 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 1);
468 reg |= XGBE_KR_TRAINING_START;
469 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
472 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 0);
475 return XGBE_AN_PAGE_RECEIVED;
478 static enum xgbe_an xgbe_an_tx_xnp(struct xgbe_prv_data *pdata,
483 *state = XGBE_RX_XNP;
485 msg = XGBE_XNP_MCF_NULL_MESSAGE;
486 msg |= XGBE_XNP_MP_FORMATTED;
488 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
489 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
490 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
492 return XGBE_AN_PAGE_RECEIVED;
495 static enum xgbe_an xgbe_an_rx_bpa(struct xgbe_prv_data *pdata,
498 unsigned int link_support;
499 unsigned int reg, ad_reg, lp_reg;
501 /* Read Base Ability register 2 first */
502 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
504 /* Check for a supported mode, otherwise restart in a different one */
505 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
506 if (!(reg & link_support))
507 return XGBE_AN_INCOMPAT_LINK;
509 /* Check Extended Next Page support */
510 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
511 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
513 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
514 (lp_reg & XGBE_XNP_NP_EXCHANGE))
515 ? xgbe_an_tx_xnp(pdata, state)
516 : xgbe_an_tx_training(pdata, state);
519 static enum xgbe_an xgbe_an_rx_xnp(struct xgbe_prv_data *pdata,
522 unsigned int ad_reg, lp_reg;
524 /* Check Extended Next Page support */
525 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
526 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
528 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
529 (lp_reg & XGBE_XNP_NP_EXCHANGE))
530 ? xgbe_an_tx_xnp(pdata, state)
531 : xgbe_an_tx_training(pdata, state);
534 static enum xgbe_an xgbe_an_page_received(struct xgbe_prv_data *pdata)
537 unsigned long an_timeout;
540 if (!pdata->an_start) {
541 pdata->an_start = ticks;
543 an_timeout = pdata->an_start +
544 ((uint64_t)XGBE_AN_MS_TIMEOUT * (uint64_t)hz) / 1000ull;
545 if ((int)(ticks - an_timeout) > 0) {
546 /* Auto-negotiation timed out, reset state */
547 pdata->kr_state = XGBE_RX_BPA;
548 pdata->kx_state = XGBE_RX_BPA;
550 pdata->an_start = ticks;
554 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state
559 ret = xgbe_an_rx_bpa(pdata, state);
563 ret = xgbe_an_rx_xnp(pdata, state);
573 static enum xgbe_an xgbe_an_incompat_link(struct xgbe_prv_data *pdata)
575 /* Be sure we aren't looping trying to negotiate */
576 if (xgbe_in_kr_mode(pdata)) {
577 pdata->kr_state = XGBE_RX_ERROR;
579 if (!(pdata->phy.advertising & ADVERTISED_1000baseKX_Full) &&
580 !(pdata->phy.advertising & ADVERTISED_2500baseX_Full))
581 return XGBE_AN_NO_LINK;
583 if (pdata->kx_state != XGBE_RX_BPA)
584 return XGBE_AN_NO_LINK;
586 pdata->kx_state = XGBE_RX_ERROR;
588 if (!(pdata->phy.advertising & ADVERTISED_10000baseKR_Full))
589 return XGBE_AN_NO_LINK;
591 if (pdata->kr_state != XGBE_RX_BPA)
592 return XGBE_AN_NO_LINK;
595 xgbe_disable_an(pdata);
597 xgbe_switch_mode(pdata);
599 xgbe_restart_an(pdata);
601 return XGBE_AN_INCOMPAT_LINK;
604 static void xgbe_an_isr(void *data)
606 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
608 /* Disable AN interrupts */
609 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
611 /* Save the interrupt(s) that fired */
612 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
615 /* Clear the interrupt(s) that fired and process them */
616 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int);
618 xgbe_an_state_machine(pdata);
620 /* Enable AN interrupts */
621 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK,
626 static void xgbe_an_state_machine(struct xgbe_prv_data *pdata)
628 enum xgbe_an cur_state = pdata->an_state;
630 sx_xlock(&pdata->an_mutex);
636 if (pdata->an_int & XGBE_AN_PG_RCV) {
637 pdata->an_state = XGBE_AN_PAGE_RECEIVED;
638 pdata->an_int &= ~XGBE_AN_PG_RCV;
639 } else if (pdata->an_int & XGBE_AN_INC_LINK) {
640 pdata->an_state = XGBE_AN_INCOMPAT_LINK;
641 pdata->an_int &= ~XGBE_AN_INC_LINK;
642 } else if (pdata->an_int & XGBE_AN_INT_CMPLT) {
643 pdata->an_state = XGBE_AN_COMPLETE;
644 pdata->an_int &= ~XGBE_AN_INT_CMPLT;
646 pdata->an_state = XGBE_AN_ERROR;
649 pdata->an_result = pdata->an_state;
652 cur_state = pdata->an_state;
654 switch (pdata->an_state) {
656 pdata->an_supported = 0;
659 case XGBE_AN_PAGE_RECEIVED:
660 pdata->an_state = xgbe_an_page_received(pdata);
661 pdata->an_supported++;
664 case XGBE_AN_INCOMPAT_LINK:
665 pdata->an_supported = 0;
666 pdata->parallel_detect = 0;
667 pdata->an_state = xgbe_an_incompat_link(pdata);
670 case XGBE_AN_COMPLETE:
671 pdata->parallel_detect = pdata->an_supported ? 0 : 1;
674 case XGBE_AN_NO_LINK:
678 pdata->an_state = XGBE_AN_ERROR;
681 if (pdata->an_state == XGBE_AN_NO_LINK) {
683 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
684 } else if (pdata->an_state == XGBE_AN_ERROR) {
686 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
689 if (pdata->an_state >= XGBE_AN_COMPLETE) {
690 pdata->an_result = pdata->an_state;
691 pdata->an_state = XGBE_AN_READY;
692 pdata->kr_state = XGBE_RX_BPA;
693 pdata->kx_state = XGBE_RX_BPA;
697 if (cur_state != pdata->an_state)
704 /* Enable AN interrupts on the way out */
705 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_INT_MASK);
707 sx_xunlock(&pdata->an_mutex);
710 static void xgbe_an_init(struct xgbe_prv_data *pdata)
714 /* Set up Advertisement register 3 first */
715 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
718 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
720 /* Set up Advertisement register 2 next */
721 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
722 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full)
727 if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) ||
728 (pdata->phy.advertising & ADVERTISED_2500baseX_Full))
733 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
735 /* Set up Advertisement register 1 last */
736 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
737 if (pdata->phy.advertising & ADVERTISED_Pause)
742 if (pdata->phy.advertising & ADVERTISED_Asym_Pause)
747 /* We don't intend to perform XNP */
748 reg &= ~XGBE_XNP_NP_EXCHANGE;
750 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
753 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
757 if (pdata->phy.link) {
758 /* Flow control support */
759 pdata->pause_autoneg = pdata->phy.pause_autoneg;
761 if (pdata->tx_pause != pdata->phy.tx_pause) {
763 pdata->hw_if.config_tx_flow_control(pdata);
764 pdata->tx_pause = pdata->phy.tx_pause;
767 if (pdata->rx_pause != pdata->phy.rx_pause) {
769 pdata->hw_if.config_rx_flow_control(pdata);
770 pdata->rx_pause = pdata->phy.rx_pause;
774 if (pdata->phy_speed != pdata->phy.speed) {
776 pdata->phy_speed = pdata->phy.speed;
779 if (pdata->phy_link != pdata->phy.link) {
781 pdata->phy_link = pdata->phy.link;
783 } else if (pdata->phy_link) {
786 pdata->phy_speed = SPEED_UNKNOWN;
790 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
793 /* Disable auto-negotiation */
794 xgbe_disable_an(pdata);
796 /* Validate/Set specified speed */
797 switch (pdata->phy.speed) {
799 xgbe_set_mode(pdata, XGBE_MODE_KR);
804 xgbe_set_mode(pdata, XGBE_MODE_KX);
811 /* Validate duplex mode */
812 if (pdata->phy.duplex != DUPLEX_FULL)
818 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
820 set_bit(XGBE_LINK_INIT, &pdata->dev_state);
821 pdata->link_check = ticks;
823 if (pdata->phy.autoneg != AUTONEG_ENABLE)
824 return xgbe_phy_config_fixed(pdata);
826 /* Disable auto-negotiation interrupt */
827 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
829 /* Clear any auto-negotitation interrupts */
830 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
832 /* Start auto-negotiation in a supported mode */
833 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) {
834 xgbe_set_mode(pdata, XGBE_MODE_KR);
835 } else if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) ||
836 (pdata->phy.advertising & ADVERTISED_2500baseX_Full)) {
837 xgbe_set_mode(pdata, XGBE_MODE_KX);
839 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07);
843 /* Disable and stop any in progress auto-negotiation */
844 xgbe_disable_an(pdata);
846 /* Clear any auto-negotitation interrupts */
847 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
849 pdata->an_result = XGBE_AN_READY;
850 pdata->an_state = XGBE_AN_READY;
851 pdata->kr_state = XGBE_RX_BPA;
852 pdata->kx_state = XGBE_RX_BPA;
854 /* Re-enable auto-negotiation interrupt */
855 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07);
857 /* Set up advertisement registers based on current settings */
860 /* Enable and start auto-negotiation */
861 xgbe_restart_an(pdata);
866 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
870 sx_xlock(&pdata->an_mutex);
872 ret = __xgbe_phy_config_aneg(pdata);
874 set_bit(XGBE_LINK_ERR, &pdata->dev_state);
876 clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
878 sx_unlock(&pdata->an_mutex);
883 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
885 return (pdata->an_result == XGBE_AN_COMPLETE);
888 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
890 unsigned long link_timeout;
892 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * hz);
893 if ((int)(ticks - link_timeout) >= 0) {
894 xgbe_phy_config_aneg(pdata);
898 static void xgbe_phy_status_force(struct xgbe_prv_data *pdata)
900 if (xgbe_in_kr_mode(pdata)) {
901 pdata->phy.speed = SPEED_10000;
903 switch (pdata->speed_set) {
904 case XGBE_SPEEDSET_1000_10000:
905 pdata->phy.speed = SPEED_1000;
908 case XGBE_SPEEDSET_2500_10000:
909 pdata->phy.speed = SPEED_2500;
913 pdata->phy.duplex = DUPLEX_FULL;
916 static void xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
918 unsigned int ad_reg, lp_reg;
920 pdata->phy.lp_advertising = 0;
922 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
923 return xgbe_phy_status_force(pdata);
925 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
926 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
928 /* Compare Advertisement and Link Partner register 1 */
929 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
930 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
932 pdata->phy.lp_advertising |= ADVERTISED_Pause;
934 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
936 if (pdata->phy.pause_autoneg) {
937 /* Set flow control based on auto-negotiation result */
938 pdata->phy.tx_pause = 0;
939 pdata->phy.rx_pause = 0;
941 if (ad_reg & lp_reg & 0x400) {
942 pdata->phy.tx_pause = 1;
943 pdata->phy.rx_pause = 1;
944 } else if (ad_reg & lp_reg & 0x800) {
946 pdata->phy.rx_pause = 1;
947 else if (lp_reg & 0x400)
948 pdata->phy.tx_pause = 1;
952 /* Compare Advertisement and Link Partner register 2 */
953 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
954 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
956 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
958 switch (pdata->speed_set) {
959 case XGBE_SPEEDSET_1000_10000:
960 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
962 case XGBE_SPEEDSET_2500_10000:
963 pdata->phy.lp_advertising |= ADVERTISED_2500baseX_Full;
970 pdata->phy.speed = SPEED_10000;
971 xgbe_set_mode(pdata, XGBE_MODE_KR);
972 } else if (ad_reg & 0x20) {
973 switch (pdata->speed_set) {
974 case XGBE_SPEEDSET_1000_10000:
975 pdata->phy.speed = SPEED_1000;
978 case XGBE_SPEEDSET_2500_10000:
979 pdata->phy.speed = SPEED_2500;
983 xgbe_set_mode(pdata, XGBE_MODE_KX);
985 pdata->phy.speed = SPEED_UNKNOWN;
988 /* Compare Advertisement and Link Partner register 3 */
989 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
990 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
993 static void xgbe_phy_status(struct xgbe_prv_data *pdata)
995 unsigned int reg, link_aneg;
997 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1002 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1004 /* Get the link status. Link status is latched low, so read
1005 * once to clear and then read again to get current state
1007 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1008 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1009 pdata->phy.link = (reg & MDIO_STAT1_LSTATUS) ? 1 : 0;
1011 if (pdata->phy.link) {
1012 if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1013 xgbe_check_link_timeout(pdata);
1017 xgbe_phy_status_aneg(pdata);
1019 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1020 clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1022 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1023 xgbe_check_link_timeout(pdata);
1029 xgbe_phy_status_aneg(pdata);
1033 xgbe_phy_adjust_link(pdata);
1036 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
1039 /* Disable auto-negotiation */
1040 xgbe_disable_an(pdata);
1042 /* Disable auto-negotiation interrupts */
1043 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
1045 bus_teardown_intr(pdata->dev, pdata->an_irq_res, pdata->an_irq_tag);
1047 pdata->phy.link = 0;
1049 xgbe_phy_adjust_link(pdata);
1052 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
1056 ret = bus_setup_intr(pdata->dev, pdata->an_irq_res,
1057 INTR_MPSAFE | INTR_TYPE_NET, NULL, xgbe_an_isr, pdata,
1058 &pdata->an_irq_tag);
1063 /* Set initial mode - call the mode setting routines
1064 * directly to insure we are properly configured
1066 if (xgbe_use_xgmii_mode(pdata)) {
1067 xgbe_xgmii_mode(pdata);
1068 } else if (xgbe_use_gmii_mode(pdata)) {
1069 xgbe_gmii_mode(pdata);
1070 } else if (xgbe_use_gmii_2500_mode(pdata)) {
1071 xgbe_gmii_2500_mode(pdata);
1077 /* Set up advertisement registers based on current settings */
1078 xgbe_an_init(pdata);
1080 /* Enable auto-negotiation interrupts */
1081 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07);
1083 return xgbe_phy_config_aneg(pdata);
1086 bus_teardown_intr(pdata->dev, pdata->an_irq_res, pdata->an_irq_tag);
1091 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1093 unsigned int count, reg;
1095 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
1096 reg |= MDIO_CTRL1_RESET;
1097 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
1102 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
1103 } while ((reg & MDIO_CTRL1_RESET) && --count);
1105 if (reg & MDIO_CTRL1_RESET)
1108 /* Disable auto-negotiation for now */
1109 xgbe_disable_an(pdata);
1111 /* Clear auto-negotiation interrupts */
1112 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
1117 static void xgbe_phy_init(struct xgbe_prv_data *pdata)
1119 sx_init(&pdata->an_mutex, "axgbe AN lock");
1120 pdata->mdio_mmd = MDIO_MMD_PCS;
1122 /* Initialize supported features */
1123 pdata->phy.supported = SUPPORTED_Autoneg;
1124 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1125 pdata->phy.supported |= SUPPORTED_Backplane;
1126 pdata->phy.supported |= SUPPORTED_10000baseKR_Full;
1127 switch (pdata->speed_set) {
1128 case XGBE_SPEEDSET_1000_10000:
1129 pdata->phy.supported |= SUPPORTED_1000baseKX_Full;
1131 case XGBE_SPEEDSET_2500_10000:
1132 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
1136 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1137 MDIO_PMA_10GBR_FECABLE);
1138 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1139 MDIO_PMA_10GBR_FECABLE_ERRABLE);
1140 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1141 pdata->phy.supported |= SUPPORTED_10000baseR_FEC;
1143 pdata->phy.advertising = pdata->phy.supported;
1145 pdata->phy.address = 0;
1147 pdata->phy.autoneg = AUTONEG_ENABLE;
1148 pdata->phy.speed = SPEED_UNKNOWN;
1149 pdata->phy.duplex = DUPLEX_UNKNOWN;
1151 pdata->phy.link = 0;
1153 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1154 pdata->phy.tx_pause = pdata->tx_pause;
1155 pdata->phy.rx_pause = pdata->rx_pause;
1157 /* Fix up Flow Control advertising */
1158 pdata->phy.advertising &= ~ADVERTISED_Pause;
1159 pdata->phy.advertising &= ~ADVERTISED_Asym_Pause;
1161 if (pdata->rx_pause) {
1162 pdata->phy.advertising |= ADVERTISED_Pause;
1163 pdata->phy.advertising |= ADVERTISED_Asym_Pause;
1166 if (pdata->tx_pause)
1167 pdata->phy.advertising ^= ADVERTISED_Asym_Pause;
1170 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if)
1172 phy_if->phy_init = xgbe_phy_init;
1174 phy_if->phy_reset = xgbe_phy_reset;
1175 phy_if->phy_start = xgbe_phy_start;
1176 phy_if->phy_stop = xgbe_phy_stop;
1178 phy_if->phy_status = xgbe_phy_status;
1179 phy_if->phy_config_aneg = xgbe_phy_config_aneg;