2 * AMD 10Gb Ethernet driver
4 * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc.
6 * This file is available to you under your choice of the following two
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
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60 * modification, are permitted provided that the following conditions are met:
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71 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
73 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
74 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
75 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
76 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81 * This file incorporates work covered by the following copyright and
83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
85 * Inc. unless otherwise expressly agreed to in writing between Synopsys
88 * The Software IS NOT an item of Licensed Software or Licensed Product
89 * under any End User Software License Agreement or Agreement for Licensed
90 * Product with Synopsys or any supplement thereto. Permission is hereby
91 * granted, free of charge, to any person obtaining a copy of this software
92 * annotated with this license and the Software, to deal in the Software
93 * without restriction, including without limitation the rights to use,
94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
95 * of the Software, and to permit persons to whom the Software is furnished
96 * to do so, subject to the following conditions:
98 * The above copyright notice and this permission notice shall be included
99 * in all copies or substantial portions of the Software.
101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
111 * THE POSSIBILITY OF SUCH DAMAGE.
114 #include <sys/cdefs.h>
115 __FBSDID("$FreeBSD$");
118 #include "xgbe-common.h"
120 static void xgbe_an_state_machine(struct xgbe_prv_data *pdata);
123 xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata)
127 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
128 reg &= ~XGBE_AN_CL37_INT_MASK;
129 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
133 xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata)
137 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
138 reg &= ~XGBE_AN_CL37_INT_MASK;
139 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
141 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
142 reg &= ~XGBE_PCS_CL37_BP;
143 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
147 xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata)
151 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
152 reg |= XGBE_PCS_CL37_BP;
153 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
155 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
156 reg |= XGBE_AN_CL37_INT_MASK;
157 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
161 xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata)
163 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
167 xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata)
169 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
173 xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata)
175 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK);
179 xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata)
181 switch (pdata->an_mode) {
182 case XGBE_AN_MODE_CL73:
183 case XGBE_AN_MODE_CL73_REDRV:
184 xgbe_an73_enable_interrupts(pdata);
186 case XGBE_AN_MODE_CL37:
187 case XGBE_AN_MODE_CL37_SGMII:
188 xgbe_an37_enable_interrupts(pdata);
196 xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata)
198 xgbe_an73_clear_interrupts(pdata);
199 xgbe_an37_clear_interrupts(pdata);
203 xgbe_kr_mode(struct xgbe_prv_data *pdata)
205 /* Set MAC to 10G speed */
206 pdata->hw_if.set_speed(pdata, SPEED_10000);
208 /* Call PHY implementation support to complete rate change */
209 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR);
213 xgbe_kx_2500_mode(struct xgbe_prv_data *pdata)
215 /* Set MAC to 2.5G speed */
216 pdata->hw_if.set_speed(pdata, SPEED_2500);
218 /* Call PHY implementation support to complete rate change */
219 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500);
223 xgbe_kx_1000_mode(struct xgbe_prv_data *pdata)
225 /* Set MAC to 1G speed */
226 pdata->hw_if.set_speed(pdata, SPEED_1000);
228 /* Call PHY implementation support to complete rate change */
229 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000);
233 xgbe_sfi_mode(struct xgbe_prv_data *pdata)
235 /* If a KR re-driver is present, change to KR mode instead */
237 return (xgbe_kr_mode(pdata));
239 /* Set MAC to 10G speed */
240 pdata->hw_if.set_speed(pdata, SPEED_10000);
242 /* Call PHY implementation support to complete rate change */
243 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI);
247 xgbe_x_mode(struct xgbe_prv_data *pdata)
249 /* Set MAC to 1G speed */
250 pdata->hw_if.set_speed(pdata, SPEED_1000);
252 /* Call PHY implementation support to complete rate change */
253 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X);
257 xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata)
259 /* Set MAC to 1G speed */
260 pdata->hw_if.set_speed(pdata, SPEED_1000);
262 /* Call PHY implementation support to complete rate change */
263 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000);
267 xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata)
269 /* Set MAC to 1G speed */
270 pdata->hw_if.set_speed(pdata, SPEED_1000);
272 /* Call PHY implementation support to complete rate change */
273 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100);
276 static enum xgbe_mode
277 xgbe_cur_mode(struct xgbe_prv_data *pdata)
279 return (pdata->phy_if.phy_impl.cur_mode(pdata));
283 xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
285 return (xgbe_cur_mode(pdata) == XGBE_MODE_KR);
289 xgbe_change_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
292 case XGBE_MODE_KX_1000:
293 xgbe_kx_1000_mode(pdata);
295 case XGBE_MODE_KX_2500:
296 xgbe_kx_2500_mode(pdata);
301 case XGBE_MODE_SGMII_100:
302 xgbe_sgmii_100_mode(pdata);
304 case XGBE_MODE_SGMII_1000:
305 xgbe_sgmii_1000_mode(pdata);
311 xgbe_sfi_mode(pdata);
313 case XGBE_MODE_UNKNOWN:
316 axgbe_error("invalid operation mode requested (%u)\n", mode);
321 xgbe_switch_mode(struct xgbe_prv_data *pdata)
323 xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata));
327 xgbe_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
329 if (mode == xgbe_cur_mode(pdata))
332 xgbe_change_mode(pdata, mode);
338 xgbe_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
340 return (pdata->phy_if.phy_impl.use_mode(pdata, mode));
344 xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable, bool restart)
348 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
349 reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE;
352 reg |= MDIO_VEND2_CTRL1_AN_ENABLE;
355 reg |= MDIO_VEND2_CTRL1_AN_RESTART;
357 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
361 xgbe_an37_restart(struct xgbe_prv_data *pdata)
363 xgbe_an37_enable_interrupts(pdata);
364 xgbe_an37_set(pdata, true, true);
368 xgbe_an37_disable(struct xgbe_prv_data *pdata)
370 xgbe_an37_set(pdata, false, false);
371 xgbe_an37_disable_interrupts(pdata);
375 xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable, bool restart)
379 /* Disable KR training for now */
380 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
381 reg &= ~XGBE_KR_TRAINING_ENABLE;
382 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
384 /* Update AN settings */
385 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
386 reg &= ~MDIO_AN_CTRL1_ENABLE;
389 reg |= MDIO_AN_CTRL1_ENABLE;
392 reg |= MDIO_AN_CTRL1_RESTART;
394 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
398 xgbe_an73_restart(struct xgbe_prv_data *pdata)
400 xgbe_an73_enable_interrupts(pdata);
401 xgbe_an73_set(pdata, true, true);
405 xgbe_an73_disable(struct xgbe_prv_data *pdata)
407 xgbe_an73_set(pdata, false, false);
408 xgbe_an73_disable_interrupts(pdata);
414 xgbe_an_restart(struct xgbe_prv_data *pdata)
416 if (pdata->phy_if.phy_impl.an_pre)
417 pdata->phy_if.phy_impl.an_pre(pdata);
419 switch (pdata->an_mode) {
420 case XGBE_AN_MODE_CL73:
421 case XGBE_AN_MODE_CL73_REDRV:
422 xgbe_an73_restart(pdata);
424 case XGBE_AN_MODE_CL37:
425 case XGBE_AN_MODE_CL37_SGMII:
426 xgbe_an37_restart(pdata);
434 xgbe_an_disable(struct xgbe_prv_data *pdata)
436 if (pdata->phy_if.phy_impl.an_post)
437 pdata->phy_if.phy_impl.an_post(pdata);
439 switch (pdata->an_mode) {
440 case XGBE_AN_MODE_CL73:
441 case XGBE_AN_MODE_CL73_REDRV:
442 xgbe_an73_disable(pdata);
444 case XGBE_AN_MODE_CL37:
445 case XGBE_AN_MODE_CL37_SGMII:
446 xgbe_an37_disable(pdata);
454 xgbe_an_disable_all(struct xgbe_prv_data *pdata)
456 xgbe_an73_disable(pdata);
457 xgbe_an37_disable(pdata);
461 xgbe_an73_tx_training(struct xgbe_prv_data *pdata, enum xgbe_rx *state)
463 unsigned int ad_reg, lp_reg, reg;
465 *state = XGBE_RX_COMPLETE;
467 /* If we're not in KR mode then we're done */
468 if (!xgbe_in_kr_mode(pdata))
469 return (XGBE_AN_PAGE_RECEIVED);
471 /* Enable/Disable FEC */
472 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
473 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
475 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
476 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
477 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
478 reg |= pdata->fec_ability;
480 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
482 /* Start KR training */
483 if (pdata->phy_if.phy_impl.kr_training_pre)
484 pdata->phy_if.phy_impl.kr_training_pre(pdata);
486 /* Start KR training */
487 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
488 reg |= XGBE_KR_TRAINING_ENABLE;
489 reg |= XGBE_KR_TRAINING_START;
490 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
492 if (pdata->phy_if.phy_impl.kr_training_post)
493 pdata->phy_if.phy_impl.kr_training_post(pdata);
495 return (XGBE_AN_PAGE_RECEIVED);
499 xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata, enum xgbe_rx *state)
503 *state = XGBE_RX_XNP;
505 msg = XGBE_XNP_MCF_NULL_MESSAGE;
506 msg |= XGBE_XNP_MP_FORMATTED;
508 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
509 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
510 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
512 return (XGBE_AN_PAGE_RECEIVED);
516 xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata, enum xgbe_rx *state)
518 unsigned int link_support;
519 unsigned int reg, ad_reg, lp_reg;
521 /* Read Base Ability register 2 first */
522 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
524 /* Check for a supported mode, otherwise restart in a different one */
525 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
526 if (!(reg & link_support))
527 return (XGBE_AN_INCOMPAT_LINK);
529 /* Check Extended Next Page support */
530 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
531 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
533 return (((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
534 (lp_reg & XGBE_XNP_NP_EXCHANGE))
535 ? xgbe_an73_tx_xnp(pdata, state)
536 : xgbe_an73_tx_training(pdata, state));
540 xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata, enum xgbe_rx *state)
542 unsigned int ad_reg, lp_reg;
544 /* Check Extended Next Page support */
545 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
546 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
548 return (((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
549 (lp_reg & XGBE_XNP_NP_EXCHANGE))
550 ? xgbe_an73_tx_xnp(pdata, state)
551 : xgbe_an73_tx_training(pdata, state));
555 xgbe_an73_page_received(struct xgbe_prv_data *pdata)
558 unsigned long an_timeout;
561 if (!pdata->an_start) {
562 pdata->an_start = ticks;
564 an_timeout = pdata->an_start +
565 ((uint64_t)XGBE_AN_MS_TIMEOUT * (uint64_t)hz) / 1000ull;
566 if ((int)(ticks - an_timeout) > 0) {
567 /* Auto-negotiation timed out, reset state */
568 pdata->kr_state = XGBE_RX_BPA;
569 pdata->kx_state = XGBE_RX_BPA;
571 pdata->an_start = ticks;
573 axgbe_printf(2, "CL73 AN timed out, resetting state\n");
577 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state : &pdata->kx_state;
581 ret = xgbe_an73_rx_bpa(pdata, state);
585 ret = xgbe_an73_rx_xnp(pdata, state);
596 xgbe_an73_incompat_link(struct xgbe_prv_data *pdata)
598 /* Be sure we aren't looping trying to negotiate */
599 if (xgbe_in_kr_mode(pdata)) {
600 pdata->kr_state = XGBE_RX_ERROR;
602 if (!(XGBE_ADV(&pdata->phy, 1000baseKX_Full)) &&
603 !(XGBE_ADV(&pdata->phy, 2500baseX_Full)))
604 return (XGBE_AN_NO_LINK);
606 if (pdata->kx_state != XGBE_RX_BPA)
607 return (XGBE_AN_NO_LINK);
609 pdata->kx_state = XGBE_RX_ERROR;
611 if (!(XGBE_ADV(&pdata->phy, 10000baseKR_Full)))
612 return (XGBE_AN_NO_LINK);
614 if (pdata->kr_state != XGBE_RX_BPA)
615 return (XGBE_AN_NO_LINK);
618 xgbe_an_disable(pdata);
620 xgbe_switch_mode(pdata);
622 xgbe_an_restart(pdata);
624 return (XGBE_AN_INCOMPAT_LINK);
628 xgbe_an37_isr(struct xgbe_prv_data *pdata)
632 /* Disable AN interrupts */
633 xgbe_an37_disable_interrupts(pdata);
635 /* Save the interrupt(s) that fired */
636 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
637 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK;
638 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK;
641 /* Clear the interrupt(s) that fired and process them */
642 reg &= ~XGBE_AN_CL37_INT_MASK;
643 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
645 xgbe_an_state_machine(pdata);
647 /* Enable AN interrupts */
648 xgbe_an37_enable_interrupts(pdata);
650 /* Reissue interrupt if status is not clear */
651 if (pdata->vdata->irq_reissue_support)
652 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
657 xgbe_an73_isr(struct xgbe_prv_data *pdata)
659 /* Disable AN interrupts */
660 xgbe_an73_disable_interrupts(pdata);
662 /* Save the interrupt(s) that fired */
663 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
666 /* Clear the interrupt(s) that fired and process them */
667 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int);
669 xgbe_an_state_machine(pdata);
671 /* Enable AN interrupts */
672 xgbe_an73_enable_interrupts(pdata);
674 /* Reissue interrupt if status is not clear */
675 if (pdata->vdata->irq_reissue_support)
676 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
681 xgbe_an_isr_task(unsigned long data)
683 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
685 axgbe_printf(2, "AN interrupt received\n");
687 switch (pdata->an_mode) {
688 case XGBE_AN_MODE_CL73:
689 case XGBE_AN_MODE_CL73_REDRV:
690 xgbe_an73_isr(pdata);
692 case XGBE_AN_MODE_CL37:
693 case XGBE_AN_MODE_CL37_SGMII:
694 xgbe_an37_isr(pdata);
702 xgbe_an_combined_isr(struct xgbe_prv_data *pdata)
704 xgbe_an_isr_task((unsigned long)pdata);
708 xgbe_state_as_string(enum xgbe_an state)
713 case XGBE_AN_PAGE_RECEIVED:
714 return ("Page-Received");
715 case XGBE_AN_INCOMPAT_LINK:
716 return ("Incompatible-Link");
717 case XGBE_AN_COMPLETE:
719 case XGBE_AN_NO_LINK:
724 return ("Undefined");
729 xgbe_an37_state_machine(struct xgbe_prv_data *pdata)
731 enum xgbe_an cur_state = pdata->an_state;
736 if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) {
737 pdata->an_state = XGBE_AN_COMPLETE;
738 pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT;
740 /* If SGMII is enabled, check the link status */
741 if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) &&
742 !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS))
743 pdata->an_state = XGBE_AN_NO_LINK;
746 axgbe_printf(2, "%s: CL37 AN %s\n", __func__,
747 xgbe_state_as_string(pdata->an_state));
749 cur_state = pdata->an_state;
751 switch (pdata->an_state) {
755 case XGBE_AN_COMPLETE:
756 axgbe_printf(2, "Auto negotiation successful\n");
759 case XGBE_AN_NO_LINK:
763 pdata->an_state = XGBE_AN_ERROR;
766 if (pdata->an_state == XGBE_AN_ERROR) {
767 axgbe_printf(2, "error during auto-negotiation, state=%u\n",
771 xgbe_an37_clear_interrupts(pdata);
774 if (pdata->an_state >= XGBE_AN_COMPLETE) {
775 pdata->an_result = pdata->an_state;
776 pdata->an_state = XGBE_AN_READY;
778 if (pdata->phy_if.phy_impl.an_post)
779 pdata->phy_if.phy_impl.an_post(pdata);
781 axgbe_printf(2, "CL37 AN result: %s\n",
782 xgbe_state_as_string(pdata->an_result));
785 axgbe_printf(2, "%s: an_state %d an_int %d an_mode %d an_status %d\n",
786 __func__, pdata->an_state, pdata->an_int, pdata->an_mode,
789 xgbe_an37_enable_interrupts(pdata);
793 xgbe_an73_state_machine(struct xgbe_prv_data *pdata)
795 enum xgbe_an cur_state = pdata->an_state;
801 if (pdata->an_int & XGBE_AN_CL73_PG_RCV) {
802 pdata->an_state = XGBE_AN_PAGE_RECEIVED;
803 pdata->an_int &= ~XGBE_AN_CL73_PG_RCV;
804 } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) {
805 pdata->an_state = XGBE_AN_INCOMPAT_LINK;
806 pdata->an_int &= ~XGBE_AN_CL73_INC_LINK;
807 } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) {
808 pdata->an_state = XGBE_AN_COMPLETE;
809 pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT;
811 pdata->an_state = XGBE_AN_ERROR;
815 axgbe_printf(2, "CL73 AN %s\n",
816 xgbe_state_as_string(pdata->an_state));
818 cur_state = pdata->an_state;
820 switch (pdata->an_state) {
822 pdata->an_supported = 0;
825 case XGBE_AN_PAGE_RECEIVED:
826 pdata->an_state = xgbe_an73_page_received(pdata);
827 pdata->an_supported++;
830 case XGBE_AN_INCOMPAT_LINK:
831 pdata->an_supported = 0;
832 pdata->parallel_detect = 0;
833 pdata->an_state = xgbe_an73_incompat_link(pdata);
836 case XGBE_AN_COMPLETE:
837 pdata->parallel_detect = pdata->an_supported ? 0 : 1;
838 axgbe_printf(2, "%s successful\n",
839 pdata->an_supported ? "Auto negotiation"
840 : "Parallel detection");
843 case XGBE_AN_NO_LINK:
847 pdata->an_state = XGBE_AN_ERROR;
850 if (pdata->an_state == XGBE_AN_NO_LINK) {
852 xgbe_an73_clear_interrupts(pdata);
853 } else if (pdata->an_state == XGBE_AN_ERROR) {
855 "error during auto-negotiation, state=%u\n",
859 xgbe_an73_clear_interrupts(pdata);
862 if (pdata->an_state >= XGBE_AN_COMPLETE) {
863 pdata->an_result = pdata->an_state;
864 pdata->an_state = XGBE_AN_READY;
865 pdata->kr_state = XGBE_RX_BPA;
866 pdata->kx_state = XGBE_RX_BPA;
869 if (pdata->phy_if.phy_impl.an_post)
870 pdata->phy_if.phy_impl.an_post(pdata);
872 axgbe_printf(2, "CL73 AN result: %s\n",
873 xgbe_state_as_string(pdata->an_result));
876 if (cur_state != pdata->an_state)
883 /* Enable AN interrupts on the way out */
884 xgbe_an73_enable_interrupts(pdata);
888 xgbe_an_state_machine(struct xgbe_prv_data *pdata)
890 sx_xlock(&pdata->an_mutex);
892 switch (pdata->an_mode) {
893 case XGBE_AN_MODE_CL73:
894 case XGBE_AN_MODE_CL73_REDRV:
895 xgbe_an73_state_machine(pdata);
897 case XGBE_AN_MODE_CL37:
898 case XGBE_AN_MODE_CL37_SGMII:
899 xgbe_an37_state_machine(pdata);
905 /* Reissue interrupt if status is not clear */
906 if (pdata->vdata->irq_reissue_support)
907 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
909 sx_xunlock(&pdata->an_mutex);
913 xgbe_an37_init(struct xgbe_prv_data *pdata)
915 struct xgbe_phy local_phy;
918 pdata->phy_if.phy_impl.an_advertising(pdata, &local_phy);
920 axgbe_printf(2, "%s: advertising 0x%x\n", __func__, local_phy.advertising);
922 /* Set up Advertisement register */
923 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
924 if (XGBE_ADV(&local_phy, Pause))
929 if (XGBE_ADV(&local_phy, Asym_Pause))
934 /* Full duplex, but not half */
935 reg |= XGBE_AN_CL37_FD_MASK;
936 reg &= ~XGBE_AN_CL37_HD_MASK;
938 axgbe_printf(2, "%s: Writing reg: 0x%x\n", __func__, reg);
939 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);
941 /* Set up the Control register */
942 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
943 axgbe_printf(2, "%s: AN_ADVERTISE reg 0x%x an_mode %d\n", __func__,
944 reg, pdata->an_mode);
945 reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK;
946 reg &= ~XGBE_AN_CL37_PCS_MODE_MASK;
948 switch (pdata->an_mode) {
949 case XGBE_AN_MODE_CL37:
950 reg |= XGBE_AN_CL37_PCS_MODE_BASEX;
952 case XGBE_AN_MODE_CL37_SGMII:
953 reg |= XGBE_AN_CL37_PCS_MODE_SGMII;
959 reg |= XGBE_AN_CL37_MII_CTRL_8BIT;
960 axgbe_printf(2, "%s: Writing reg: 0x%x\n", __func__, reg);
961 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
963 axgbe_printf(2, "CL37 AN (%s) initialized\n",
964 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII");
968 xgbe_an73_init(struct xgbe_prv_data *pdata)
971 * This local_phy is needed because phy-v2 alters the
972 * advertising flag variable. so phy-v1 an_advertising is just copying
974 struct xgbe_phy local_phy;
977 pdata->phy_if.phy_impl.an_advertising(pdata, &local_phy);
979 /* Set up Advertisement register 3 first */
980 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
981 if (XGBE_ADV(&local_phy, 10000baseR_FEC))
986 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
988 /* Set up Advertisement register 2 next */
989 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
990 if (XGBE_ADV(&local_phy, 10000baseKR_Full))
995 if (XGBE_ADV(&local_phy, 1000baseKX_Full) ||
996 XGBE_ADV(&local_phy, 2500baseX_Full))
1001 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
1003 /* Set up Advertisement register 1 last */
1004 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1005 if (XGBE_ADV(&local_phy, Pause))
1010 if (XGBE_ADV(&local_phy, Asym_Pause))
1015 /* We don't intend to perform XNP */
1016 reg &= ~XGBE_XNP_NP_EXCHANGE;
1018 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
1020 axgbe_printf(2, "CL73 AN initialized\n");
1024 xgbe_an_init(struct xgbe_prv_data *pdata)
1026 /* Set up advertisement registers based on current settings */
1027 pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata);
1028 axgbe_printf(2, "%s: setting up an_mode %d\n", __func__, pdata->an_mode);
1030 switch (pdata->an_mode) {
1031 case XGBE_AN_MODE_CL73:
1032 case XGBE_AN_MODE_CL73_REDRV:
1033 xgbe_an73_init(pdata);
1035 case XGBE_AN_MODE_CL37:
1036 case XGBE_AN_MODE_CL37_SGMII:
1037 xgbe_an37_init(pdata);
1045 xgbe_phy_fc_string(struct xgbe_prv_data *pdata)
1047 if (pdata->tx_pause && pdata->rx_pause)
1049 else if (pdata->rx_pause)
1051 else if (pdata->tx_pause)
1058 xgbe_phy_speed_string(int speed)
1072 return ("Unsupported");
1077 xgbe_phy_print_status(struct xgbe_prv_data *pdata)
1079 if (pdata->phy.link)
1081 "Link is UP - %s/%s - flow control %s\n",
1082 xgbe_phy_speed_string(pdata->phy.speed),
1083 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",
1084 xgbe_phy_fc_string(pdata));
1086 axgbe_printf(0, "Link is DOWN\n");
1090 xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
1094 axgbe_printf(1, "link %d/%d tx %d/%d rx %d/%d speed %d/%d autoneg %d/%d\n",
1095 pdata->phy_link, pdata->phy.link,
1096 pdata->tx_pause, pdata->phy.tx_pause,
1097 pdata->rx_pause, pdata->phy.rx_pause,
1098 pdata->phy_speed, pdata->phy.speed,
1099 pdata->pause_autoneg, pdata->phy.pause_autoneg);
1101 if (pdata->phy.link) {
1102 /* Flow control support */
1103 pdata->pause_autoneg = pdata->phy.pause_autoneg;
1105 if (pdata->tx_pause != pdata->phy.tx_pause) {
1107 axgbe_printf(2, "tx pause %d/%d\n", pdata->tx_pause,
1108 pdata->phy.tx_pause);
1109 pdata->tx_pause = pdata->phy.tx_pause;
1110 pdata->hw_if.config_tx_flow_control(pdata);
1113 if (pdata->rx_pause != pdata->phy.rx_pause) {
1115 axgbe_printf(2, "rx pause %d/%d\n", pdata->rx_pause,
1116 pdata->phy.rx_pause);
1117 pdata->rx_pause = pdata->phy.rx_pause;
1118 pdata->hw_if.config_rx_flow_control(pdata);
1122 if (pdata->phy_speed != pdata->phy.speed) {
1124 pdata->phy_speed = pdata->phy.speed;
1127 if (pdata->phy_link != pdata->phy.link) {
1129 pdata->phy_link = pdata->phy.link;
1131 } else if (pdata->phy_link) {
1133 pdata->phy_link = 0;
1134 pdata->phy_speed = SPEED_UNKNOWN;
1137 axgbe_printf(2, "phy_link %d Link %d new_state %d\n", pdata->phy_link,
1138 pdata->phy.link, new_state);
1141 xgbe_phy_print_status(pdata);
1145 xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
1147 return (pdata->phy_if.phy_impl.valid_speed(pdata, speed));
1151 xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
1153 enum xgbe_mode mode;
1155 axgbe_printf(2, "fixed PHY configuration\n");
1157 /* Disable auto-negotiation */
1158 xgbe_an_disable(pdata);
1160 /* Set specified mode for specified speed */
1161 mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed);
1163 case XGBE_MODE_KX_1000:
1164 case XGBE_MODE_KX_2500:
1166 case XGBE_MODE_SGMII_100:
1167 case XGBE_MODE_SGMII_1000:
1171 case XGBE_MODE_UNKNOWN:
1176 /* Validate duplex mode */
1177 if (pdata->phy.duplex != DUPLEX_FULL)
1180 xgbe_set_mode(pdata, mode);
1186 __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata, bool set_mode)
1189 unsigned int reg = 0;
1191 sx_xlock(&pdata->an_mutex);
1193 set_bit(XGBE_LINK_INIT, &pdata->dev_state);
1194 pdata->link_check = ticks;
1196 ret = pdata->phy_if.phy_impl.an_config(pdata);
1198 axgbe_error("%s: an_config fail %d\n", __func__, ret);
1202 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1203 ret = xgbe_phy_config_fixed(pdata);
1204 if (ret || !pdata->kr_redrv) {
1206 axgbe_error("%s: fix conf fail %d\n", __func__, ret);
1210 axgbe_printf(2, "AN redriver support\n");
1212 axgbe_printf(2, "AN PHY configuration\n");
1214 /* Disable auto-negotiation interrupt */
1215 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
1216 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK);
1217 axgbe_printf(2, "%s: set_mode %d AN int reg value 0x%x\n", __func__,
1220 /* Clear any auto-negotitation interrupts */
1221 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
1223 /* Start auto-negotiation in a supported mode */
1225 /* Start auto-negotiation in a supported mode */
1226 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1227 xgbe_set_mode(pdata, XGBE_MODE_KR);
1228 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1229 xgbe_set_mode(pdata, XGBE_MODE_KX_2500);
1230 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1231 xgbe_set_mode(pdata, XGBE_MODE_KX_1000);
1232 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1233 xgbe_set_mode(pdata, XGBE_MODE_SFI);
1234 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1235 xgbe_set_mode(pdata, XGBE_MODE_X);
1236 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1237 xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000);
1238 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1239 xgbe_set_mode(pdata, XGBE_MODE_SGMII_100);
1241 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07);
1247 /* Disable and stop any in progress auto-negotiation */
1248 xgbe_an_disable_all(pdata);
1250 /* Clear any auto-negotitation interrupts */
1251 xgbe_an_clear_interrupts_all(pdata);
1253 pdata->an_result = XGBE_AN_READY;
1254 pdata->an_state = XGBE_AN_READY;
1255 pdata->kr_state = XGBE_RX_BPA;
1256 pdata->kx_state = XGBE_RX_BPA;
1258 /* Re-enable auto-negotiation interrupt */
1259 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07);
1260 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK);
1262 /* Set up advertisement registers based on current settings */
1263 xgbe_an_init(pdata);
1265 /* Enable and start auto-negotiation */
1266 xgbe_an_restart(pdata);
1270 axgbe_printf(0, "%s: set_mode %d AN int reg value 0x%x ret value %d\n",
1271 __func__, set_mode, reg, ret);
1272 set_bit(XGBE_LINK_ERR, &pdata->dev_state);
1274 clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
1276 sx_unlock(&pdata->an_mutex);
1282 xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1284 return (__xgbe_phy_config_aneg(pdata, true));
1288 xgbe_phy_reconfig_aneg(struct xgbe_prv_data *pdata)
1290 return (__xgbe_phy_config_aneg(pdata, false));
1294 xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
1296 return (pdata->an_result == XGBE_AN_COMPLETE);
1300 xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
1302 unsigned long link_timeout;
1304 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * hz);
1305 if ((int)(ticks - link_timeout) > 0) {
1306 axgbe_printf(2, "AN link timeout\n");
1307 xgbe_phy_config_aneg(pdata);
1311 static enum xgbe_mode
1312 xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
1314 return (pdata->phy_if.phy_impl.an_outcome(pdata));
1318 xgbe_phy_status_result(struct xgbe_prv_data *pdata)
1320 enum xgbe_mode mode;
1322 XGBE_ZERO_LP_ADV(&pdata->phy);
1324 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
1325 mode = xgbe_cur_mode(pdata);
1327 mode = xgbe_phy_status_aneg(pdata);
1329 axgbe_printf(3, "%s: xgbe mode %d\n", __func__, mode);
1331 case XGBE_MODE_SGMII_100:
1332 pdata->phy.speed = SPEED_100;
1335 case XGBE_MODE_KX_1000:
1336 case XGBE_MODE_SGMII_1000:
1337 pdata->phy.speed = SPEED_1000;
1339 case XGBE_MODE_KX_2500:
1340 pdata->phy.speed = SPEED_2500;
1344 pdata->phy.speed = SPEED_10000;
1346 case XGBE_MODE_UNKNOWN:
1348 axgbe_printf(1, "%s: unknown mode\n", __func__);
1349 pdata->phy.speed = SPEED_UNKNOWN;
1352 pdata->phy.duplex = DUPLEX_FULL;
1353 axgbe_printf(2, "%s: speed %d duplex %d\n", __func__, pdata->phy.speed,
1356 if (xgbe_set_mode(pdata, mode) && pdata->an_again)
1357 xgbe_phy_reconfig_aneg(pdata);
1361 xgbe_phy_status(struct xgbe_prv_data *pdata)
1366 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1367 axgbe_error("%s: LINK_ERR\n", __func__);
1368 pdata->phy.link = 0;
1372 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1373 axgbe_printf(3, "link_aneg - %d\n", link_aneg);
1375 /* Get the link status. Link status is latched low, so read
1376 * once to clear and then read again to get current state
1378 pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata,
1381 axgbe_printf(1, "link_status returned Link:%d an_restart:%d aneg:%d\n",
1382 pdata->phy.link, an_restart, link_aneg);
1385 xgbe_phy_config_aneg(pdata);
1389 if (pdata->phy.link) {
1390 axgbe_printf(2, "Link Active\n");
1391 if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1392 axgbe_printf(1, "phy_link set check timeout\n");
1393 xgbe_check_link_timeout(pdata);
1397 axgbe_printf(2, "%s: Link write phy_status result\n", __func__);
1398 xgbe_phy_status_result(pdata);
1400 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1401 clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1404 axgbe_printf(2, "Link Deactive\n");
1405 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1406 axgbe_printf(1, "phy_link not set check timeout\n");
1407 xgbe_check_link_timeout(pdata);
1410 axgbe_printf(2, "link_aneg case\n");
1415 xgbe_phy_status_result(pdata);
1420 axgbe_printf(2, "%s: Link %d\n", __func__, pdata->phy.link);
1421 xgbe_phy_adjust_link(pdata);
1425 xgbe_phy_stop(struct xgbe_prv_data *pdata)
1427 axgbe_printf(2, "stopping PHY\n");
1429 if (!pdata->phy_started)
1432 /* Indicate the PHY is down */
1433 pdata->phy_started = 0;
1435 /* Disable auto-negotiation */
1436 xgbe_an_disable_all(pdata);
1438 pdata->phy_if.phy_impl.stop(pdata);
1440 pdata->phy.link = 0;
1442 xgbe_phy_adjust_link(pdata);
1446 xgbe_phy_start(struct xgbe_prv_data *pdata)
1450 DBGPR("-->xgbe_phy_start\n");
1452 ret = pdata->phy_if.phy_impl.start(pdata);
1454 axgbe_error("%s: impl start ret %d\n", __func__, ret);
1458 /* Set initial mode - call the mode setting routines
1459 * directly to insure we are properly configured
1461 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1462 axgbe_printf(2, "%s: KR\n", __func__);
1463 xgbe_kr_mode(pdata);
1464 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1465 axgbe_printf(2, "%s: KX 2500\n", __func__);
1466 xgbe_kx_2500_mode(pdata);
1467 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1468 axgbe_printf(2, "%s: KX 1000\n", __func__);
1469 xgbe_kx_1000_mode(pdata);
1470 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1471 axgbe_printf(2, "%s: SFI\n", __func__);
1472 xgbe_sfi_mode(pdata);
1473 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1474 axgbe_printf(2, "%s: X\n", __func__);
1476 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1477 axgbe_printf(2, "%s: SGMII 1000\n", __func__);
1478 xgbe_sgmii_1000_mode(pdata);
1479 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1480 axgbe_printf(2, "%s: SGMII 100\n", __func__);
1481 xgbe_sgmii_100_mode(pdata);
1483 axgbe_error("%s: invalid mode\n", __func__);
1488 /* Indicate the PHY is up and running */
1489 pdata->phy_started = 1;
1491 /* Set up advertisement registers based on current settings */
1492 xgbe_an_init(pdata);
1494 /* Enable auto-negotiation interrupts */
1495 xgbe_an_enable_interrupts(pdata);
1497 ret = xgbe_phy_config_aneg(pdata);
1499 axgbe_error("%s: phy_config_aneg %d\n", __func__, ret);
1504 pdata->phy_if.phy_impl.stop(pdata);
1510 xgbe_phy_reset(struct xgbe_prv_data *pdata)
1514 ret = pdata->phy_if.phy_impl.reset(pdata);
1516 axgbe_error("%s: impl phy reset %d\n", __func__, ret);
1520 /* Disable auto-negotiation for now */
1521 xgbe_an_disable_all(pdata);
1523 /* Clear auto-negotiation interrupts */
1524 xgbe_an_clear_interrupts_all(pdata);
1530 xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata)
1533 if (XGBE_ADV(&pdata->phy, 10000baseKR_Full))
1534 return (SPEED_10000);
1535 else if (XGBE_ADV(&pdata->phy, 10000baseT_Full))
1536 return (SPEED_10000);
1537 else if (XGBE_ADV(&pdata->phy, 2500baseX_Full))
1538 return (SPEED_2500);
1539 else if (XGBE_ADV(&pdata->phy, 2500baseT_Full))
1540 return (SPEED_2500);
1541 else if (XGBE_ADV(&pdata->phy, 1000baseKX_Full))
1542 return (SPEED_1000);
1543 else if (XGBE_ADV(&pdata->phy, 1000baseT_Full))
1544 return (SPEED_1000);
1545 else if (XGBE_ADV(&pdata->phy, 100baseT_Full))
1548 return (SPEED_UNKNOWN);
1552 xgbe_phy_exit(struct xgbe_prv_data *pdata)
1554 pdata->phy_if.phy_impl.exit(pdata);
1558 xgbe_phy_init(struct xgbe_prv_data *pdata)
1562 DBGPR("-->xgbe_phy_init\n");
1564 sx_init(&pdata->an_mutex, "axgbe AN lock");
1565 pdata->mdio_mmd = MDIO_MMD_PCS;
1567 /* Initialize supported features */
1568 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1569 MDIO_PMA_10GBR_FECABLE);
1570 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1571 MDIO_PMA_10GBR_FECABLE_ERRABLE);
1573 /* Setup the phy (including supported features) */
1574 ret = pdata->phy_if.phy_impl.init(pdata);
1578 /* Copy supported link modes to advertising link modes */
1579 XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);
1581 pdata->phy.address = 0;
1583 if (XGBE_ADV(&pdata->phy, Autoneg)) {
1584 pdata->phy.autoneg = AUTONEG_ENABLE;
1585 pdata->phy.speed = SPEED_UNKNOWN;
1586 pdata->phy.duplex = DUPLEX_UNKNOWN;
1588 pdata->phy.autoneg = AUTONEG_DISABLE;
1589 pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata);
1590 pdata->phy.duplex = DUPLEX_FULL;
1593 pdata->phy.link = 0;
1595 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1596 pdata->phy.tx_pause = pdata->tx_pause;
1597 pdata->phy.rx_pause = pdata->rx_pause;
1599 /* Fix up Flow Control advertising */
1600 XGBE_CLR_ADV(&pdata->phy, Pause);
1601 XGBE_CLR_ADV(&pdata->phy, Asym_Pause);
1603 if (pdata->rx_pause) {
1604 XGBE_SET_ADV(&pdata->phy, Pause);
1605 XGBE_SET_ADV(&pdata->phy, Asym_Pause);
1608 if (pdata->tx_pause) {
1609 if (XGBE_ADV(&pdata->phy, Asym_Pause))
1610 XGBE_CLR_ADV(&pdata->phy, Asym_Pause);
1612 XGBE_SET_ADV(&pdata->phy, Asym_Pause);
1619 xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if)
1621 phy_if->phy_init = xgbe_phy_init;
1622 phy_if->phy_exit = xgbe_phy_exit;
1624 phy_if->phy_reset = xgbe_phy_reset;
1625 phy_if->phy_start = xgbe_phy_start;
1626 phy_if->phy_stop = xgbe_phy_stop;
1628 phy_if->phy_status = xgbe_phy_status;
1629 phy_if->phy_config_aneg = xgbe_phy_config_aneg;
1631 phy_if->phy_valid_speed = xgbe_phy_valid_speed;
1633 phy_if->an_isr = xgbe_an_combined_isr;