2 * AMD 10Gb Ethernet driver
4 * Copyright (c) 2020 Advanced Micro Devices, Inc.
6 * This file is available to you under your choice of the following two
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Redistribution and use in source and binary forms, with or without
60 * modification, are permitted provided that the following conditions are met:
61 * * Redistributions of source code must retain the above copyright
62 * notice, this list of conditions and the following disclaimer.
63 * * Redistributions in binary form must reproduce the above copyright
64 * notice, this list of conditions and the following disclaimer in the
65 * documentation and/or other materials provided with the distribution.
66 * * Neither the name of Advanced Micro Devices, Inc. nor the
67 * names of its contributors may be used to endorse or promote products
68 * derived from this software without specific prior written permission.
70 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
71 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
73 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
74 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
75 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
76 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81 * This file incorporates work covered by the following copyright and
83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
85 * Inc. unless otherwise expressly agreed to in writing between Synopsys
88 * The Software IS NOT an item of Licensed Software or Licensed Product
89 * under any End User Software License Agreement or Agreement for Licensed
90 * Product with Synopsys or any supplement thereto. Permission is hereby
91 * granted, free of charge, to any person obtaining a copy of this software
92 * annotated with this license and the Software, to deal in the Software
93 * without restriction, including without limitation the rights to use,
94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
95 * of the Software, and to permit persons to whom the Software is furnished
96 * to do so, subject to the following conditions:
98 * The above copyright notice and this permission notice shall be included
99 * in all copies or substantial portions of the Software.
101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
111 * THE POSSIBILITY OF SUCH DAMAGE.
114 #include <sys/cdefs.h>
115 __FBSDID("$FreeBSD$");
118 #include "xgbe-common.h"
120 struct xgbe_phy_data {
121 /* 1000/10000 vs 2500/10000 indicator */
122 unsigned int speed_set;
124 /* SerDes UEFI configurable settings.
125 * Switching between modes/speeds requires new values for some
126 * SerDes settings. The values can be supplied as device
127 * properties in array format. The first array entry is for
128 * 1GbE, second for 2.5GbE and third for 10GbE
130 uint32_t blwc[XGBE_SPEEDS];
131 uint32_t cdr_rate[XGBE_SPEEDS];
132 uint32_t pq_skew[XGBE_SPEEDS];
133 uint32_t tx_amp[XGBE_SPEEDS];
134 uint32_t dfe_tap_cfg[XGBE_SPEEDS];
135 uint32_t dfe_tap_ena[XGBE_SPEEDS];
139 xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
141 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 1);
145 xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
147 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 0);
150 static enum xgbe_mode
151 xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
153 struct xgbe_phy_data *phy_data = pdata->phy_data;
155 unsigned int ad_reg, lp_reg;
157 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
158 XGBE_SET_LP_ADV(&pdata->phy, Backplane);
160 /* Compare Advertisement and Link Partner register 1 */
161 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
162 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
164 XGBE_SET_LP_ADV(&pdata->phy, Pause);
166 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
168 axgbe_printf(1, "%s: pause_autoneg %d ad_reg 0x%x lp_reg 0x%x\n",
169 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);
171 if (pdata->phy.pause_autoneg) {
172 /* Set flow control based on auto-negotiation result */
173 pdata->phy.tx_pause = 0;
174 pdata->phy.rx_pause = 0;
176 if (ad_reg & lp_reg & 0x400) {
177 pdata->phy.tx_pause = 1;
178 pdata->phy.rx_pause = 1;
179 } else if (ad_reg & lp_reg & 0x800) {
181 pdata->phy.rx_pause = 1;
182 else if (lp_reg & 0x400)
183 pdata->phy.tx_pause = 1;
187 /* Compare Advertisement and Link Partner register 2 */
188 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
189 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
191 XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);
193 if (phy_data->speed_set == XGBE_SPEEDSET_2500_10000)
194 XGBE_SET_LP_ADV(&pdata->phy, 2500baseX_Full);
196 XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);
201 pdata->phy.speed = SPEED_10000;
203 } else if (ad_reg & 0x20) {
204 switch (pdata->speed_set) {
205 case XGBE_SPEEDSET_1000_10000:
206 pdata->phy.speed = SPEED_1000;
207 mode = XGBE_MODE_KX_1000;
210 case XGBE_SPEEDSET_2500_10000:
211 pdata->phy.speed = SPEED_2500;
212 mode = XGBE_MODE_KX_2500;
216 mode = XGBE_MODE_UNKNOWN;
217 pdata->phy.speed = SPEED_UNKNOWN;
220 /* Compare Advertisement and Link Partner register 3 */
221 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
222 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
224 XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);
230 xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, struct xgbe_phy *dphy)
232 XGBE_LM_COPY(dphy, advertising, &pdata->phy, advertising);
236 xgbe_phy_an_config(struct xgbe_prv_data *pdata)
238 /* Nothing uniquely required for an configuration */
242 static enum xgbe_an_mode
243 xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
245 return (XGBE_AN_MODE_CL73);
249 xgbe_phy_pcs_power_cycle(struct xgbe_prv_data *pdata)
253 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
255 reg |= MDIO_CTRL1_LPOWER;
256 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
260 reg &= ~MDIO_CTRL1_LPOWER;
261 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
265 xgbe_phy_start_ratechange(struct xgbe_prv_data *pdata)
267 /* Assert Rx and Tx ratechange */
268 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 1);
272 xgbe_phy_complete_ratechange(struct xgbe_prv_data *pdata)
277 /* Release Rx and Tx ratechange */
278 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 0);
280 /* Wait for Rx and Tx ready */
281 wait = XGBE_RATECHANGE_COUNT;
285 status = XSIR0_IOREAD(pdata, SIR0_STATUS);
286 if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) &&
287 XSIR_GET_BITS(status, SIR0_STATUS, TX_READY))
291 axgbe_printf(2, "SerDes rx/tx not ready (%#hx)\n", status);
294 /* Perform Rx reset for the DFE changes */
295 XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 0);
296 XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 1);
300 xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
302 struct xgbe_phy_data *phy_data = pdata->phy_data;
305 /* Set PCS to KR/10G speed */
306 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
307 reg &= ~MDIO_PCS_CTRL2_TYPE;
308 reg |= MDIO_PCS_CTRL2_10GBR;
309 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
311 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
312 reg &= ~MDIO_CTRL1_SPEEDSEL;
313 reg |= MDIO_CTRL1_SPEED10G;
314 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
316 xgbe_phy_pcs_power_cycle(pdata);
318 /* Set SerDes to 10G speed */
319 xgbe_phy_start_ratechange(pdata);
321 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_10000_RATE);
322 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_10000_WORD);
323 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_10000_PLL);
325 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
326 phy_data->cdr_rate[XGBE_SPEED_10000]);
327 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
328 phy_data->tx_amp[XGBE_SPEED_10000]);
329 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
330 phy_data->blwc[XGBE_SPEED_10000]);
331 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
332 phy_data->pq_skew[XGBE_SPEED_10000]);
333 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
334 phy_data->dfe_tap_cfg[XGBE_SPEED_10000]);
335 XRXTX_IOWRITE(pdata, RXTX_REG22,
336 phy_data->dfe_tap_ena[XGBE_SPEED_10000]);
338 xgbe_phy_complete_ratechange(pdata);
340 axgbe_printf(2, "10GbE KR mode set\n");
344 xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
346 struct xgbe_phy_data *phy_data = pdata->phy_data;
349 /* Set PCS to KX/1G speed */
350 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
351 reg &= ~MDIO_PCS_CTRL2_TYPE;
352 reg |= MDIO_PCS_CTRL2_10GBX;
353 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
355 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
356 reg &= ~MDIO_CTRL1_SPEEDSEL;
357 reg |= MDIO_CTRL1_SPEED1G;
358 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
360 xgbe_phy_pcs_power_cycle(pdata);
362 /* Set SerDes to 2.5G speed */
363 xgbe_phy_start_ratechange(pdata);
365 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_2500_RATE);
366 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_2500_WORD);
367 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_2500_PLL);
369 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
370 phy_data->cdr_rate[XGBE_SPEED_2500]);
371 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
372 phy_data->tx_amp[XGBE_SPEED_2500]);
373 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
374 phy_data->blwc[XGBE_SPEED_2500]);
375 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
376 phy_data->pq_skew[XGBE_SPEED_2500]);
377 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
378 phy_data->dfe_tap_cfg[XGBE_SPEED_2500]);
379 XRXTX_IOWRITE(pdata, RXTX_REG22,
380 phy_data->dfe_tap_ena[XGBE_SPEED_2500]);
382 xgbe_phy_complete_ratechange(pdata);
384 axgbe_printf(2, "2.5GbE KX mode set\n");
388 xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
390 struct xgbe_phy_data *phy_data = pdata->phy_data;
393 /* Set PCS to KX/1G speed */
394 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
395 reg &= ~MDIO_PCS_CTRL2_TYPE;
396 reg |= MDIO_PCS_CTRL2_10GBX;
397 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
399 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
400 reg &= ~MDIO_CTRL1_SPEEDSEL;
401 reg |= MDIO_CTRL1_SPEED1G;
402 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
404 xgbe_phy_pcs_power_cycle(pdata);
406 /* Set SerDes to 1G speed */
407 xgbe_phy_start_ratechange(pdata);
409 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_1000_RATE);
410 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_1000_WORD);
411 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_1000_PLL);
413 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
414 phy_data->cdr_rate[XGBE_SPEED_1000]);
415 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
416 phy_data->tx_amp[XGBE_SPEED_1000]);
417 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
418 phy_data->blwc[XGBE_SPEED_1000]);
419 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
420 phy_data->pq_skew[XGBE_SPEED_1000]);
421 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
422 phy_data->dfe_tap_cfg[XGBE_SPEED_1000]);
423 XRXTX_IOWRITE(pdata, RXTX_REG22,
424 phy_data->dfe_tap_ena[XGBE_SPEED_1000]);
426 xgbe_phy_complete_ratechange(pdata);
428 axgbe_printf(2, "1GbE KX mode set\n");
431 static enum xgbe_mode
432 xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
434 struct xgbe_phy_data *phy_data = pdata->phy_data;
438 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
439 reg &= MDIO_PCS_CTRL2_TYPE;
441 if (reg == MDIO_PCS_CTRL2_10GBR) {
444 if (phy_data->speed_set == XGBE_SPEEDSET_2500_10000)
445 mode = XGBE_MODE_KX_2500;
447 mode = XGBE_MODE_KX_1000;
453 static enum xgbe_mode
454 xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
456 struct xgbe_phy_data *phy_data = pdata->phy_data;
459 /* If we are in KR switch to KX, and vice-versa */
460 if (xgbe_phy_cur_mode(pdata) == XGBE_MODE_KR) {
461 if (phy_data->speed_set == XGBE_SPEEDSET_2500_10000)
462 mode = XGBE_MODE_KX_2500;
464 mode = XGBE_MODE_KX_1000;
472 static enum xgbe_mode
473 xgbe_phy_get_mode(struct xgbe_prv_data *pdata, int speed)
475 struct xgbe_phy_data *phy_data = pdata->phy_data;
479 return ((phy_data->speed_set == XGBE_SPEEDSET_1000_10000)
480 ? XGBE_MODE_KX_1000 : XGBE_MODE_UNKNOWN);
482 return ((phy_data->speed_set == XGBE_SPEEDSET_2500_10000)
483 ? XGBE_MODE_KX_2500 : XGBE_MODE_UNKNOWN);
485 return (XGBE_MODE_KR);
487 return (XGBE_MODE_UNKNOWN);
492 xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
495 case XGBE_MODE_KX_1000:
496 xgbe_phy_kx_1000_mode(pdata);
498 case XGBE_MODE_KX_2500:
499 xgbe_phy_kx_2500_mode(pdata);
502 xgbe_phy_kr_mode(pdata);
510 xgbe_phy_get_type(struct xgbe_prv_data *pdata, struct ifmediareq * ifmr)
513 switch (pdata->phy.speed) {
515 ifmr->ifm_active |= IFM_10G_KR;
518 ifmr->ifm_active |= IFM_2500_KX;
521 ifmr->ifm_active |= IFM_1000_KX;
524 ifmr->ifm_active |= IFM_OTHER;
530 xgbe_phy_check_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode, bool advert)
533 if (pdata->phy.autoneg == AUTONEG_ENABLE)
536 enum xgbe_mode cur_mode;
538 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
539 if (cur_mode == mode)
547 xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
551 case XGBE_MODE_KX_1000:
552 return (xgbe_phy_check_mode(pdata, mode,
553 XGBE_ADV(&pdata->phy, 1000baseKX_Full)));
554 case XGBE_MODE_KX_2500:
555 return (xgbe_phy_check_mode(pdata, mode,
556 XGBE_ADV(&pdata->phy, 2500baseX_Full)));
558 return (xgbe_phy_check_mode(pdata, mode,
559 XGBE_ADV(&pdata->phy, 10000baseKR_Full)));
566 xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
568 struct xgbe_phy_data *phy_data = pdata->phy_data;
572 if (phy_data->speed_set != XGBE_SPEEDSET_1000_10000)
576 if (phy_data->speed_set != XGBE_SPEEDSET_2500_10000)
587 xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
593 /* Link status is latched low, so read once to clear
594 * and then read again to get current state
596 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
597 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
599 return ((reg & MDIO_STAT1_LSTATUS) ? 1 : 0);
603 xgbe_phy_stop(struct xgbe_prv_data *pdata)
605 /* Nothing uniquely required for stop */
609 xgbe_phy_start(struct xgbe_prv_data *pdata)
611 /* Nothing uniquely required for start */
616 xgbe_phy_reset(struct xgbe_prv_data *pdata)
618 unsigned int reg, count;
620 /* Perform a software reset of the PCS */
621 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
622 reg |= MDIO_CTRL1_RESET;
623 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
628 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
629 } while ((reg & MDIO_CTRL1_RESET) && --count);
631 if (reg & MDIO_CTRL1_RESET)
638 xgbe_phy_exit(struct xgbe_prv_data *pdata)
640 /* Nothing uniquely required for exit */
644 xgbe_phy_init(struct xgbe_prv_data *pdata)
646 struct xgbe_phy_data *phy_data;
648 phy_data = malloc(sizeof(*phy_data), M_AXGBE, M_WAITOK | M_ZERO);
650 /* Initialize supported features */
651 XGBE_ZERO_SUP(&pdata->phy);
652 XGBE_SET_SUP(&pdata->phy, Autoneg);
653 XGBE_SET_SUP(&pdata->phy, Pause);
654 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
655 XGBE_SET_SUP(&pdata->phy, Backplane);
656 XGBE_SET_SUP(&pdata->phy, 10000baseKR_Full);
657 switch (phy_data->speed_set) {
658 case XGBE_SPEEDSET_1000_10000:
659 XGBE_SET_SUP(&pdata->phy, 1000baseKX_Full);
661 case XGBE_SPEEDSET_2500_10000:
662 XGBE_SET_SUP(&pdata->phy, 2500baseX_Full);
666 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
667 XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);
669 pdata->phy_data = phy_data;
675 xgbe_init_function_ptrs_phy_v1(struct xgbe_phy_if *phy_if)
677 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
679 phy_impl->init = xgbe_phy_init;
680 phy_impl->exit = xgbe_phy_exit;
682 phy_impl->reset = xgbe_phy_reset;
683 phy_impl->start = xgbe_phy_start;
684 phy_impl->stop = xgbe_phy_stop;
686 phy_impl->link_status = xgbe_phy_link_status;
688 phy_impl->valid_speed = xgbe_phy_valid_speed;
690 phy_impl->use_mode = xgbe_phy_use_mode;
691 phy_impl->set_mode = xgbe_phy_set_mode;
692 phy_impl->get_mode = xgbe_phy_get_mode;
693 phy_impl->switch_mode = xgbe_phy_switch_mode;
694 phy_impl->cur_mode = xgbe_phy_cur_mode;
695 phy_impl->get_type = xgbe_phy_get_type;
697 phy_impl->an_mode = xgbe_phy_an_mode;
699 phy_impl->an_config = xgbe_phy_an_config;
701 phy_impl->an_advertising = xgbe_phy_an_advertising;
703 phy_impl->an_outcome = xgbe_phy_an_outcome;
705 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
706 phy_impl->kr_training_post = xgbe_phy_kr_training_post;