2 * AMD 10Gb Ethernet driver
4 * Copyright (c) 2020 Advanced Micro Devices, Inc.
6 * This file is available to you under your choice of the following two
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
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60 * modification, are permitted provided that the following conditions are met:
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71 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
72 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
73 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
74 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
75 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
76 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
77 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81 * This file incorporates work covered by the following copyright and
83 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
84 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
85 * Inc. unless otherwise expressly agreed to in writing between Synopsys
88 * The Software IS NOT an item of Licensed Software or Licensed Product
89 * under any End User Software License Agreement or Agreement for Licensed
90 * Product with Synopsys or any supplement thereto. Permission is hereby
91 * granted, free of charge, to any person obtaining a copy of this software
92 * annotated with this license and the Software, to deal in the Software
93 * without restriction, including without limitation the rights to use,
94 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
95 * of the Software, and to permit persons to whom the Software is furnished
96 * to do so, subject to the following conditions:
98 * The above copyright notice and this permission notice shall be included
99 * in all copies or substantial portions of the Software.
101 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
102 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
103 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
104 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
105 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
106 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
107 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
108 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
109 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
110 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
111 * THE POSSIBILITY OF SUCH DAMAGE.
114 #include <sys/cdefs.h>
115 __FBSDID("$FreeBSD$");
118 #include "xgbe-common.h"
120 struct mtx xgbe_phy_comm_lock;
122 #define XGBE_PHY_PORT_SPEED_100 BIT(0)
123 #define XGBE_PHY_PORT_SPEED_1000 BIT(1)
124 #define XGBE_PHY_PORT_SPEED_2500 BIT(2)
125 #define XGBE_PHY_PORT_SPEED_10000 BIT(3)
127 #define XGBE_MUTEX_RELEASE 0x80000000
129 #define XGBE_SFP_DIRECT 7
130 #define GPIO_MASK_WIDTH 4
132 /* I2C target addresses */
133 #define XGBE_SFP_SERIAL_ID_ADDRESS 0x50
134 #define XGBE_SFP_DIAG_INFO_ADDRESS 0x51
135 #define XGBE_SFP_PHY_ADDRESS 0x56
136 #define XGBE_GPIO_ADDRESS_PCA9555 0x20
138 /* SFP sideband signal indicators */
139 #define XGBE_GPIO_NO_TX_FAULT BIT(0)
140 #define XGBE_GPIO_NO_RATE_SELECT BIT(1)
141 #define XGBE_GPIO_NO_MOD_ABSENT BIT(2)
142 #define XGBE_GPIO_NO_RX_LOS BIT(3)
144 /* Rate-change complete wait/retry count */
145 #define XGBE_RATECHANGE_COUNT 500
147 /* CDR delay values for KR support (in usec) */
148 #define XGBE_CDR_DELAY_INIT 10000
149 #define XGBE_CDR_DELAY_INC 10000
150 #define XGBE_CDR_DELAY_MAX 100000
152 /* RRC frequency during link status check */
153 #define XGBE_RRC_FREQUENCY 10
155 enum xgbe_port_mode {
156 XGBE_PORT_MODE_RSVD = 0,
157 XGBE_PORT_MODE_BACKPLANE,
158 XGBE_PORT_MODE_BACKPLANE_2500,
159 XGBE_PORT_MODE_1000BASE_T,
160 XGBE_PORT_MODE_1000BASE_X,
161 XGBE_PORT_MODE_NBASE_T,
162 XGBE_PORT_MODE_10GBASE_T,
163 XGBE_PORT_MODE_10GBASE_R,
168 enum xgbe_conn_type {
169 XGBE_CONN_TYPE_NONE = 0,
172 XGBE_CONN_TYPE_RSVD1,
173 XGBE_CONN_TYPE_BACKPLANE,
177 /* SFP/SFP+ related definitions */
179 XGBE_SFP_COMM_DIRECT = 0,
180 XGBE_SFP_COMM_PCA9545,
183 enum xgbe_sfp_cable {
184 XGBE_SFP_CABLE_UNKNOWN = 0,
185 XGBE_SFP_CABLE_ACTIVE,
186 XGBE_SFP_CABLE_PASSIVE,
190 XGBE_SFP_BASE_UNKNOWN = 0,
191 XGBE_SFP_BASE_1000_T,
192 XGBE_SFP_BASE_1000_SX,
193 XGBE_SFP_BASE_1000_LX,
194 XGBE_SFP_BASE_1000_CX,
195 XGBE_SFP_BASE_10000_SR,
196 XGBE_SFP_BASE_10000_LR,
197 XGBE_SFP_BASE_10000_LRM,
198 XGBE_SFP_BASE_10000_ER,
199 XGBE_SFP_BASE_10000_CR,
202 enum xgbe_sfp_speed {
203 XGBE_SFP_SPEED_UNKNOWN = 0,
204 XGBE_SFP_SPEED_100_1000,
206 XGBE_SFP_SPEED_10000,
209 /* SFP Serial ID Base ID values relative to an offset of 0 */
210 #define XGBE_SFP_BASE_ID 0
211 #define XGBE_SFP_ID_SFP 0x03
213 #define XGBE_SFP_BASE_EXT_ID 1
214 #define XGBE_SFP_EXT_ID_SFP 0x04
216 #define XGBE_SFP_BASE_10GBE_CC 3
217 #define XGBE_SFP_BASE_10GBE_CC_SR BIT(4)
218 #define XGBE_SFP_BASE_10GBE_CC_LR BIT(5)
219 #define XGBE_SFP_BASE_10GBE_CC_LRM BIT(6)
220 #define XGBE_SFP_BASE_10GBE_CC_ER BIT(7)
222 #define XGBE_SFP_BASE_1GBE_CC 6
223 #define XGBE_SFP_BASE_1GBE_CC_SX BIT(0)
224 #define XGBE_SFP_BASE_1GBE_CC_LX BIT(1)
225 #define XGBE_SFP_BASE_1GBE_CC_CX BIT(2)
226 #define XGBE_SFP_BASE_1GBE_CC_T BIT(3)
228 #define XGBE_SFP_BASE_CABLE 8
229 #define XGBE_SFP_BASE_CABLE_PASSIVE BIT(2)
230 #define XGBE_SFP_BASE_CABLE_ACTIVE BIT(3)
232 #define XGBE_SFP_BASE_BR 12
233 #define XGBE_SFP_BASE_BR_1GBE_MIN 0x0a
234 #define XGBE_SFP_BASE_BR_1GBE_MAX 0x0d
235 #define XGBE_SFP_BASE_BR_10GBE_MIN 0x64
236 #define XGBE_SFP_BASE_BR_10GBE_MAX 0x68
238 #define XGBE_SFP_BASE_CU_CABLE_LEN 18
240 #define XGBE_SFP_BASE_VENDOR_NAME 20
241 #define XGBE_SFP_BASE_VENDOR_NAME_LEN 16
242 #define XGBE_SFP_BASE_VENDOR_PN 40
243 #define XGBE_SFP_BASE_VENDOR_PN_LEN 16
244 #define XGBE_SFP_BASE_VENDOR_REV 56
245 #define XGBE_SFP_BASE_VENDOR_REV_LEN 4
247 #define XGBE_SFP_BASE_CC 63
249 /* SFP Serial ID Extended ID values relative to an offset of 64 */
250 #define XGBE_SFP_BASE_VENDOR_SN 4
251 #define XGBE_SFP_BASE_VENDOR_SN_LEN 16
253 #define XGBE_SFP_EXTD_OPT1 1
254 #define XGBE_SFP_EXTD_OPT1_RX_LOS BIT(1)
255 #define XGBE_SFP_EXTD_OPT1_TX_FAULT BIT(3)
257 #define XGBE_SFP_EXTD_DIAG 28
258 #define XGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2)
260 #define XGBE_SFP_EXTD_SFF_8472 30
262 #define XGBE_SFP_EXTD_CC 31
264 struct xgbe_sfp_eeprom {
270 #define XGBE_SFP_DIAGS_SUPPORTED(_x) \
271 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
272 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
274 #define XGBE_SFP_EEPROM_BASE_LEN 256
275 #define XGBE_SFP_EEPROM_DIAG_LEN 256
276 #define XGBE_SFP_EEPROM_MAX (XGBE_SFP_EEPROM_BASE_LEN + \
277 XGBE_SFP_EEPROM_DIAG_LEN)
279 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
280 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
282 struct xgbe_sfp_ascii {
284 char vendor[XGBE_SFP_BASE_VENDOR_NAME_LEN + 1];
285 char partno[XGBE_SFP_BASE_VENDOR_PN_LEN + 1];
286 char rev[XGBE_SFP_BASE_VENDOR_REV_LEN + 1];
287 char serno[XGBE_SFP_BASE_VENDOR_SN_LEN + 1];
291 /* MDIO PHY reset types */
292 enum xgbe_mdio_reset {
293 XGBE_MDIO_RESET_NONE = 0,
294 XGBE_MDIO_RESET_I2C_GPIO,
295 XGBE_MDIO_RESET_INT_GPIO,
299 /* Re-driver related definitions */
300 enum xgbe_phy_redrv_if {
301 XGBE_PHY_REDRV_IF_MDIO = 0,
302 XGBE_PHY_REDRV_IF_I2C,
303 XGBE_PHY_REDRV_IF_MAX,
306 enum xgbe_phy_redrv_model {
307 XGBE_PHY_REDRV_MODEL_4223 = 0,
308 XGBE_PHY_REDRV_MODEL_4227,
309 XGBE_PHY_REDRV_MODEL_MAX,
312 enum xgbe_phy_redrv_mode {
313 XGBE_PHY_REDRV_MODE_CX = 5,
314 XGBE_PHY_REDRV_MODE_SR = 9,
317 #define XGBE_PHY_REDRV_MODE_REG 0x12b0
319 /* PHY related configuration information */
320 struct xgbe_phy_data {
321 enum xgbe_port_mode port_mode;
323 unsigned int port_id;
325 unsigned int port_speeds;
327 enum xgbe_conn_type conn_type;
329 enum xgbe_mode cur_mode;
330 enum xgbe_mode start_mode;
332 unsigned int rrc_count;
334 unsigned int mdio_addr;
337 enum xgbe_sfp_comm sfp_comm;
338 unsigned int sfp_mux_address;
339 unsigned int sfp_mux_channel;
341 unsigned int sfp_gpio_address;
342 unsigned int sfp_gpio_mask;
343 unsigned int sfp_gpio_inputs;
344 unsigned int sfp_gpio_rx_los;
345 unsigned int sfp_gpio_tx_fault;
346 unsigned int sfp_gpio_mod_absent;
347 unsigned int sfp_gpio_rate_select;
349 unsigned int sfp_rx_los;
350 unsigned int sfp_tx_fault;
351 unsigned int sfp_mod_absent;
352 unsigned int sfp_changed;
353 unsigned int sfp_phy_avail;
354 unsigned int sfp_cable_len;
355 enum xgbe_sfp_base sfp_base;
356 enum xgbe_sfp_cable sfp_cable;
357 enum xgbe_sfp_speed sfp_speed;
358 struct xgbe_sfp_eeprom sfp_eeprom;
360 /* External PHY support */
361 enum xgbe_mdio_mode phydev_mode;
364 enum xgbe_mdio_reset mdio_reset;
365 unsigned int mdio_reset_addr;
366 unsigned int mdio_reset_gpio;
368 /* Re-driver support */
370 unsigned int redrv_if;
371 unsigned int redrv_addr;
372 unsigned int redrv_lane;
373 unsigned int redrv_model;
376 unsigned int phy_cdr_notrack;
377 unsigned int phy_cdr_delay;
379 uint8_t port_sfp_inputs;
382 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata);
385 xgbe_phy_i2c_xfer(struct xgbe_prv_data *pdata, struct xgbe_i2c_op *i2c_op)
387 return (pdata->i2c_if.i2c_xfer(pdata, i2c_op));
391 xgbe_phy_redrv_write(struct xgbe_prv_data *pdata, unsigned int reg,
394 struct xgbe_phy_data *phy_data = pdata->phy_data;
395 struct xgbe_i2c_op i2c_op;
397 uint8_t redrv_data[5], csum;
398 unsigned int i, retry;
401 /* High byte of register contains read/write indicator */
402 redrv_data[0] = ((reg >> 8) & 0xff) << 1;
403 redrv_data[1] = reg & 0xff;
404 redrv_val = (__be16 *)&redrv_data[2];
405 *redrv_val = cpu_to_be16(val);
407 /* Calculate 1 byte checksum */
409 for (i = 0; i < 4; i++) {
410 csum += redrv_data[i];
411 if (redrv_data[i] > csum)
414 redrv_data[4] = ~csum;
418 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
419 i2c_op.target = phy_data->redrv_addr;
420 i2c_op.len = sizeof(redrv_data);
421 i2c_op.buf = redrv_data;
422 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
424 if ((ret == -EAGAIN) && retry--)
432 i2c_op.cmd = XGBE_I2C_CMD_READ;
433 i2c_op.target = phy_data->redrv_addr;
435 i2c_op.buf = redrv_data;
436 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
438 if ((ret == -EAGAIN) && retry--)
444 if (redrv_data[0] != 0xff) {
445 axgbe_error("Redriver write checksum error\n");
453 xgbe_phy_i2c_write(struct xgbe_prv_data *pdata, unsigned int target, void *val,
454 unsigned int val_len)
456 struct xgbe_i2c_op i2c_op;
461 /* Write the specfied register */
462 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
463 i2c_op.target = target;
464 i2c_op.len = val_len;
466 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
467 if ((ret == -EAGAIN) && retry--)
474 xgbe_phy_i2c_read(struct xgbe_prv_data *pdata, unsigned int target, void *reg,
475 unsigned int reg_len, void *val, unsigned int val_len)
477 struct xgbe_i2c_op i2c_op;
480 axgbe_printf(3, "%s: target 0x%x reg_len %d val_len %d\n", __func__,
481 target, reg_len, val_len);
484 /* Set the specified register to read */
485 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
486 i2c_op.target = target;
487 i2c_op.len = reg_len;
489 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
490 axgbe_printf(3, "%s: ret1 %d retry %d\n", __func__, ret, retry);
492 if ((ret == -EAGAIN) && retry--)
500 /* Read the specfied register */
501 i2c_op.cmd = XGBE_I2C_CMD_READ;
502 i2c_op.target = target;
503 i2c_op.len = val_len;
505 ret = xgbe_phy_i2c_xfer(pdata, &i2c_op);
506 axgbe_printf(3, "%s: ret2 %d retry %d\n", __func__, ret, retry);
507 if ((ret == -EAGAIN) && retry--)
514 xgbe_phy_sfp_put_mux(struct xgbe_prv_data *pdata)
516 struct xgbe_phy_data *phy_data = pdata->phy_data;
517 struct xgbe_i2c_op i2c_op;
520 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
523 /* Select no mux channels */
525 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
526 i2c_op.target = phy_data->sfp_mux_address;
527 i2c_op.len = sizeof(mux_channel);
528 i2c_op.buf = &mux_channel;
530 return (xgbe_phy_i2c_xfer(pdata, &i2c_op));
534 xgbe_phy_sfp_get_mux(struct xgbe_prv_data *pdata)
536 struct xgbe_phy_data *phy_data = pdata->phy_data;
537 struct xgbe_i2c_op i2c_op;
540 if (phy_data->sfp_comm == XGBE_SFP_COMM_DIRECT)
543 /* Select desired mux channel */
544 mux_channel = 1 << phy_data->sfp_mux_channel;
545 i2c_op.cmd = XGBE_I2C_CMD_WRITE;
546 i2c_op.target = phy_data->sfp_mux_address;
547 i2c_op.len = sizeof(mux_channel);
548 i2c_op.buf = &mux_channel;
550 return (xgbe_phy_i2c_xfer(pdata, &i2c_op));
554 xgbe_phy_put_comm_ownership(struct xgbe_prv_data *pdata)
556 mtx_unlock(&xgbe_phy_comm_lock);
560 xgbe_phy_get_comm_ownership(struct xgbe_prv_data *pdata)
562 struct xgbe_phy_data *phy_data = pdata->phy_data;
563 unsigned long timeout;
564 unsigned int mutex_id;
566 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices,
567 * the driver needs to take the software mutex and then the hardware
568 * mutexes before being able to use the busses.
570 mtx_lock(&xgbe_phy_comm_lock);
572 /* Clear the mutexes */
573 XP_IOWRITE(pdata, XP_I2C_MUTEX, XGBE_MUTEX_RELEASE);
574 XP_IOWRITE(pdata, XP_MDIO_MUTEX, XGBE_MUTEX_RELEASE);
576 /* Mutex formats are the same for I2C and MDIO/GPIO */
578 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id);
579 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1);
581 timeout = ticks + (5 * hz);
582 while (ticks < timeout) {
583 /* Must be all zeroes in order to obtain the mutex */
584 if (XP_IOREAD(pdata, XP_I2C_MUTEX) ||
585 XP_IOREAD(pdata, XP_MDIO_MUTEX)) {
590 /* Obtain the mutex */
591 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id);
592 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id);
597 mtx_unlock(&xgbe_phy_comm_lock);
599 axgbe_error("unable to obtain hardware mutexes\n");
605 xgbe_phy_mdio_mii_write(struct xgbe_prv_data *pdata, int addr, int reg,
608 struct xgbe_phy_data *phy_data = pdata->phy_data;
610 if (reg & MII_ADDR_C45) {
611 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
614 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
618 return (pdata->hw_if.write_ext_mii_regs(pdata, addr, reg, val));
622 xgbe_phy_i2c_mii_write(struct xgbe_prv_data *pdata, int reg, uint16_t val)
628 ret = xgbe_phy_sfp_get_mux(pdata);
632 mii_data[0] = reg & 0xff;
633 mii_val = (__be16 *)&mii_data[1];
634 *mii_val = cpu_to_be16(val);
636 ret = xgbe_phy_i2c_write(pdata, XGBE_SFP_PHY_ADDRESS,
637 mii_data, sizeof(mii_data));
639 xgbe_phy_sfp_put_mux(pdata);
645 xgbe_phy_mii_write(struct xgbe_prv_data *pdata, int addr, int reg, uint16_t val)
647 struct xgbe_phy_data *phy_data = pdata->phy_data;
650 axgbe_printf(3, "%s: addr %d reg %d val %#x\n", __func__, addr, reg, val);
651 ret = xgbe_phy_get_comm_ownership(pdata);
655 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
656 ret = xgbe_phy_i2c_mii_write(pdata, reg, val);
657 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
658 ret = xgbe_phy_mdio_mii_write(pdata, addr, reg, val);
662 xgbe_phy_put_comm_ownership(pdata);
668 xgbe_phy_mdio_mii_read(struct xgbe_prv_data *pdata, int addr, int reg)
670 struct xgbe_phy_data *phy_data = pdata->phy_data;
672 if (reg & MII_ADDR_C45) {
673 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL45)
676 if (phy_data->phydev_mode != XGBE_MDIO_MODE_CL22)
680 return (pdata->hw_if.read_ext_mii_regs(pdata, addr, reg));
684 xgbe_phy_i2c_mii_read(struct xgbe_prv_data *pdata, int reg)
690 ret = xgbe_phy_sfp_get_mux(pdata);
695 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_PHY_ADDRESS,
696 &mii_reg, sizeof(mii_reg),
697 &mii_val, sizeof(mii_val));
699 ret = be16_to_cpu(mii_val);
701 xgbe_phy_sfp_put_mux(pdata);
707 xgbe_phy_mii_read(struct xgbe_prv_data *pdata, int addr, int reg)
709 struct xgbe_phy_data *phy_data = pdata->phy_data;
712 axgbe_printf(3, "%s: addr %d reg %d\n", __func__, addr, reg);
713 ret = xgbe_phy_get_comm_ownership(pdata);
717 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
718 ret = xgbe_phy_i2c_mii_read(pdata, reg);
719 else if (phy_data->conn_type & XGBE_CONN_TYPE_MDIO)
720 ret = xgbe_phy_mdio_mii_read(pdata, addr, reg);
724 xgbe_phy_put_comm_ownership(pdata);
730 xgbe_phy_sfp_phy_settings(struct xgbe_prv_data *pdata)
732 struct xgbe_phy_data *phy_data = pdata->phy_data;
734 if (!phy_data->sfp_mod_absent && !phy_data->sfp_changed)
737 XGBE_ZERO_SUP(&pdata->phy);
739 if (phy_data->sfp_mod_absent) {
740 pdata->phy.speed = SPEED_UNKNOWN;
741 pdata->phy.duplex = DUPLEX_UNKNOWN;
742 pdata->phy.autoneg = AUTONEG_ENABLE;
743 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
745 XGBE_SET_SUP(&pdata->phy, Autoneg);
746 XGBE_SET_SUP(&pdata->phy, Pause);
747 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
748 XGBE_SET_SUP(&pdata->phy, TP);
749 XGBE_SET_SUP(&pdata->phy, FIBRE);
751 XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);
756 switch (phy_data->sfp_base) {
757 case XGBE_SFP_BASE_1000_T:
758 case XGBE_SFP_BASE_1000_SX:
759 case XGBE_SFP_BASE_1000_LX:
760 case XGBE_SFP_BASE_1000_CX:
761 pdata->phy.speed = SPEED_UNKNOWN;
762 pdata->phy.duplex = DUPLEX_UNKNOWN;
763 pdata->phy.autoneg = AUTONEG_ENABLE;
764 pdata->phy.pause_autoneg = AUTONEG_ENABLE;
765 XGBE_SET_SUP(&pdata->phy, Autoneg);
766 XGBE_SET_SUP(&pdata->phy, Pause);
767 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
768 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T) {
769 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
770 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
771 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
772 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
774 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
775 XGBE_SET_SUP(&pdata->phy, 1000baseX_Full);
778 case XGBE_SFP_BASE_10000_SR:
779 case XGBE_SFP_BASE_10000_LR:
780 case XGBE_SFP_BASE_10000_LRM:
781 case XGBE_SFP_BASE_10000_ER:
782 case XGBE_SFP_BASE_10000_CR:
783 pdata->phy.speed = SPEED_10000;
784 pdata->phy.duplex = DUPLEX_FULL;
785 pdata->phy.autoneg = AUTONEG_DISABLE;
786 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
787 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
788 switch (phy_data->sfp_base) {
789 case XGBE_SFP_BASE_10000_SR:
790 XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full);
792 case XGBE_SFP_BASE_10000_LR:
793 XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full);
795 case XGBE_SFP_BASE_10000_LRM:
796 XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full);
798 case XGBE_SFP_BASE_10000_ER:
799 XGBE_SET_SUP(&pdata->phy, 10000baseER_Full);
801 case XGBE_SFP_BASE_10000_CR:
802 XGBE_SET_SUP(&pdata->phy, 10000baseCR_Full);
810 pdata->phy.speed = SPEED_UNKNOWN;
811 pdata->phy.duplex = DUPLEX_UNKNOWN;
812 pdata->phy.autoneg = AUTONEG_DISABLE;
813 pdata->phy.pause_autoneg = AUTONEG_DISABLE;
817 switch (phy_data->sfp_base) {
818 case XGBE_SFP_BASE_1000_T:
819 case XGBE_SFP_BASE_1000_CX:
820 case XGBE_SFP_BASE_10000_CR:
821 XGBE_SET_SUP(&pdata->phy, TP);
824 XGBE_SET_SUP(&pdata->phy, FIBRE);
828 XGBE_LM_COPY(&pdata->phy, advertising, &pdata->phy, supported);
830 axgbe_printf(1, "%s: link speed %d spf_base 0x%x pause_autoneg %d "
831 "advert 0x%x support 0x%x\n", __func__, pdata->phy.speed,
832 phy_data->sfp_base, pdata->phy.pause_autoneg,
833 pdata->phy.advertising, pdata->phy.supported);
837 xgbe_phy_sfp_bit_rate(struct xgbe_sfp_eeprom *sfp_eeprom,
838 enum xgbe_sfp_speed sfp_speed)
840 uint8_t *sfp_base, min, max;
842 sfp_base = sfp_eeprom->base;
845 case XGBE_SFP_SPEED_1000:
846 min = XGBE_SFP_BASE_BR_1GBE_MIN;
847 max = XGBE_SFP_BASE_BR_1GBE_MAX;
849 case XGBE_SFP_SPEED_10000:
850 min = XGBE_SFP_BASE_BR_10GBE_MIN;
851 max = XGBE_SFP_BASE_BR_10GBE_MAX;
857 return ((sfp_base[XGBE_SFP_BASE_BR] >= min) &&
858 (sfp_base[XGBE_SFP_BASE_BR] <= max));
862 xgbe_phy_free_phy_device(struct xgbe_prv_data *pdata)
864 struct xgbe_phy_data *phy_data = pdata->phy_data;
866 if (phy_data->phydev)
867 phy_data->phydev = 0;
871 xgbe_phy_finisar_phy_quirks(struct xgbe_prv_data *pdata)
873 struct xgbe_phy_data *phy_data = pdata->phy_data;
874 unsigned int phy_id = phy_data->phy_id;
876 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
879 if ((phy_id & 0xfffffff0) != 0x01ff0cc0)
882 /* Enable Base-T AN */
883 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0001);
884 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140);
885 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x16, 0x0000);
887 /* Enable SGMII at 100Base-T/1000Base-T Full Duplex */
888 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1b, 0x9084);
889 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x09, 0x0e00);
890 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x8140);
891 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x04, 0x0d01);
892 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, 0x9140);
894 axgbe_printf(3, "Finisar PHY quirk in place\n");
900 xgbe_phy_belfuse_phy_quirks(struct xgbe_prv_data *pdata)
902 struct xgbe_phy_data *phy_data = pdata->phy_data;
903 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
904 unsigned int phy_id = phy_data->phy_id;
907 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
910 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
911 XGBE_BEL_FUSE_VENDOR, XGBE_SFP_BASE_VENDOR_NAME_LEN))
914 /* For Bel-Fuse, use the extra AN flag */
917 if (memcmp(&sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
918 XGBE_BEL_FUSE_PARTNO, XGBE_SFP_BASE_VENDOR_PN_LEN))
921 if ((phy_id & 0xfffffff0) != 0x03625d10)
924 /* Disable RGMII mode */
925 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, 0x7007);
926 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x18);
927 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x18, reg & ~0x0080);
929 /* Enable fiber register bank */
930 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
931 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
934 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
937 /* Power down SerDes */
938 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
939 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg | 0x00800);
941 /* Configure SGMII-to-Copper mode */
942 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
943 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
946 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
949 /* Power up SerDes */
950 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
951 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);
953 /* Enable copper register bank */
954 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x7c00);
955 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x1c);
958 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x1c, 0x8000 | 0x7c00 |
961 /* Power up SerDes */
962 reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x00);
963 xgbe_phy_mii_write(pdata, phy_data->mdio_addr, 0x00, reg & ~0x00800);
965 axgbe_printf(3, "BelFuse PHY quirk in place\n");
971 xgbe_phy_external_phy_quirks(struct xgbe_prv_data *pdata)
973 if (xgbe_phy_belfuse_phy_quirks(pdata))
976 if (xgbe_phy_finisar_phy_quirks(pdata))
981 xgbe_get_phy_id(struct xgbe_prv_data *pdata)
983 struct xgbe_phy_data *phy_data = pdata->phy_data;
984 uint32_t oui, model, phy_id1, phy_id2;
987 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x02);
991 phy_id1 = (phy_reg & 0xffff);
992 phy_data->phy_id = (phy_reg & 0xffff) << 16;
994 phy_reg = xgbe_phy_mii_read(pdata, phy_data->mdio_addr, 0x03);
998 phy_id2 = (phy_reg & 0xffff);
999 phy_data->phy_id |= (phy_reg & 0xffff);
1001 oui = MII_OUI(phy_id1, phy_id2);
1002 model = MII_MODEL(phy_id2);
1004 axgbe_printf(2, "%s: phy_id1: 0x%x phy_id2: 0x%x oui: %#x model %#x\n",
1005 __func__, phy_id1, phy_id2, oui, model);
1011 xgbe_phy_start_aneg(struct xgbe_prv_data *pdata)
1017 if (AUTONEG_ENABLE != pdata->phy.autoneg) {
1018 if (SPEED_1000 == pdata->phy.speed)
1020 else if (SPEED_100 == pdata->phy.speed)
1021 ctl |= BMCR_SPEED100;
1023 if (DUPLEX_FULL == pdata->phy.duplex)
1026 ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR);
1030 ret = xgbe_phy_mii_write(pdata, pdata->mdio_addr, MII_BMCR,
1031 (ret & ~(~(BMCR_LOOP | BMCR_ISO | BMCR_PDOWN))) | ctl);
1034 ctl = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR);
1038 if (!(ctl & BMCR_AUTOEN) || (ctl & BMCR_ISO))
1042 ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR);
1046 ret = xgbe_phy_mii_write(pdata, pdata->mdio_addr, MII_BMCR,
1047 (ret & ~(BMCR_ISO)) | (BMCR_AUTOEN | BMCR_STARTNEG));
1054 xgbe_phy_find_phy_device(struct xgbe_prv_data *pdata)
1056 struct xgbe_phy_data *phy_data = pdata->phy_data;
1059 axgbe_printf(2, "%s: phydev %d phydev_mode %d sfp_phy_avail %d phy_id "
1060 "0x%08x\n", __func__, phy_data->phydev, phy_data->phydev_mode,
1061 phy_data->sfp_phy_avail, phy_data->phy_id);
1063 /* If we already have a PHY, just return */
1064 if (phy_data->phydev) {
1065 axgbe_printf(3, "%s: phy present already\n", __func__);
1069 /* Clear the extra AN flag */
1070 pdata->an_again = 0;
1072 /* Check for the use of an external PHY */
1073 if (phy_data->phydev_mode == XGBE_MDIO_MODE_NONE) {
1074 axgbe_printf(3, "%s: phydev_mode %d\n", __func__,
1075 phy_data->phydev_mode);
1079 /* For SFP, only use an external PHY if available */
1080 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
1081 !phy_data->sfp_phy_avail) {
1082 axgbe_printf(3, "%s: port_mode %d avail %d\n", __func__,
1083 phy_data->port_mode, phy_data->sfp_phy_avail);
1087 /* Set the proper MDIO mode for the PHY */
1088 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
1089 phy_data->phydev_mode);
1091 axgbe_error("mdio port/clause not compatible (%u/%u) ret %d\n",
1092 phy_data->mdio_addr, phy_data->phydev_mode, ret);
1096 ret = xgbe_get_phy_id(pdata);
1099 axgbe_printf(2, "Get phy_id 0x%08x\n", phy_data->phy_id);
1101 phy_data->phydev = 1;
1102 xgbe_phy_external_phy_quirks(pdata);
1103 xgbe_phy_start_aneg(pdata);
1109 xgbe_phy_sfp_external_phy(struct xgbe_prv_data *pdata)
1111 struct xgbe_phy_data *phy_data = pdata->phy_data;
1114 axgbe_printf(3, "%s: sfp_changed: 0x%x\n", __func__,
1115 phy_data->sfp_changed);
1116 if (!phy_data->sfp_changed)
1119 phy_data->sfp_phy_avail = 0;
1121 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
1124 /* Check access to the PHY by reading CTRL1 */
1125 ret = xgbe_phy_i2c_mii_read(pdata, MII_BMCR);
1127 axgbe_error("%s: ext phy fail %d\n", __func__, ret);
1131 /* Successfully accessed the PHY */
1132 phy_data->sfp_phy_avail = 1;
1133 axgbe_printf(3, "Successfully accessed External PHY\n");
1137 xgbe_phy_check_sfp_rx_los(struct xgbe_phy_data *phy_data)
1139 uint8_t *sfp_extd = phy_data->sfp_eeprom.extd;
1141 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_RX_LOS))
1144 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_RX_LOS)
1147 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_rx_los))
1154 xgbe_phy_check_sfp_tx_fault(struct xgbe_phy_data *phy_data)
1156 uint8_t *sfp_extd = phy_data->sfp_eeprom.extd;
1158 if (!(sfp_extd[XGBE_SFP_EXTD_OPT1] & XGBE_SFP_EXTD_OPT1_TX_FAULT))
1161 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_TX_FAULT)
1164 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_tx_fault))
1171 xgbe_phy_check_sfp_mod_absent(struct xgbe_phy_data *phy_data)
1173 if (phy_data->sfp_gpio_mask & XGBE_GPIO_NO_MOD_ABSENT)
1176 if (phy_data->sfp_gpio_inputs & (1 << phy_data->sfp_gpio_mod_absent))
1183 xgbe_phy_sfp_parse_eeprom(struct xgbe_prv_data *pdata)
1185 struct xgbe_phy_data *phy_data = pdata->phy_data;
1186 struct xgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom;
1189 sfp_base = sfp_eeprom->base;
1191 if (sfp_base[XGBE_SFP_BASE_ID] != XGBE_SFP_ID_SFP) {
1192 axgbe_error("base id %d\n", sfp_base[XGBE_SFP_BASE_ID]);
1196 if (sfp_base[XGBE_SFP_BASE_EXT_ID] != XGBE_SFP_EXT_ID_SFP) {
1197 axgbe_error("base id %d\n", sfp_base[XGBE_SFP_BASE_EXT_ID]);
1201 /* Update transceiver signals (eeprom extd/options) */
1202 phy_data->sfp_tx_fault = xgbe_phy_check_sfp_tx_fault(phy_data);
1203 phy_data->sfp_rx_los = xgbe_phy_check_sfp_rx_los(phy_data);
1205 /* Assume ACTIVE cable unless told it is PASSIVE */
1206 if (sfp_base[XGBE_SFP_BASE_CABLE] & XGBE_SFP_BASE_CABLE_PASSIVE) {
1207 phy_data->sfp_cable = XGBE_SFP_CABLE_PASSIVE;
1208 phy_data->sfp_cable_len = sfp_base[XGBE_SFP_BASE_CU_CABLE_LEN];
1210 phy_data->sfp_cable = XGBE_SFP_CABLE_ACTIVE;
1212 /* Determine the type of SFP */
1213 if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_SR)
1214 phy_data->sfp_base = XGBE_SFP_BASE_10000_SR;
1215 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LR)
1216 phy_data->sfp_base = XGBE_SFP_BASE_10000_LR;
1217 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_LRM)
1218 phy_data->sfp_base = XGBE_SFP_BASE_10000_LRM;
1219 else if (sfp_base[XGBE_SFP_BASE_10GBE_CC] & XGBE_SFP_BASE_10GBE_CC_ER)
1220 phy_data->sfp_base = XGBE_SFP_BASE_10000_ER;
1221 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_SX)
1222 phy_data->sfp_base = XGBE_SFP_BASE_1000_SX;
1223 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_LX)
1224 phy_data->sfp_base = XGBE_SFP_BASE_1000_LX;
1225 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_CX)
1226 phy_data->sfp_base = XGBE_SFP_BASE_1000_CX;
1227 else if (sfp_base[XGBE_SFP_BASE_1GBE_CC] & XGBE_SFP_BASE_1GBE_CC_T)
1228 phy_data->sfp_base = XGBE_SFP_BASE_1000_T;
1229 else if ((phy_data->sfp_cable == XGBE_SFP_CABLE_PASSIVE) &&
1230 xgbe_phy_sfp_bit_rate(sfp_eeprom, XGBE_SFP_SPEED_10000))
1231 phy_data->sfp_base = XGBE_SFP_BASE_10000_CR;
1233 switch (phy_data->sfp_base) {
1234 case XGBE_SFP_BASE_1000_T:
1235 phy_data->sfp_speed = XGBE_SFP_SPEED_100_1000;
1237 case XGBE_SFP_BASE_1000_SX:
1238 case XGBE_SFP_BASE_1000_LX:
1239 case XGBE_SFP_BASE_1000_CX:
1240 phy_data->sfp_speed = XGBE_SFP_SPEED_1000;
1242 case XGBE_SFP_BASE_10000_SR:
1243 case XGBE_SFP_BASE_10000_LR:
1244 case XGBE_SFP_BASE_10000_LRM:
1245 case XGBE_SFP_BASE_10000_ER:
1246 case XGBE_SFP_BASE_10000_CR:
1247 phy_data->sfp_speed = XGBE_SFP_SPEED_10000;
1252 axgbe_printf(3, "%s: sfp_base: 0x%x sfp_speed: 0x%x sfp_cable: 0x%x "
1253 "rx_los 0x%x tx_fault 0x%x\n", __func__, phy_data->sfp_base,
1254 phy_data->sfp_speed, phy_data->sfp_cable, phy_data->sfp_rx_los,
1255 phy_data->sfp_tx_fault);
1259 xgbe_phy_sfp_eeprom_info(struct xgbe_prv_data *pdata,
1260 struct xgbe_sfp_eeprom *sfp_eeprom)
1262 struct xgbe_sfp_ascii sfp_ascii;
1263 char *sfp_data = (char *)&sfp_ascii;
1265 axgbe_printf(3, "SFP detected:\n");
1266 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_NAME],
1267 XGBE_SFP_BASE_VENDOR_NAME_LEN);
1268 sfp_data[XGBE_SFP_BASE_VENDOR_NAME_LEN] = '\0';
1269 axgbe_printf(3, " vendor: %s\n",
1272 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_PN],
1273 XGBE_SFP_BASE_VENDOR_PN_LEN);
1274 sfp_data[XGBE_SFP_BASE_VENDOR_PN_LEN] = '\0';
1275 axgbe_printf(3, " part number: %s\n",
1278 memcpy(sfp_data, &sfp_eeprom->base[XGBE_SFP_BASE_VENDOR_REV],
1279 XGBE_SFP_BASE_VENDOR_REV_LEN);
1280 sfp_data[XGBE_SFP_BASE_VENDOR_REV_LEN] = '\0';
1281 axgbe_printf(3, " revision level: %s\n",
1284 memcpy(sfp_data, &sfp_eeprom->extd[XGBE_SFP_BASE_VENDOR_SN],
1285 XGBE_SFP_BASE_VENDOR_SN_LEN);
1286 sfp_data[XGBE_SFP_BASE_VENDOR_SN_LEN] = '\0';
1287 axgbe_printf(3, " serial number: %s\n",
1292 xgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf, unsigned int len)
1296 for (cc = 0; len; buf++, len--)
1299 return ((cc == cc_in) ? true : false);
1303 dump_sfp_eeprom(struct xgbe_prv_data *pdata, uint8_t *sfp_base)
1305 axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_ID] : 0x%04x\n",
1306 sfp_base[XGBE_SFP_BASE_ID]);
1307 axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_EXT_ID] : 0x%04x\n",
1308 sfp_base[XGBE_SFP_BASE_EXT_ID]);
1309 axgbe_printf(3, "sfp_base[XGBE_SFP_BASE_CABLE] : 0x%04x\n",
1310 sfp_base[XGBE_SFP_BASE_CABLE]);
1314 xgbe_phy_sfp_read_eeprom(struct xgbe_prv_data *pdata)
1316 struct xgbe_phy_data *phy_data = pdata->phy_data;
1317 struct xgbe_sfp_eeprom sfp_eeprom, *eeprom;
1318 uint8_t eeprom_addr, *base;
1321 ret = xgbe_phy_sfp_get_mux(pdata);
1323 axgbe_error("I2C error setting SFP MUX\n");
1327 /* Read the SFP serial ID eeprom */
1329 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1330 &eeprom_addr, sizeof(eeprom_addr),
1331 &sfp_eeprom, sizeof(sfp_eeprom));
1333 eeprom = &sfp_eeprom;
1334 base = eeprom->base;
1335 dump_sfp_eeprom(pdata, base);
1337 axgbe_error("I2C error reading SFP EEPROM\n");
1341 /* Validate the contents read */
1342 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[XGBE_SFP_BASE_CC],
1343 sfp_eeprom.base, sizeof(sfp_eeprom.base) - 1)) {
1344 axgbe_error("verify eeprom base failed\n");
1349 if (!xgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[XGBE_SFP_EXTD_CC],
1350 sfp_eeprom.extd, sizeof(sfp_eeprom.extd) - 1)) {
1351 axgbe_error("verify eeprom extd failed\n");
1356 /* Check for an added or changed SFP */
1357 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) {
1358 phy_data->sfp_changed = 1;
1360 xgbe_phy_sfp_eeprom_info(pdata, &sfp_eeprom);
1362 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom));
1364 xgbe_phy_free_phy_device(pdata);
1366 phy_data->sfp_changed = 0;
1369 xgbe_phy_sfp_put_mux(pdata);
1375 xgbe_phy_sfp_signals(struct xgbe_prv_data *pdata)
1377 struct xgbe_phy_data *phy_data = pdata->phy_data;
1378 uint8_t gpio_reg, gpio_ports[2];
1379 int ret, prev_sfp_inputs = phy_data->port_sfp_inputs;
1380 int shift = GPIO_MASK_WIDTH * (3 - phy_data->port_id);
1382 /* Read the input port registers */
1383 axgbe_printf(3, "%s: befor sfp_mod:%d sfp_gpio_address:0x%x\n",
1384 __func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_address);
1387 ret = xgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, &gpio_reg,
1388 sizeof(gpio_reg), gpio_ports, sizeof(gpio_ports));
1390 axgbe_error("%s: I2C error reading SFP GPIO addr:0x%x\n",
1391 __func__, phy_data->sfp_gpio_address);
1395 phy_data->sfp_gpio_inputs = (gpio_ports[1] << 8) | gpio_ports[0];
1396 phy_data->port_sfp_inputs = (phy_data->sfp_gpio_inputs >> shift) & 0x0F;
1398 if (prev_sfp_inputs != phy_data->port_sfp_inputs)
1399 axgbe_printf(0, "%s: port_sfp_inputs: 0x%0x\n", __func__,
1400 phy_data->port_sfp_inputs);
1402 phy_data->sfp_mod_absent = xgbe_phy_check_sfp_mod_absent(phy_data);
1404 axgbe_printf(3, "%s: after sfp_mod:%d sfp_gpio_inputs:0x%x\n",
1405 __func__, phy_data->sfp_mod_absent, phy_data->sfp_gpio_inputs);
1409 xgbe_phy_sfp_mod_absent(struct xgbe_prv_data *pdata)
1411 struct xgbe_phy_data *phy_data = pdata->phy_data;
1413 xgbe_phy_free_phy_device(pdata);
1415 phy_data->sfp_mod_absent = 1;
1416 phy_data->sfp_phy_avail = 0;
1417 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom));
1421 xgbe_phy_sfp_reset(struct xgbe_phy_data *phy_data)
1423 phy_data->sfp_rx_los = 0;
1424 phy_data->sfp_tx_fault = 0;
1425 phy_data->sfp_mod_absent = 1;
1426 phy_data->sfp_base = XGBE_SFP_BASE_UNKNOWN;
1427 phy_data->sfp_cable = XGBE_SFP_CABLE_UNKNOWN;
1428 phy_data->sfp_speed = XGBE_SFP_SPEED_UNKNOWN;
1432 xgbe_phy_sfp_detect(struct xgbe_prv_data *pdata)
1434 struct xgbe_phy_data *phy_data = pdata->phy_data;
1435 int ret, prev_sfp_state = phy_data->sfp_mod_absent;
1437 /* Reset the SFP signals and info */
1438 xgbe_phy_sfp_reset(phy_data);
1440 ret = xgbe_phy_get_comm_ownership(pdata);
1444 /* Read the SFP signals and check for module presence */
1445 xgbe_phy_sfp_signals(pdata);
1446 if (phy_data->sfp_mod_absent) {
1447 if (prev_sfp_state != phy_data->sfp_mod_absent)
1448 axgbe_error("%s: mod absent\n", __func__);
1449 xgbe_phy_sfp_mod_absent(pdata);
1453 ret = xgbe_phy_sfp_read_eeprom(pdata);
1455 /* Treat any error as if there isn't an SFP plugged in */
1456 axgbe_error("%s: eeprom read failed\n", __func__);
1457 xgbe_phy_sfp_reset(phy_data);
1458 xgbe_phy_sfp_mod_absent(pdata);
1462 xgbe_phy_sfp_parse_eeprom(pdata);
1464 xgbe_phy_sfp_external_phy(pdata);
1467 xgbe_phy_sfp_phy_settings(pdata);
1469 axgbe_printf(3, "%s: phy speed: 0x%x duplex: 0x%x autoneg: 0x%x "
1470 "pause_autoneg: 0x%x\n", __func__, pdata->phy.speed,
1471 pdata->phy.duplex, pdata->phy.autoneg, pdata->phy.pause_autoneg);
1473 xgbe_phy_put_comm_ownership(pdata);
1477 xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata)
1479 struct xgbe_phy_data *phy_data = pdata->phy_data;
1480 uint8_t eeprom_addr, eeprom_data[XGBE_SFP_EEPROM_MAX];
1481 struct xgbe_sfp_eeprom *sfp_eeprom;
1484 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
1489 if (phy_data->sfp_mod_absent) {
1494 ret = xgbe_phy_get_comm_ownership(pdata);
1500 ret = xgbe_phy_sfp_get_mux(pdata);
1502 axgbe_error("I2C error setting SFP MUX\n");
1507 /* Read the SFP serial ID eeprom */
1509 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_SERIAL_ID_ADDRESS,
1510 &eeprom_addr, sizeof(eeprom_addr),
1511 eeprom_data, XGBE_SFP_EEPROM_BASE_LEN);
1513 axgbe_error("I2C error reading SFP EEPROM\n");
1518 sfp_eeprom = (struct xgbe_sfp_eeprom *)eeprom_data;
1520 if (XGBE_SFP_DIAGS_SUPPORTED(sfp_eeprom)) {
1521 /* Read the SFP diagnostic eeprom */
1523 ret = xgbe_phy_i2c_read(pdata, XGBE_SFP_DIAG_INFO_ADDRESS,
1524 &eeprom_addr, sizeof(eeprom_addr),
1525 eeprom_data + XGBE_SFP_EEPROM_BASE_LEN,
1526 XGBE_SFP_EEPROM_DIAG_LEN);
1528 axgbe_error("I2C error reading SFP DIAGS\n");
1535 xgbe_phy_sfp_put_mux(pdata);
1538 xgbe_phy_put_comm_ownership(pdata);
1545 xgbe_phy_module_info(struct xgbe_prv_data *pdata)
1547 struct xgbe_phy_data *phy_data = pdata->phy_data;
1549 if (phy_data->port_mode != XGBE_PORT_MODE_SFP)
1552 if (phy_data->sfp_mod_absent)
1559 xgbe_phy_phydev_flowctrl(struct xgbe_prv_data *pdata)
1561 struct xgbe_phy_data *phy_data = pdata->phy_data;
1563 pdata->phy.tx_pause = 0;
1564 pdata->phy.rx_pause = 0;
1566 if (!phy_data->phydev)
1569 if (pdata->phy.pause)
1570 XGBE_SET_LP_ADV(&pdata->phy, Pause);
1572 if (pdata->phy.asym_pause)
1573 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
1575 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__,
1576 pdata->phy.tx_pause, pdata->phy.rx_pause);
1579 static enum xgbe_mode
1580 xgbe_phy_an37_sgmii_outcome(struct xgbe_prv_data *pdata)
1582 enum xgbe_mode mode;
1584 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1585 XGBE_SET_LP_ADV(&pdata->phy, TP);
1587 axgbe_printf(1, "%s: pause_autoneg %d\n", __func__,
1588 pdata->phy.pause_autoneg);
1590 /* Use external PHY to determine flow control */
1591 if (pdata->phy.pause_autoneg)
1592 xgbe_phy_phydev_flowctrl(pdata);
1594 switch (pdata->an_status & XGBE_SGMII_AN_LINK_SPEED) {
1595 case XGBE_SGMII_AN_LINK_SPEED_100:
1596 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1597 XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Full);
1598 mode = XGBE_MODE_SGMII_100;
1600 /* Half-duplex not supported */
1601 XGBE_SET_LP_ADV(&pdata->phy, 100baseT_Half);
1602 mode = XGBE_MODE_UNKNOWN;
1605 case XGBE_SGMII_AN_LINK_SPEED_1000:
1606 if (pdata->an_status & XGBE_SGMII_AN_LINK_DUPLEX) {
1607 XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Full);
1608 mode = XGBE_MODE_SGMII_1000;
1610 /* Half-duplex not supported */
1611 XGBE_SET_LP_ADV(&pdata->phy, 1000baseT_Half);
1612 mode = XGBE_MODE_UNKNOWN;
1616 mode = XGBE_MODE_UNKNOWN;
1622 static enum xgbe_mode
1623 xgbe_phy_an37_outcome(struct xgbe_prv_data *pdata)
1625 enum xgbe_mode mode;
1626 unsigned int ad_reg, lp_reg;
1628 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1629 XGBE_SET_LP_ADV(&pdata->phy, FIBRE);
1631 /* Compare Advertisement and Link Partner register */
1632 ad_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
1633 lp_reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_LP_ABILITY);
1635 XGBE_SET_LP_ADV(&pdata->phy, Pause);
1637 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
1639 axgbe_printf(1, "%s: pause_autoneg %d ad_reg 0x%x lp_reg 0x%x\n",
1640 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);
1642 if (pdata->phy.pause_autoneg) {
1643 /* Set flow control based on auto-negotiation result */
1644 pdata->phy.tx_pause = 0;
1645 pdata->phy.rx_pause = 0;
1647 if (ad_reg & lp_reg & 0x100) {
1648 pdata->phy.tx_pause = 1;
1649 pdata->phy.rx_pause = 1;
1650 } else if (ad_reg & lp_reg & 0x80) {
1652 pdata->phy.rx_pause = 1;
1653 else if (lp_reg & 0x100)
1654 pdata->phy.tx_pause = 1;
1658 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause,
1659 pdata->phy.rx_pause);
1662 XGBE_SET_LP_ADV(&pdata->phy, 1000baseX_Full);
1664 /* Half duplex is not supported */
1666 mode = (ad_reg & 0x20) ? XGBE_MODE_X : XGBE_MODE_UNKNOWN;
1671 static enum xgbe_mode
1672 xgbe_phy_an73_redrv_outcome(struct xgbe_prv_data *pdata)
1674 struct xgbe_phy_data *phy_data = pdata->phy_data;
1675 enum xgbe_mode mode;
1676 unsigned int ad_reg, lp_reg;
1678 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1679 XGBE_SET_LP_ADV(&pdata->phy, Backplane);
1681 axgbe_printf(1, "%s: pause_autoneg %d\n", __func__,
1682 pdata->phy.pause_autoneg);
1684 /* Use external PHY to determine flow control */
1685 if (pdata->phy.pause_autoneg)
1686 xgbe_phy_phydev_flowctrl(pdata);
1688 /* Compare Advertisement and Link Partner register 2 */
1689 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1690 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1692 XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);
1694 XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);
1697 if (ad_reg & 0x80) {
1698 switch (phy_data->port_mode) {
1699 case XGBE_PORT_MODE_BACKPLANE:
1700 mode = XGBE_MODE_KR;
1703 mode = XGBE_MODE_SFI;
1706 } else if (ad_reg & 0x20) {
1707 switch (phy_data->port_mode) {
1708 case XGBE_PORT_MODE_BACKPLANE:
1709 mode = XGBE_MODE_KX_1000;
1711 case XGBE_PORT_MODE_1000BASE_X:
1714 case XGBE_PORT_MODE_SFP:
1715 switch (phy_data->sfp_base) {
1716 case XGBE_SFP_BASE_1000_T:
1717 if ((phy_data->phydev) &&
1718 (pdata->phy.speed == SPEED_100))
1719 mode = XGBE_MODE_SGMII_100;
1721 mode = XGBE_MODE_SGMII_1000;
1723 case XGBE_SFP_BASE_1000_SX:
1724 case XGBE_SFP_BASE_1000_LX:
1725 case XGBE_SFP_BASE_1000_CX:
1732 if ((phy_data->phydev) &&
1733 (pdata->phy.speed == SPEED_100))
1734 mode = XGBE_MODE_SGMII_100;
1736 mode = XGBE_MODE_SGMII_1000;
1740 mode = XGBE_MODE_UNKNOWN;
1743 /* Compare Advertisement and Link Partner register 3 */
1744 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1745 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1746 if (lp_reg & 0xc000)
1747 XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);
1752 static enum xgbe_mode
1753 xgbe_phy_an73_outcome(struct xgbe_prv_data *pdata)
1755 enum xgbe_mode mode;
1756 unsigned int ad_reg, lp_reg;
1758 XGBE_SET_LP_ADV(&pdata->phy, Autoneg);
1759 XGBE_SET_LP_ADV(&pdata->phy, Backplane);
1761 /* Compare Advertisement and Link Partner register 1 */
1762 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1763 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
1765 XGBE_SET_LP_ADV(&pdata->phy, Pause);
1767 XGBE_SET_LP_ADV(&pdata->phy, Asym_Pause);
1769 axgbe_printf(1, "%s: pause_autoneg %d ad_reg 0x%x lp_reg 0x%x\n",
1770 __func__, pdata->phy.pause_autoneg, ad_reg, lp_reg);
1772 if (pdata->phy.pause_autoneg) {
1773 /* Set flow control based on auto-negotiation result */
1774 pdata->phy.tx_pause = 0;
1775 pdata->phy.rx_pause = 0;
1777 if (ad_reg & lp_reg & 0x400) {
1778 pdata->phy.tx_pause = 1;
1779 pdata->phy.rx_pause = 1;
1780 } else if (ad_reg & lp_reg & 0x800) {
1782 pdata->phy.rx_pause = 1;
1783 else if (lp_reg & 0x400)
1784 pdata->phy.tx_pause = 1;
1788 axgbe_printf(1, "%s: pause tx/rx %d/%d\n", __func__, pdata->phy.tx_pause,
1789 pdata->phy.rx_pause);
1791 /* Compare Advertisement and Link Partner register 2 */
1792 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1793 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1795 XGBE_SET_LP_ADV(&pdata->phy, 10000baseKR_Full);
1797 XGBE_SET_LP_ADV(&pdata->phy, 1000baseKX_Full);
1801 mode = XGBE_MODE_KR;
1802 else if (ad_reg & 0x20)
1803 mode = XGBE_MODE_KX_1000;
1805 mode = XGBE_MODE_UNKNOWN;
1807 /* Compare Advertisement and Link Partner register 3 */
1808 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1809 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1810 if (lp_reg & 0xc000)
1811 XGBE_SET_LP_ADV(&pdata->phy, 10000baseR_FEC);
1816 static enum xgbe_mode
1817 xgbe_phy_an_outcome(struct xgbe_prv_data *pdata)
1819 switch (pdata->an_mode) {
1820 case XGBE_AN_MODE_CL73:
1821 return (xgbe_phy_an73_outcome(pdata));
1822 case XGBE_AN_MODE_CL73_REDRV:
1823 return (xgbe_phy_an73_redrv_outcome(pdata));
1824 case XGBE_AN_MODE_CL37:
1825 return (xgbe_phy_an37_outcome(pdata));
1826 case XGBE_AN_MODE_CL37_SGMII:
1827 return (xgbe_phy_an37_sgmii_outcome(pdata));
1829 return (XGBE_MODE_UNKNOWN);
1834 xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, struct xgbe_phy *dphy)
1836 struct xgbe_phy_data *phy_data = pdata->phy_data;
1838 XGBE_LM_COPY(dphy, advertising, &pdata->phy, advertising);
1840 /* Without a re-driver, just return current advertising */
1841 if (!phy_data->redrv)
1844 /* With the KR re-driver we need to advertise a single speed */
1845 XGBE_CLR_ADV(dphy, 1000baseKX_Full);
1846 XGBE_CLR_ADV(dphy, 10000baseKR_Full);
1848 /* Advertise FEC support is present */
1849 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1850 XGBE_SET_ADV(dphy, 10000baseR_FEC);
1852 switch (phy_data->port_mode) {
1853 case XGBE_PORT_MODE_BACKPLANE:
1854 XGBE_SET_ADV(dphy, 10000baseKR_Full);
1856 case XGBE_PORT_MODE_BACKPLANE_2500:
1857 XGBE_SET_ADV(dphy, 1000baseKX_Full);
1859 case XGBE_PORT_MODE_1000BASE_T:
1860 case XGBE_PORT_MODE_1000BASE_X:
1861 case XGBE_PORT_MODE_NBASE_T:
1862 XGBE_SET_ADV(dphy, 1000baseKX_Full);
1864 case XGBE_PORT_MODE_10GBASE_T:
1865 if ((phy_data->phydev) &&
1866 (pdata->phy.speed == SPEED_10000))
1867 XGBE_SET_ADV(dphy, 10000baseKR_Full);
1869 XGBE_SET_ADV(dphy, 1000baseKX_Full);
1871 case XGBE_PORT_MODE_10GBASE_R:
1872 XGBE_SET_ADV(dphy, 10000baseKR_Full);
1874 case XGBE_PORT_MODE_SFP:
1875 switch (phy_data->sfp_base) {
1876 case XGBE_SFP_BASE_1000_T:
1877 case XGBE_SFP_BASE_1000_SX:
1878 case XGBE_SFP_BASE_1000_LX:
1879 case XGBE_SFP_BASE_1000_CX:
1880 XGBE_SET_ADV(dphy, 1000baseKX_Full);
1883 XGBE_SET_ADV(dphy, 10000baseKR_Full);
1888 XGBE_SET_ADV(dphy, 10000baseKR_Full);
1894 xgbe_phy_an_config(struct xgbe_prv_data *pdata)
1896 struct xgbe_phy_data *phy_data = pdata->phy_data;
1899 ret = xgbe_phy_find_phy_device(pdata);
1903 axgbe_printf(2, "%s: find_phy_device return %s.\n", __func__,
1904 ret ? "Failure" : "Success");
1906 if (!phy_data->phydev)
1909 ret = xgbe_phy_start_aneg(pdata);
1913 static enum xgbe_an_mode
1914 xgbe_phy_an_sfp_mode(struct xgbe_phy_data *phy_data)
1916 switch (phy_data->sfp_base) {
1917 case XGBE_SFP_BASE_1000_T:
1918 return (XGBE_AN_MODE_CL37_SGMII);
1919 case XGBE_SFP_BASE_1000_SX:
1920 case XGBE_SFP_BASE_1000_LX:
1921 case XGBE_SFP_BASE_1000_CX:
1922 return (XGBE_AN_MODE_CL37);
1924 return (XGBE_AN_MODE_NONE);
1928 static enum xgbe_an_mode
1929 xgbe_phy_an_mode(struct xgbe_prv_data *pdata)
1931 struct xgbe_phy_data *phy_data = pdata->phy_data;
1933 /* A KR re-driver will always require CL73 AN */
1934 if (phy_data->redrv)
1935 return (XGBE_AN_MODE_CL73_REDRV);
1937 switch (phy_data->port_mode) {
1938 case XGBE_PORT_MODE_BACKPLANE:
1939 return (XGBE_AN_MODE_CL73);
1940 case XGBE_PORT_MODE_BACKPLANE_2500:
1941 return (XGBE_AN_MODE_NONE);
1942 case XGBE_PORT_MODE_1000BASE_T:
1943 return (XGBE_AN_MODE_CL37_SGMII);
1944 case XGBE_PORT_MODE_1000BASE_X:
1945 return (XGBE_AN_MODE_CL37);
1946 case XGBE_PORT_MODE_NBASE_T:
1947 return (XGBE_AN_MODE_CL37_SGMII);
1948 case XGBE_PORT_MODE_10GBASE_T:
1949 return (XGBE_AN_MODE_CL73);
1950 case XGBE_PORT_MODE_10GBASE_R:
1951 return (XGBE_AN_MODE_NONE);
1952 case XGBE_PORT_MODE_SFP:
1953 return (xgbe_phy_an_sfp_mode(phy_data));
1955 return (XGBE_AN_MODE_NONE);
1960 xgbe_phy_set_redrv_mode_mdio(struct xgbe_prv_data *pdata,
1961 enum xgbe_phy_redrv_mode mode)
1963 struct xgbe_phy_data *phy_data = pdata->phy_data;
1964 uint16_t redrv_reg, redrv_val;
1966 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1967 redrv_val = (uint16_t)mode;
1969 return (pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr,
1970 redrv_reg, redrv_val));
1974 xgbe_phy_set_redrv_mode_i2c(struct xgbe_prv_data *pdata,
1975 enum xgbe_phy_redrv_mode mode)
1977 struct xgbe_phy_data *phy_data = pdata->phy_data;
1978 unsigned int redrv_reg;
1981 /* Calculate the register to write */
1982 redrv_reg = XGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000);
1984 ret = xgbe_phy_redrv_write(pdata, redrv_reg, mode);
1990 xgbe_phy_set_redrv_mode(struct xgbe_prv_data *pdata)
1992 struct xgbe_phy_data *phy_data = pdata->phy_data;
1993 enum xgbe_phy_redrv_mode mode;
1996 if (!phy_data->redrv)
1999 mode = XGBE_PHY_REDRV_MODE_CX;
2000 if ((phy_data->port_mode == XGBE_PORT_MODE_SFP) &&
2001 (phy_data->sfp_base != XGBE_SFP_BASE_1000_CX) &&
2002 (phy_data->sfp_base != XGBE_SFP_BASE_10000_CR))
2003 mode = XGBE_PHY_REDRV_MODE_SR;
2005 ret = xgbe_phy_get_comm_ownership(pdata);
2009 axgbe_printf(2, "%s: redrv_if set: %d\n", __func__, phy_data->redrv_if);
2010 if (phy_data->redrv_if)
2011 xgbe_phy_set_redrv_mode_i2c(pdata, mode);
2013 xgbe_phy_set_redrv_mode_mdio(pdata, mode);
2015 xgbe_phy_put_comm_ownership(pdata);
2019 xgbe_phy_perform_ratechange(struct xgbe_prv_data *pdata, unsigned int cmd,
2020 unsigned int sub_cmd)
2022 unsigned int s0 = 0;
2025 /* Log if a previous command did not complete */
2026 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS))
2027 axgbe_error("firmware mailbox not ready for command\n");
2029 /* Construct the command */
2030 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd);
2031 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd);
2033 /* Issue the command */
2034 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0);
2035 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0);
2036 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1);
2038 /* Wait for command to complete */
2039 wait = XGBE_RATECHANGE_COUNT;
2041 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) {
2042 axgbe_printf(3, "%s: Rate change done\n", __func__);
2049 axgbe_printf(3, "firmware mailbox command did not complete\n");
2053 xgbe_phy_rrc(struct xgbe_prv_data *pdata)
2055 /* Receiver Reset Cycle */
2056 xgbe_phy_perform_ratechange(pdata, 5, 0);
2058 axgbe_printf(3, "receiver reset complete\n");
2062 xgbe_phy_power_off(struct xgbe_prv_data *pdata)
2064 struct xgbe_phy_data *phy_data = pdata->phy_data;
2067 xgbe_phy_perform_ratechange(pdata, 0, 0);
2069 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
2071 axgbe_printf(3, "phy powered off\n");
2075 xgbe_phy_sfi_mode(struct xgbe_prv_data *pdata)
2077 struct xgbe_phy_data *phy_data = pdata->phy_data;
2079 xgbe_phy_set_redrv_mode(pdata);
2082 axgbe_printf(3, "%s: cable %d len %d\n", __func__, phy_data->sfp_cable,
2083 phy_data->sfp_cable_len);
2085 if (phy_data->sfp_cable != XGBE_SFP_CABLE_PASSIVE)
2086 xgbe_phy_perform_ratechange(pdata, 3, 0);
2088 if (phy_data->sfp_cable_len <= 1)
2089 xgbe_phy_perform_ratechange(pdata, 3, 1);
2090 else if (phy_data->sfp_cable_len <= 3)
2091 xgbe_phy_perform_ratechange(pdata, 3, 2);
2093 xgbe_phy_perform_ratechange(pdata, 3, 3);
2096 phy_data->cur_mode = XGBE_MODE_SFI;
2098 axgbe_printf(3, "10GbE SFI mode set\n");
2102 xgbe_phy_x_mode(struct xgbe_prv_data *pdata)
2104 struct xgbe_phy_data *phy_data = pdata->phy_data;
2106 xgbe_phy_set_redrv_mode(pdata);
2109 xgbe_phy_perform_ratechange(pdata, 1, 3);
2111 phy_data->cur_mode = XGBE_MODE_X;
2113 axgbe_printf(3, "1GbE X mode set\n");
2117 xgbe_phy_sgmii_1000_mode(struct xgbe_prv_data *pdata)
2119 struct xgbe_phy_data *phy_data = pdata->phy_data;
2121 xgbe_phy_set_redrv_mode(pdata);
2124 xgbe_phy_perform_ratechange(pdata, 1, 2);
2126 phy_data->cur_mode = XGBE_MODE_SGMII_1000;
2128 axgbe_printf(2, "1GbE SGMII mode set\n");
2132 xgbe_phy_sgmii_100_mode(struct xgbe_prv_data *pdata)
2134 struct xgbe_phy_data *phy_data = pdata->phy_data;
2136 xgbe_phy_set_redrv_mode(pdata);
2139 xgbe_phy_perform_ratechange(pdata, 1, 1);
2141 phy_data->cur_mode = XGBE_MODE_SGMII_100;
2143 axgbe_printf(3, "100MbE SGMII mode set\n");
2147 xgbe_phy_kr_mode(struct xgbe_prv_data *pdata)
2149 struct xgbe_phy_data *phy_data = pdata->phy_data;
2151 xgbe_phy_set_redrv_mode(pdata);
2154 xgbe_phy_perform_ratechange(pdata, 4, 0);
2156 phy_data->cur_mode = XGBE_MODE_KR;
2158 axgbe_printf(3, "10GbE KR mode set\n");
2162 xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata)
2164 struct xgbe_phy_data *phy_data = pdata->phy_data;
2166 xgbe_phy_set_redrv_mode(pdata);
2169 xgbe_phy_perform_ratechange(pdata, 2, 0);
2171 phy_data->cur_mode = XGBE_MODE_KX_2500;
2173 axgbe_printf(3, "2.5GbE KX mode set\n");
2177 xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata)
2179 struct xgbe_phy_data *phy_data = pdata->phy_data;
2181 xgbe_phy_set_redrv_mode(pdata);
2184 xgbe_phy_perform_ratechange(pdata, 1, 3);
2186 phy_data->cur_mode = XGBE_MODE_KX_1000;
2188 axgbe_printf(3, "1GbE KX mode set\n");
2191 static enum xgbe_mode
2192 xgbe_phy_cur_mode(struct xgbe_prv_data *pdata)
2194 struct xgbe_phy_data *phy_data = pdata->phy_data;
2196 return (phy_data->cur_mode);
2199 static enum xgbe_mode
2200 xgbe_phy_switch_baset_mode(struct xgbe_prv_data *pdata)
2202 struct xgbe_phy_data *phy_data = pdata->phy_data;
2204 /* No switching if not 10GBase-T */
2205 if (phy_data->port_mode != XGBE_PORT_MODE_10GBASE_T)
2206 return (xgbe_phy_cur_mode(pdata));
2208 switch (xgbe_phy_cur_mode(pdata)) {
2209 case XGBE_MODE_SGMII_100:
2210 case XGBE_MODE_SGMII_1000:
2211 return (XGBE_MODE_KR);
2214 return (XGBE_MODE_SGMII_1000);
2218 static enum xgbe_mode
2219 xgbe_phy_switch_bp_2500_mode(struct xgbe_prv_data *pdata)
2221 return (XGBE_MODE_KX_2500);
2224 static enum xgbe_mode
2225 xgbe_phy_switch_bp_mode(struct xgbe_prv_data *pdata)
2227 /* If we are in KR switch to KX, and vice-versa */
2228 switch (xgbe_phy_cur_mode(pdata)) {
2229 case XGBE_MODE_KX_1000:
2230 return (XGBE_MODE_KR);
2233 return (XGBE_MODE_KX_1000);
2237 static enum xgbe_mode
2238 xgbe_phy_switch_mode(struct xgbe_prv_data *pdata)
2240 struct xgbe_phy_data *phy_data = pdata->phy_data;
2242 switch (phy_data->port_mode) {
2243 case XGBE_PORT_MODE_BACKPLANE:
2244 return (xgbe_phy_switch_bp_mode(pdata));
2245 case XGBE_PORT_MODE_BACKPLANE_2500:
2246 return (xgbe_phy_switch_bp_2500_mode(pdata));
2247 case XGBE_PORT_MODE_1000BASE_T:
2248 case XGBE_PORT_MODE_NBASE_T:
2249 case XGBE_PORT_MODE_10GBASE_T:
2250 return (xgbe_phy_switch_baset_mode(pdata));
2251 case XGBE_PORT_MODE_1000BASE_X:
2252 case XGBE_PORT_MODE_10GBASE_R:
2253 case XGBE_PORT_MODE_SFP:
2254 /* No switching, so just return current mode */
2255 return (xgbe_phy_cur_mode(pdata));
2257 return (XGBE_MODE_UNKNOWN);
2261 static enum xgbe_mode
2262 xgbe_phy_get_basex_mode(struct xgbe_phy_data *phy_data, int speed)
2266 return (XGBE_MODE_X);
2268 return (XGBE_MODE_KR);
2270 return (XGBE_MODE_UNKNOWN);
2274 static enum xgbe_mode
2275 xgbe_phy_get_baset_mode(struct xgbe_phy_data *phy_data, int speed)
2279 return (XGBE_MODE_SGMII_100);
2281 return (XGBE_MODE_SGMII_1000);
2283 return (XGBE_MODE_KX_2500);
2285 return (XGBE_MODE_KR);
2287 return (XGBE_MODE_UNKNOWN);
2291 static enum xgbe_mode
2292 xgbe_phy_get_sfp_mode(struct xgbe_phy_data *phy_data, int speed)
2296 return (XGBE_MODE_SGMII_100);
2298 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2299 return (XGBE_MODE_SGMII_1000);
2301 return (XGBE_MODE_X);
2304 return (XGBE_MODE_SFI);
2306 return (XGBE_MODE_UNKNOWN);
2310 static enum xgbe_mode
2311 xgbe_phy_get_bp_2500_mode(int speed)
2315 return (XGBE_MODE_KX_2500);
2317 return (XGBE_MODE_UNKNOWN);
2321 static enum xgbe_mode
2322 xgbe_phy_get_bp_mode(int speed)
2326 return (XGBE_MODE_KX_1000);
2328 return (XGBE_MODE_KR);
2330 return (XGBE_MODE_UNKNOWN);
2334 static enum xgbe_mode
2335 xgbe_phy_get_mode(struct xgbe_prv_data *pdata, int speed)
2337 struct xgbe_phy_data *phy_data = pdata->phy_data;
2339 switch (phy_data->port_mode) {
2340 case XGBE_PORT_MODE_BACKPLANE:
2341 return (xgbe_phy_get_bp_mode(speed));
2342 case XGBE_PORT_MODE_BACKPLANE_2500:
2343 return (xgbe_phy_get_bp_2500_mode(speed));
2344 case XGBE_PORT_MODE_1000BASE_T:
2345 case XGBE_PORT_MODE_NBASE_T:
2346 case XGBE_PORT_MODE_10GBASE_T:
2347 return (xgbe_phy_get_baset_mode(phy_data, speed));
2348 case XGBE_PORT_MODE_1000BASE_X:
2349 case XGBE_PORT_MODE_10GBASE_R:
2350 return (xgbe_phy_get_basex_mode(phy_data, speed));
2351 case XGBE_PORT_MODE_SFP:
2352 return (xgbe_phy_get_sfp_mode(phy_data, speed));
2354 return (XGBE_MODE_UNKNOWN);
2359 xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2362 case XGBE_MODE_KX_1000:
2363 xgbe_phy_kx_1000_mode(pdata);
2365 case XGBE_MODE_KX_2500:
2366 xgbe_phy_kx_2500_mode(pdata);
2369 xgbe_phy_kr_mode(pdata);
2371 case XGBE_MODE_SGMII_100:
2372 xgbe_phy_sgmii_100_mode(pdata);
2374 case XGBE_MODE_SGMII_1000:
2375 xgbe_phy_sgmii_1000_mode(pdata);
2378 xgbe_phy_x_mode(pdata);
2381 xgbe_phy_sfi_mode(pdata);
2389 xgbe_phy_get_type(struct xgbe_prv_data *pdata, struct ifmediareq * ifmr)
2391 struct xgbe_phy_data *phy_data = pdata->phy_data;
2393 switch (pdata->phy.speed) {
2395 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE)
2396 ifmr->ifm_active |= IFM_10G_KR;
2397 else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T)
2398 ifmr->ifm_active |= IFM_10G_T;
2399 else if(phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R)
2400 ifmr->ifm_active |= IFM_10G_KR;
2401 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
2402 ifmr->ifm_active |= IFM_10G_SFI;
2404 ifmr->ifm_active |= IFM_OTHER;
2407 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE_2500)
2408 ifmr->ifm_active |= IFM_2500_KX;
2410 ifmr->ifm_active |= IFM_OTHER;
2413 if (phy_data->port_mode == XGBE_PORT_MODE_BACKPLANE)
2414 ifmr->ifm_active |= IFM_1000_KX;
2415 else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_T)
2416 ifmr->ifm_active |= IFM_1000_T;
2418 else if(phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X)
2419 ifmr->ifm_active |= IFM_1000_SX;
2420 ifmr->ifm_active |= IFM_1000_LX;
2421 ifmr->ifm_active |= IFM_1000_CX;
2423 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
2424 ifmr->ifm_active |= IFM_1000_SGMII;
2426 ifmr->ifm_active |= IFM_OTHER;
2429 if(phy_data->port_mode == XGBE_PORT_MODE_NBASE_T)
2430 ifmr->ifm_active |= IFM_100_T;
2431 else if(phy_data->port_mode == XGBE_PORT_MODE_SFP)
2432 ifmr->ifm_active |= IFM_1000_SGMII;
2434 ifmr->ifm_active |= IFM_OTHER;
2437 ifmr->ifm_active |= IFM_OTHER;
2438 axgbe_printf(1, "Unknown mode detected\n");
2444 xgbe_phy_check_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode,
2448 if (pdata->phy.autoneg == AUTONEG_ENABLE)
2451 enum xgbe_mode cur_mode;
2453 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed);
2454 if (cur_mode == mode)
2462 xgbe_phy_use_basex_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2467 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2470 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2471 10000baseKR_Full)));
2478 xgbe_phy_use_baset_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2481 axgbe_printf(3, "%s: check mode %d\n", __func__, mode);
2483 case XGBE_MODE_SGMII_100:
2484 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2486 case XGBE_MODE_SGMII_1000:
2487 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2489 case XGBE_MODE_KX_2500:
2490 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2493 return (xgbe_phy_check_mode(pdata, mode, XGBE_ADV(&pdata->phy,
2501 xgbe_phy_use_sfp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2503 struct xgbe_phy_data *phy_data = pdata->phy_data;
2507 if (phy_data->sfp_base == XGBE_SFP_BASE_1000_T)
2509 return (xgbe_phy_check_mode(pdata, mode,
2510 XGBE_ADV(&pdata->phy, 1000baseX_Full)));
2511 case XGBE_MODE_SGMII_100:
2512 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2514 return (xgbe_phy_check_mode(pdata, mode,
2515 XGBE_ADV(&pdata->phy, 100baseT_Full)));
2516 case XGBE_MODE_SGMII_1000:
2517 if (phy_data->sfp_base != XGBE_SFP_BASE_1000_T)
2519 return (xgbe_phy_check_mode(pdata, mode,
2520 XGBE_ADV(&pdata->phy, 1000baseT_Full)));
2522 if (phy_data->sfp_mod_absent)
2524 return (xgbe_phy_check_mode(pdata, mode,
2525 XGBE_ADV(&pdata->phy, 10000baseSR_Full) ||
2526 XGBE_ADV(&pdata->phy, 10000baseLR_Full) ||
2527 XGBE_ADV(&pdata->phy, 10000baseLRM_Full) ||
2528 XGBE_ADV(&pdata->phy, 10000baseER_Full) ||
2529 XGBE_ADV(&pdata->phy, 10000baseCR_Full)));
2536 xgbe_phy_use_bp_2500_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2540 case XGBE_MODE_KX_2500:
2541 return (xgbe_phy_check_mode(pdata, mode,
2542 XGBE_ADV(&pdata->phy, 2500baseX_Full)));
2549 xgbe_phy_use_bp_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2553 case XGBE_MODE_KX_1000:
2554 return (xgbe_phy_check_mode(pdata, mode,
2555 XGBE_ADV(&pdata->phy, 1000baseKX_Full)));
2557 return (xgbe_phy_check_mode(pdata, mode,
2558 XGBE_ADV(&pdata->phy, 10000baseKR_Full)));
2565 xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode)
2567 struct xgbe_phy_data *phy_data = pdata->phy_data;
2569 switch (phy_data->port_mode) {
2570 case XGBE_PORT_MODE_BACKPLANE:
2571 return (xgbe_phy_use_bp_mode(pdata, mode));
2572 case XGBE_PORT_MODE_BACKPLANE_2500:
2573 return (xgbe_phy_use_bp_2500_mode(pdata, mode));
2574 case XGBE_PORT_MODE_1000BASE_T:
2575 axgbe_printf(3, "use_mode %s\n",
2576 xgbe_phy_use_baset_mode(pdata, mode) ? "found" : "Not found");
2577 case XGBE_PORT_MODE_NBASE_T:
2578 case XGBE_PORT_MODE_10GBASE_T:
2579 return (xgbe_phy_use_baset_mode(pdata, mode));
2580 case XGBE_PORT_MODE_1000BASE_X:
2581 case XGBE_PORT_MODE_10GBASE_R:
2582 return (xgbe_phy_use_basex_mode(pdata, mode));
2583 case XGBE_PORT_MODE_SFP:
2584 return (xgbe_phy_use_sfp_mode(pdata, mode));
2591 xgbe_phy_valid_speed_basex_mode(struct xgbe_phy_data *phy_data, int speed)
2596 return (phy_data->port_mode == XGBE_PORT_MODE_1000BASE_X);
2598 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_R);
2605 xgbe_phy_valid_speed_baset_mode(struct xgbe_phy_data *phy_data, int speed)
2613 return (phy_data->port_mode == XGBE_PORT_MODE_NBASE_T);
2615 return (phy_data->port_mode == XGBE_PORT_MODE_10GBASE_T);
2622 xgbe_phy_valid_speed_sfp_mode(struct xgbe_phy_data *phy_data, int speed)
2627 return (phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000);
2629 return ((phy_data->sfp_speed == XGBE_SFP_SPEED_100_1000) ||
2630 (phy_data->sfp_speed == XGBE_SFP_SPEED_1000));
2632 return (phy_data->sfp_speed == XGBE_SFP_SPEED_10000);
2639 xgbe_phy_valid_speed_bp_2500_mode(int speed)
2651 xgbe_phy_valid_speed_bp_mode(int speed)
2664 xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
2666 struct xgbe_phy_data *phy_data = pdata->phy_data;
2668 switch (phy_data->port_mode) {
2669 case XGBE_PORT_MODE_BACKPLANE:
2670 return (xgbe_phy_valid_speed_bp_mode(speed));
2671 case XGBE_PORT_MODE_BACKPLANE_2500:
2672 return (xgbe_phy_valid_speed_bp_2500_mode(speed));
2673 case XGBE_PORT_MODE_1000BASE_T:
2674 case XGBE_PORT_MODE_NBASE_T:
2675 case XGBE_PORT_MODE_10GBASE_T:
2676 return (xgbe_phy_valid_speed_baset_mode(phy_data, speed));
2677 case XGBE_PORT_MODE_1000BASE_X:
2678 case XGBE_PORT_MODE_10GBASE_R:
2679 return (xgbe_phy_valid_speed_basex_mode(phy_data, speed));
2680 case XGBE_PORT_MODE_SFP:
2681 return (xgbe_phy_valid_speed_sfp_mode(phy_data, speed));
2688 xgbe_upd_link(struct xgbe_prv_data *pdata)
2692 axgbe_printf(2, "%s: Link %d\n", __func__, pdata->phy.link);
2693 reg = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);
2697 if ((reg & BMSR_LINK) == 0)
2698 pdata->phy.link = 0;
2700 pdata->phy.link = 1;
2702 axgbe_printf(2, "Link: %d updated reg %#x\n", pdata->phy.link, reg);
2707 xgbe_phy_read_status(struct xgbe_prv_data *pdata)
2715 ret = xgbe_upd_link(pdata);
2717 axgbe_printf(2, "Link Update return %d\n", ret);
2721 if (AUTONEG_ENABLE == pdata->phy.autoneg) {
2722 if (pdata->phy.supported == SUPPORTED_1000baseT_Half ||
2723 pdata->phy.supported == SUPPORTED_1000baseT_Full) {
2724 lpagb = xgbe_phy_mii_read(pdata, pdata->mdio_addr,
2729 adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr,
2734 if (lpagb & GTSR_MAN_MS_FLT) {
2735 if (adv & GTCR_MAN_MS)
2736 axgbe_printf(2, "Master/Slave Resolution "
2737 "failed, maybe conflicting manual settings\n");
2739 axgbe_printf(2, "Master/Slave Resolution failed\n");
2743 if (pdata->phy.supported == SUPPORTED_1000baseT_Half)
2744 XGBE_ADV(&pdata->phy, 1000baseT_Half);
2745 else if (pdata->phy.supported == SUPPORTED_1000baseT_Full)
2746 XGBE_ADV(&pdata->phy, 1000baseT_Full);
2748 common_adv_gb = lpagb & adv << 2;
2751 lpa = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANLPAR);
2755 if (pdata->phy.supported == SUPPORTED_Autoneg)
2756 XGBE_ADV(&pdata->phy, Autoneg);
2758 adv = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_ANAR);
2762 common_adv = lpa & adv;
2764 pdata->phy.speed = SPEED_10;
2765 pdata->phy.duplex = DUPLEX_HALF;
2766 pdata->phy.pause = 0;
2767 pdata->phy.asym_pause = 0;
2769 axgbe_printf(2, "%s: lpa %#x adv %#x common_adv_gb %#x "
2770 "common_adv %#x\n", __func__, lpa, adv, common_adv_gb,
2772 if (common_adv_gb & (GTSR_LP_1000TFDX | GTSR_LP_1000THDX)) {
2773 axgbe_printf(2, "%s: SPEED 1000\n", __func__);
2774 pdata->phy.speed = SPEED_1000;
2776 if (common_adv_gb & GTSR_LP_1000TFDX)
2777 pdata->phy.duplex = DUPLEX_FULL;
2778 } else if (common_adv & (ANLPAR_TX_FD | ANLPAR_TX)) {
2779 axgbe_printf(2, "%s: SPEED 100\n", __func__);
2780 pdata->phy.speed = SPEED_100;
2782 if (common_adv & ANLPAR_TX_FD)
2783 pdata->phy.duplex = DUPLEX_FULL;
2785 if (common_adv & ANLPAR_10_FD)
2786 pdata->phy.duplex = DUPLEX_FULL;
2788 if (pdata->phy.duplex == DUPLEX_FULL) {
2789 pdata->phy.pause = lpa & ANLPAR_FC ? 1 : 0;
2790 pdata->phy.asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
2793 int bmcr = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMCR);
2797 if (bmcr & BMCR_FDX)
2798 pdata->phy.duplex = DUPLEX_FULL;
2800 pdata->phy.duplex = DUPLEX_HALF;
2802 if (bmcr & BMCR_SPEED1)
2803 pdata->phy.speed = SPEED_1000;
2804 else if (bmcr & BMCR_SPEED100)
2805 pdata->phy.speed = SPEED_100;
2807 pdata->phy.speed = SPEED_10;
2809 pdata->phy.pause = 0;
2810 pdata->phy.asym_pause = 0;
2811 axgbe_printf(2, "%s: link speed %#x duplex %#x media %#x "
2812 "autoneg %#x\n", __func__, pdata->phy.speed,
2813 pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg);
2820 xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart)
2822 struct xgbe_phy_data *phy_data = pdata->phy_data;
2823 struct mii_data *mii = NULL;
2829 if (phy_data->port_mode == XGBE_PORT_MODE_SFP) {
2830 /* Check SFP signals */
2831 axgbe_printf(3, "%s: calling phy detect\n", __func__);
2832 xgbe_phy_sfp_detect(pdata);
2834 if (phy_data->sfp_changed) {
2835 axgbe_printf(1, "%s: SFP changed observed\n", __func__);
2840 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) {
2841 axgbe_printf(1, "%s: SFP absent 0x%x & sfp_rx_los 0x%x\n",
2842 __func__, phy_data->sfp_mod_absent,
2843 phy_data->sfp_rx_los);
2847 mii = device_get_softc(pdata->axgbe_miibus);
2850 ret = xgbe_phy_read_status(pdata);
2852 axgbe_printf(2, "Link: Read status returned %d\n", ret);
2856 axgbe_printf(2, "%s: link speed %#x duplex %#x media %#x "
2857 "autoneg %#x\n", __func__, pdata->phy.speed,
2858 pdata->phy.duplex, pdata->phy.link, pdata->phy.autoneg);
2859 ret = xgbe_phy_mii_read(pdata, pdata->mdio_addr, MII_BMSR);
2860 ret = (ret < 0) ? ret : (ret & BMSR_ACOMP);
2861 axgbe_printf(2, "Link: BMCR returned %d\n", ret);
2862 if ((pdata->phy.autoneg == AUTONEG_ENABLE) && !ret)
2865 return (pdata->phy.link);
2868 /* Link status is latched low, so read once to clear
2869 * and then read again to get current state
2871 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2872 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
2873 axgbe_printf(1, "%s: link_status reg: 0x%x\n", __func__, reg);
2874 if (reg & MDIO_STAT1_LSTATUS)
2877 /* No link, attempt a receiver reset cycle */
2878 if (phy_data->rrc_count++ > XGBE_RRC_FREQUENCY) {
2879 axgbe_printf(1, "ENTERED RRC: rrc_count: %d\n",
2880 phy_data->rrc_count);
2881 phy_data->rrc_count = 0;
2882 xgbe_phy_rrc(pdata);
2889 xgbe_phy_sfp_gpio_setup(struct xgbe_prv_data *pdata)
2891 struct xgbe_phy_data *phy_data = pdata->phy_data;
2893 phy_data->sfp_gpio_address = XGBE_GPIO_ADDRESS_PCA9555 +
2894 XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_ADDR);
2895 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2897 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2899 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2901 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2903 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3,
2906 DBGPR("SFP: gpio_address=%#x\n", phy_data->sfp_gpio_address);
2907 DBGPR("SFP: gpio_mask=%#x\n", phy_data->sfp_gpio_mask);
2908 DBGPR("SFP: gpio_rx_los=%u\n", phy_data->sfp_gpio_rx_los);
2909 DBGPR("SFP: gpio_tx_fault=%u\n", phy_data->sfp_gpio_tx_fault);
2910 DBGPR("SFP: gpio_mod_absent=%u\n",
2911 phy_data->sfp_gpio_mod_absent);
2912 DBGPR("SFP: gpio_rate_select=%u\n",
2913 phy_data->sfp_gpio_rate_select);
2917 xgbe_phy_sfp_comm_setup(struct xgbe_prv_data *pdata)
2919 struct xgbe_phy_data *phy_data = pdata->phy_data;
2920 unsigned int mux_addr_hi, mux_addr_lo;
2922 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI);
2923 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO);
2924 if (mux_addr_lo == XGBE_SFP_DIRECT)
2927 phy_data->sfp_comm = XGBE_SFP_COMM_PCA9545;
2928 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo;
2929 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4,
2932 DBGPR("SFP: mux_address=%#x\n", phy_data->sfp_mux_address);
2933 DBGPR("SFP: mux_channel=%u\n", phy_data->sfp_mux_channel);
2937 xgbe_phy_sfp_setup(struct xgbe_prv_data *pdata)
2939 xgbe_phy_sfp_comm_setup(pdata);
2940 xgbe_phy_sfp_gpio_setup(pdata);
2944 xgbe_phy_int_mdio_reset(struct xgbe_prv_data *pdata)
2946 struct xgbe_phy_data *phy_data = pdata->phy_data;
2949 ret = pdata->hw_if.set_gpio(pdata, phy_data->mdio_reset_gpio);
2953 ret = pdata->hw_if.clr_gpio(pdata, phy_data->mdio_reset_gpio);
2959 xgbe_phy_i2c_mdio_reset(struct xgbe_prv_data *pdata)
2961 struct xgbe_phy_data *phy_data = pdata->phy_data;
2962 uint8_t gpio_reg, gpio_ports[2], gpio_data[3];
2965 /* Read the output port registers */
2967 ret = xgbe_phy_i2c_read(pdata, phy_data->mdio_reset_addr,
2968 &gpio_reg, sizeof(gpio_reg),
2969 gpio_ports, sizeof(gpio_ports));
2973 /* Prepare to write the GPIO data */
2975 gpio_data[1] = gpio_ports[0];
2976 gpio_data[2] = gpio_ports[1];
2978 /* Set the GPIO pin */
2979 if (phy_data->mdio_reset_gpio < 8)
2980 gpio_data[1] |= (1 << (phy_data->mdio_reset_gpio % 8));
2982 gpio_data[2] |= (1 << (phy_data->mdio_reset_gpio % 8));
2984 /* Write the output port registers */
2985 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2986 gpio_data, sizeof(gpio_data));
2990 /* Clear the GPIO pin */
2991 if (phy_data->mdio_reset_gpio < 8)
2992 gpio_data[1] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2994 gpio_data[2] &= ~(1 << (phy_data->mdio_reset_gpio % 8));
2996 /* Write the output port registers */
2997 ret = xgbe_phy_i2c_write(pdata, phy_data->mdio_reset_addr,
2998 gpio_data, sizeof(gpio_data));
3004 xgbe_phy_mdio_reset(struct xgbe_prv_data *pdata)
3006 struct xgbe_phy_data *phy_data = pdata->phy_data;
3009 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3012 ret = xgbe_phy_get_comm_ownership(pdata);
3016 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO)
3017 ret = xgbe_phy_i2c_mdio_reset(pdata);
3018 else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
3019 ret = xgbe_phy_int_mdio_reset(pdata);
3021 xgbe_phy_put_comm_ownership(pdata);
3027 xgbe_phy_redrv_error(struct xgbe_phy_data *phy_data)
3029 if (!phy_data->redrv)
3032 if (phy_data->redrv_if >= XGBE_PHY_REDRV_IF_MAX)
3035 switch (phy_data->redrv_model) {
3036 case XGBE_PHY_REDRV_MODEL_4223:
3037 if (phy_data->redrv_lane > 3)
3040 case XGBE_PHY_REDRV_MODEL_4227:
3041 if (phy_data->redrv_lane > 1)
3052 xgbe_phy_mdio_reset_setup(struct xgbe_prv_data *pdata)
3054 struct xgbe_phy_data *phy_data = pdata->phy_data;
3056 if (phy_data->conn_type != XGBE_CONN_TYPE_MDIO)
3059 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET);
3060 switch (phy_data->mdio_reset) {
3061 case XGBE_MDIO_RESET_NONE:
3062 case XGBE_MDIO_RESET_I2C_GPIO:
3063 case XGBE_MDIO_RESET_INT_GPIO:
3066 axgbe_error("unsupported MDIO reset (%#x)\n",
3067 phy_data->mdio_reset);
3071 if (phy_data->mdio_reset == XGBE_MDIO_RESET_I2C_GPIO) {
3072 phy_data->mdio_reset_addr = XGBE_GPIO_ADDRESS_PCA9555 +
3073 XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET_I2C_ADDR);
3074 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3075 MDIO_RESET_I2C_GPIO);
3076 } else if (phy_data->mdio_reset == XGBE_MDIO_RESET_INT_GPIO)
3077 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3,
3078 MDIO_RESET_INT_GPIO);
3084 xgbe_phy_port_mode_mismatch(struct xgbe_prv_data *pdata)
3086 struct xgbe_phy_data *phy_data = pdata->phy_data;
3088 switch (phy_data->port_mode) {
3089 case XGBE_PORT_MODE_BACKPLANE:
3090 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3091 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3094 case XGBE_PORT_MODE_BACKPLANE_2500:
3095 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500)
3098 case XGBE_PORT_MODE_1000BASE_T:
3099 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3100 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000))
3103 case XGBE_PORT_MODE_1000BASE_X:
3104 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3107 case XGBE_PORT_MODE_NBASE_T:
3108 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3109 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3110 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500))
3113 case XGBE_PORT_MODE_10GBASE_T:
3114 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3115 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3116 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3119 case XGBE_PORT_MODE_10GBASE_R:
3120 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3123 case XGBE_PORT_MODE_SFP:
3124 if ((phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) ||
3125 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) ||
3126 (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000))
3137 xgbe_phy_conn_type_mismatch(struct xgbe_prv_data *pdata)
3139 struct xgbe_phy_data *phy_data = pdata->phy_data;
3141 switch (phy_data->port_mode) {
3142 case XGBE_PORT_MODE_BACKPLANE:
3143 case XGBE_PORT_MODE_BACKPLANE_2500:
3144 if (phy_data->conn_type == XGBE_CONN_TYPE_BACKPLANE)
3147 case XGBE_PORT_MODE_1000BASE_T:
3148 case XGBE_PORT_MODE_1000BASE_X:
3149 case XGBE_PORT_MODE_NBASE_T:
3150 case XGBE_PORT_MODE_10GBASE_T:
3151 case XGBE_PORT_MODE_10GBASE_R:
3152 if (phy_data->conn_type == XGBE_CONN_TYPE_MDIO)
3155 case XGBE_PORT_MODE_SFP:
3156 if (phy_data->conn_type == XGBE_CONN_TYPE_SFP)
3167 xgbe_phy_port_enabled(struct xgbe_prv_data *pdata)
3170 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS))
3172 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE))
3179 xgbe_phy_cdr_track(struct xgbe_prv_data *pdata)
3181 struct xgbe_phy_data *phy_data = pdata->phy_data;
3183 axgbe_printf(2, "%s: an_cdr_workaround %d phy_cdr_notrack %d\n",
3184 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack);
3186 if (!pdata->sysctl_an_cdr_workaround)
3189 if (!phy_data->phy_cdr_notrack)
3192 DELAY(phy_data->phy_cdr_delay + 500);
3194 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3195 XGBE_PMA_CDR_TRACK_EN_MASK, XGBE_PMA_CDR_TRACK_EN_ON);
3197 phy_data->phy_cdr_notrack = 0;
3199 axgbe_printf(2, "CDR TRACK DONE\n");
3203 xgbe_phy_cdr_notrack(struct xgbe_prv_data *pdata)
3205 struct xgbe_phy_data *phy_data = pdata->phy_data;
3207 axgbe_printf(2, "%s: an_cdr_workaround %d phy_cdr_notrack %d\n",
3208 __func__, pdata->sysctl_an_cdr_workaround, phy_data->phy_cdr_notrack);
3210 if (!pdata->sysctl_an_cdr_workaround)
3213 if (phy_data->phy_cdr_notrack)
3216 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL,
3217 XGBE_PMA_CDR_TRACK_EN_MASK, XGBE_PMA_CDR_TRACK_EN_OFF);
3219 xgbe_phy_rrc(pdata);
3221 phy_data->phy_cdr_notrack = 1;
3225 xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata)
3227 if (!pdata->sysctl_an_cdr_track_early)
3228 xgbe_phy_cdr_track(pdata);
3232 xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata)
3234 if (pdata->sysctl_an_cdr_track_early)
3235 xgbe_phy_cdr_track(pdata);
3239 xgbe_phy_an_post(struct xgbe_prv_data *pdata)
3241 struct xgbe_phy_data *phy_data = pdata->phy_data;
3243 switch (pdata->an_mode) {
3244 case XGBE_AN_MODE_CL73:
3245 case XGBE_AN_MODE_CL73_REDRV:
3246 if (phy_data->cur_mode != XGBE_MODE_KR)
3249 xgbe_phy_cdr_track(pdata);
3251 switch (pdata->an_result) {
3253 case XGBE_AN_COMPLETE:
3256 if (phy_data->phy_cdr_delay < XGBE_CDR_DELAY_MAX)
3257 phy_data->phy_cdr_delay += XGBE_CDR_DELAY_INC;
3259 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3269 xgbe_phy_an_pre(struct xgbe_prv_data *pdata)
3271 struct xgbe_phy_data *phy_data = pdata->phy_data;
3273 switch (pdata->an_mode) {
3274 case XGBE_AN_MODE_CL73:
3275 case XGBE_AN_MODE_CL73_REDRV:
3276 if (phy_data->cur_mode != XGBE_MODE_KR)
3279 xgbe_phy_cdr_notrack(pdata);
3287 xgbe_phy_stop(struct xgbe_prv_data *pdata)
3289 struct xgbe_phy_data *phy_data = pdata->phy_data;
3291 /* If we have an external PHY, free it */
3292 xgbe_phy_free_phy_device(pdata);
3294 /* Reset SFP data */
3295 xgbe_phy_sfp_reset(phy_data);
3296 xgbe_phy_sfp_mod_absent(pdata);
3298 /* Reset CDR support */
3299 xgbe_phy_cdr_track(pdata);
3301 /* Power off the PHY */
3302 xgbe_phy_power_off(pdata);
3304 /* Stop the I2C controller */
3305 pdata->i2c_if.i2c_stop(pdata);
3309 xgbe_phy_start(struct xgbe_prv_data *pdata)
3311 struct xgbe_phy_data *phy_data = pdata->phy_data;
3314 axgbe_printf(2, "%s: redrv %d redrv_if %d start_mode %d\n", __func__,
3315 phy_data->redrv, phy_data->redrv_if, phy_data->start_mode);
3317 /* Start the I2C controller */
3318 ret = pdata->i2c_if.i2c_start(pdata);
3320 axgbe_error("%s: impl i2c start ret %d\n", __func__, ret);
3324 /* Set the proper MDIO mode for the re-driver */
3325 if (phy_data->redrv && !phy_data->redrv_if) {
3326 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3327 XGBE_MDIO_MODE_CL22);
3329 axgbe_error("redriver mdio port not compatible (%u)\n",
3330 phy_data->redrv_addr);
3335 /* Start in highest supported mode */
3336 xgbe_phy_set_mode(pdata, phy_data->start_mode);
3338 /* Reset CDR support */
3339 xgbe_phy_cdr_track(pdata);
3341 /* After starting the I2C controller, we can check for an SFP */
3342 switch (phy_data->port_mode) {
3343 case XGBE_PORT_MODE_SFP:
3344 axgbe_printf(3, "%s: calling phy detect\n", __func__);
3345 xgbe_phy_sfp_detect(pdata);
3351 /* If we have an external PHY, start it */
3352 ret = xgbe_phy_find_phy_device(pdata);
3354 axgbe_error("%s: impl find phy dev ret %d\n", __func__, ret);
3358 axgbe_printf(3, "%s: impl return success\n", __func__);
3362 pdata->i2c_if.i2c_stop(pdata);
3368 xgbe_phy_reset(struct xgbe_prv_data *pdata)
3370 struct xgbe_phy_data *phy_data = pdata->phy_data;
3371 enum xgbe_mode cur_mode;
3374 /* Reset by power cycling the PHY */
3375 cur_mode = phy_data->cur_mode;
3376 xgbe_phy_power_off(pdata);
3377 xgbe_phy_set_mode(pdata, cur_mode);
3379 axgbe_printf(3, "%s: mode %d\n", __func__, cur_mode);
3380 if (!phy_data->phydev) {
3381 axgbe_printf(1, "%s: no phydev\n", __func__);
3385 /* Reset the external PHY */
3386 ret = xgbe_phy_mdio_reset(pdata);
3388 axgbe_error("%s: mdio reset %d\n", __func__, ret);
3392 axgbe_printf(3, "%s: return success\n", __func__);
3398 axgbe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
3400 struct axgbe_if_softc *sc;
3401 struct xgbe_prv_data *pdata;
3402 struct mii_data *mii;
3407 axgbe_printf(2, "%s: Invoked\n", __func__);
3408 mtx_lock_spin(&pdata->mdio_mutex);
3409 mii = device_get_softc(pdata->axgbe_miibus);
3410 axgbe_printf(2, "%s: media_active %#x media_status %#x\n", __func__,
3411 mii->mii_media_active, mii->mii_media_status);
3413 ifmr->ifm_active = mii->mii_media_active;
3414 ifmr->ifm_status = mii->mii_media_status;
3415 mtx_unlock_spin(&pdata->mdio_mutex);
3419 axgbe_ifmedia_upd(struct ifnet *ifp)
3421 struct xgbe_prv_data *pdata;
3422 struct axgbe_if_softc *sc;
3423 struct mii_data *mii;
3424 struct mii_softc *miisc;
3430 axgbe_printf(2, "%s: Invoked\n", __func__);
3431 mtx_lock_spin(&pdata->mdio_mutex);
3432 mii = device_get_softc(pdata->axgbe_miibus);
3433 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
3435 ret = mii_mediachg(mii);
3436 mtx_unlock_spin(&pdata->mdio_mutex);
3442 xgbe_phy_exit(struct xgbe_prv_data *pdata)
3444 if (pdata->axgbe_miibus != NULL)
3445 device_delete_child(pdata->dev, pdata->axgbe_miibus);
3447 /* free phy_data structure */
3448 free(pdata->phy_data, M_AXGBE);
3452 xgbe_phy_init(struct xgbe_prv_data *pdata)
3454 struct xgbe_phy_data *phy_data;
3457 /* Initialize the global lock */
3458 if (!mtx_initialized(&xgbe_phy_comm_lock))
3459 mtx_init(&xgbe_phy_comm_lock, "xgbe phy common lock", NULL, MTX_DEF);
3461 /* Check if enabled */
3462 if (!xgbe_phy_port_enabled(pdata)) {
3463 axgbe_error("device is not enabled\n");
3467 /* Initialize the I2C controller */
3468 ret = pdata->i2c_if.i2c_init(pdata);
3472 phy_data = malloc(sizeof(*phy_data), M_AXGBE, M_WAITOK | M_ZERO);
3475 pdata->phy_data = phy_data;
3477 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE);
3478 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID);
3479 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS);
3480 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE);
3481 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR);
3483 pdata->mdio_addr = phy_data->mdio_addr;
3484 DBGPR("port mode=%u\n", phy_data->port_mode);
3485 DBGPR("port id=%u\n", phy_data->port_id);
3486 DBGPR("port speeds=%#x\n", phy_data->port_speeds);
3487 DBGPR("conn type=%u\n", phy_data->conn_type);
3488 DBGPR("mdio addr=%u\n", phy_data->mdio_addr);
3490 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT);
3491 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF);
3492 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR);
3493 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE);
3494 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL);
3496 if (phy_data->redrv) {
3497 DBGPR("redrv present\n");
3498 DBGPR("redrv i/f=%u\n", phy_data->redrv_if);
3499 DBGPR("redrv addr=%#x\n", phy_data->redrv_addr);
3500 DBGPR("redrv lane=%u\n", phy_data->redrv_lane);
3501 DBGPR("redrv model=%u\n", phy_data->redrv_model);
3504 DBGPR("%s: redrv addr=%#x redrv i/f=%u\n", __func__,
3505 phy_data->redrv_addr, phy_data->redrv_if);
3506 /* Validate the connection requested */
3507 if (xgbe_phy_conn_type_mismatch(pdata)) {
3508 axgbe_error("phy mode/connection mismatch "
3509 "(%#x/%#x)\n", phy_data->port_mode, phy_data->conn_type);
3513 /* Validate the mode requested */
3514 if (xgbe_phy_port_mode_mismatch(pdata)) {
3515 axgbe_error("phy mode/speed mismatch "
3516 "(%#x/%#x)\n", phy_data->port_mode, phy_data->port_speeds);
3520 /* Check for and validate MDIO reset support */
3521 ret = xgbe_phy_mdio_reset_setup(pdata);
3523 axgbe_error("%s, mdio_reset_setup ret %d\n", __func__, ret);
3527 /* Validate the re-driver information */
3528 if (xgbe_phy_redrv_error(phy_data)) {
3529 axgbe_error("phy re-driver settings error\n");
3532 pdata->kr_redrv = phy_data->redrv;
3534 /* Indicate current mode is unknown */
3535 phy_data->cur_mode = XGBE_MODE_UNKNOWN;
3537 /* Initialize supported features. Current code does not support ethtool */
3538 XGBE_ZERO_SUP(&pdata->phy);
3540 DBGPR("%s: port mode %d\n", __func__, phy_data->port_mode);
3541 switch (phy_data->port_mode) {
3542 /* Backplane support */
3543 case XGBE_PORT_MODE_BACKPLANE:
3544 XGBE_SET_SUP(&pdata->phy, Autoneg);
3545 XGBE_SET_SUP(&pdata->phy, Pause);
3546 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3547 XGBE_SET_SUP(&pdata->phy, Backplane);
3548 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3549 XGBE_SET_SUP(&pdata->phy, 1000baseKX_Full);
3550 phy_data->start_mode = XGBE_MODE_KX_1000;
3552 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3553 XGBE_SET_SUP(&pdata->phy, 10000baseKR_Full);
3554 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3555 XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);
3556 phy_data->start_mode = XGBE_MODE_KR;
3559 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3561 case XGBE_PORT_MODE_BACKPLANE_2500:
3562 XGBE_SET_SUP(&pdata->phy, Pause);
3563 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3564 XGBE_SET_SUP(&pdata->phy, Backplane);
3565 XGBE_SET_SUP(&pdata->phy, 2500baseX_Full);
3566 phy_data->start_mode = XGBE_MODE_KX_2500;
3568 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3571 /* MDIO 1GBase-T support */
3572 case XGBE_PORT_MODE_1000BASE_T:
3573 XGBE_SET_SUP(&pdata->phy, Autoneg);
3574 XGBE_SET_SUP(&pdata->phy, Pause);
3575 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3576 XGBE_SET_SUP(&pdata->phy, TP);
3577 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3578 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
3579 phy_data->start_mode = XGBE_MODE_SGMII_100;
3581 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3582 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
3583 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3586 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3589 /* MDIO Base-X support */
3590 case XGBE_PORT_MODE_1000BASE_X:
3591 XGBE_SET_SUP(&pdata->phy, Autoneg);
3592 XGBE_SET_SUP(&pdata->phy, Pause);
3593 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3594 XGBE_SET_SUP(&pdata->phy, FIBRE);
3595 XGBE_SET_SUP(&pdata->phy, 1000baseX_Full);
3596 phy_data->start_mode = XGBE_MODE_X;
3598 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3601 /* MDIO NBase-T support */
3602 case XGBE_PORT_MODE_NBASE_T:
3603 XGBE_SET_SUP(&pdata->phy, Autoneg);
3604 XGBE_SET_SUP(&pdata->phy, Pause);
3605 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3606 XGBE_SET_SUP(&pdata->phy, TP);
3607 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3608 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
3609 phy_data->start_mode = XGBE_MODE_SGMII_100;
3611 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3612 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
3613 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3615 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_2500) {
3616 XGBE_SET_SUP(&pdata->phy, 2500baseT_Full);
3617 phy_data->start_mode = XGBE_MODE_KX_2500;
3620 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3623 /* 10GBase-T support */
3624 case XGBE_PORT_MODE_10GBASE_T:
3625 XGBE_SET_SUP(&pdata->phy, Autoneg);
3626 XGBE_SET_SUP(&pdata->phy, Pause);
3627 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3628 XGBE_SET_SUP(&pdata->phy, TP);
3629 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100) {
3630 XGBE_SET_SUP(&pdata->phy, 100baseT_Full);
3631 phy_data->start_mode = XGBE_MODE_SGMII_100;
3633 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000) {
3634 XGBE_SET_SUP(&pdata->phy, 1000baseT_Full);
3635 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3637 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000) {
3638 XGBE_SET_SUP(&pdata->phy, 10000baseT_Full);
3639 phy_data->start_mode = XGBE_MODE_KR;
3642 phy_data->phydev_mode = XGBE_MDIO_MODE_CL45;
3645 /* 10GBase-R support */
3646 case XGBE_PORT_MODE_10GBASE_R:
3647 XGBE_SET_SUP(&pdata->phy, Autoneg);
3648 XGBE_SET_SUP(&pdata->phy, Pause);
3649 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3650 XGBE_SET_SUP(&pdata->phy, FIBRE);
3651 XGBE_SET_SUP(&pdata->phy, 10000baseSR_Full);
3652 XGBE_SET_SUP(&pdata->phy, 10000baseLR_Full);
3653 XGBE_SET_SUP(&pdata->phy, 10000baseLRM_Full);
3654 XGBE_SET_SUP(&pdata->phy, 10000baseER_Full);
3655 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
3656 XGBE_SET_SUP(&pdata->phy, 10000baseR_FEC);
3657 phy_data->start_mode = XGBE_MODE_SFI;
3659 phy_data->phydev_mode = XGBE_MDIO_MODE_NONE;
3663 case XGBE_PORT_MODE_SFP:
3664 XGBE_SET_SUP(&pdata->phy, Autoneg);
3665 XGBE_SET_SUP(&pdata->phy, Pause);
3666 XGBE_SET_SUP(&pdata->phy, Asym_Pause);
3667 XGBE_SET_SUP(&pdata->phy, TP);
3668 XGBE_SET_SUP(&pdata->phy, FIBRE);
3669 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_100)
3670 phy_data->start_mode = XGBE_MODE_SGMII_100;
3671 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_1000)
3672 phy_data->start_mode = XGBE_MODE_SGMII_1000;
3673 if (phy_data->port_speeds & XGBE_PHY_PORT_SPEED_10000)
3674 phy_data->start_mode = XGBE_MODE_SFI;
3676 phy_data->phydev_mode = XGBE_MDIO_MODE_CL22;
3678 xgbe_phy_sfp_setup(pdata);
3679 DBGPR("%s: start %d mode %d adv 0x%x\n", __func__,
3680 phy_data->start_mode, phy_data->phydev_mode,
3681 pdata->phy.advertising);
3687 axgbe_printf(2, "%s: start %d mode %d adv 0x%x\n", __func__,
3688 phy_data->start_mode, phy_data->phydev_mode, pdata->phy.advertising);
3690 DBGPR("%s: conn type %d mode %d\n", __func__,
3691 phy_data->conn_type, phy_data->phydev_mode);
3692 if ((phy_data->conn_type & XGBE_CONN_TYPE_MDIO) &&
3693 (phy_data->phydev_mode != XGBE_MDIO_MODE_NONE)) {
3694 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr,
3695 phy_data->phydev_mode);
3697 axgbe_error("mdio port/clause not compatible (%d/%u)\n",
3698 phy_data->mdio_addr, phy_data->phydev_mode);
3703 if (phy_data->redrv && !phy_data->redrv_if) {
3704 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr,
3705 XGBE_MDIO_MODE_CL22);
3707 axgbe_error("redriver mdio port not compatible (%u)\n",
3708 phy_data->redrv_addr);
3713 phy_data->phy_cdr_delay = XGBE_CDR_DELAY_INIT;
3715 if (phy_data->port_mode != XGBE_PORT_MODE_SFP) {
3716 ret = mii_attach(pdata->dev, &pdata->axgbe_miibus, pdata->netdev,
3717 (ifm_change_cb_t)axgbe_ifmedia_upd,
3718 (ifm_stat_cb_t)axgbe_ifmedia_sts, BMSR_DEFCAPMASK,
3719 pdata->mdio_addr, MII_OFFSET_ANY, MIIF_FORCEANEG);
3722 axgbe_printf(2, "mii attach failed with err=(%d)\n", ret);
3727 DBGPR("%s: return success\n", __func__);
3733 xgbe_init_function_ptrs_phy_v2(struct xgbe_phy_if *phy_if)
3735 struct xgbe_phy_impl_if *phy_impl = &phy_if->phy_impl;
3737 phy_impl->init = xgbe_phy_init;
3738 phy_impl->exit = xgbe_phy_exit;
3740 phy_impl->reset = xgbe_phy_reset;
3741 phy_impl->start = xgbe_phy_start;
3742 phy_impl->stop = xgbe_phy_stop;
3744 phy_impl->link_status = xgbe_phy_link_status;
3746 phy_impl->valid_speed = xgbe_phy_valid_speed;
3748 phy_impl->use_mode = xgbe_phy_use_mode;
3749 phy_impl->set_mode = xgbe_phy_set_mode;
3750 phy_impl->get_mode = xgbe_phy_get_mode;
3751 phy_impl->switch_mode = xgbe_phy_switch_mode;
3752 phy_impl->cur_mode = xgbe_phy_cur_mode;
3753 phy_impl->get_type = xgbe_phy_get_type;
3755 phy_impl->an_mode = xgbe_phy_an_mode;
3757 phy_impl->an_config = xgbe_phy_an_config;
3759 phy_impl->an_advertising = xgbe_phy_an_advertising;
3761 phy_impl->an_outcome = xgbe_phy_an_outcome;
3763 phy_impl->an_pre = xgbe_phy_an_pre;
3764 phy_impl->an_post = xgbe_phy_an_post;
3766 phy_impl->kr_training_pre = xgbe_phy_kr_training_pre;
3767 phy_impl->kr_training_post = xgbe_phy_kr_training_post;
3769 phy_impl->module_info = xgbe_phy_module_info;
3770 phy_impl->module_eeprom = xgbe_phy_module_eeprom;